mtk-sd.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
   4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
   5 */
   6
   7#include <linux/module.h>
   8#include <linux/bitfield.h>
   9#include <linux/bitops.h>
  10#include <linux/clk.h>
  11#include <linux/delay.h>
  12#include <linux/dma-mapping.h>
  13#include <linux/iopoll.h>
  14#include <linux/ioport.h>
  15#include <linux/irq.h>
  16#include <linux/of.h>
  17#include <linux/pinctrl/consumer.h>
  18#include <linux/platform_device.h>
  19#include <linux/pm.h>
  20#include <linux/pm_runtime.h>
  21#include <linux/pm_wakeirq.h>
  22#include <linux/regulator/consumer.h>
  23#include <linux/slab.h>
  24#include <linux/spinlock.h>
  25#include <linux/interrupt.h>
  26#include <linux/reset.h>
  27
  28#include <linux/mmc/card.h>
  29#include <linux/mmc/core.h>
  30#include <linux/mmc/host.h>
  31#include <linux/mmc/mmc.h>
  32#include <linux/mmc/sd.h>
  33#include <linux/mmc/sdio.h>
  34#include <linux/mmc/slot-gpio.h>
  35
  36#include "cqhci.h"
  37#include "mmc_hsq.h"
  38
  39#define MAX_BD_NUM          1024
  40#define MSDC_NR_CLOCKS      3
  41
  42/*--------------------------------------------------------------------------*/
  43/* Common Definition                                                        */
  44/*--------------------------------------------------------------------------*/
  45#define MSDC_BUS_1BITS          0x0
  46#define MSDC_BUS_4BITS          0x1
  47#define MSDC_BUS_8BITS          0x2
  48
  49#define MSDC_BURST_64B          0x6
  50
  51/*--------------------------------------------------------------------------*/
  52/* Register Offset                                                          */
  53/*--------------------------------------------------------------------------*/
  54#define MSDC_CFG         0x0
  55#define MSDC_IOCON       0x04
  56#define MSDC_PS          0x08
  57#define MSDC_INT         0x0c
  58#define MSDC_INTEN       0x10
  59#define MSDC_FIFOCS      0x14
  60#define SDC_CFG          0x30
  61#define SDC_CMD          0x34
  62#define SDC_ARG          0x38
  63#define SDC_STS          0x3c
  64#define SDC_RESP0        0x40
  65#define SDC_RESP1        0x44
  66#define SDC_RESP2        0x48
  67#define SDC_RESP3        0x4c
  68#define SDC_BLK_NUM      0x50
  69#define SDC_ADV_CFG0     0x64
  70#define MSDC_NEW_RX_CFG  0x68
  71#define EMMC_IOCON       0x7c
  72#define SDC_ACMD_RESP    0x80
  73#define DMA_SA_H4BIT     0x8c
  74#define MSDC_DMA_SA      0x90
  75#define MSDC_DMA_CTRL    0x98
  76#define MSDC_DMA_CFG     0x9c
  77#define MSDC_PATCH_BIT   0xb0
  78#define MSDC_PATCH_BIT1  0xb4
  79#define MSDC_PATCH_BIT2  0xb8
  80#define MSDC_PAD_TUNE    0xec
  81#define MSDC_PAD_TUNE0   0xf0
  82#define PAD_DS_TUNE      0x188
  83#define PAD_CMD_TUNE     0x18c
  84#define EMMC51_CFG0	 0x204
  85#define EMMC50_CFG0      0x208
  86#define EMMC50_CFG1      0x20c
  87#define EMMC50_CFG2      0x21c
  88#define EMMC50_CFG3      0x220
  89#define SDC_FIFO_CFG     0x228
  90#define CQHCI_SETTING	 0x7fc
  91
  92/*--------------------------------------------------------------------------*/
  93/* Top Pad Register Offset                                                  */
  94/*--------------------------------------------------------------------------*/
  95#define EMMC_TOP_CONTROL	0x00
  96#define EMMC_TOP_CMD		0x04
  97#define EMMC50_PAD_DS_TUNE	0x0c
  98#define LOOP_TEST_CONTROL	0x30
  99
 100/*--------------------------------------------------------------------------*/
 101/* Register Mask                                                            */
 102/*--------------------------------------------------------------------------*/
 103
 104/* MSDC_CFG mask */
 105#define MSDC_CFG_MODE           BIT(0)	/* RW */
 106#define MSDC_CFG_CKPDN          BIT(1)	/* RW */
 107#define MSDC_CFG_RST            BIT(2)	/* RW */
 108#define MSDC_CFG_PIO            BIT(3)	/* RW */
 109#define MSDC_CFG_CKDRVEN        BIT(4)	/* RW */
 110#define MSDC_CFG_BV18SDT        BIT(5)	/* RW */
 111#define MSDC_CFG_BV18PSS        BIT(6)	/* R  */
 112#define MSDC_CFG_CKSTB          BIT(7)	/* R  */
 113#define MSDC_CFG_CKDIV          GENMASK(15, 8)	/* RW */
 114#define MSDC_CFG_CKMOD          GENMASK(17, 16)	/* RW */
 115#define MSDC_CFG_HS400_CK_MODE  BIT(18)	/* RW */
 116#define MSDC_CFG_HS400_CK_MODE_EXTRA  BIT(22)	/* RW */
 117#define MSDC_CFG_CKDIV_EXTRA    GENMASK(19, 8)	/* RW */
 118#define MSDC_CFG_CKMOD_EXTRA    GENMASK(21, 20)	/* RW */
 119
 120/* MSDC_IOCON mask */
 121#define MSDC_IOCON_SDR104CKS    BIT(0)	/* RW */
 122#define MSDC_IOCON_RSPL         BIT(1)	/* RW */
 123#define MSDC_IOCON_DSPL         BIT(2)	/* RW */
 124#define MSDC_IOCON_DDLSEL       BIT(3)	/* RW */
 125#define MSDC_IOCON_DDR50CKD     BIT(4)	/* RW */
 126#define MSDC_IOCON_DSPLSEL      BIT(5)	/* RW */
 127#define MSDC_IOCON_W_DSPL       BIT(8)	/* RW */
 128#define MSDC_IOCON_D0SPL        BIT(16)	/* RW */
 129#define MSDC_IOCON_D1SPL        BIT(17)	/* RW */
 130#define MSDC_IOCON_D2SPL        BIT(18)	/* RW */
 131#define MSDC_IOCON_D3SPL        BIT(19)	/* RW */
 132#define MSDC_IOCON_D4SPL        BIT(20)	/* RW */
 133#define MSDC_IOCON_D5SPL        BIT(21)	/* RW */
 134#define MSDC_IOCON_D6SPL        BIT(22)	/* RW */
 135#define MSDC_IOCON_D7SPL        BIT(23)	/* RW */
 136#define MSDC_IOCON_RISCSZ       GENMASK(25, 24)	/* RW */
 137
 138/* MSDC_PS mask */
 139#define MSDC_PS_CDEN            BIT(0)	/* RW */
 140#define MSDC_PS_CDSTS           BIT(1)	/* R  */
 141#define MSDC_PS_CDDEBOUNCE      GENMASK(15, 12)	/* RW */
 142#define MSDC_PS_DAT             GENMASK(23, 16)	/* R  */
 143#define MSDC_PS_DATA1           BIT(17)	/* R  */
 144#define MSDC_PS_CMD             BIT(24)	/* R  */
 145#define MSDC_PS_WP              BIT(31)	/* R  */
 146
 147/* MSDC_INT mask */
 148#define MSDC_INT_MMCIRQ         BIT(0)	/* W1C */
 149#define MSDC_INT_CDSC           BIT(1)	/* W1C */
 150#define MSDC_INT_ACMDRDY        BIT(3)	/* W1C */
 151#define MSDC_INT_ACMDTMO        BIT(4)	/* W1C */
 152#define MSDC_INT_ACMDCRCERR     BIT(5)	/* W1C */
 153#define MSDC_INT_DMAQ_EMPTY     BIT(6)	/* W1C */
 154#define MSDC_INT_SDIOIRQ        BIT(7)	/* W1C */
 155#define MSDC_INT_CMDRDY         BIT(8)	/* W1C */
 156#define MSDC_INT_CMDTMO         BIT(9)	/* W1C */
 157#define MSDC_INT_RSPCRCERR      BIT(10)	/* W1C */
 158#define MSDC_INT_CSTA           BIT(11)	/* R */
 159#define MSDC_INT_XFER_COMPL     BIT(12)	/* W1C */
 160#define MSDC_INT_DXFER_DONE     BIT(13)	/* W1C */
 161#define MSDC_INT_DATTMO         BIT(14)	/* W1C */
 162#define MSDC_INT_DATCRCERR      BIT(15)	/* W1C */
 163#define MSDC_INT_ACMD19_DONE    BIT(16)	/* W1C */
 164#define MSDC_INT_DMA_BDCSERR    BIT(17)	/* W1C */
 165#define MSDC_INT_DMA_GPDCSERR   BIT(18)	/* W1C */
 166#define MSDC_INT_DMA_PROTECT    BIT(19)	/* W1C */
 167#define MSDC_INT_CMDQ           BIT(28)	/* W1C */
 168
 169/* MSDC_INTEN mask */
 170#define MSDC_INTEN_MMCIRQ       BIT(0)	/* RW */
 171#define MSDC_INTEN_CDSC         BIT(1)	/* RW */
 172#define MSDC_INTEN_ACMDRDY      BIT(3)	/* RW */
 173#define MSDC_INTEN_ACMDTMO      BIT(4)	/* RW */
 174#define MSDC_INTEN_ACMDCRCERR   BIT(5)	/* RW */
 175#define MSDC_INTEN_DMAQ_EMPTY   BIT(6)	/* RW */
 176#define MSDC_INTEN_SDIOIRQ      BIT(7)	/* RW */
 177#define MSDC_INTEN_CMDRDY       BIT(8)	/* RW */
 178#define MSDC_INTEN_CMDTMO       BIT(9)	/* RW */
 179#define MSDC_INTEN_RSPCRCERR    BIT(10)	/* RW */
 180#define MSDC_INTEN_CSTA         BIT(11)	/* RW */
 181#define MSDC_INTEN_XFER_COMPL   BIT(12)	/* RW */
 182#define MSDC_INTEN_DXFER_DONE   BIT(13)	/* RW */
 183#define MSDC_INTEN_DATTMO       BIT(14)	/* RW */
 184#define MSDC_INTEN_DATCRCERR    BIT(15)	/* RW */
 185#define MSDC_INTEN_ACMD19_DONE  BIT(16)	/* RW */
 186#define MSDC_INTEN_DMA_BDCSERR  BIT(17)	/* RW */
 187#define MSDC_INTEN_DMA_GPDCSERR BIT(18)	/* RW */
 188#define MSDC_INTEN_DMA_PROTECT  BIT(19)	/* RW */
 189
 190/* MSDC_FIFOCS mask */
 191#define MSDC_FIFOCS_RXCNT       GENMASK(7, 0)	/* R */
 192#define MSDC_FIFOCS_TXCNT       GENMASK(23, 16)	/* R */
 193#define MSDC_FIFOCS_CLR         BIT(31)	/* RW */
 194
 195/* SDC_CFG mask */
 196#define SDC_CFG_SDIOINTWKUP     BIT(0)	/* RW */
 197#define SDC_CFG_INSWKUP         BIT(1)	/* RW */
 198#define SDC_CFG_WRDTOC          GENMASK(14, 2)  /* RW */
 199#define SDC_CFG_BUSWIDTH        GENMASK(17, 16)	/* RW */
 200#define SDC_CFG_SDIO            BIT(19)	/* RW */
 201#define SDC_CFG_SDIOIDE         BIT(20)	/* RW */
 202#define SDC_CFG_INTATGAP        BIT(21)	/* RW */
 203#define SDC_CFG_DTOC            GENMASK(31, 24)	/* RW */
 204
 205/* SDC_STS mask */
 206#define SDC_STS_SDCBUSY         BIT(0)	/* RW */
 207#define SDC_STS_CMDBUSY         BIT(1)	/* RW */
 208#define SDC_STS_SWR_COMPL       BIT(31)	/* RW */
 209
 210/* SDC_ADV_CFG0 mask */
 211#define SDC_DAT1_IRQ_TRIGGER	BIT(19)	/* RW */
 212#define SDC_RX_ENHANCE_EN	BIT(20)	/* RW */
 213#define SDC_NEW_TX_EN		BIT(31)	/* RW */
 214
 215/* MSDC_NEW_RX_CFG mask */
 216#define MSDC_NEW_RX_PATH_SEL	BIT(0)	/* RW */
 217
 218/* DMA_SA_H4BIT mask */
 219#define DMA_ADDR_HIGH_4BIT      GENMASK(3, 0)	/* RW */
 220
 221/* MSDC_DMA_CTRL mask */
 222#define MSDC_DMA_CTRL_START     BIT(0)	/* W */
 223#define MSDC_DMA_CTRL_STOP      BIT(1)	/* W */
 224#define MSDC_DMA_CTRL_RESUME    BIT(2)	/* W */
 225#define MSDC_DMA_CTRL_MODE      BIT(8)	/* RW */
 226#define MSDC_DMA_CTRL_LASTBUF   BIT(10)	/* RW */
 227#define MSDC_DMA_CTRL_BRUSTSZ   GENMASK(14, 12)	/* RW */
 228
 229/* MSDC_DMA_CFG mask */
 230#define MSDC_DMA_CFG_STS        BIT(0)	/* R */
 231#define MSDC_DMA_CFG_DECSEN     BIT(1)	/* RW */
 232#define MSDC_DMA_CFG_AHBHPROT2  BIT(9)	/* RW */
 233#define MSDC_DMA_CFG_ACTIVEEN   BIT(13)	/* RW */
 234#define MSDC_DMA_CFG_CS12B16B   BIT(16)	/* RW */
 235
 236/* MSDC_PATCH_BIT mask */
 237#define MSDC_PATCH_BIT_ODDSUPP    BIT(1)	/* RW */
 238#define MSDC_PATCH_BIT_DIS_WRMON  BIT(2)	/* RW */
 239#define MSDC_PATCH_BIT_RD_DAT_SEL BIT(3)	/* RW */
 240#define MSDC_PATCH_BIT_DESCUP_SEL BIT(6)	/* RW */
 241#define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
 242#define MSDC_CKGEN_MSDC_DLY_SEL   GENMASK(14, 10)
 243#define MSDC_PATCH_BIT_IODSSEL    BIT(16)	/* RW */
 244#define MSDC_PATCH_BIT_IOINTSEL   BIT(17)	/* RW */
 245#define MSDC_PATCH_BIT_BUSYDLY    GENMASK(21, 18)	/* RW */
 246#define MSDC_PATCH_BIT_WDOD       GENMASK(25, 22)	/* RW */
 247#define MSDC_PATCH_BIT_IDRTSEL    BIT(26)	/* RW */
 248#define MSDC_PATCH_BIT_CMDFSEL    BIT(27)	/* RW */
 249#define MSDC_PATCH_BIT_INTDLSEL   BIT(28)	/* RW */
 250#define MSDC_PATCH_BIT_SPCPUSH    BIT(29)	/* RW */
 251#define MSDC_PATCH_BIT_DECRCTMO   BIT(30)	/* RW */
 252
 253/* MSDC_PATCH_BIT1 mask */
 254#define MSDC_PB1_WRDAT_CRC_TACNTR GENMASK(2, 0)     /* RW */
 255#define MSDC_PATCH_BIT1_CMDTA     GENMASK(5, 3)     /* RW */
 256#define MSDC_PB1_BUSY_CHECK_SEL   BIT(7)    /* RW */
 257#define MSDC_PATCH_BIT1_STOP_DLY  GENMASK(11, 8)    /* RW */
 258#define MSDC_PB1_DDR_CMD_FIX_SEL  BIT(14)           /* RW */
 259#define MSDC_PB1_SINGLE_BURST     BIT(16)           /* RW */
 260#define MSDC_PB1_RSVD20           GENMASK(18, 17)   /* RW */
 261#define MSDC_PB1_AUTO_SYNCST_CLR  BIT(19)           /* RW */
 262#define MSDC_PB1_MARK_POP_WATER   BIT(20)           /* RW */
 263#define MSDC_PB1_LP_DCM_EN        BIT(21)           /* RW */
 264#define MSDC_PB1_RSVD3            BIT(22)           /* RW */
 265#define MSDC_PB1_AHB_GDMA_HCLK    BIT(23)           /* RW */
 266#define MSDC_PB1_MSDC_CLK_ENFEAT  GENMASK(31, 24)   /* RW */
 267
 268/* MSDC_PATCH_BIT2 mask */
 269#define MSDC_PATCH_BIT2_CFGRESP   BIT(15)   /* RW */
 270#define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28)   /* RW */
 271#define MSDC_PB2_SUPPORT_64G      BIT(1)    /* RW */
 272#define MSDC_PB2_RESPWAIT         GENMASK(3, 2)   /* RW */
 273#define MSDC_PB2_RESPSTSENSEL     GENMASK(18, 16) /* RW */
 274#define MSDC_PB2_POP_EN_CNT       GENMASK(23, 20) /* RW */
 275#define MSDC_PB2_CFGCRCSTSEDGE    BIT(25)   /* RW */
 276#define MSDC_PB2_CRCSTSENSEL      GENMASK(31, 29) /* RW */
 277
 278#define MSDC_PAD_TUNE_DATWRDLY	  GENMASK(4, 0)		/* RW */
 279#define MSDC_PAD_TUNE_DATRRDLY	  GENMASK(12, 8)	/* RW */
 280#define MSDC_PAD_TUNE_DATRRDLY2	  GENMASK(12, 8)	/* RW */
 281#define MSDC_PAD_TUNE_CMDRDLY	  GENMASK(20, 16)	/* RW */
 282#define MSDC_PAD_TUNE_CMDRDLY2	  GENMASK(20, 16)	/* RW */
 283#define MSDC_PAD_TUNE_CMDRRDLY	  GENMASK(26, 22)	/* RW */
 284#define MSDC_PAD_TUNE_CLKTDLY	  GENMASK(31, 27)	/* RW */
 285#define MSDC_PAD_TUNE_RXDLYSEL	  BIT(15)   /* RW */
 286#define MSDC_PAD_TUNE_RD_SEL	  BIT(13)   /* RW */
 287#define MSDC_PAD_TUNE_CMD_SEL	  BIT(21)   /* RW */
 288#define MSDC_PAD_TUNE_RD2_SEL	  BIT(13)   /* RW */
 289#define MSDC_PAD_TUNE_CMD2_SEL	  BIT(21)   /* RW */
 290
 291#define PAD_DS_TUNE_DLY_SEL       BIT(0)	  /* RW */
 292#define PAD_DS_TUNE_DLY2_SEL      BIT(1)	  /* RW */
 293#define PAD_DS_TUNE_DLY1	  GENMASK(6, 2)   /* RW */
 294#define PAD_DS_TUNE_DLY2	  GENMASK(11, 7)  /* RW */
 295#define PAD_DS_TUNE_DLY3	  GENMASK(16, 12) /* RW */
 296
 297#define PAD_CMD_TUNE_RX_DLY3	  GENMASK(5, 1)   /* RW */
 298
 299/* EMMC51_CFG0 mask */
 300#define CMDQ_RDAT_CNT		  GENMASK(21, 12) /* RW */
 301
 302#define EMMC50_CFG_PADCMD_LATCHCK BIT(0)   /* RW */
 303#define EMMC50_CFG_CRCSTS_EDGE    BIT(3)   /* RW */
 304#define EMMC50_CFG_CFCSTS_SEL     BIT(4)   /* RW */
 305#define EMMC50_CFG_CMD_RESP_SEL   BIT(9)   /* RW */
 306
 307/* EMMC50_CFG1 mask */
 308#define EMMC50_CFG1_DS_CFG        BIT(28)  /* RW */
 309
 310/* EMMC50_CFG2 mask */
 311#define EMMC50_CFG2_AXI_SET_LEN   GENMASK(27, 24) /* RW */
 312
 313#define EMMC50_CFG3_OUTS_WR       GENMASK(4, 0)   /* RW */
 314
 315#define SDC_FIFO_CFG_WRVALIDSEL   BIT(24)  /* RW */
 316#define SDC_FIFO_CFG_RDVALIDSEL   BIT(25)  /* RW */
 317
 318/* CQHCI_SETTING */
 319#define CQHCI_RD_CMD_WND_SEL	  BIT(14) /* RW */
 320#define CQHCI_WR_CMD_WND_SEL	  BIT(15) /* RW */
 321
 322/* EMMC_TOP_CONTROL mask */
 323#define PAD_RXDLY_SEL           BIT(0)      /* RW */
 324#define DELAY_EN                BIT(1)      /* RW */
 325#define PAD_DAT_RD_RXDLY2       GENMASK(6, 2)     /* RW */
 326#define PAD_DAT_RD_RXDLY        GENMASK(11, 7)    /* RW */
 327#define PAD_DAT_RD_RXDLY2_SEL   BIT(12)     /* RW */
 328#define PAD_DAT_RD_RXDLY_SEL    BIT(13)     /* RW */
 329#define DATA_K_VALUE_SEL        BIT(14)     /* RW */
 330#define SDC_RX_ENH_EN           BIT(15)     /* TW */
 331
 332/* EMMC_TOP_CMD mask */
 333#define PAD_CMD_RXDLY2          GENMASK(4, 0)	/* RW */
 334#define PAD_CMD_RXDLY           GENMASK(9, 5)	/* RW */
 335#define PAD_CMD_RD_RXDLY2_SEL   BIT(10)		/* RW */
 336#define PAD_CMD_RD_RXDLY_SEL    BIT(11)		/* RW */
 337#define PAD_CMD_TX_DLY          GENMASK(16, 12)	/* RW */
 338
 339/* EMMC50_PAD_DS_TUNE mask */
 340#define PAD_DS_DLY_SEL		BIT(16)	/* RW */
 341#define PAD_DS_DLY2_SEL		BIT(15)	/* RW */
 342#define PAD_DS_DLY1		GENMASK(14, 10)	/* RW */
 343#define PAD_DS_DLY3		GENMASK(4, 0)	/* RW */
 344
 345/* LOOP_TEST_CONTROL mask */
 346#define TEST_LOOP_DSCLK_MUX_SEL        BIT(0)	/* RW */
 347#define TEST_LOOP_LATCH_MUX_SEL        BIT(1)	/* RW */
 348#define LOOP_EN_SEL_CLK                BIT(20)	/* RW */
 349#define TEST_HS400_CMD_LOOP_MUX_SEL    BIT(31)	/* RW */
 350
 351#define REQ_CMD_EIO  BIT(0)
 352#define REQ_CMD_TMO  BIT(1)
 353#define REQ_DAT_ERR  BIT(2)
 354#define REQ_STOP_EIO BIT(3)
 355#define REQ_STOP_TMO BIT(4)
 356#define REQ_CMD_BUSY BIT(5)
 357
 358#define MSDC_PREPARE_FLAG BIT(0)
 359#define MSDC_ASYNC_FLAG BIT(1)
 360#define MSDC_MMAP_FLAG BIT(2)
 361
 362#define MTK_MMC_AUTOSUSPEND_DELAY	50
 363#define CMD_TIMEOUT         (HZ/10 * 5)	/* 100ms x5 */
 364#define DAT_TIMEOUT         (HZ    * 5)	/* 1000ms x5 */
 365
 366#define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */
 367
 368#define TUNING_REG2_FIXED_OFFEST	4
 369#define PAD_DELAY_HALF	32 /* PAD delay cells */
 370#define PAD_DELAY_FULL	64
 371/*--------------------------------------------------------------------------*/
 372/* Descriptor Structure                                                     */
 373/*--------------------------------------------------------------------------*/
 374struct mt_gpdma_desc {
 375	u32 gpd_info;
 376#define GPDMA_DESC_HWO		BIT(0)
 377#define GPDMA_DESC_BDP		BIT(1)
 378#define GPDMA_DESC_CHECKSUM	GENMASK(15, 8)
 379#define GPDMA_DESC_INT		BIT(16)
 380#define GPDMA_DESC_NEXT_H4	GENMASK(27, 24)
 381#define GPDMA_DESC_PTR_H4	GENMASK(31, 28)
 382	u32 next;
 383	u32 ptr;
 384	u32 gpd_data_len;
 385#define GPDMA_DESC_BUFLEN	GENMASK(15, 0)
 386#define GPDMA_DESC_EXTLEN	GENMASK(23, 16)
 387	u32 arg;
 388	u32 blknum;
 389	u32 cmd;
 390};
 391
 392struct mt_bdma_desc {
 393	u32 bd_info;
 394#define BDMA_DESC_EOL		BIT(0)
 395#define BDMA_DESC_CHECKSUM	GENMASK(15, 8)
 396#define BDMA_DESC_BLKPAD	BIT(17)
 397#define BDMA_DESC_DWPAD		BIT(18)
 398#define BDMA_DESC_NEXT_H4	GENMASK(27, 24)
 399#define BDMA_DESC_PTR_H4	GENMASK(31, 28)
 400	u32 next;
 401	u32 ptr;
 402	u32 bd_data_len;
 403#define BDMA_DESC_BUFLEN	GENMASK(15, 0)
 404#define BDMA_DESC_BUFLEN_EXT	GENMASK(23, 0)
 405};
 406
 407struct msdc_dma {
 408	struct scatterlist *sg;	/* I/O scatter list */
 409	struct mt_gpdma_desc *gpd;		/* pointer to gpd array */
 410	struct mt_bdma_desc *bd;		/* pointer to bd array */
 411	dma_addr_t gpd_addr;	/* the physical address of gpd array */
 412	dma_addr_t bd_addr;	/* the physical address of bd array */
 413};
 414
 415struct msdc_save_para {
 416	u32 msdc_cfg;
 417	u32 iocon;
 418	u32 sdc_cfg;
 419	u32 pad_tune;
 420	u32 patch_bit0;
 421	u32 patch_bit1;
 422	u32 patch_bit2;
 423	u32 pad_ds_tune;
 424	u32 pad_cmd_tune;
 425	u32 emmc50_cfg0;
 426	u32 emmc50_cfg3;
 427	u32 sdc_fifo_cfg;
 428	u32 emmc_top_control;
 429	u32 emmc_top_cmd;
 430	u32 emmc50_pad_ds_tune;
 431	u32 loop_test_control;
 432};
 433
 434struct mtk_mmc_compatible {
 435	u8 clk_div_bits;
 436	bool recheck_sdio_irq;
 437	bool hs400_tune; /* only used for MT8173 */
 438	bool needs_top_base;
 439	u32 pad_tune_reg;
 440	bool async_fifo;
 441	bool data_tune;
 442	bool busy_check;
 443	bool stop_clk_fix;
 444	u8 stop_dly_sel;
 445	u8 pop_en_cnt;
 446	bool enhance_rx;
 447	bool support_64g;
 448	bool use_internal_cd;
 449	bool support_new_tx;
 450	bool support_new_rx;
 451};
 452
 453struct msdc_tune_para {
 454	u32 iocon;
 455	u32 pad_tune;
 456	u32 pad_cmd_tune;
 457	u32 emmc_top_control;
 458	u32 emmc_top_cmd;
 459};
 460
 461struct msdc_delay_phase {
 462	u8 maxlen;
 463	u8 start;
 464	u8 final_phase;
 465};
 466
 467struct msdc_host {
 468	struct device *dev;
 469	const struct mtk_mmc_compatible *dev_comp;
 470	int cmd_rsp;
 471
 472	spinlock_t lock;
 473	struct mmc_request *mrq;
 474	struct mmc_command *cmd;
 475	struct mmc_data *data;
 476	int error;
 477
 478	void __iomem *base;		/* host base address */
 479	void __iomem *top_base;		/* host top register base address */
 480
 481	struct msdc_dma dma;	/* dma channel */
 482	u64 dma_mask;
 483
 484	u32 timeout_ns;		/* data timeout ns */
 485	u32 timeout_clks;	/* data timeout clks */
 486
 487	struct pinctrl *pinctrl;
 488	struct pinctrl_state *pins_default;
 489	struct pinctrl_state *pins_uhs;
 490	struct pinctrl_state *pins_eint;
 491	struct delayed_work req_timeout;
 492	int irq;		/* host interrupt */
 493	int eint_irq;		/* interrupt from sdio device for waking up system */
 494	struct reset_control *reset;
 495
 496	struct clk *src_clk;	/* msdc source clock */
 497	struct clk *h_clk;      /* msdc h_clk */
 498	struct clk *bus_clk;	/* bus clock which used to access register */
 499	struct clk *src_clk_cg; /* msdc source clock control gate */
 500	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
 501	struct clk *crypto_clk; /* msdc crypto clock control gate */
 502	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
 503	u32 mclk;		/* mmc subsystem clock frequency */
 504	u32 src_clk_freq;	/* source clock frequency */
 505	unsigned char timing;
 506	bool vqmmc_enabled;
 507	u32 latch_ck;
 508	u32 hs400_ds_delay;
 509	u32 hs400_ds_dly3;
 510	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
 511	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
 512	u32 tuning_step;
 513	bool hs400_cmd_resp_sel_rising;
 514				 /* cmd response sample selection for HS400 */
 515	bool hs400_mode;	/* current eMMC will run at hs400 mode */
 516	bool hs400_tuning;	/* hs400 mode online tuning */
 517	bool internal_cd;	/* Use internal card-detect logic */
 518	bool cqhci;		/* support eMMC hw cmdq */
 519	bool hsq_en;		/* Host Software Queue is enabled */
 520	struct msdc_save_para save_para; /* used when gate HCLK */
 521	struct msdc_tune_para def_tune_para; /* default tune setting */
 522	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
 523	struct cqhci_host *cq_host;
 524	u32 cq_ssc1_time;
 525};
 526
 527static const struct mtk_mmc_compatible mt2701_compat = {
 528	.clk_div_bits = 12,
 529	.recheck_sdio_irq = true,
 530	.hs400_tune = false,
 531	.pad_tune_reg = MSDC_PAD_TUNE0,
 532	.async_fifo = true,
 533	.data_tune = true,
 534	.busy_check = false,
 535	.stop_clk_fix = false,
 536	.enhance_rx = false,
 537	.support_64g = false,
 538};
 539
 540static const struct mtk_mmc_compatible mt2712_compat = {
 541	.clk_div_bits = 12,
 542	.recheck_sdio_irq = false,
 543	.hs400_tune = false,
 544	.pad_tune_reg = MSDC_PAD_TUNE0,
 545	.async_fifo = true,
 546	.data_tune = true,
 547	.busy_check = true,
 548	.stop_clk_fix = true,
 549	.stop_dly_sel = 3,
 550	.enhance_rx = true,
 551	.support_64g = true,
 552};
 553
 554static const struct mtk_mmc_compatible mt6779_compat = {
 555	.clk_div_bits = 12,
 556	.recheck_sdio_irq = false,
 557	.hs400_tune = false,
 558	.pad_tune_reg = MSDC_PAD_TUNE0,
 559	.async_fifo = true,
 560	.data_tune = true,
 561	.busy_check = true,
 562	.stop_clk_fix = true,
 563	.stop_dly_sel = 3,
 564	.enhance_rx = true,
 565	.support_64g = true,
 566};
 567
 568static const struct mtk_mmc_compatible mt6795_compat = {
 569	.clk_div_bits = 8,
 570	.recheck_sdio_irq = false,
 571	.hs400_tune = true,
 572	.pad_tune_reg = MSDC_PAD_TUNE,
 573	.async_fifo = false,
 574	.data_tune = false,
 575	.busy_check = false,
 576	.stop_clk_fix = false,
 577	.enhance_rx = false,
 578	.support_64g = false,
 579};
 580
 581static const struct mtk_mmc_compatible mt7620_compat = {
 582	.clk_div_bits = 8,
 583	.recheck_sdio_irq = true,
 584	.hs400_tune = false,
 585	.pad_tune_reg = MSDC_PAD_TUNE,
 586	.async_fifo = false,
 587	.data_tune = false,
 588	.busy_check = false,
 589	.stop_clk_fix = false,
 590	.enhance_rx = false,
 591	.use_internal_cd = true,
 592};
 593
 594static const struct mtk_mmc_compatible mt7622_compat = {
 595	.clk_div_bits = 12,
 596	.recheck_sdio_irq = true,
 597	.hs400_tune = false,
 598	.pad_tune_reg = MSDC_PAD_TUNE0,
 599	.async_fifo = true,
 600	.data_tune = true,
 601	.busy_check = true,
 602	.stop_clk_fix = true,
 603	.stop_dly_sel = 3,
 604	.enhance_rx = true,
 605	.support_64g = false,
 606};
 607
 608static const struct mtk_mmc_compatible mt7986_compat = {
 609	.clk_div_bits = 12,
 610	.recheck_sdio_irq = true,
 611	.hs400_tune = false,
 612	.needs_top_base = true,
 613	.pad_tune_reg = MSDC_PAD_TUNE0,
 614	.async_fifo = true,
 615	.data_tune = true,
 616	.busy_check = true,
 617	.stop_clk_fix = true,
 618	.stop_dly_sel = 3,
 619	.enhance_rx = true,
 620	.support_64g = true,
 621};
 622
 623static const struct mtk_mmc_compatible mt8135_compat = {
 624	.clk_div_bits = 8,
 625	.recheck_sdio_irq = true,
 626	.hs400_tune = false,
 627	.pad_tune_reg = MSDC_PAD_TUNE,
 628	.async_fifo = false,
 629	.data_tune = false,
 630	.busy_check = false,
 631	.stop_clk_fix = false,
 632	.enhance_rx = false,
 633	.support_64g = false,
 634};
 635
 636static const struct mtk_mmc_compatible mt8173_compat = {
 637	.clk_div_bits = 8,
 638	.recheck_sdio_irq = true,
 639	.hs400_tune = true,
 640	.pad_tune_reg = MSDC_PAD_TUNE,
 641	.async_fifo = false,
 642	.data_tune = false,
 643	.busy_check = false,
 644	.stop_clk_fix = false,
 645	.enhance_rx = false,
 646	.support_64g = false,
 647};
 648
 649static const struct mtk_mmc_compatible mt8183_compat = {
 650	.clk_div_bits = 12,
 651	.recheck_sdio_irq = false,
 652	.hs400_tune = false,
 653	.needs_top_base = true,
 654	.pad_tune_reg = MSDC_PAD_TUNE0,
 655	.async_fifo = true,
 656	.data_tune = true,
 657	.busy_check = true,
 658	.stop_clk_fix = true,
 659	.stop_dly_sel = 3,
 660	.enhance_rx = true,
 661	.support_64g = true,
 662};
 663
 664static const struct mtk_mmc_compatible mt8516_compat = {
 665	.clk_div_bits = 12,
 666	.recheck_sdio_irq = true,
 667	.hs400_tune = false,
 668	.pad_tune_reg = MSDC_PAD_TUNE0,
 669	.async_fifo = true,
 670	.data_tune = true,
 671	.busy_check = true,
 672	.stop_clk_fix = true,
 673	.stop_dly_sel = 3,
 674};
 675
 676static const struct mtk_mmc_compatible mt8196_compat = {
 677	.clk_div_bits = 12,
 678	.recheck_sdio_irq = false,
 679	.hs400_tune = false,
 680	.needs_top_base = true,
 681	.pad_tune_reg = MSDC_PAD_TUNE0,
 682	.async_fifo = true,
 683	.data_tune = true,
 684	.busy_check = true,
 685	.stop_clk_fix = true,
 686	.stop_dly_sel = 1,
 687	.pop_en_cnt = 2,
 688	.enhance_rx = true,
 689	.support_64g = true,
 690	.support_new_tx = true,
 691	.support_new_rx = true,
 692};
 693
 694static const struct of_device_id msdc_of_ids[] = {
 695	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
 696	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
 697	{ .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
 698	{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
 699	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
 700	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
 701	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
 702	{ .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat},
 703	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
 704	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
 705	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
 706	{ .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
 707	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
 708
 709	{}
 710};
 711MODULE_DEVICE_TABLE(of, msdc_of_ids);
 712
 713static void sdr_set_bits(void __iomem *reg, u32 bs)
 714{
 715	u32 val = readl(reg);
 716
 717	val |= bs;
 718	writel(val, reg);
 719}
 720
 721static void sdr_clr_bits(void __iomem *reg, u32 bs)
 722{
 723	u32 val = readl(reg);
 724
 725	val &= ~bs;
 726	writel(val, reg);
 727}
 728
 729static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
 730{
 731	unsigned int tv = readl(reg);
 732
 733	tv &= ~field;
 734	tv |= ((val) << (ffs((unsigned int)field) - 1));
 735	writel(tv, reg);
 736}
 737
 738static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
 739{
 740	unsigned int tv = readl(reg);
 741
 742	*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
 743}
 744
 745static void msdc_reset_hw(struct msdc_host *host)
 746{
 747	u32 val;
 748
 749	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
 750	readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
 751
 752	sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
 753	readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
 754				  !(val & MSDC_FIFOCS_CLR), 0, 0);
 755
 756	val = readl(host->base + MSDC_INT);
 757	writel(val, host->base + MSDC_INT);
 758}
 759
 760static void msdc_cmd_next(struct msdc_host *host,
 761		struct mmc_request *mrq, struct mmc_command *cmd);
 762static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
 763
 764static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
 765			MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
 766			MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
 767static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
 768			MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
 769			MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
 770
 771static u8 msdc_dma_calcs(u8 *buf, u32 len)
 772{
 773	u32 i, sum = 0;
 774
 775	for (i = 0; i < len; i++)
 776		sum += buf[i];
 777	return 0xff - (u8) sum;
 778}
 779
 780static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
 781		struct mmc_data *data)
 782{
 783	unsigned int j, dma_len;
 784	dma_addr_t dma_address;
 785	u32 dma_ctrl;
 786	struct scatterlist *sg;
 787	struct mt_gpdma_desc *gpd;
 788	struct mt_bdma_desc *bd;
 789
 790	sg = data->sg;
 791
 792	gpd = dma->gpd;
 793	bd = dma->bd;
 794
 795	/* modify gpd */
 796	gpd->gpd_info |= GPDMA_DESC_HWO;
 797	gpd->gpd_info |= GPDMA_DESC_BDP;
 798	/* need to clear first. use these bits to calc checksum */
 799	gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
 800	gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
 801
 802	/* modify bd */
 803	for_each_sg(data->sg, sg, data->sg_count, j) {
 804		dma_address = sg_dma_address(sg);
 805		dma_len = sg_dma_len(sg);
 806
 807		/* init bd */
 808		bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
 809		bd[j].bd_info &= ~BDMA_DESC_DWPAD;
 810		bd[j].ptr = lower_32_bits(dma_address);
 811		if (host->dev_comp->support_64g) {
 812			bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
 813			bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
 814					 << 28;
 815		}
 816
 817		if (host->dev_comp->support_64g) {
 818			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
 819			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
 820		} else {
 821			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
 822			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
 823		}
 824
 825		if (j == data->sg_count - 1) /* the last bd */
 826			bd[j].bd_info |= BDMA_DESC_EOL;
 827		else
 828			bd[j].bd_info &= ~BDMA_DESC_EOL;
 829
 830		/* checksum need to clear first */
 831		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
 832		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
 833	}
 834
 835	sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
 836	dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
 837	dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
 838	dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
 839	writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
 840	if (host->dev_comp->support_64g)
 841		sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
 842			      upper_32_bits(dma->gpd_addr) & 0xf);
 843	writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
 844}
 845
 846static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
 847{
 848	if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
 849		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
 850					    mmc_get_dma_dir(data));
 851		if (data->sg_count)
 852			data->host_cookie |= MSDC_PREPARE_FLAG;
 853	}
 854}
 855
 856static bool msdc_data_prepared(struct mmc_data *data)
 857{
 858	return data->host_cookie & MSDC_PREPARE_FLAG;
 859}
 860
 861static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
 862{
 863	if (data->host_cookie & MSDC_ASYNC_FLAG)
 864		return;
 865
 866	if (data->host_cookie & MSDC_PREPARE_FLAG) {
 867		dma_unmap_sg(host->dev, data->sg, data->sg_len,
 868			     mmc_get_dma_dir(data));
 869		data->host_cookie &= ~MSDC_PREPARE_FLAG;
 870	}
 871}
 872
 873static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
 874{
 875	struct mmc_host *mmc = mmc_from_priv(host);
 876	u64 timeout;
 877	u32 clk_ns, mode = 0;
 878
 879	if (mmc->actual_clock == 0) {
 880		timeout = 0;
 881	} else {
 882		clk_ns = 1000000000U / mmc->actual_clock;
 883		timeout = ns + clk_ns - 1;
 884		do_div(timeout, clk_ns);
 885		timeout += clks;
 886		/* in 1048576 sclk cycle unit */
 887		timeout = DIV_ROUND_UP(timeout, BIT(20));
 888		if (host->dev_comp->clk_div_bits == 8)
 889			sdr_get_field(host->base + MSDC_CFG,
 890				      MSDC_CFG_CKMOD, &mode);
 891		else
 892			sdr_get_field(host->base + MSDC_CFG,
 893				      MSDC_CFG_CKMOD_EXTRA, &mode);
 894		/*DDR mode will double the clk cycles for data timeout */
 895		timeout = mode >= 2 ? timeout * 2 : timeout;
 896		timeout = timeout > 1 ? timeout - 1 : 0;
 897	}
 898	return timeout;
 899}
 900
 901/* clock control primitives */
 902static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
 903{
 904	u64 timeout;
 905
 906	host->timeout_ns = ns;
 907	host->timeout_clks = clks;
 908
 909	timeout = msdc_timeout_cal(host, ns, clks);
 910	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
 911		      min_t(u32, timeout, 255));
 912}
 913
 914static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
 915{
 916	u64 timeout;
 917
 918	timeout = msdc_timeout_cal(host, ns, clks);
 919	sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
 920		      min_t(u32, timeout, 8191));
 921}
 922
 923static void msdc_gate_clock(struct msdc_host *host)
 924{
 925	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
 926	clk_disable_unprepare(host->crypto_clk);
 927	clk_disable_unprepare(host->src_clk_cg);
 928	clk_disable_unprepare(host->src_clk);
 929	clk_disable_unprepare(host->bus_clk);
 930	clk_disable_unprepare(host->h_clk);
 931}
 932
 933static int msdc_ungate_clock(struct msdc_host *host)
 934{
 935	u32 val;
 936	int ret;
 937
 938	clk_prepare_enable(host->h_clk);
 939	clk_prepare_enable(host->bus_clk);
 940	clk_prepare_enable(host->src_clk);
 941	clk_prepare_enable(host->src_clk_cg);
 942	clk_prepare_enable(host->crypto_clk);
 943	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
 944	if (ret) {
 945		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
 946		return ret;
 947	}
 948
 949	return readl_poll_timeout(host->base + MSDC_CFG, val,
 950				  (val & MSDC_CFG_CKSTB), 1, 20000);
 951}
 952
 953static void msdc_new_tx_setting(struct msdc_host *host)
 954{
 955	u32 val;
 956
 957	if (!host->top_base)
 958		return;
 959
 960	val = readl(host->top_base + LOOP_TEST_CONTROL);
 961	val |= TEST_LOOP_DSCLK_MUX_SEL;
 962	val |= TEST_LOOP_LATCH_MUX_SEL;
 963	val &= ~TEST_HS400_CMD_LOOP_MUX_SEL;
 964
 965	switch (host->timing) {
 966	case MMC_TIMING_LEGACY:
 967	case MMC_TIMING_MMC_HS:
 968	case MMC_TIMING_SD_HS:
 969	case MMC_TIMING_UHS_SDR12:
 970	case MMC_TIMING_UHS_SDR25:
 971	case MMC_TIMING_UHS_DDR50:
 972	case MMC_TIMING_MMC_DDR52:
 973		val &= ~LOOP_EN_SEL_CLK;
 974		break;
 975	case MMC_TIMING_UHS_SDR50:
 976	case MMC_TIMING_UHS_SDR104:
 977	case MMC_TIMING_MMC_HS200:
 978	case MMC_TIMING_MMC_HS400:
 979		val |= LOOP_EN_SEL_CLK;
 980		break;
 981	default:
 982		break;
 983	}
 984	writel(val, host->top_base + LOOP_TEST_CONTROL);
 985}
 986
 987static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
 988{
 989	struct mmc_host *mmc = mmc_from_priv(host);
 990	u32 mode;
 991	u32 flags;
 992	u32 div;
 993	u32 sclk;
 994	u32 tune_reg = host->dev_comp->pad_tune_reg;
 995	u32 val;
 996	bool timing_changed;
 997
 998	if (!hz) {
 999		dev_dbg(host->dev, "set mclk to 0\n");
1000		host->mclk = 0;
1001		mmc->actual_clock = 0;
1002		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1003		return;
1004	}
1005
1006	if (host->timing != timing)
1007		timing_changed = true;
1008	else
1009		timing_changed = false;
1010
1011	flags = readl(host->base + MSDC_INTEN);
1012	sdr_clr_bits(host->base + MSDC_INTEN, flags);
1013	if (host->dev_comp->clk_div_bits == 8)
1014		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
1015	else
1016		sdr_clr_bits(host->base + MSDC_CFG,
1017			     MSDC_CFG_HS400_CK_MODE_EXTRA);
1018	if (timing == MMC_TIMING_UHS_DDR50 ||
1019	    timing == MMC_TIMING_MMC_DDR52 ||
1020	    timing == MMC_TIMING_MMC_HS400) {
1021		if (timing == MMC_TIMING_MMC_HS400)
1022			mode = 0x3;
1023		else
1024			mode = 0x2; /* ddr mode and use divisor */
1025
1026		if (hz >= (host->src_clk_freq >> 2)) {
1027			div = 0; /* mean div = 1/4 */
1028			sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
1029		} else {
1030			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1031			sclk = (host->src_clk_freq >> 2) / div;
1032			div = (div >> 1);
1033		}
1034
1035		if (timing == MMC_TIMING_MMC_HS400 &&
1036		    hz >= (host->src_clk_freq >> 1)) {
1037			if (host->dev_comp->clk_div_bits == 8)
1038				sdr_set_bits(host->base + MSDC_CFG,
1039					     MSDC_CFG_HS400_CK_MODE);
1040			else
1041				sdr_set_bits(host->base + MSDC_CFG,
1042					     MSDC_CFG_HS400_CK_MODE_EXTRA);
1043			sclk = host->src_clk_freq >> 1;
1044			div = 0; /* div is ignore when bit18 is set */
1045		}
1046	} else if (hz >= host->src_clk_freq) {
1047		mode = 0x1; /* no divisor */
1048		div = 0;
1049		sclk = host->src_clk_freq;
1050	} else {
1051		mode = 0x0; /* use divisor */
1052		if (hz >= (host->src_clk_freq >> 1)) {
1053			div = 0; /* mean div = 1/2 */
1054			sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
1055		} else {
1056			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1057			sclk = (host->src_clk_freq >> 2) / div;
1058		}
1059	}
1060	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1061
1062	clk_disable_unprepare(host->src_clk_cg);
1063	if (host->dev_comp->clk_div_bits == 8)
1064		sdr_set_field(host->base + MSDC_CFG,
1065			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
1066			      (mode << 8) | div);
1067	else
1068		sdr_set_field(host->base + MSDC_CFG,
1069			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
1070			      (mode << 12) | div);
1071
1072	clk_prepare_enable(host->src_clk_cg);
1073	readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
1074	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1075	mmc->actual_clock = sclk;
1076	host->mclk = hz;
1077	host->timing = timing;
1078	/* need because clk changed. */
1079	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
1080	sdr_set_bits(host->base + MSDC_INTEN, flags);
1081
1082	/*
1083	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
1084	 * tune result of hs200/200Mhz is not suitable for 50Mhz
1085	 */
1086	if (mmc->actual_clock <= 52000000) {
1087		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
1088		if (host->top_base) {
1089			writel(host->def_tune_para.emmc_top_control,
1090			       host->top_base + EMMC_TOP_CONTROL);
1091			writel(host->def_tune_para.emmc_top_cmd,
1092			       host->top_base + EMMC_TOP_CMD);
1093		} else {
1094			writel(host->def_tune_para.pad_tune,
1095			       host->base + tune_reg);
1096		}
1097	} else {
1098		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
1099		writel(host->saved_tune_para.pad_cmd_tune,
1100		       host->base + PAD_CMD_TUNE);
1101		if (host->top_base) {
1102			writel(host->saved_tune_para.emmc_top_control,
1103			       host->top_base + EMMC_TOP_CONTROL);
1104			writel(host->saved_tune_para.emmc_top_cmd,
1105			       host->top_base + EMMC_TOP_CMD);
1106		} else {
1107			writel(host->saved_tune_para.pad_tune,
1108			       host->base + tune_reg);
1109		}
1110	}
1111
1112	if (timing == MMC_TIMING_MMC_HS400 &&
1113	    host->dev_comp->hs400_tune)
1114		sdr_set_field(host->base + tune_reg,
1115			      MSDC_PAD_TUNE_CMDRRDLY,
1116			      host->hs400_cmd_int_delay);
1117	if (host->dev_comp->support_new_tx && timing_changed)
1118		msdc_new_tx_setting(host);
1119
1120	dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1121		timing);
1122}
1123
1124static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1125		struct mmc_command *cmd)
1126{
1127	u32 resp;
1128
1129	switch (mmc_resp_type(cmd)) {
1130	/* Actually, R1, R5, R6, R7 are the same */
1131	case MMC_RSP_R1:
1132		resp = 0x1;
1133		break;
1134	case MMC_RSP_R1B:
1135	case MMC_RSP_R1B_NO_CRC:
1136		resp = 0x7;
1137		break;
1138	case MMC_RSP_R2:
1139		resp = 0x2;
1140		break;
1141	case MMC_RSP_R3:
1142		resp = 0x3;
1143		break;
1144	case MMC_RSP_NONE:
1145	default:
1146		resp = 0x0;
1147		break;
1148	}
1149
1150	return resp;
1151}
1152
1153static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1154		struct mmc_request *mrq, struct mmc_command *cmd)
1155{
1156	struct mmc_host *mmc = mmc_from_priv(host);
1157	/* rawcmd :
1158	 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1159	 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1160	 */
1161	u32 opcode = cmd->opcode;
1162	u32 resp = msdc_cmd_find_resp(host, cmd);
1163	u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1164
1165	host->cmd_rsp = resp;
1166
1167	if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1168	    opcode == MMC_STOP_TRANSMISSION)
1169		rawcmd |= BIT(14);
1170	else if (opcode == SD_SWITCH_VOLTAGE)
1171		rawcmd |= BIT(30);
1172	else if (opcode == SD_APP_SEND_SCR ||
1173		 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1174		 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1175		 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1176		 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1177		rawcmd |= BIT(11);
1178
1179	if (cmd->data) {
1180		struct mmc_data *data = cmd->data;
1181
1182		if (mmc_op_multi(opcode)) {
1183			if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1184			    !(mrq->sbc->arg & 0xFFFF0000))
1185				rawcmd |= BIT(29); /* AutoCMD23 */
1186		}
1187
1188		rawcmd |= ((data->blksz & 0xFFF) << 16);
1189		if (data->flags & MMC_DATA_WRITE)
1190			rawcmd |= BIT(13);
1191		if (data->blocks > 1)
1192			rawcmd |= BIT(12);
1193		else
1194			rawcmd |= BIT(11);
1195		/* Always use dma mode */
1196		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1197
1198		if (host->timeout_ns != data->timeout_ns ||
1199		    host->timeout_clks != data->timeout_clks)
1200			msdc_set_timeout(host, data->timeout_ns,
1201					data->timeout_clks);
1202
1203		writel(data->blocks, host->base + SDC_BLK_NUM);
1204	}
1205	return rawcmd;
1206}
1207
1208static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1209		struct mmc_data *data)
1210{
1211	bool read;
1212
1213	WARN_ON(host->data);
1214	host->data = data;
1215	read = data->flags & MMC_DATA_READ;
1216
1217	mod_delayed_work(system_percpu_wq, &host->req_timeout, DAT_TIMEOUT);
1218	msdc_dma_setup(host, &host->dma, data);
1219	sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1220	sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1221	dev_dbg(host->dev, "DMA start\n");
1222	dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1223			__func__, cmd->opcode, data->blocks, read);
1224}
1225
1226static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1227		struct mmc_command *cmd)
1228{
1229	u32 *rsp = cmd->resp;
1230
1231	rsp[0] = readl(host->base + SDC_ACMD_RESP);
1232
1233	if (events & MSDC_INT_ACMDRDY) {
1234		cmd->error = 0;
1235	} else {
1236		msdc_reset_hw(host);
1237		if (events & MSDC_INT_ACMDCRCERR) {
1238			cmd->error = -EILSEQ;
1239			host->error |= REQ_STOP_EIO;
1240		} else if (events & MSDC_INT_ACMDTMO) {
1241			cmd->error = -ETIMEDOUT;
1242			host->error |= REQ_STOP_TMO;
1243		}
1244		dev_err(host->dev,
1245			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1246			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1247	}
1248	return cmd->error;
1249}
1250
1251/*
1252 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1253 *
1254 * Host controller may lost interrupt in some special case.
1255 * Add SDIO irq recheck mechanism to make sure all interrupts
1256 * can be processed immediately
1257 */
1258static void msdc_recheck_sdio_irq(struct msdc_host *host)
1259{
1260	struct mmc_host *mmc = mmc_from_priv(host);
1261	u32 reg_int, reg_inten, reg_ps;
1262
1263	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1264		reg_inten = readl(host->base + MSDC_INTEN);
1265		if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1266			reg_int = readl(host->base + MSDC_INT);
1267			reg_ps = readl(host->base + MSDC_PS);
1268			if (!(reg_int & MSDC_INT_SDIOIRQ ||
1269			      reg_ps & MSDC_PS_DATA1)) {
1270				__msdc_enable_sdio_irq(host, 0);
1271				sdio_signal_irq(mmc);
1272			}
1273		}
1274	}
1275}
1276
1277static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1278{
1279	if (host->error &&
1280	    ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1281	     cmd->error == -ETIMEDOUT))
1282		dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1283			 __func__, cmd->opcode, cmd->arg, host->error);
1284}
1285
1286static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1287{
1288	struct mmc_host *mmc = mmc_from_priv(host);
1289	unsigned long flags;
1290	bool hsq_req_done;
1291
1292	/*
1293	 * No need check the return value of cancel_delayed_work, as only ONE
1294	 * path will go here!
1295	 */
1296	cancel_delayed_work(&host->req_timeout);
1297
1298	/*
1299	 * If the request was handled from Host Software Queue, there's almost
1300	 * nothing to do here, and we also don't need to reset mrq as any race
1301	 * condition would not have any room to happen, since HSQ stores the
1302	 * "scheduled" mrqs in an internal array of mrq slots anyway.
1303	 * However, if the controller experienced an error, we still want to
1304	 * reset it as soon as possible.
1305	 *
1306	 * Note that non-HSQ requests will still be happening at times, even
1307	 * though it is enabled, and that's what is going to reset host->mrq.
1308	 * Also, msdc_unprepare_data() is going to be called by HSQ when needed
1309	 * as HSQ request finalization will eventually call the .post_req()
1310	 * callback of this driver which, in turn, unprepares the data.
1311	 */
1312	hsq_req_done = host->hsq_en ? mmc_hsq_finalize_request(mmc, mrq) : false;
1313	if (hsq_req_done) {
1314		if (host->error)
1315			msdc_reset_hw(host);
1316		return;
1317	}
1318
1319	spin_lock_irqsave(&host->lock, flags);
1320	host->mrq = NULL;
1321	spin_unlock_irqrestore(&host->lock, flags);
1322
1323	msdc_track_cmd_data(host, mrq->cmd);
1324	if (mrq->data)
1325		msdc_unprepare_data(host, mrq->data);
1326	if (host->error)
1327		msdc_reset_hw(host);
1328	mmc_request_done(mmc, mrq);
1329	if (host->dev_comp->recheck_sdio_irq)
1330		msdc_recheck_sdio_irq(host);
1331}
1332
1333/* returns true if command is fully handled; returns false otherwise */
1334static bool msdc_cmd_done(struct msdc_host *host, int events,
1335			  struct mmc_request *mrq, struct mmc_command *cmd)
1336{
1337	bool done = false;
1338	bool sbc_error;
1339	unsigned long flags;
1340	u32 *rsp;
1341
1342	if (mrq->sbc && cmd == mrq->cmd &&
1343	    (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1344				   | MSDC_INT_ACMDTMO)))
1345		msdc_auto_cmd_done(host, events, mrq->sbc);
1346
1347	sbc_error = mrq->sbc && mrq->sbc->error;
1348
1349	if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1350					| MSDC_INT_RSPCRCERR
1351					| MSDC_INT_CMDTMO)))
1352		return done;
1353
1354	spin_lock_irqsave(&host->lock, flags);
1355	done = !host->cmd;
1356	host->cmd = NULL;
1357	spin_unlock_irqrestore(&host->lock, flags);
1358
1359	if (done)
1360		return true;
1361	rsp = cmd->resp;
1362
1363	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1364
1365	if (cmd->flags & MMC_RSP_PRESENT) {
1366		if (cmd->flags & MMC_RSP_136) {
1367			rsp[0] = readl(host->base + SDC_RESP3);
1368			rsp[1] = readl(host->base + SDC_RESP2);
1369			rsp[2] = readl(host->base + SDC_RESP1);
1370			rsp[3] = readl(host->base + SDC_RESP0);
1371		} else {
1372			rsp[0] = readl(host->base + SDC_RESP0);
1373		}
1374	}
1375
1376	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1377		if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1378		    (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1379			/*
1380			 * should not clear fifo/interrupt as the tune data
1381			 * may have already come when cmd19/cmd21 gets response
1382			 * CRC error.
1383			 */
1384			msdc_reset_hw(host);
1385		if (events & MSDC_INT_RSPCRCERR &&
1386		    mmc_resp_type(cmd) != MMC_RSP_R1B_NO_CRC) {
1387			cmd->error = -EILSEQ;
1388			host->error |= REQ_CMD_EIO;
1389		} else if (events & MSDC_INT_CMDTMO) {
1390			cmd->error = -ETIMEDOUT;
1391			host->error |= REQ_CMD_TMO;
1392		}
1393	}
1394	if (cmd->error)
1395		dev_dbg(host->dev,
1396				"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1397				__func__, cmd->opcode, cmd->arg, rsp[0],
1398				cmd->error);
1399
1400	msdc_cmd_next(host, mrq, cmd);
1401	return true;
1402}
1403
1404/* It is the core layer's responsibility to ensure card status
1405 * is correct before issue a request. but host design do below
1406 * checks recommended.
1407 */
1408static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1409		struct mmc_request *mrq, struct mmc_command *cmd)
1410{
1411	u32 val;
1412	int ret;
1413
1414	/* The max busy time we can endure is 20ms */
1415	ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1416					!(val & SDC_STS_CMDBUSY), 1, 20000);
1417	if (ret) {
1418		dev_err(host->dev, "CMD bus busy detected\n");
1419		host->error |= REQ_CMD_BUSY;
1420		msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1421		return false;
1422	}
1423
1424	if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1425		/* R1B or with data, should check SDCBUSY */
1426		ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1427						!(val & SDC_STS_SDCBUSY), 1, 20000);
1428		if (ret) {
1429			dev_err(host->dev, "Controller busy detected\n");
1430			host->error |= REQ_CMD_BUSY;
1431			msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1432			return false;
1433		}
1434	}
1435	return true;
1436}
1437
1438static void msdc_start_command(struct msdc_host *host,
1439		struct mmc_request *mrq, struct mmc_command *cmd)
1440{
1441	u32 rawcmd;
1442	unsigned long flags;
1443
1444	WARN_ON(host->cmd);
1445	host->cmd = cmd;
1446
1447	mod_delayed_work(system_percpu_wq, &host->req_timeout, DAT_TIMEOUT);
1448	if (!msdc_cmd_is_ready(host, mrq, cmd))
1449		return;
1450
1451	if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1452	    readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1453		dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1454		msdc_reset_hw(host);
1455	}
1456
1457	cmd->error = 0;
1458	rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1459
1460	spin_lock_irqsave(&host->lock, flags);
1461	sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1462	spin_unlock_irqrestore(&host->lock, flags);
1463
1464	writel(cmd->arg, host->base + SDC_ARG);
1465	writel(rawcmd, host->base + SDC_CMD);
1466}
1467
1468static void msdc_cmd_next(struct msdc_host *host,
1469		struct mmc_request *mrq, struct mmc_command *cmd)
1470{
1471	if ((cmd->error && !host->hs400_tuning &&
1472	     !(cmd->error == -EILSEQ &&
1473	     mmc_op_tuning(cmd->opcode))) ||
1474	    (mrq->sbc && mrq->sbc->error))
1475		msdc_request_done(host, mrq);
1476	else if (cmd == mrq->sbc)
1477		msdc_start_command(host, mrq, mrq->cmd);
1478	else if (!cmd->data)
1479		msdc_request_done(host, mrq);
1480	else
1481		msdc_start_data(host, cmd, cmd->data);
1482}
1483
1484static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1485{
1486	struct msdc_host *host = mmc_priv(mmc);
1487
1488	host->error = 0;
1489	WARN_ON(!host->hsq_en && host->mrq);
1490	host->mrq = mrq;
1491
1492	if (mrq->data) {
1493		msdc_prepare_data(host, mrq->data);
1494		if (!msdc_data_prepared(mrq->data)) {
1495			host->mrq = NULL;
1496			/*
1497			 * Failed to prepare DMA area, fail fast before
1498			 * starting any commands.
1499			 */
1500			mrq->cmd->error = -ENOSPC;
1501			mmc_request_done(mmc_from_priv(host), mrq);
1502			return;
1503		}
1504	}
1505
1506	/* if SBC is required, we have HW option and SW option.
1507	 * if HW option is enabled, and SBC does not have "special" flags,
1508	 * use HW option,  otherwise use SW option
1509	 */
1510	if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1511	    (mrq->sbc->arg & 0xFFFF0000)))
1512		msdc_start_command(host, mrq, mrq->sbc);
1513	else
1514		msdc_start_command(host, mrq, mrq->cmd);
1515}
1516
1517static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1518{
1519	struct msdc_host *host = mmc_priv(mmc);
1520	struct mmc_data *data = mrq->data;
1521
1522	if (!data)
1523		return;
1524
1525	msdc_prepare_data(host, data);
1526	data->host_cookie |= MSDC_ASYNC_FLAG;
1527}
1528
1529static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1530		int err)
1531{
1532	struct msdc_host *host = mmc_priv(mmc);
1533	struct mmc_data *data = mrq->data;
1534
1535	if (!data)
1536		return;
1537
1538	if (data->host_cookie) {
1539		data->host_cookie &= ~MSDC_ASYNC_FLAG;
1540		msdc_unprepare_data(host, data);
1541	}
1542}
1543
1544static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1545{
1546	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1547	    !mrq->sbc)
1548		msdc_start_command(host, mrq, mrq->stop);
1549	else
1550		msdc_request_done(host, mrq);
1551}
1552
1553static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1554				struct mmc_request *mrq, struct mmc_data *data)
1555{
1556	struct mmc_command *stop;
1557	unsigned long flags;
1558	bool done;
1559	unsigned int check_data = events &
1560	    (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1561	     | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1562	     | MSDC_INT_DMA_PROTECT);
1563	u32 val;
1564	int ret;
1565
1566	spin_lock_irqsave(&host->lock, flags);
1567	done = !host->data;
1568	if (check_data)
1569		host->data = NULL;
1570	spin_unlock_irqrestore(&host->lock, flags);
1571
1572	if (done)
1573		return;
1574	stop = data->stop;
1575
1576	if (check_data || (stop && stop->error)) {
1577		dev_dbg(host->dev, "DMA status: 0x%8X\n",
1578				readl(host->base + MSDC_DMA_CFG));
1579		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1580				1);
1581
1582		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1583						!(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1584		if (ret)
1585			dev_dbg(host->dev, "DMA stop timed out\n");
1586
1587		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1588						!(val & MSDC_DMA_CFG_STS), 1, 20000);
1589		if (ret)
1590			dev_dbg(host->dev, "DMA inactive timed out\n");
1591
1592		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1593		dev_dbg(host->dev, "DMA stop\n");
1594
1595		if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1596			data->bytes_xfered = data->blocks * data->blksz;
1597		} else {
1598			dev_dbg(host->dev, "interrupt events: %x\n", events);
1599			msdc_reset_hw(host);
1600			host->error |= REQ_DAT_ERR;
1601			data->bytes_xfered = 0;
1602
1603			if (events & MSDC_INT_DATTMO)
1604				data->error = -ETIMEDOUT;
1605			else if (events & MSDC_INT_DATCRCERR)
1606				data->error = -EILSEQ;
1607
1608			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1609				__func__, mrq->cmd->opcode, data->blocks);
1610			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1611				(int)data->error, data->bytes_xfered);
1612		}
1613
1614		msdc_data_xfer_next(host, mrq);
1615	}
1616}
1617
1618static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1619{
1620	u32 val = readl(host->base + SDC_CFG);
1621
1622	val &= ~SDC_CFG_BUSWIDTH;
1623
1624	switch (width) {
1625	default:
1626	case MMC_BUS_WIDTH_1:
1627		val |= (MSDC_BUS_1BITS << 16);
1628		break;
1629	case MMC_BUS_WIDTH_4:
1630		val |= (MSDC_BUS_4BITS << 16);
1631		break;
1632	case MMC_BUS_WIDTH_8:
1633		val |= (MSDC_BUS_8BITS << 16);
1634		break;
1635	}
1636
1637	writel(val, host->base + SDC_CFG);
1638	dev_dbg(host->dev, "Bus Width = %d", width);
1639}
1640
1641static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1642{
1643	struct msdc_host *host = mmc_priv(mmc);
1644	int ret;
1645
1646	if (!IS_ERR(mmc->supply.vqmmc)) {
1647		if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1648		    ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1649			dev_err(host->dev, "Unsupported signal voltage!\n");
1650			return -EINVAL;
1651		}
1652
1653		ret = mmc_regulator_set_vqmmc(mmc, ios);
1654		if (ret < 0) {
1655			dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1656				ret, ios->signal_voltage);
1657			return ret;
1658		}
1659
1660		/* Apply different pinctrl settings for different signal voltage */
1661		if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1662			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1663		else
1664			pinctrl_select_state(host->pinctrl, host->pins_default);
1665	}
1666	return 0;
1667}
1668
1669static int msdc_card_busy(struct mmc_host *mmc)
1670{
1671	struct msdc_host *host = mmc_priv(mmc);
1672	u32 status = readl(host->base + MSDC_PS);
1673
1674	/* only check if data0 is low */
1675	return !(status & BIT(16));
1676}
1677
1678static void msdc_request_timeout(struct work_struct *work)
1679{
1680	struct msdc_host *host = container_of(work, struct msdc_host,
1681			req_timeout.work);
1682
1683	/* simulate HW timeout status */
1684	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1685	if (host->mrq) {
1686		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1687				host->mrq, host->mrq->cmd->opcode);
1688		if (host->cmd) {
1689			dev_err(host->dev, "%s: aborting cmd=%d\n",
1690					__func__, host->cmd->opcode);
1691			msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1692					host->cmd);
1693		} else if (host->data) {
1694			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1695					__func__, host->mrq->cmd->opcode,
1696					host->data->blocks);
1697			msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1698					host->data);
1699		}
1700	}
1701}
1702
1703static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1704{
1705	if (enb) {
1706		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1707		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1708		if (host->dev_comp->recheck_sdio_irq)
1709			msdc_recheck_sdio_irq(host);
1710	} else {
1711		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1712		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1713	}
1714}
1715
1716static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1717{
1718	struct msdc_host *host = mmc_priv(mmc);
1719	unsigned long flags;
1720	int ret;
1721
1722	spin_lock_irqsave(&host->lock, flags);
1723	__msdc_enable_sdio_irq(host, enb);
1724	spin_unlock_irqrestore(&host->lock, flags);
1725
1726	if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1727		if (enb) {
1728			/*
1729			 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1730			 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1731			 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1732			 * affect successfully, we change the pinstate to pins_eint firstly.
1733			 */
1734			pinctrl_select_state(host->pinctrl, host->pins_eint);
1735			ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1736
1737			if (ret) {
1738				dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1739				host->pins_eint = NULL;
1740				pm_runtime_get_noresume(host->dev);
1741			} else {
1742				dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1743			}
1744
1745			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1746		} else {
1747			dev_pm_clear_wake_irq(host->dev);
1748		}
1749	} else {
1750		if (enb) {
1751			/* Ensure host->pins_eint is NULL */
1752			host->pins_eint = NULL;
1753			pm_runtime_get_noresume(host->dev);
1754		} else {
1755			pm_runtime_put_noidle(host->dev);
1756		}
1757	}
1758}
1759
1760static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1761{
1762	struct mmc_host *mmc = mmc_from_priv(host);
1763	int cmd_err = 0, dat_err = 0;
1764
1765	if (intsts & MSDC_INT_RSPCRCERR) {
1766		cmd_err = -EILSEQ;
1767		dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1768	} else if (intsts & MSDC_INT_CMDTMO) {
1769		cmd_err = -ETIMEDOUT;
1770		dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1771	}
1772
1773	if (intsts & MSDC_INT_DATCRCERR) {
1774		dat_err = -EILSEQ;
1775		dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1776	} else if (intsts & MSDC_INT_DATTMO) {
1777		dat_err = -ETIMEDOUT;
1778		dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1779	}
1780
1781	if (cmd_err || dat_err) {
1782		dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1783			cmd_err, dat_err, intsts);
1784	}
1785
1786	return cqhci_irq(mmc, 0, cmd_err, dat_err);
1787}
1788
1789static irqreturn_t msdc_irq(int irq, void *dev_id)
1790{
1791	struct msdc_host *host = (struct msdc_host *) dev_id;
1792	struct mmc_host *mmc = mmc_from_priv(host);
1793
1794	while (true) {
1795		struct mmc_request *mrq;
1796		struct mmc_command *cmd;
1797		struct mmc_data *data;
1798		u32 events, event_mask;
1799
1800		spin_lock(&host->lock);
1801		events = readl(host->base + MSDC_INT);
1802		event_mask = readl(host->base + MSDC_INTEN);
1803		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1804			__msdc_enable_sdio_irq(host, 0);
1805		/* clear interrupts */
1806		writel(events & event_mask, host->base + MSDC_INT);
1807
1808		mrq = host->mrq;
1809		cmd = host->cmd;
1810		data = host->data;
1811		spin_unlock(&host->lock);
1812
1813		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1814			sdio_signal_irq(mmc);
1815
1816		if ((events & event_mask) & MSDC_INT_CDSC) {
1817			if (host->internal_cd)
1818				mmc_detect_change(mmc, msecs_to_jiffies(20));
1819			events &= ~MSDC_INT_CDSC;
1820		}
1821
1822		if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1823			break;
1824
1825		if ((mmc->caps2 & MMC_CAP2_CQE) &&
1826		    (events & MSDC_INT_CMDQ)) {
1827			msdc_cmdq_irq(host, events);
1828			/* clear interrupts */
1829			writel(events, host->base + MSDC_INT);
1830			return IRQ_HANDLED;
1831		}
1832
1833		if (!mrq) {
1834			dev_err(host->dev,
1835				"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1836				__func__, events, event_mask);
1837			WARN_ON(1);
1838			break;
1839		}
1840
1841		dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1842
1843		if (cmd)
1844			msdc_cmd_done(host, events, mrq, cmd);
1845		else if (data)
1846			msdc_data_xfer_done(host, events, mrq, data);
1847	}
1848
1849	return IRQ_HANDLED;
1850}
1851
1852static void msdc_init_hw(struct msdc_host *host)
1853{
1854	u32 val, pb1_val, pb2_val;
1855	u32 tune_reg = host->dev_comp->pad_tune_reg;
1856	struct mmc_host *mmc = mmc_from_priv(host);
1857
1858	if (host->reset) {
1859		reset_control_assert(host->reset);
1860		usleep_range(10, 50);
1861		reset_control_deassert(host->reset);
1862	}
1863
1864	/* New tx/rx enable bit need to be 0->1 for hardware check */
1865	if (host->dev_comp->support_new_tx) {
1866		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1867		sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1868		msdc_new_tx_setting(host);
1869	}
1870	if (host->dev_comp->support_new_rx) {
1871		sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1872		sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1873	}
1874
1875	/* Configure to MMC/SD mode, clock free running */
1876	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1877
1878	/* Reset */
1879	msdc_reset_hw(host);
1880
1881	/* Disable and clear all interrupts */
1882	writel(0, host->base + MSDC_INTEN);
1883	val = readl(host->base + MSDC_INT);
1884	writel(val, host->base + MSDC_INT);
1885
1886	/* Configure card detection */
1887	if (host->internal_cd) {
1888		sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1889			      DEFAULT_DEBOUNCE);
1890		sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1891		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1892		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1893	} else {
1894		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1895		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1896		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1897	}
1898
1899	if (host->top_base) {
1900		writel(0, host->top_base + EMMC_TOP_CONTROL);
1901		writel(0, host->top_base + EMMC_TOP_CMD);
1902	} else {
1903		writel(0, host->base + tune_reg);
1904	}
1905	writel(0, host->base + MSDC_IOCON);
1906	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1907
1908	/*
1909	 * Patch bit 0 and 1 are completely rewritten, but for patch bit 2
1910	 * defaults are retained and, if necessary, only some bits are fixed
1911	 * up: read the PB2 register here for later usage in this function.
1912	 */
1913	pb2_val = readl(host->base + MSDC_PATCH_BIT2);
1914
1915	/* Enable odd number support for 8-bit data bus */
1916	val = MSDC_PATCH_BIT_ODDSUPP;
1917
1918	/* Disable SD command register write monitor */
1919	val |= MSDC_PATCH_BIT_DIS_WRMON;
1920
1921	/* Issue transfer done interrupt after GPD update */
1922	val |= MSDC_PATCH_BIT_DESCUP_SEL;
1923
1924	/* Extend R1B busy detection delay (in clock cycles) */
1925	val |= FIELD_PREP(MSDC_PATCH_BIT_BUSYDLY, 15);
1926
1927	/* Enable CRC phase timeout during data write operation */
1928	val |= MSDC_PATCH_BIT_DECRCTMO;
1929
1930	/* Set CKGEN delay to one stage */
1931	val |= FIELD_PREP(MSDC_CKGEN_MSDC_DLY_SEL, 1);
1932
1933	/* First MSDC_PATCH_BIT setup is done: pull the trigger! */
1934	writel(val, host->base + MSDC_PATCH_BIT);
1935
1936	/* Set wr data, crc status, cmd response turnaround period for UHS104 */
1937	pb1_val = FIELD_PREP(MSDC_PB1_WRDAT_CRC_TACNTR, 1);
1938	pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_CMDTA, 1);
1939	pb1_val |= MSDC_PB1_DDR_CMD_FIX_SEL;
1940
1941	/* Support 'single' burst type only when AXI_LEN is 0 */
1942	sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val);
1943	if (!val)
1944		pb1_val |= MSDC_PB1_SINGLE_BURST;
1945
1946	/* Set auto sync state clear, block gap stop clk */
1947	pb1_val |= MSDC_PB1_RSVD20 | MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
1948
1949	/* Set low power DCM, use HCLK for GDMA, use MSDC CLK for everything else */
1950	pb1_val |= MSDC_PB1_LP_DCM_EN | MSDC_PB1_RSVD3 |
1951		   MSDC_PB1_AHB_GDMA_HCLK | MSDC_PB1_MSDC_CLK_ENFEAT;
1952
1953	/* If needed, enable R1b command busy check at controller init time */
1954	if (!host->dev_comp->busy_check)
1955		pb1_val |= MSDC_PB1_BUSY_CHECK_SEL;
1956
1957	if (host->dev_comp->stop_clk_fix) {
1958		if (host->dev_comp->stop_dly_sel)
1959			pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_STOP_DLY,
1960					      host->dev_comp->stop_dly_sel);
1961
1962		if (host->dev_comp->pop_en_cnt) {
1963			pb2_val &= ~MSDC_PB2_POP_EN_CNT;
1964			pb2_val |= FIELD_PREP(MSDC_PB2_POP_EN_CNT,
1965					      host->dev_comp->pop_en_cnt);
1966		}
1967
1968		sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_WRVALIDSEL);
1969		sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_RDVALIDSEL);
1970	}
1971
1972	if (host->dev_comp->async_fifo) {
1973		/* Set CMD response timeout multiplier to 65 + (16 * 3) cycles */
1974		pb2_val &= ~MSDC_PB2_RESPWAIT;
1975		pb2_val |= FIELD_PREP(MSDC_PB2_RESPWAIT, 3);
1976
1977		/* eMMC4.5: Select async FIFO path for CMD resp and CRC status */
1978		pb2_val &= ~MSDC_PATCH_BIT2_CFGRESP;
1979		pb2_val |= MSDC_PATCH_BIT2_CFGCRCSTS;
1980
1981		if (!host->dev_comp->enhance_rx) {
1982			/* eMMC4.5: Delay 2T for CMD resp and CRC status EN signals */
1983			pb2_val &= ~(MSDC_PB2_RESPSTSENSEL | MSDC_PB2_CRCSTSENSEL);
1984			pb2_val |= FIELD_PREP(MSDC_PB2_RESPSTSENSEL, 2);
1985			pb2_val |= FIELD_PREP(MSDC_PB2_CRCSTSENSEL, 2);
1986		} else if (host->top_base) {
1987			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, SDC_RX_ENH_EN);
1988		} else {
1989			sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_RX_ENHANCE_EN);
1990		}
1991	}
1992
1993	if (host->dev_comp->support_64g)
1994		pb2_val |= MSDC_PB2_SUPPORT_64G;
1995
1996	/* Patch Bit 1/2 setup is done: pull the trigger! */
1997	writel(pb1_val, host->base + MSDC_PATCH_BIT1);
1998	writel(pb2_val, host->base + MSDC_PATCH_BIT2);
1999	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
2000
2001	if (host->dev_comp->data_tune) {
2002		if (host->top_base) {
2003			u32 top_ctl_val = readl(host->top_base + EMMC_TOP_CONTROL);
2004			u32 top_cmd_val = readl(host->top_base + EMMC_TOP_CMD);
2005
2006			top_cmd_val |= PAD_CMD_RD_RXDLY_SEL;
2007			top_ctl_val |= PAD_DAT_RD_RXDLY_SEL;
2008			top_ctl_val &= ~DATA_K_VALUE_SEL;
2009			if (host->tuning_step > PAD_DELAY_HALF) {
2010				top_cmd_val |= PAD_CMD_RD_RXDLY2_SEL;
2011				top_ctl_val |= PAD_DAT_RD_RXDLY2_SEL;
2012			}
2013
2014			writel(top_ctl_val, host->top_base + EMMC_TOP_CONTROL);
2015			writel(top_cmd_val, host->top_base + EMMC_TOP_CMD);
2016		} else {
2017			sdr_set_bits(host->base + tune_reg,
2018				     MSDC_PAD_TUNE_RD_SEL |
2019				     MSDC_PAD_TUNE_CMD_SEL);
2020			if (host->tuning_step > PAD_DELAY_HALF)
2021				sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2022					     MSDC_PAD_TUNE_RD2_SEL |
2023					     MSDC_PAD_TUNE_CMD2_SEL);
2024		}
2025	} else {
2026		/* choose clock tune */
2027		if (host->top_base)
2028			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
2029				     PAD_RXDLY_SEL);
2030		else
2031			sdr_set_bits(host->base + tune_reg,
2032				     MSDC_PAD_TUNE_RXDLYSEL);
2033	}
2034
2035	if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
2036		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
2037		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
2038		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
2039	} else {
2040		/* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
2041		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
2042
2043		/* Config SDIO device detect interrupt function */
2044		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
2045		sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
2046	}
2047
2048	/* Configure to default data timeout */
2049	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
2050
2051	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
2052	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2053	if (host->top_base) {
2054		host->def_tune_para.emmc_top_control =
2055			readl(host->top_base + EMMC_TOP_CONTROL);
2056		host->def_tune_para.emmc_top_cmd =
2057			readl(host->top_base + EMMC_TOP_CMD);
2058		host->saved_tune_para.emmc_top_control =
2059			readl(host->top_base + EMMC_TOP_CONTROL);
2060		host->saved_tune_para.emmc_top_cmd =
2061			readl(host->top_base + EMMC_TOP_CMD);
2062	} else {
2063		host->def_tune_para.pad_tune = readl(host->base + tune_reg);
2064		host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2065	}
2066	dev_dbg(host->dev, "init hardware done!");
2067}
2068
2069static void msdc_deinit_hw(struct msdc_host *host)
2070{
2071	u32 val;
2072
2073	if (host->internal_cd) {
2074		/* Disabled card-detect */
2075		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
2076		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
2077	}
2078
2079	/* Disable and clear all interrupts */
2080	writel(0, host->base + MSDC_INTEN);
2081
2082	val = readl(host->base + MSDC_INT);
2083	writel(val, host->base + MSDC_INT);
2084}
2085
2086/* init gpd and bd list in msdc_drv_probe */
2087static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2088{
2089	struct mt_gpdma_desc *gpd = dma->gpd;
2090	struct mt_bdma_desc *bd = dma->bd;
2091	dma_addr_t dma_addr;
2092	int i;
2093
2094	memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
2095
2096	dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
2097	gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
2098	/* gpd->next is must set for desc DMA
2099	 * That's why must alloc 2 gpd structure.
2100	 */
2101	gpd->next = lower_32_bits(dma_addr);
2102	if (host->dev_comp->support_64g)
2103		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2104
2105	dma_addr = dma->bd_addr;
2106	gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
2107	if (host->dev_comp->support_64g)
2108		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
2109
2110	memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
2111	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
2112		dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
2113		bd[i].next = lower_32_bits(dma_addr);
2114		if (host->dev_comp->support_64g)
2115			bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2116	}
2117}
2118
2119static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2120{
2121	struct msdc_host *host = mmc_priv(mmc);
2122	int ret;
2123
2124	msdc_set_buswidth(host, ios->bus_width);
2125
2126	/* Suspend/Resume will do power off/on */
2127	switch (ios->power_mode) {
2128	case MMC_POWER_UP:
2129		if (!IS_ERR(mmc->supply.vmmc)) {
2130			msdc_init_hw(host);
2131			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
2132					ios->vdd);
2133			if (ret) {
2134				dev_err(host->dev, "Failed to set vmmc power!\n");
2135				return;
2136			}
2137		}
2138		break;
2139	case MMC_POWER_ON:
2140		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
2141			ret = regulator_enable(mmc->supply.vqmmc);
2142			if (ret)
2143				dev_err(host->dev, "Failed to set vqmmc power!\n");
2144			else
2145				host->vqmmc_enabled = true;
2146		}
2147		break;
2148	case MMC_POWER_OFF:
2149		if (!IS_ERR(mmc->supply.vmmc))
2150			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2151
2152		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
2153			regulator_disable(mmc->supply.vqmmc);
2154			host->vqmmc_enabled = false;
2155		}
2156		break;
2157	default:
2158		break;
2159	}
2160
2161	if (host->mclk != ios->clock || host->timing != ios->timing)
2162		msdc_set_mclk(host, ios->timing, ios->clock);
2163}
2164
2165static u64 test_delay_bit(u64 delay, u32 bit)
2166{
2167	bit %= PAD_DELAY_FULL;
2168	return delay & BIT_ULL(bit);
2169}
2170
2171static int get_delay_len(u64 delay, u32 start_bit)
2172{
2173	int i;
2174
2175	for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
2176		if (test_delay_bit(delay, start_bit + i) == 0)
2177			return i;
2178	}
2179	return PAD_DELAY_FULL - start_bit;
2180}
2181
2182static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
2183{
2184	int start = 0, len = 0;
2185	int start_final = 0, len_final = 0;
2186	u8 final_phase = 0xff;
2187	struct msdc_delay_phase delay_phase = { 0, };
2188
2189	if (delay == 0) {
2190		dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
2191		delay_phase.final_phase = final_phase;
2192		return delay_phase;
2193	}
2194
2195	while (start < PAD_DELAY_FULL) {
2196		len = get_delay_len(delay, start);
2197		if (len_final < len) {
2198			start_final = start;
2199			len_final = len;
2200		}
2201		start += len ? len : 1;
2202		if (!upper_32_bits(delay) && len >= 12 && start_final < 4)
2203			break;
2204	}
2205
2206	/* The rule is that to find the smallest delay cell */
2207	if (start_final == 0)
2208		final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;
2209	else
2210		final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;
2211	dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
2212		delay, len_final, final_phase);
2213
2214	delay_phase.maxlen = len_final;
2215	delay_phase.start = start_final;
2216	delay_phase.final_phase = final_phase;
2217	return delay_phase;
2218}
2219
2220static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2221{
2222	u32 tune_reg = host->dev_comp->pad_tune_reg;
2223
2224	if (host->top_base) {
2225		u32 regval = readl(host->top_base + EMMC_TOP_CMD);
2226
2227		regval &= ~(PAD_CMD_RXDLY | PAD_CMD_RXDLY2);
2228
2229		if (value < PAD_DELAY_HALF) {
2230			regval |= FIELD_PREP(PAD_CMD_RXDLY, value);
2231		} else {
2232			regval |= FIELD_PREP(PAD_CMD_RXDLY, PAD_DELAY_HALF - 1);
2233			regval |= FIELD_PREP(PAD_CMD_RXDLY2, value - PAD_DELAY_HALF);
2234		}
2235		writel(regval, host->top_base + EMMC_TOP_CMD);
2236	} else {
2237		if (value < PAD_DELAY_HALF) {
2238			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2239			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2240				      MSDC_PAD_TUNE_CMDRDLY2, 0);
2241		} else {
2242			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2243				      PAD_DELAY_HALF - 1);
2244			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2245				      MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);
2246		}
2247	}
2248}
2249
2250static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2251{
2252	u32 tune_reg = host->dev_comp->pad_tune_reg;
2253
2254	if (host->top_base) {
2255		u32 regval = readl(host->top_base + EMMC_TOP_CONTROL);
2256
2257		regval &= ~(PAD_DAT_RD_RXDLY | PAD_DAT_RD_RXDLY2);
2258
2259		if (value < PAD_DELAY_HALF) {
2260			regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, value);
2261			regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value);
2262		} else {
2263			regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);
2264			regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);
2265		}
2266		writel(regval, host->top_base + EMMC_TOP_CONTROL);
2267	} else {
2268		if (value < PAD_DELAY_HALF) {
2269			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2270			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2271				      MSDC_PAD_TUNE_DATRRDLY2, 0);
2272		} else {
2273			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2274				      PAD_DELAY_HALF - 1);
2275			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2276				      MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);
2277		}
2278	}
2279}
2280
2281static inline void msdc_set_data_sample_edge(struct msdc_host *host, bool rising)
2282{
2283	u32 value = rising ? 0 : 1;
2284
2285	if (host->dev_comp->support_new_rx) {
2286		sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value);
2287		sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value);
2288	} else {
2289		sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value);
2290		sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value);
2291	}
2292}
2293
2294static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2295{
2296	struct msdc_host *host = mmc_priv(mmc);
2297	u64 rise_delay = 0, fall_delay = 0;
2298	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2299	struct msdc_delay_phase internal_delay_phase;
2300	u8 final_delay, final_maxlen;
2301	u32 internal_delay = 0;
2302	u32 tune_reg = host->dev_comp->pad_tune_reg;
2303	int cmd_err;
2304	int i, j;
2305
2306	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2307	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2308		sdr_set_field(host->base + tune_reg,
2309			      MSDC_PAD_TUNE_CMDRRDLY,
2310			      host->hs200_cmd_int_delay);
2311
2312	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2313	for (i = 0; i < host->tuning_step; i++) {
2314		msdc_set_cmd_delay(host, i);
2315		/*
2316		 * Using the same parameters, it may sometimes pass the test,
2317		 * but sometimes it may fail. To make sure the parameters are
2318		 * more stable, we test each set of parameters 3 times.
2319		 */
2320		for (j = 0; j < 3; j++) {
2321			mmc_send_tuning(mmc, opcode, &cmd_err);
2322			if (!cmd_err) {
2323				rise_delay |= BIT_ULL(i);
2324			} else {
2325				rise_delay &= ~BIT_ULL(i);
2326				break;
2327			}
2328		}
2329	}
2330	final_rise_delay = get_best_delay(host, rise_delay);
2331	/* if rising edge has enough margin, then do not scan falling edge */
2332	if (final_rise_delay.maxlen >= 12 ||
2333	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2334		goto skip_fall;
2335
2336	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2337	for (i = 0; i < host->tuning_step; i++) {
2338		msdc_set_cmd_delay(host, i);
2339		/*
2340		 * Using the same parameters, it may sometimes pass the test,
2341		 * but sometimes it may fail. To make sure the parameters are
2342		 * more stable, we test each set of parameters 3 times.
2343		 */
2344		for (j = 0; j < 3; j++) {
2345			mmc_send_tuning(mmc, opcode, &cmd_err);
2346			if (!cmd_err) {
2347				fall_delay |= BIT_ULL(i);
2348			} else {
2349				fall_delay &= ~BIT_ULL(i);
2350				break;
2351			}
2352		}
2353	}
2354	final_fall_delay = get_best_delay(host, fall_delay);
2355
2356skip_fall:
2357	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2358	if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2359		final_maxlen = final_fall_delay.maxlen;
2360	if (final_maxlen == final_rise_delay.maxlen) {
2361		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2362		final_delay = final_rise_delay.final_phase;
2363	} else {
2364		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2365		final_delay = final_fall_delay.final_phase;
2366	}
2367	msdc_set_cmd_delay(host, final_delay);
2368
2369	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2370		goto skip_internal;
2371
2372	for (i = 0; i < host->tuning_step; i++) {
2373		sdr_set_field(host->base + tune_reg,
2374			      MSDC_PAD_TUNE_CMDRRDLY, i);
2375		mmc_send_tuning(mmc, opcode, &cmd_err);
2376		if (!cmd_err)
2377			internal_delay |= BIT_ULL(i);
2378	}
2379	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2380	internal_delay_phase = get_best_delay(host, internal_delay);
2381	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2382		      internal_delay_phase.final_phase);
2383skip_internal:
2384	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2385	return final_delay == 0xff ? -EIO : 0;
2386}
2387
2388static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2389{
2390	struct msdc_host *host = mmc_priv(mmc);
2391	u32 cmd_delay = 0;
2392	struct msdc_delay_phase final_cmd_delay = { 0,};
2393	u8 final_delay;
2394	int cmd_err;
2395	int i, j;
2396
2397	/* select EMMC50 PAD CMD tune */
2398	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2399	sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2400
2401	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2402	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2403		sdr_set_field(host->base + MSDC_PAD_TUNE,
2404			      MSDC_PAD_TUNE_CMDRRDLY,
2405			      host->hs200_cmd_int_delay);
2406
2407	if (host->hs400_cmd_resp_sel_rising)
2408		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2409	else
2410		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2411
2412	for (i = 0; i < PAD_DELAY_HALF; i++) {
2413		sdr_set_field(host->base + PAD_CMD_TUNE,
2414			      PAD_CMD_TUNE_RX_DLY3, i);
2415		/*
2416		 * Using the same parameters, it may sometimes pass the test,
2417		 * but sometimes it may fail. To make sure the parameters are
2418		 * more stable, we test each set of parameters 3 times.
2419		 */
2420		for (j = 0; j < 3; j++) {
2421			mmc_send_tuning(mmc, opcode, &cmd_err);
2422			if (!cmd_err) {
2423				cmd_delay |= BIT(i);
2424			} else {
2425				cmd_delay &= ~BIT(i);
2426				break;
2427			}
2428		}
2429	}
2430	final_cmd_delay = get_best_delay(host, cmd_delay);
2431	sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2432		      final_cmd_delay.final_phase);
2433	final_delay = final_cmd_delay.final_phase;
2434
2435	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2436	return final_delay == 0xff ? -EIO : 0;
2437}
2438
2439static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2440{
2441	struct msdc_host *host = mmc_priv(mmc);
2442	u64 rise_delay = 0, fall_delay = 0;
2443	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2444	u8 final_delay, final_maxlen;
2445	int i, ret;
2446
2447	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2448		      host->latch_ck);
2449	msdc_set_data_sample_edge(host, true);
2450	for (i = 0; i < host->tuning_step; i++) {
2451		msdc_set_data_delay(host, i);
2452		ret = mmc_send_tuning(mmc, opcode, NULL);
2453		if (!ret)
2454			rise_delay |= BIT_ULL(i);
2455	}
2456	final_rise_delay = get_best_delay(host, rise_delay);
2457	/* if rising edge has enough margin, then do not scan falling edge */
2458	if (final_rise_delay.maxlen >= 12 ||
2459	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2460		goto skip_fall;
2461
2462	msdc_set_data_sample_edge(host, false);
2463	for (i = 0; i < host->tuning_step; i++) {
2464		msdc_set_data_delay(host, i);
2465		ret = mmc_send_tuning(mmc, opcode, NULL);
2466		if (!ret)
2467			fall_delay |= BIT_ULL(i);
2468	}
2469	final_fall_delay = get_best_delay(host, fall_delay);
2470
2471skip_fall:
2472	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2473	if (final_maxlen == final_rise_delay.maxlen) {
2474		msdc_set_data_sample_edge(host, true);
2475		final_delay = final_rise_delay.final_phase;
2476	} else {
2477		msdc_set_data_sample_edge(host, false);
2478		final_delay = final_fall_delay.final_phase;
2479	}
2480	msdc_set_data_delay(host, final_delay);
2481
2482	dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2483	return final_delay == 0xff ? -EIO : 0;
2484}
2485
2486/*
2487 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2488 * together, which can save the tuning time.
2489 */
2490static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2491{
2492	struct msdc_host *host = mmc_priv(mmc);
2493	u64 rise_delay = 0, fall_delay = 0;
2494	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2495	u8 final_delay, final_maxlen;
2496	int i, ret;
2497
2498	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2499		      host->latch_ck);
2500
2501	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2502	msdc_set_data_sample_edge(host, true);
2503	for (i = 0; i < host->tuning_step; i++) {
2504		msdc_set_cmd_delay(host, i);
2505		msdc_set_data_delay(host, i);
2506		ret = mmc_send_tuning(mmc, opcode, NULL);
2507		if (!ret)
2508			rise_delay |= BIT_ULL(i);
2509	}
2510	final_rise_delay = get_best_delay(host, rise_delay);
2511	/* if rising edge has enough margin, then do not scan falling edge */
2512	if (final_rise_delay.maxlen >= 12 ||
2513	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2514		goto skip_fall;
2515
2516	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2517	msdc_set_data_sample_edge(host, false);
2518	for (i = 0; i < host->tuning_step; i++) {
2519		msdc_set_cmd_delay(host, i);
2520		msdc_set_data_delay(host, i);
2521		ret = mmc_send_tuning(mmc, opcode, NULL);
2522		if (!ret)
2523			fall_delay |= BIT_ULL(i);
2524	}
2525	final_fall_delay = get_best_delay(host, fall_delay);
2526
2527skip_fall:
2528	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2529	if (final_maxlen == final_rise_delay.maxlen) {
2530		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2531		msdc_set_data_sample_edge(host, true);
2532		final_delay = final_rise_delay.final_phase;
2533	} else {
2534		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2535		msdc_set_data_sample_edge(host, false);
2536		final_delay = final_fall_delay.final_phase;
2537	}
2538
2539	msdc_set_cmd_delay(host, final_delay);
2540	msdc_set_data_delay(host, final_delay);
2541
2542	dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2543	return final_delay == 0xff ? -EIO : 0;
2544}
2545
2546static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2547{
2548	struct msdc_host *host = mmc_priv(mmc);
2549	int ret;
2550	u32 tune_reg = host->dev_comp->pad_tune_reg;
2551
2552	if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2553		ret = msdc_tune_together(mmc, opcode);
2554		if (host->hs400_mode) {
2555			msdc_set_data_sample_edge(host, true);
2556			msdc_set_data_delay(host, 0);
2557		}
2558		goto tune_done;
2559	}
2560	if (host->hs400_mode &&
2561	    host->dev_comp->hs400_tune)
2562		ret = hs400_tune_response(mmc, opcode);
2563	else
2564		ret = msdc_tune_response(mmc, opcode);
2565	if (ret == -EIO) {
2566		dev_err(host->dev, "Tune response fail!\n");
2567		return ret;
2568	}
2569	if (host->hs400_mode == false) {
2570		ret = msdc_tune_data(mmc, opcode);
2571		if (ret == -EIO)
2572			dev_err(host->dev, "Tune data fail!\n");
2573	}
2574
2575tune_done:
2576	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2577	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2578	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2579	if (host->top_base) {
2580		host->saved_tune_para.emmc_top_control = readl(host->top_base +
2581				EMMC_TOP_CONTROL);
2582		host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2583				EMMC_TOP_CMD);
2584	}
2585	return ret;
2586}
2587
2588static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2589{
2590	struct msdc_host *host = mmc_priv(mmc);
2591
2592	host->hs400_mode = true;
2593
2594	if (host->top_base) {
2595		if (host->hs400_ds_dly3)
2596			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2597				      PAD_DS_DLY3, host->hs400_ds_dly3);
2598		if (host->hs400_ds_delay)
2599			writel(host->hs400_ds_delay,
2600			       host->top_base + EMMC50_PAD_DS_TUNE);
2601	} else {
2602		if (host->hs400_ds_dly3)
2603			sdr_set_field(host->base + PAD_DS_TUNE,
2604				      PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2605		if (host->hs400_ds_delay)
2606			writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2607	}
2608	/* hs400 mode must set it to 0 */
2609	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2610	/* to improve read performance, set outstanding to 2 */
2611	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2612
2613	return 0;
2614}
2615
2616static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2617{
2618	struct msdc_host *host = mmc_priv(mmc);
2619	struct msdc_delay_phase dly1_delay;
2620	u32 val, result_dly1 = 0;
2621	u8 *ext_csd;
2622	int i, ret;
2623
2624	if (host->top_base) {
2625		sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2626			     PAD_DS_DLY_SEL);
2627		sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2628			     PAD_DS_DLY2_SEL);
2629	} else {
2630		sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2631		sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL);
2632	}
2633
2634	host->hs400_tuning = true;
2635	for (i = 0; i < PAD_DELAY_HALF; i++) {
2636		if (host->top_base)
2637			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2638				      PAD_DS_DLY1, i);
2639		else
2640			sdr_set_field(host->base + PAD_DS_TUNE,
2641				      PAD_DS_TUNE_DLY1, i);
2642		ret = mmc_get_ext_csd(card, &ext_csd);
2643		if (!ret) {
2644			result_dly1 |= BIT(i);
2645			kfree(ext_csd);
2646		}
2647	}
2648	host->hs400_tuning = false;
2649
2650	dly1_delay = get_best_delay(host, result_dly1);
2651	if (dly1_delay.maxlen == 0) {
2652		dev_err(host->dev, "Failed to get DLY1 delay!\n");
2653		goto fail;
2654	}
2655	if (host->top_base)
2656		sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2657			      PAD_DS_DLY1, dly1_delay.final_phase);
2658	else
2659		sdr_set_field(host->base + PAD_DS_TUNE,
2660			      PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2661
2662	if (host->top_base)
2663		val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2664	else
2665		val = readl(host->base + PAD_DS_TUNE);
2666
2667	dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2668
2669	return 0;
2670
2671fail:
2672	dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2673	return -EIO;
2674}
2675
2676static void msdc_hw_reset(struct mmc_host *mmc)
2677{
2678	struct msdc_host *host = mmc_priv(mmc);
2679
2680	sdr_set_bits(host->base + EMMC_IOCON, 1);
2681	udelay(10); /* 10us is enough */
2682	sdr_clr_bits(host->base + EMMC_IOCON, 1);
2683}
2684
2685static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2686{
2687	unsigned long flags;
2688	struct msdc_host *host = mmc_priv(mmc);
2689
2690	spin_lock_irqsave(&host->lock, flags);
2691	__msdc_enable_sdio_irq(host, 1);
2692	spin_unlock_irqrestore(&host->lock, flags);
2693}
2694
2695static int msdc_get_cd(struct mmc_host *mmc)
2696{
2697	struct msdc_host *host = mmc_priv(mmc);
2698	int val;
2699
2700	if (mmc->caps & MMC_CAP_NONREMOVABLE)
2701		return 1;
2702
2703	if (!host->internal_cd)
2704		return mmc_gpio_get_cd(mmc);
2705
2706	val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2707	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2708		return !!val;
2709	else
2710		return !val;
2711}
2712
2713static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2714				       struct mmc_ios *ios)
2715{
2716	struct msdc_host *host = mmc_priv(mmc);
2717
2718	if (ios->enhanced_strobe) {
2719		msdc_prepare_hs400_tuning(mmc, ios);
2720		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2721		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2722		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2723
2724		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2725		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2726		sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2727	} else {
2728		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2729		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2730		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2731
2732		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2733		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2734		sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2735	}
2736}
2737
2738static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2739{
2740	struct mmc_host *mmc = mmc_from_priv(host);
2741	struct cqhci_host *cq_host = mmc->cqe_private;
2742	u8 itcfmul;
2743	u64 hclk_freq, value;
2744
2745	/*
2746	 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2747	 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2748	 * Send Status Command Idle Timer (CIT) value.
2749	 */
2750	hclk_freq = (u64)clk_get_rate(host->h_clk);
2751	itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2752	switch (itcfmul) {
2753	case 0x0:
2754		do_div(hclk_freq, 1000);
2755		break;
2756	case 0x1:
2757		do_div(hclk_freq, 100);
2758		break;
2759	case 0x2:
2760		do_div(hclk_freq, 10);
2761		break;
2762	case 0x3:
2763		break;
2764	case 0x4:
2765		hclk_freq = hclk_freq * 10;
2766		break;
2767	default:
2768		host->cq_ssc1_time = 0x40;
2769		return;
2770	}
2771
2772	value = hclk_freq * timer_ns;
2773	do_div(value, 1000000000);
2774	host->cq_ssc1_time = value;
2775}
2776
2777static void msdc_cqe_enable(struct mmc_host *mmc)
2778{
2779	struct msdc_host *host = mmc_priv(mmc);
2780	struct cqhci_host *cq_host = mmc->cqe_private;
2781
2782	/* enable cmdq irq */
2783	writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2784	/* enable busy check */
2785	sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2786	/* default write data / busy timeout 20s */
2787	msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2788	/* default read data timeout 1s */
2789	msdc_set_timeout(host, 1000000000ULL, 0);
2790
2791	/* Set the send status command idle timer */
2792	cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2793}
2794
2795static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2796{
2797	struct msdc_host *host = mmc_priv(mmc);
2798	unsigned int val = 0;
2799
2800	/* disable cmdq irq */
2801	sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2802	/* disable busy check */
2803	sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2804
2805	val = readl(host->base + MSDC_INT);
2806	writel(val, host->base + MSDC_INT);
2807
2808	if (recovery) {
2809		sdr_set_field(host->base + MSDC_DMA_CTRL,
2810			      MSDC_DMA_CTRL_STOP, 1);
2811		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2812			!(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2813			return;
2814		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2815			!(val & MSDC_DMA_CFG_STS), 1, 3000)))
2816			return;
2817		msdc_reset_hw(host);
2818	}
2819}
2820
2821static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2822{
2823	struct cqhci_host *cq_host = mmc->cqe_private;
2824	u32 reg;
2825
2826	reg = cqhci_readl(cq_host, CQHCI_CFG);
2827	reg |= CQHCI_ENABLE;
2828	cqhci_writel(cq_host, reg, CQHCI_CFG);
2829}
2830
2831static void msdc_cqe_post_disable(struct mmc_host *mmc)
2832{
2833	struct cqhci_host *cq_host = mmc->cqe_private;
2834	u32 reg;
2835
2836	reg = cqhci_readl(cq_host, CQHCI_CFG);
2837	reg &= ~CQHCI_ENABLE;
2838	cqhci_writel(cq_host, reg, CQHCI_CFG);
2839}
2840
2841static const struct mmc_host_ops mt_msdc_ops = {
2842	.post_req = msdc_post_req,
2843	.pre_req = msdc_pre_req,
2844	.request = msdc_ops_request,
2845	.set_ios = msdc_ops_set_ios,
2846	.get_ro = mmc_gpio_get_ro,
2847	.get_cd = msdc_get_cd,
2848	.hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2849	.enable_sdio_irq = msdc_enable_sdio_irq,
2850	.ack_sdio_irq = msdc_ack_sdio_irq,
2851	.start_signal_voltage_switch = msdc_ops_switch_volt,
2852	.card_busy = msdc_card_busy,
2853	.execute_tuning = msdc_execute_tuning,
2854	.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2855	.execute_hs400_tuning = msdc_execute_hs400_tuning,
2856	.card_hw_reset = msdc_hw_reset,
2857};
2858
2859static const struct cqhci_host_ops msdc_cmdq_ops = {
2860	.enable         = msdc_cqe_enable,
2861	.disable        = msdc_cqe_disable,
2862	.pre_enable = msdc_cqe_pre_enable,
2863	.post_disable = msdc_cqe_post_disable,
2864};
2865
2866static void msdc_of_property_parse(struct platform_device *pdev,
2867				   struct msdc_host *host)
2868{
2869	struct mmc_host *mmc = mmc_from_priv(host);
2870
2871	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2872			     &host->latch_ck);
2873
2874	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2875			     &host->hs400_ds_delay);
2876
2877	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2878			     &host->hs400_ds_dly3);
2879
2880	of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2881			     &host->hs200_cmd_int_delay);
2882
2883	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2884			     &host->hs400_cmd_int_delay);
2885
2886	if (of_property_read_bool(pdev->dev.of_node,
2887				  "mediatek,hs400-cmd-resp-sel-rising"))
2888		host->hs400_cmd_resp_sel_rising = true;
2889	else
2890		host->hs400_cmd_resp_sel_rising = false;
2891
2892	if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step",
2893				 &host->tuning_step)) {
2894		if (mmc->caps2 & MMC_CAP2_NO_MMC)
2895			host->tuning_step = PAD_DELAY_FULL;
2896		else
2897			host->tuning_step = PAD_DELAY_HALF;
2898	}
2899
2900	if (of_property_read_bool(pdev->dev.of_node,
2901				  "supports-cqe"))
2902		host->cqhci = true;
2903	else
2904		host->cqhci = false;
2905}
2906
2907static int msdc_of_clock_parse(struct platform_device *pdev,
2908			       struct msdc_host *host)
2909{
2910	int ret;
2911
2912	host->src_clk = devm_clk_get(&pdev->dev, "source");
2913	if (IS_ERR(host->src_clk))
2914		return PTR_ERR(host->src_clk);
2915
2916	host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2917	if (IS_ERR(host->h_clk))
2918		return PTR_ERR(host->h_clk);
2919
2920	host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2921	if (IS_ERR(host->bus_clk))
2922		host->bus_clk = NULL;
2923
2924	/*source clock control gate is optional clock*/
2925	host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2926	if (IS_ERR(host->src_clk_cg))
2927		return PTR_ERR(host->src_clk_cg);
2928
2929	/*
2930	 * Fallback for legacy device-trees: src_clk and HCLK use the same
2931	 * bit to control gating but they are parented to a different mux,
2932	 * hence if our intention is to gate only the source, required
2933	 * during a clk mode switch to avoid hw hangs, we need to gate
2934	 * its parent (specified as a different clock only on new DTs).
2935	 */
2936	if (!host->src_clk_cg) {
2937		host->src_clk_cg = clk_get_parent(host->src_clk);
2938		if (IS_ERR(host->src_clk_cg))
2939			return PTR_ERR(host->src_clk_cg);
2940	}
2941
2942	/* If present, always enable for this clock gate */
2943	host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2944	if (IS_ERR(host->sys_clk_cg))
2945		host->sys_clk_cg = NULL;
2946
2947	host->bulk_clks[0].id = "pclk_cg";
2948	host->bulk_clks[1].id = "axi_cg";
2949	host->bulk_clks[2].id = "ahb_cg";
2950	ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2951					 host->bulk_clks);
2952	if (ret) {
2953		dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2954		return ret;
2955	}
2956
2957	return 0;
2958}
2959
2960static int msdc_drv_probe(struct platform_device *pdev)
2961{
2962	struct mmc_host *mmc;
2963	struct msdc_host *host;
2964	int ret;
2965
2966	if (!pdev->dev.of_node) {
2967		dev_err(&pdev->dev, "No DT found\n");
2968		return -EINVAL;
2969	}
2970
2971	/* Allocate MMC host for this device */
2972	mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host));
2973	if (!mmc)
2974		return -ENOMEM;
2975
2976	host = mmc_priv(mmc);
2977	ret = mmc_of_parse(mmc);
2978	if (ret)
2979		return ret;
2980
2981	host->base = devm_platform_ioremap_resource(pdev, 0);
2982	if (IS_ERR(host->base))
2983		return PTR_ERR(host->base);
2984
2985	host->dev_comp = of_device_get_match_data(&pdev->dev);
2986
2987	if (host->dev_comp->needs_top_base) {
2988		host->top_base = devm_platform_ioremap_resource(pdev, 1);
2989		if (IS_ERR(host->top_base))
2990			return PTR_ERR(host->top_base);
2991	}
2992
2993	ret = mmc_regulator_get_supply(mmc);
2994	if (ret)
2995		return ret;
2996
2997	ret = msdc_of_clock_parse(pdev, host);
2998	if (ret)
2999		return ret;
3000
3001	host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
3002								"hrst");
3003	if (IS_ERR(host->reset))
3004		return PTR_ERR(host->reset);
3005
3006	/* only eMMC has crypto property */
3007	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
3008		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
3009		if (IS_ERR(host->crypto_clk))
3010			return PTR_ERR(host->crypto_clk);
3011		else if (host->crypto_clk)
3012			mmc->caps2 |= MMC_CAP2_CRYPTO;
3013	}
3014
3015	host->irq = platform_get_irq(pdev, 0);
3016	if (host->irq < 0)
3017		return host->irq;
3018
3019	host->pinctrl = devm_pinctrl_get(&pdev->dev);
3020	if (IS_ERR(host->pinctrl))
3021		return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl),
3022				     "Cannot find pinctrl");
3023
3024	host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
3025	if (IS_ERR(host->pins_default)) {
3026		dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
3027		return PTR_ERR(host->pins_default);
3028	}
3029
3030	host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
3031	if (IS_ERR(host->pins_uhs)) {
3032		dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
3033		return PTR_ERR(host->pins_uhs);
3034	}
3035
3036	/* Support for SDIO eint irq ? */
3037	if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
3038		host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
3039		if (host->eint_irq > 0) {
3040			host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
3041			if (IS_ERR(host->pins_eint)) {
3042				dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
3043				host->pins_eint = NULL;
3044			} else {
3045				device_init_wakeup(&pdev->dev, true);
3046			}
3047		}
3048	}
3049
3050	msdc_of_property_parse(pdev, host);
3051
3052	host->dev = &pdev->dev;
3053	host->src_clk_freq = clk_get_rate(host->src_clk);
3054	/* Set host parameters to mmc */
3055	mmc->ops = &mt_msdc_ops;
3056	if (host->dev_comp->clk_div_bits == 8)
3057		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
3058	else
3059		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
3060
3061	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3062	    !mmc_host_can_gpio_cd(mmc) &&
3063	    host->dev_comp->use_internal_cd) {
3064		/*
3065		 * Is removable but no GPIO declared, so
3066		 * use internal functionality.
3067		 */
3068		host->internal_cd = true;
3069	}
3070
3071	if (mmc->caps & MMC_CAP_SDIO_IRQ)
3072		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3073
3074	mmc->caps |= MMC_CAP_CMD23;
3075	if (host->cqhci)
3076		mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
3077	/* MMC core transfer sizes tunable parameters */
3078	mmc->max_segs = MAX_BD_NUM;
3079	if (host->dev_comp->support_64g)
3080		mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
3081	else
3082		mmc->max_seg_size = BDMA_DESC_BUFLEN;
3083	mmc->max_blk_size = 2048;
3084	mmc->max_req_size = 512 * 1024;
3085	mmc->max_blk_count = mmc->max_req_size / 512;
3086	if (host->dev_comp->support_64g)
3087		host->dma_mask = DMA_BIT_MASK(36);
3088	else
3089		host->dma_mask = DMA_BIT_MASK(32);
3090	mmc_dev(mmc)->dma_mask = &host->dma_mask;
3091
3092	host->timeout_clks = 3 * 1048576;
3093	host->dma.gpd = dma_alloc_coherent(&pdev->dev,
3094				2 * sizeof(struct mt_gpdma_desc),
3095				&host->dma.gpd_addr, GFP_KERNEL);
3096	host->dma.bd = dma_alloc_coherent(&pdev->dev,
3097				MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3098				&host->dma.bd_addr, GFP_KERNEL);
3099	if (!host->dma.gpd || !host->dma.bd) {
3100		ret = -ENOMEM;
3101		goto release_mem;
3102	}
3103	msdc_init_gpd_bd(host, &host->dma);
3104	INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
3105	spin_lock_init(&host->lock);
3106
3107	platform_set_drvdata(pdev, mmc);
3108	ret = msdc_ungate_clock(host);
3109	if (ret) {
3110		dev_err(&pdev->dev, "Cannot ungate clocks!\n");
3111		goto release_clk;
3112	}
3113	msdc_init_hw(host);
3114
3115	if (mmc->caps2 & MMC_CAP2_CQE) {
3116		host->cq_host = devm_kzalloc(mmc->parent,
3117					     sizeof(*host->cq_host),
3118					     GFP_KERNEL);
3119		if (!host->cq_host) {
3120			ret = -ENOMEM;
3121			goto release;
3122		}
3123		host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
3124		host->cq_host->mmio = host->base + 0x800;
3125		host->cq_host->ops = &msdc_cmdq_ops;
3126		ret = cqhci_init(host->cq_host, mmc, true);
3127		if (ret)
3128			goto release;
3129		mmc->max_segs = 128;
3130		/* cqhci 16bit length */
3131		/* 0 size, means 65536 so we don't have to -1 here */
3132		mmc->max_seg_size = 64 * 1024;
3133		/* Reduce CIT to 0x40 that corresponds to 2.35us */
3134		msdc_cqe_cit_cal(host, 2350);
3135	} else if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
3136		/* Use HSQ on eMMC/SD (but not on SDIO) if HW CQE not supported */
3137		struct mmc_hsq *hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
3138		if (!hsq) {
3139			ret = -ENOMEM;
3140			goto release;
3141		}
3142
3143		ret = mmc_hsq_init(hsq, mmc);
3144		if (ret)
3145			goto release;
3146
3147		host->hsq_en = true;
3148	}
3149
3150	ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
3151			       IRQF_TRIGGER_NONE, pdev->name, host);
3152	if (ret)
3153		goto release;
3154
3155	pm_runtime_set_active(host->dev);
3156	pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
3157	pm_runtime_use_autosuspend(host->dev);
3158	pm_runtime_enable(host->dev);
3159	ret = mmc_add_host(mmc);
3160
3161	if (ret)
3162		goto end;
3163
3164	return 0;
3165end:
3166	pm_runtime_disable(host->dev);
3167release:
3168	msdc_deinit_hw(host);
3169release_clk:
3170	msdc_gate_clock(host);
3171	platform_set_drvdata(pdev, NULL);
3172release_mem:
3173	device_init_wakeup(&pdev->dev, false);
3174	if (host->dma.gpd)
3175		dma_free_coherent(&pdev->dev,
3176			2 * sizeof(struct mt_gpdma_desc),
3177			host->dma.gpd, host->dma.gpd_addr);
3178	if (host->dma.bd)
3179		dma_free_coherent(&pdev->dev,
3180				  MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3181				  host->dma.bd, host->dma.bd_addr);
3182	return ret;
3183}
3184
3185static void msdc_drv_remove(struct platform_device *pdev)
3186{
3187	struct mmc_host *mmc;
3188	struct msdc_host *host;
3189
3190	mmc = platform_get_drvdata(pdev);
3191	host = mmc_priv(mmc);
3192
3193	pm_runtime_get_sync(host->dev);
3194
3195	platform_set_drvdata(pdev, NULL);
3196	mmc_remove_host(mmc);
3197	msdc_deinit_hw(host);
3198	msdc_gate_clock(host);
3199
3200	pm_runtime_disable(host->dev);
3201	pm_runtime_put_noidle(host->dev);
3202	dma_free_coherent(&pdev->dev,
3203			2 * sizeof(struct mt_gpdma_desc),
3204			host->dma.gpd, host->dma.gpd_addr);
3205	dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3206			  host->dma.bd, host->dma.bd_addr);
3207	device_init_wakeup(&pdev->dev, false);
3208}
3209
3210static void msdc_save_reg(struct msdc_host *host)
3211{
3212	u32 tune_reg = host->dev_comp->pad_tune_reg;
3213
3214	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
3215	host->save_para.iocon = readl(host->base + MSDC_IOCON);
3216	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
3217	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
3218	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
3219	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
3220	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
3221	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
3222	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
3223	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
3224	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
3225	if (host->top_base) {
3226		host->save_para.emmc_top_control =
3227			readl(host->top_base + EMMC_TOP_CONTROL);
3228		host->save_para.emmc_top_cmd =
3229			readl(host->top_base + EMMC_TOP_CMD);
3230		host->save_para.emmc50_pad_ds_tune =
3231			readl(host->top_base + EMMC50_PAD_DS_TUNE);
3232		host->save_para.loop_test_control =
3233			readl(host->top_base + LOOP_TEST_CONTROL);
3234	} else {
3235		host->save_para.pad_tune = readl(host->base + tune_reg);
3236	}
3237}
3238
3239static void msdc_restore_reg(struct msdc_host *host)
3240{
3241	struct mmc_host *mmc = mmc_from_priv(host);
3242	u32 tune_reg = host->dev_comp->pad_tune_reg;
3243
3244	if (host->dev_comp->support_new_tx) {
3245		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3246		sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3247	}
3248	if (host->dev_comp->support_new_rx) {
3249		sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3250		sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3251	}
3252
3253	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3254	writel(host->save_para.iocon, host->base + MSDC_IOCON);
3255	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3256	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3257	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3258	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3259	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3260	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3261	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3262	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3263	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3264	if (host->top_base) {
3265		writel(host->save_para.emmc_top_control,
3266		       host->top_base + EMMC_TOP_CONTROL);
3267		writel(host->save_para.emmc_top_cmd,
3268		       host->top_base + EMMC_TOP_CMD);
3269		writel(host->save_para.emmc50_pad_ds_tune,
3270		       host->top_base + EMMC50_PAD_DS_TUNE);
3271		writel(host->save_para.loop_test_control,
3272		       host->top_base + LOOP_TEST_CONTROL);
3273	} else {
3274		writel(host->save_para.pad_tune, host->base + tune_reg);
3275	}
3276
3277	if (sdio_irq_claimed(mmc))
3278		__msdc_enable_sdio_irq(host, 1);
3279}
3280
3281static int msdc_runtime_suspend(struct device *dev)
3282{
3283	struct mmc_host *mmc = dev_get_drvdata(dev);
3284	struct msdc_host *host = mmc_priv(mmc);
3285
3286	if (host->hsq_en)
3287		mmc_hsq_suspend(mmc);
3288
3289	msdc_save_reg(host);
3290
3291	if (sdio_irq_claimed(mmc)) {
3292		if (host->pins_eint) {
3293			disable_irq(host->irq);
3294			pinctrl_select_state(host->pinctrl, host->pins_eint);
3295		}
3296
3297		__msdc_enable_sdio_irq(host, 0);
3298	}
3299	msdc_gate_clock(host);
3300	return 0;
3301}
3302
3303static int msdc_runtime_resume(struct device *dev)
3304{
3305	struct mmc_host *mmc = dev_get_drvdata(dev);
3306	struct msdc_host *host = mmc_priv(mmc);
3307	int ret;
3308
3309	ret = msdc_ungate_clock(host);
3310	if (ret)
3311		return ret;
3312
3313	msdc_restore_reg(host);
3314
3315	if (sdio_irq_claimed(mmc) && host->pins_eint) {
3316		pinctrl_select_state(host->pinctrl, host->pins_uhs);
3317		enable_irq(host->irq);
3318	}
3319
3320	if (host->hsq_en)
3321		mmc_hsq_resume(mmc);
3322
3323	return 0;
3324}
3325
3326static int msdc_suspend(struct device *dev)
3327{
3328	struct mmc_host *mmc = dev_get_drvdata(dev);
3329	struct msdc_host *host = mmc_priv(mmc);
3330	int ret;
3331	u32 val;
3332
3333	if (mmc->caps2 & MMC_CAP2_CQE) {
3334		ret = cqhci_suspend(mmc);
3335		if (ret)
3336			return ret;
3337		val = readl(host->base + MSDC_INT);
3338		writel(val, host->base + MSDC_INT);
3339	}
3340
3341	/*
3342	 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3343	 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3344	 */
3345	if (sdio_irq_claimed(mmc) && host->pins_eint)
3346		pm_runtime_get_noresume(dev);
3347
3348	return pm_runtime_force_suspend(dev);
3349}
3350
3351static int msdc_resume(struct device *dev)
3352{
3353	struct mmc_host *mmc = dev_get_drvdata(dev);
3354	struct msdc_host *host = mmc_priv(mmc);
3355
3356	if (sdio_irq_claimed(mmc) && host->pins_eint)
3357		pm_runtime_put_noidle(dev);
3358
3359	return pm_runtime_force_resume(dev);
3360}
3361
3362static const struct dev_pm_ops msdc_dev_pm_ops = {
3363	SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3364	RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3365};
3366
3367static struct platform_driver mt_msdc_driver = {
3368	.probe = msdc_drv_probe,
3369	.remove = msdc_drv_remove,
3370	.driver = {
3371		.name = "mtk-msdc",
3372		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3373		.of_match_table = msdc_of_ids,
3374		.pm = pm_ptr(&msdc_dev_pm_ops),
3375	},
3376};
3377
3378module_platform_driver(mt_msdc_driver);
3379MODULE_LICENSE("GPL v2");
3380MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");