dw_mmc-rockchip.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  4 */
  5
  6#include <linux/module.h>
  7#include <linux/platform_device.h>
  8#include <linux/clk.h>
  9#include <linux/hw_bitfield.h>
 10#include <linux/mmc/host.h>
 11#include <linux/of_address.h>
 12#include <linux/mmc/slot-gpio.h>
 13#include <linux/pm_runtime.h>
 14#include <linux/slab.h>
 15
 16#include "dw_mmc.h"
 17#include "dw_mmc-pltfm.h"
 18
 19#define RK3288_CLKGEN_DIV		2
 20#define SDMMC_TIMING_CON0		0x130
 21#define SDMMC_TIMING_CON1		0x134
 22#define SDMMC_MISC_CON			0x138
 23#define MEM_CLK_AUTOGATE_ENABLE		BIT(5)
 24#define ROCKCHIP_MMC_DELAY_SEL		BIT(10)
 25#define ROCKCHIP_MMC_DEGREE_MASK	0x3
 26#define ROCKCHIP_MMC_DEGREE_OFFSET	1
 27#define ROCKCHIP_MMC_DELAYNUM_OFFSET	2
 28#define ROCKCHIP_MMC_DELAYNUM_MASK	(0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
 29#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC	60
 30
 31static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
 32
 33struct dw_mci_rockchip_priv_data {
 34	struct clk		*drv_clk;
 35	struct clk		*sample_clk;
 36	int			default_sample_phase;
 37	int			num_phases;
 38	bool			internal_phase;
 39	int                     sample_phase;
 40	int                     drv_phase;
 41};
 42
 43/*
 44 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
 45 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
 46 */
 47static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample)
 48{
 49	unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
 50	u32 raw_value;
 51	u16 degrees;
 52	u32 delay_num = 0;
 53
 54	/* Constant signal, no measurable phase shift */
 55	if (!rate)
 56		return 0;
 57
 58	if (sample)
 59		raw_value = mci_readl(host, TIMING_CON1);
 60	else
 61		raw_value = mci_readl(host, TIMING_CON0);
 62
 63	raw_value >>= ROCKCHIP_MMC_DEGREE_OFFSET;
 64	degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
 65
 66	if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
 67		/* degrees/delaynum * 1000000 */
 68		unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
 69					36 * (rate / 10000);
 70
 71		delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
 72		delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
 73		degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000);
 74	}
 75
 76	return degrees % 360;
 77}
 78
 79static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample)
 80{
 81	struct dw_mci_rockchip_priv_data *priv = host->priv;
 82	struct clk *clock = sample ? priv->sample_clk : priv->drv_clk;
 83
 84	if (priv->internal_phase)
 85		return rockchip_mmc_get_internal_phase(host, sample);
 86	else
 87		return clk_get_phase(clock);
 88}
 89
 90static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees)
 91{
 92	unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
 93	u8 nineties, remainder;
 94	u8 delay_num;
 95	u32 raw_value;
 96	u32 delay;
 97
 98	/*
 99	 * The below calculation is based on the output clock from
100	 * MMC host to the card, which expects the phase clock inherits
101	 * the clock rate from its parent, namely the output clock
102	 * provider of MMC host. However, things may go wrong if
103	 * (1) It is orphan.
104	 * (2) It is assigned to the wrong parent.
105	 *
106	 * This check help debug the case (1), which seems to be the
107	 * most likely problem we often face and which makes it difficult
108	 * for people to debug unstable mmc tuning results.
109	 */
110	if (!rate) {
111		dev_err(host->dev, "%s: invalid clk rate\n", __func__);
112		return -EINVAL;
113	}
114
115	nineties = degrees / 90;
116	remainder = (degrees % 90);
117
118	/*
119	 * Due to the inexact nature of the "fine" delay, we might
120	 * actually go non-monotonic.  We don't go _too_ monotonic
121	 * though, so we should be OK.  Here are options of how we may
122	 * work:
123	 *
124	 * Ideally we end up with:
125	 *   1.0, 2.0, ..., 69.0, 70.0, ...,  89.0, 90.0
126	 *
127	 * On one extreme (if delay is actually 44ps):
128	 *   .73, 1.5, ..., 50.6, 51.3, ...,  65.3, 90.0
129	 * The other (if delay is actually 77ps):
130	 *   1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
131	 *
132	 * It's possible we might make a delay that is up to 25
133	 * degrees off from what we think we're making.  That's OK
134	 * though because we should be REALLY far from any bad range.
135	 */
136
137	/*
138	 * Convert to delay; do a little extra work to make sure we
139	 * don't overflow 32-bit / 64-bit numbers.
140	 */
141	delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
142	delay *= remainder;
143	delay = DIV_ROUND_CLOSEST(delay,
144			(rate / 1000) * 36 *
145				(ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
146
147	delay_num = (u8) min_t(u32, delay, 255);
148
149	raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
150	raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
151	raw_value |= nineties;
152
153	if (sample)
154		mci_writel(host, TIMING_CON1,
155			   FIELD_PREP_WM16(GENMASK(11, 1), raw_value));
156	else
157		mci_writel(host, TIMING_CON0,
158			   FIELD_PREP_WM16(GENMASK(11, 1), raw_value));
159
160	dev_dbg(host->dev, "set %s_phase(%d) delay_nums=%u actual_degrees=%d\n",
161		sample ? "sample" : "drv", degrees, delay_num,
162		rockchip_mmc_get_phase(host, sample)
163	);
164
165	return 0;
166}
167
168static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees)
169{
170	struct dw_mci_rockchip_priv_data *priv = host->priv;
171	struct clk *clock = sample ? priv->sample_clk : priv->drv_clk;
172
173	if (priv->internal_phase)
174		return rockchip_mmc_set_internal_phase(host, sample, degrees);
175	else
176		return clk_set_phase(clock, degrees);
177}
178
179static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
180{
181	struct dw_mci_rockchip_priv_data *priv = host->priv;
182	int ret;
183	unsigned int cclkin;
184	u32 bus_hz;
185
186	if (ios->clock == 0)
187		return;
188
189	/*
190	 * cclkin: source clock of mmc controller
191	 * bus_hz: card interface clock generated by CLKGEN
192	 * bus_hz = cclkin / RK3288_CLKGEN_DIV
193	 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
194	 *
195	 * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
196	 * DDR52 8-bit mode.
197	 */
198	if (ios->bus_width == MMC_BUS_WIDTH_8 &&
199	    ios->timing == MMC_TIMING_MMC_DDR52)
200		cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
201	else
202		cclkin = ios->clock * RK3288_CLKGEN_DIV;
203
204	ret = clk_set_rate(host->ciu_clk, cclkin);
205	if (ret)
206		dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
207
208	bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
209	if (bus_hz != host->bus_hz) {
210		host->bus_hz = bus_hz;
211		/* force dw_mci_setup_bus() */
212		host->current_speed = 0;
213	}
214
215	/* Make sure we use phases which we can enumerate with */
216	if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS)
217		rockchip_mmc_set_phase(host, true, priv->default_sample_phase);
218
219	/*
220	 * Set the drive phase offset based on speed mode to achieve hold times.
221	 *
222	 * NOTE: this is _not_ a value that is dynamically tuned and is also
223	 * _not_ a value that will vary from board to board.  It is a value
224	 * that could vary between different SoC models if they had massively
225	 * different output clock delays inside their dw_mmc IP block (delay_o),
226	 * but since it's OK to overshoot a little we don't need to do complex
227	 * calculations and can pick values that will just work for everyone.
228	 *
229	 * When picking values we'll stick with picking 0/90/180/270 since
230	 * those can be made very accurately on all known Rockchip SoCs.
231	 *
232	 * Note that these values match values from the DesignWare Databook
233	 * tables for the most part except for SDR12 and "ID mode".  For those
234	 * two modes the databook calculations assume a clock in of 50MHz.  As
235	 * seen above, we always use a clock in rate that is exactly the
236	 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
237	 * back out before the controller sees it).
238	 *
239	 * From measurement of a single device, it appears that delay_o is
240	 * about .5 ns.  Since we try to leave a bit of margin, it's expected
241	 * that numbers here will be fine even with much larger delay_o
242	 * (the 1.4 ns assumed by the DesignWare Databook would result in the
243	 * same results, for instance).
244	 */
245	if (!IS_ERR(priv->drv_clk)) {
246		int phase;
247
248		/*
249		 * In almost all cases a 90 degree phase offset will provide
250		 * sufficient hold times across all valid input clock rates
251		 * assuming delay_o is not absurd for a given SoC.  We'll use
252		 * that as a default.
253		 */
254		phase = 90;
255
256		switch (ios->timing) {
257		case MMC_TIMING_MMC_DDR52:
258			/*
259			 * Since clock in rate with MMC_DDR52 is doubled when
260			 * bus width is 8 we need to double the phase offset
261			 * to get the same timings.
262			 */
263			if (ios->bus_width == MMC_BUS_WIDTH_8)
264				phase = 180;
265			break;
266		case MMC_TIMING_UHS_SDR104:
267		case MMC_TIMING_MMC_HS200:
268			/*
269			 * In the case of 150 MHz clock (typical max for
270			 * Rockchip SoCs), 90 degree offset will add a delay
271			 * of 1.67 ns.  That will meet min hold time of .8 ns
272			 * as long as clock output delay is < .87 ns.  On
273			 * SoCs measured this seems to be OK, but it doesn't
274			 * hurt to give margin here, so we use 180.
275			 */
276			phase = 180;
277			break;
278		}
279
280		rockchip_mmc_set_phase(host, false, phase);
281	}
282}
283
284#define TUNING_ITERATION_TO_PHASE(i, num_phases) \
285		(DIV_ROUND_UP((i) * 360, num_phases))
286
287static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
288{
289	struct dw_mci *host = slot->host;
290	struct dw_mci_rockchip_priv_data *priv = host->priv;
291	struct mmc_host *mmc = slot->mmc;
292	int ret = 0;
293	int i;
294	bool v, prev_v = 0, first_v;
295	struct range_t {
296		int start;
297		int end; /* inclusive */
298	};
299	struct range_t *ranges;
300	unsigned int range_count = 0;
301	int longest_range_len = -1;
302	int longest_range = -1;
303	int middle_phase;
304	int phase;
305
306	if (IS_ERR(priv->sample_clk)) {
307		dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
308		return -EIO;
309	}
310
311	ranges = kmalloc_array(priv->num_phases / 2 + 1,
312			       sizeof(*ranges), GFP_KERNEL);
313	if (!ranges)
314		return -ENOMEM;
315
316	/* Try each phase and extract good ranges */
317	for (i = 0; i < priv->num_phases; ) {
318		rockchip_mmc_set_phase(host, true,
319				       TUNING_ITERATION_TO_PHASE(
320						i,
321						priv->num_phases));
322
323		v = !mmc_send_tuning(mmc, opcode, NULL);
324
325		if (i == 0)
326			first_v = v;
327
328		if ((!prev_v) && v) {
329			range_count++;
330			ranges[range_count-1].start = i;
331		}
332		if (v) {
333			ranges[range_count-1].end = i;
334			i++;
335		} else if (i == priv->num_phases - 1) {
336			/* No extra skipping rules if we're at the end */
337			i++;
338		} else {
339			/*
340			 * No need to check too close to an invalid
341			 * one since testing bad phases is slow.  Skip
342			 * 20 degrees.
343			 */
344			i += DIV_ROUND_UP(20 * priv->num_phases, 360);
345
346			/* Always test the last one */
347			if (i >= priv->num_phases)
348				i = priv->num_phases - 1;
349		}
350
351		prev_v = v;
352	}
353
354	if (range_count == 0) {
355		dev_warn(host->dev, "All phases bad!");
356		ret = -EIO;
357		goto free;
358	}
359
360	/* wrap around case, merge the end points */
361	if ((range_count > 1) && first_v && v) {
362		ranges[0].start = ranges[range_count-1].start;
363		range_count--;
364	}
365
366	if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
367		rockchip_mmc_set_phase(host, true, priv->default_sample_phase);
368
369		dev_info(host->dev, "All phases work, using default phase %d.",
370			 priv->default_sample_phase);
371		goto free;
372	}
373
374	/* Find the longest range */
375	for (i = 0; i < range_count; i++) {
376		int len = (ranges[i].end - ranges[i].start + 1);
377
378		if (len < 0)
379			len += priv->num_phases;
380
381		if (longest_range_len < len) {
382			longest_range_len = len;
383			longest_range = i;
384		}
385
386		dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
387			TUNING_ITERATION_TO_PHASE(ranges[i].start,
388						  priv->num_phases),
389			TUNING_ITERATION_TO_PHASE(ranges[i].end,
390						  priv->num_phases),
391			len
392		);
393	}
394
395	dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
396		TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
397					  priv->num_phases),
398		TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
399					  priv->num_phases),
400		longest_range_len
401	);
402
403	middle_phase = ranges[longest_range].start + longest_range_len / 2;
404	middle_phase %= priv->num_phases;
405	phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases);
406	dev_info(host->dev, "Successfully tuned phase to %d\n", phase);
407
408	rockchip_mmc_set_phase(host, true, phase);
409
410free:
411	kfree(ranges);
412	return ret;
413}
414
415static int dw_mci_common_parse_dt(struct dw_mci *host)
416{
417	struct device_node *np = host->dev->of_node;
418	struct dw_mci_rockchip_priv_data *priv;
419
420	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
421	if (!priv)
422		return -ENOMEM;
423
424	if (of_property_read_u32(np, "rockchip,desired-num-phases",
425				 &priv->num_phases))
426		priv->num_phases = 360;
427
428	if (of_property_read_u32(np, "rockchip,default-sample-phase",
429				 &priv->default_sample_phase))
430		priv->default_sample_phase = 0;
431
432	host->priv = priv;
433
434	return 0;
435}
436
437static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
438{
439	struct dw_mci_rockchip_priv_data *priv;
440	int err;
441
442	err = dw_mci_common_parse_dt(host);
443	if (err)
444		return err;
445
446	priv = host->priv;
447
448	priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
449	if (IS_ERR(priv->drv_clk))
450		dev_dbg(host->dev, "ciu-drive not available\n");
451
452	priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
453	if (IS_ERR(priv->sample_clk))
454		dev_dbg(host->dev, "ciu-sample not available\n");
455
456	priv->internal_phase = false;
457
458	return 0;
459}
460
461static int dw_mci_rk3576_parse_dt(struct dw_mci *host)
462{
463	struct dw_mci_rockchip_priv_data *priv;
464	int err = dw_mci_common_parse_dt(host);
465	if (err)
466		return err;
467
468	priv = host->priv;
469
470	priv->internal_phase = true;
471
472	return 0;
473}
474
475static int dw_mci_rockchip_init(struct dw_mci *host)
476{
477	struct dw_mci_rockchip_priv_data *priv = host->priv;
478	int ret, i;
479
480	/* It is slot 8 on Rockchip SoCs */
481	host->sdio_id0 = 8;
482
483	if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
484		host->bus_hz /= RK3288_CLKGEN_DIV;
485
486		/* clock driver will fail if the clock is less than the lowest source clock
487		 * divided by the internal clock divider. Test for the lowest available
488		 * clock and set the minimum freq to clock / clock divider.
489		 */
490
491		for (i = 0; i < ARRAY_SIZE(freqs); i++) {
492			ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
493			if (ret > 0) {
494				host->minimum_speed = ret / RK3288_CLKGEN_DIV;
495				break;
496			}
497		}
498		if (ret < 0)
499			dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
500	}
501
502	if (priv->internal_phase)
503		mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
504
505	return 0;
506}
507
508static const struct dw_mci_drv_data rk2928_drv_data = {
509	.init			= dw_mci_rockchip_init,
510};
511
512static const struct dw_mci_drv_data rk3288_drv_data = {
513	.common_caps		= MMC_CAP_CMD23,
514	.set_ios		= dw_mci_rk3288_set_ios,
515	.execute_tuning		= dw_mci_rk3288_execute_tuning,
516	.parse_dt		= dw_mci_rk3288_parse_dt,
517	.init			= dw_mci_rockchip_init,
518};
519
520static const struct dw_mci_drv_data rk3576_drv_data = {
521	.common_caps		= MMC_CAP_CMD23,
522	.set_ios		= dw_mci_rk3288_set_ios,
523	.execute_tuning		= dw_mci_rk3288_execute_tuning,
524	.parse_dt		= dw_mci_rk3576_parse_dt,
525	.init			= dw_mci_rockchip_init,
526};
527
528static const struct of_device_id dw_mci_rockchip_match[] = {
529	{ .compatible = "rockchip,rk2928-dw-mshc",
530		.data = &rk2928_drv_data },
531	{ .compatible = "rockchip,rk3288-dw-mshc",
532		.data = &rk3288_drv_data },
533	{ .compatible = "rockchip,rk3576-dw-mshc",
534		.data = &rk3576_drv_data },
535	{},
536};
537MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
538
539static int dw_mci_rockchip_probe(struct platform_device *pdev)
540{
541	const struct dw_mci_drv_data *drv_data;
542	const struct of_device_id *match;
543	int ret;
544
545	if (!pdev->dev.of_node)
546		return -ENODEV;
547
548	match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
549	drv_data = match->data;
550
551	pm_runtime_get_noresume(&pdev->dev);
552	pm_runtime_set_active(&pdev->dev);
553	pm_runtime_enable(&pdev->dev);
554	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
555	pm_runtime_use_autosuspend(&pdev->dev);
556
557	ret = dw_mci_pltfm_register(pdev, drv_data);
558	if (ret) {
559		pm_runtime_disable(&pdev->dev);
560		pm_runtime_set_suspended(&pdev->dev);
561		pm_runtime_put_noidle(&pdev->dev);
562		return ret;
563	}
564
565	pm_runtime_put_autosuspend(&pdev->dev);
566
567	return 0;
568}
569
570static void dw_mci_rockchip_remove(struct platform_device *pdev)
571{
572	pm_runtime_get_sync(&pdev->dev);
573	pm_runtime_disable(&pdev->dev);
574	pm_runtime_put_noidle(&pdev->dev);
575
576	dw_mci_pltfm_remove(pdev);
577}
578
579static int dw_mci_rockchip_runtime_suspend(struct device *dev)
580{
581	struct platform_device *pdev = to_platform_device(dev);
582	struct dw_mci *host = platform_get_drvdata(pdev);
583	struct dw_mci_rockchip_priv_data *priv = host->priv;
584
585	if (priv->internal_phase) {
586		priv->sample_phase = rockchip_mmc_get_phase(host, true);
587		priv->drv_phase = rockchip_mmc_get_phase(host, false);
588	}
589
590	return dw_mci_runtime_suspend(dev);
591}
592
593static int dw_mci_rockchip_runtime_resume(struct device *dev)
594{
595	struct platform_device *pdev = to_platform_device(dev);
596	struct dw_mci *host = platform_get_drvdata(pdev);
597	struct dw_mci_rockchip_priv_data *priv = host->priv;
598	int ret;
599
600	ret = dw_mci_runtime_resume(dev);
601	if (ret)
602		return ret;
603
604	if (priv->internal_phase) {
605		rockchip_mmc_set_phase(host, true, priv->sample_phase);
606		rockchip_mmc_set_phase(host, false, priv->drv_phase);
607		mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
608	}
609
610	return ret;
611}
612
613static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
614	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
615	RUNTIME_PM_OPS(dw_mci_rockchip_runtime_suspend, dw_mci_rockchip_runtime_resume, NULL)
616};
617
618static struct platform_driver dw_mci_rockchip_pltfm_driver = {
619	.probe		= dw_mci_rockchip_probe,
620	.remove		= dw_mci_rockchip_remove,
621	.driver		= {
622		.name		= "dwmmc_rockchip",
623		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
624		.of_match_table	= dw_mci_rockchip_match,
625		.pm		= pm_ptr(&dw_mci_rockchip_dev_pm_ops),
626	},
627};
628
629module_platform_driver(dw_mci_rockchip_pltfm_driver);
630
631MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
632MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
633MODULE_ALIAS("platform:dwmmc_rockchip");
634MODULE_LICENSE("GPL v2");