cqhci.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
  3 */
  4#ifndef LINUX_MMC_CQHCI_H
  5#define LINUX_MMC_CQHCI_H
  6
  7#include <linux/compiler.h>
  8#include <linux/bitfield.h>
  9#include <linux/bitops.h>
 10#include <linux/spinlock_types.h>
 11#include <linux/types.h>
 12#include <linux/completion.h>
 13#include <linux/wait.h>
 14#include <linux/irqreturn.h>
 15#include <asm/io.h>
 16
 17/* registers */
 18/* version */
 19#define CQHCI_VER			0x00
 20#define CQHCI_VER_MAJOR(x)		(((x) & GENMASK(11, 8)) >> 8)
 21#define CQHCI_VER_MINOR1(x)		(((x) & GENMASK(7, 4)) >> 4)
 22#define CQHCI_VER_MINOR2(x)		((x) & GENMASK(3, 0))
 23
 24/* capabilities */
 25#define CQHCI_CAP			0x04
 26#define CQHCI_CAP_CS			0x10000000 /* Crypto Support */
 27#define CQHCI_CAP_ITCFMUL		GENMASK(15, 12)
 28#define CQHCI_ITCFMUL(x)		FIELD_GET(CQHCI_CAP_ITCFMUL, (x))
 29
 30/* configuration */
 31#define CQHCI_CFG			0x08
 32#define CQHCI_DCMD			0x00001000
 33#define CQHCI_TASK_DESC_SZ		0x00000100
 34#define CQHCI_CRYPTO_GENERAL_ENABLE	0x00000002
 35#define CQHCI_ENABLE			0x00000001
 36
 37/* control */
 38#define CQHCI_CTL			0x0C
 39#define CQHCI_CLEAR_ALL_TASKS		0x00000100
 40#define CQHCI_HALT			0x00000001
 41
 42/* interrupt status */
 43#define CQHCI_IS			0x10
 44#define CQHCI_IS_HAC			BIT(0)
 45#define CQHCI_IS_TCC			BIT(1)
 46#define CQHCI_IS_RED			BIT(2)
 47#define CQHCI_IS_TCL			BIT(3)
 48#define CQHCI_IS_GCE			BIT(4) /* General Crypto Error */
 49#define CQHCI_IS_ICCE			BIT(5) /* Invalid Crypto Config Error */
 50
 51#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
 52		       CQHCI_IS_GCE | CQHCI_IS_ICCE)
 53
 54/* interrupt status enable */
 55#define CQHCI_ISTE			0x14
 56
 57/* interrupt signal enable */
 58#define CQHCI_ISGE			0x18
 59
 60/* interrupt coalescing */
 61#define CQHCI_IC			0x1C
 62#define CQHCI_IC_ENABLE			BIT(31)
 63#define CQHCI_IC_RESET			BIT(16)
 64#define CQHCI_IC_ICCTHWEN		BIT(15)
 65#define CQHCI_IC_ICCTH(x)		(((x) & 0x1F) << 8)
 66#define CQHCI_IC_ICTOVALWEN		BIT(7)
 67#define CQHCI_IC_ICTOVAL(x)		((x) & 0x7F)
 68
 69/* task list base address */
 70#define CQHCI_TDLBA			0x20
 71
 72/* task list base address upper */
 73#define CQHCI_TDLBAU			0x24
 74
 75/* door-bell */
 76#define CQHCI_TDBR			0x28
 77
 78/* task completion notification */
 79#define CQHCI_TCN			0x2C
 80
 81/* device queue status */
 82#define CQHCI_DQS			0x30
 83
 84/* device pending tasks */
 85#define CQHCI_DPT			0x34
 86
 87/* task clear */
 88#define CQHCI_TCLR			0x38
 89
 90/* task descriptor processing error */
 91#define CQHCI_TDPE			0x3c
 92
 93/* send status config 1 */
 94#define CQHCI_SSC1			0x40
 95#define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)
 96#define CQHCI_SSC1_CIT_MASK		GENMASK(15, 0)
 97
 98/* send status config 2 */
 99#define CQHCI_SSC2			0x44
100
101/* response for dcmd */
102#define CQHCI_CRDCT			0x48
103
104/* response mode error mask */
105#define CQHCI_RMEM			0x50
106
107/* task error info */
108#define CQHCI_TERRI			0x54
109
110#define CQHCI_TERRI_C_INDEX(x)		((x) & GENMASK(5, 0))
111#define CQHCI_TERRI_C_TASK(x)		(((x) & GENMASK(12, 8)) >> 8)
112#define CQHCI_TERRI_C_VALID(x)		((x) & BIT(15))
113#define CQHCI_TERRI_D_INDEX(x)		(((x) & GENMASK(21, 16)) >> 16)
114#define CQHCI_TERRI_D_TASK(x)		(((x) & GENMASK(28, 24)) >> 24)
115#define CQHCI_TERRI_D_VALID(x)		((x) & BIT(31))
116
117/* command response index */
118#define CQHCI_CRI			0x58
119
120/* command response argument */
121#define CQHCI_CRA			0x5C
122
123/* crypto capabilities */
124#define CQHCI_CCAP			0x100
125#define CQHCI_CRYPTOCAP			0x104
126
127#define CQHCI_INT_ALL			0xF
128#define CQHCI_IC_DEFAULT_ICCTH		31
129#define CQHCI_IC_DEFAULT_ICTOVAL	1
130
131/* attribute fields */
132#define CQHCI_VALID(x)			(((x) & 1) << 0)
133#define CQHCI_END(x)			(((x) & 1) << 1)
134#define CQHCI_INT(x)			(((x) & 1) << 2)
135#define CQHCI_ACT(x)			(((x) & 0x7) << 3)
136
137/* data command task descriptor fields */
138#define CQHCI_FORCED_PROG(x)		(((x) & 1) << 6)
139#define CQHCI_CONTEXT(x)		(((x) & 0xF) << 7)
140#define CQHCI_DATA_TAG(x)		(((x) & 1) << 11)
141#define CQHCI_DATA_DIR(x)		(((x) & 1) << 12)
142#define CQHCI_PRIORITY(x)		(((x) & 1) << 13)
143#define CQHCI_QBAR(x)			(((x) & 1) << 14)
144#define CQHCI_REL_WRITE(x)		(((x) & 1) << 15)
145#define CQHCI_BLK_COUNT(x)		(((x) & 0xFFFF) << 16)
146#define CQHCI_BLK_ADDR(x)		(((x) & 0xFFFFFFFF) << 32)
147
148/* direct command task descriptor fields */
149#define CQHCI_CMD_INDEX(x)		(((x) & 0x3F) << 16)
150#define CQHCI_CMD_TIMING(x)		(((x) & 1) << 22)
151#define CQHCI_RESP_TYPE(x)		(((x) & 0x3) << 23)
152
153/* crypto task descriptor fields (for bits 64-127 of task descriptor) */
154#define CQHCI_CRYPTO_ENABLE_BIT		(1ULL << 47)
155#define CQHCI_CRYPTO_KEYSLOT(x)		((u64)(x) << 32)
156
157/* transfer descriptor fields */
158#define CQHCI_DAT_LENGTH(x)		(((x) & 0xFFFF) << 16)
159#define CQHCI_DAT_ADDR_LO(x)		(((x) & 0xFFFFFFFF) << 32)
160#define CQHCI_DAT_ADDR_HI(x)		(((x) & 0xFFFFFFFF) << 0)
161
162/* CCAP - Crypto Capability 100h */
163union cqhci_crypto_capabilities {
164	__le32 reg_val;
165	struct {
166		u8 num_crypto_cap;
167		u8 config_count;
168		u8 reserved;
169		u8 config_array_ptr;
170	};
171};
172
173enum cqhci_crypto_key_size {
174	CQHCI_CRYPTO_KEY_SIZE_INVALID	= 0,
175	CQHCI_CRYPTO_KEY_SIZE_128	= 1,
176	CQHCI_CRYPTO_KEY_SIZE_192	= 2,
177	CQHCI_CRYPTO_KEY_SIZE_256	= 3,
178	CQHCI_CRYPTO_KEY_SIZE_512	= 4,
179};
180
181enum cqhci_crypto_alg {
182	CQHCI_CRYPTO_ALG_AES_XTS		= 0,
183	CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC	= 1,
184	CQHCI_CRYPTO_ALG_AES_ECB		= 2,
185	CQHCI_CRYPTO_ALG_ESSIV_AES_CBC		= 3,
186};
187
188/* x-CRYPTOCAP - Crypto Capability X */
189union cqhci_crypto_cap_entry {
190	__le32 reg_val;
191	struct {
192		u8 algorithm_id;
193		u8 sdus_mask; /* Supported data unit size mask */
194		u8 key_size;
195		u8 reserved;
196	};
197};
198
199#define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
200#define CQHCI_CRYPTO_KEY_MAX_SIZE 64
201/* x-CRYPTOCFG - Crypto Configuration X */
202union cqhci_crypto_cfg_entry {
203	__le32 reg_val[32];
204	struct {
205		u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
206		u8 data_unit_size;
207		u8 crypto_cap_idx;
208		u8 reserved_1;
209		u8 config_enable;
210		u8 reserved_multi_host;
211		u8 reserved_2;
212		u8 vsb[2];
213		u8 reserved_3[56];
214	};
215};
216
217struct cqhci_host_ops;
218struct mmc_host;
219struct mmc_request;
220struct cqhci_slot;
221
222struct cqhci_host {
223	const struct cqhci_host_ops *ops;
224	void __iomem *mmio;
225	struct mmc_host *mmc;
226
227	spinlock_t lock;
228
229	/* relative card address of device */
230	unsigned int rca;
231
232	/* 64 bit DMA */
233	bool dma64;
234	int num_slots;
235	int qcnt;
236
237	u32 dcmd_slot;
238	u32 caps;
239#define CQHCI_TASK_DESC_SZ_128		0x1
240
241	u32 quirks;
242#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ	0x1
243
244	bool enabled;
245	bool halted;
246	bool init_done;
247	bool activated;
248	bool waiting_for_idle;
249	bool recovery_halt;
250
251	size_t desc_size;
252	size_t data_size;
253
254	u8 *desc_base;
255
256	/* total descriptor size */
257	u8 slot_sz;
258
259	/* 64/128 bit depends on CQHCI_CFG */
260	u8 task_desc_len;
261
262	/* 64 bit on 32-bit arch, 128 bit on 64-bit */
263	u8 link_desc_len;
264
265	u8 *trans_desc_base;
266	/* same length as transfer descriptor */
267	u8 trans_desc_len;
268
269	dma_addr_t desc_dma_base;
270	dma_addr_t trans_desc_dma_base;
271
272	struct completion halt_comp;
273	wait_queue_head_t wait_queue;
274	struct cqhci_slot *slot;
275
276#ifdef CONFIG_MMC_CRYPTO
277	union cqhci_crypto_capabilities crypto_capabilities;
278	union cqhci_crypto_cap_entry *crypto_cap_array;
279	u32 crypto_cfg_register;
280#endif
281};
282
283struct cqhci_host_ops {
284	void (*dumpregs)(struct mmc_host *mmc);
285	void (*write_l)(struct cqhci_host *host, u32 val, int reg);
286	u32 (*read_l)(struct cqhci_host *host, int reg);
287	void (*enable)(struct mmc_host *mmc);
288	void (*disable)(struct mmc_host *mmc, bool recovery);
289	void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
290				 u64 *data);
291	void (*pre_enable)(struct mmc_host *mmc);
292	void (*post_disable)(struct mmc_host *mmc);
293	void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc,
294			      dma_addr_t addr, int len, bool end, bool dma64);
295#ifdef CONFIG_MMC_CRYPTO
296	bool uses_custom_crypto_profile;
297#endif
298};
299
300static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
301{
302	if (unlikely(host->ops->write_l))
303		host->ops->write_l(host, val, reg);
304	else
305		writel_relaxed(val, host->mmio + reg);
306}
307
308static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
309{
310	if (unlikely(host->ops->read_l))
311		return host->ops->read_l(host, reg);
312	else
313		return readl_relaxed(host->mmio + reg);
314}
315
316struct platform_device;
317
318irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
319		      int data_error);
320int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
321struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
322int cqhci_deactivate(struct mmc_host *mmc);
323void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, bool dma64);
324static inline int cqhci_suspend(struct mmc_host *mmc)
325{
326	return cqhci_deactivate(mmc);
327}
328int cqhci_resume(struct mmc_host *mmc);
329
330#endif