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bcm2835.c
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linux-6.19.14/drivers/mmc/host/bcm2835.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * bcm2835 sdhost driver. 4 * 5 * The 2835 has two SD controllers: The Arasan sdhci controller 6 * (supported by the iproc driver) and a custom sdhost controller 7 * (supported by this driver). 8 * 9 * The sdhci controller supports both sdcard and sdio. The sdhost 10 * controller supports the sdcard only, but has better performance. 11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with 12 * the sdhost controller allows to use the sdhci controller for wifi 13 * support. 14 * 15 * The configuration is done by devicetree via pin muxing. Both 16 * SD controller are available on the same pins (2 pin groups = pin 22 17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers 18 * at the same time with different pin groups. 19 * 20 * Author: Phil Elwell <phil@raspberrypi.org> 21 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 22 * 23 * Based on 24 * mmc-bcm2835.c by Gellert Weisz 25 * which is, in turn, based on 26 * sdhci-bcm2708.c by Broadcom 27 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 28 * sdhci.c and sdhci-pci.c by Pierre Ossman 29 */ 30#include <linux/clk.h> 31#include <linux/delay.h> 32#include <linux/device.h> 33#include <linux/dmaengine.h> 34#include <linux/dma-mapping.h> 35#include <linux/err.h> 36#include <linux/highmem.h> 37#include <linux/interrupt.h> 38#include <linux/io.h> 39#include <linux/iopoll.h> 40#include <linux/module.h> 41#include <linux/of_address.h> 42#include <linux/of_irq.h> 43#include <linux/platform_device.h> 44#include <linux/scatterlist.h> 45#include <linux/time.h> 46#include <linux/workqueue.h> 47#include <linux/string_choices.h> 48 49#include <linux/mmc/host.h> 50#include <linux/mmc/mmc.h> 51#include <linux/mmc/sd.h> 52 53#define SDCMD 0x00 /* Command to SD card - 16 R/W */ 54#define SDARG 0x04 /* Argument to SD card - 32 R/W */ 55#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 56#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 57#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 58#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 59#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 60#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 61#define SDHSTS 0x20 /* SD host status - 11 R/W */ 62#define SDVDD 0x30 /* SD card power control - 1 R/W */ 63#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 64#define SDHCFG 0x38 /* Host configuration - 2 R/W */ 65#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 66#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 67#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 68 69#define SDCMD_NEW_FLAG 0x8000 70#define SDCMD_FAIL_FLAG 0x4000 71#define SDCMD_BUSYWAIT 0x800 72#define SDCMD_NO_RESPONSE 0x400 73#define SDCMD_LONG_RESPONSE 0x200 74#define SDCMD_WRITE_CMD 0x80 75#define SDCMD_READ_CMD 0x40 76#define SDCMD_CMD_MASK 0x3f 77 78#define SDCDIV_MAX_CDIV 0x7ff 79 80#define SDHSTS_BUSY_IRPT 0x400 81#define SDHSTS_BLOCK_IRPT 0x200 82#define SDHSTS_SDIO_IRPT 0x100 83#define SDHSTS_REW_TIME_OUT 0x80 84#define SDHSTS_CMD_TIME_OUT 0x40 85#define SDHSTS_CRC16_ERROR 0x20 86#define SDHSTS_CRC7_ERROR 0x10 87#define SDHSTS_FIFO_ERROR 0x08 88/* Reserved */ 89/* Reserved */ 90#define SDHSTS_DATA_FLAG 0x01 91 92#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 93 SDHSTS_CRC16_ERROR | \ 94 SDHSTS_REW_TIME_OUT | \ 95 SDHSTS_FIFO_ERROR) 96 97#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 98 SDHSTS_TRANSFER_ERROR_MASK) 99 100#define SDHCFG_BUSY_IRPT_EN BIT(10) 101#define SDHCFG_BLOCK_IRPT_EN BIT(8) 102#define SDHCFG_SDIO_IRPT_EN BIT(5) 103#define SDHCFG_DATA_IRPT_EN BIT(4) 104#define SDHCFG_SLOW_CARD BIT(3) 105#define SDHCFG_WIDE_EXT_BUS BIT(2) 106#define SDHCFG_WIDE_INT_BUS BIT(1) 107#define SDHCFG_REL_CMD_LINE BIT(0) 108 109#define SDVDD_POWER_OFF 0 110#define SDVDD_POWER_ON 1 111 112#define SDEDM_FORCE_DATA_MODE BIT(19) 113#define SDEDM_CLOCK_PULSE BIT(20) 114#define SDEDM_BYPASS BIT(21) 115 116#define SDEDM_WRITE_THRESHOLD_SHIFT 9 117#define SDEDM_READ_THRESHOLD_SHIFT 14 118#define SDEDM_THRESHOLD_MASK 0x1f 119 120#define SDEDM_FSM_MASK 0xf 121#define SDEDM_FSM_IDENTMODE 0x0 122#define SDEDM_FSM_DATAMODE 0x1 123#define SDEDM_FSM_READDATA 0x2 124#define SDEDM_FSM_WRITEDATA 0x3 125#define SDEDM_FSM_READWAIT 0x4 126#define SDEDM_FSM_READCRC 0x5 127#define SDEDM_FSM_WRITECRC 0x6 128#define SDEDM_FSM_WRITEWAIT1 0x7 129#define SDEDM_FSM_POWERDOWN 0x8 130#define SDEDM_FSM_POWERUP 0x9 131#define SDEDM_FSM_WRITESTART1 0xa 132#define SDEDM_FSM_WRITESTART2 0xb 133#define SDEDM_FSM_GENPULSES 0xc 134#define SDEDM_FSM_WRITEWAIT2 0xd 135#define SDEDM_FSM_STARTPOWDOWN 0xf 136 137#define SDDATA_FIFO_WORDS 16 138 139#define FIFO_READ_THRESHOLD 4 140#define FIFO_WRITE_THRESHOLD 4 141#define SDDATA_FIFO_PIO_BURST 8 142 143#define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */ 144 145struct bcm2835_host { 146 spinlock_t lock; 147 struct mutex mutex; 148 149 void __iomem *ioaddr; 150 u32 phys_addr; 151 152 struct clk *clk; 153 struct platform_device *pdev; 154 155 unsigned int clock; /* Current clock speed */ 156 unsigned int max_clk; /* Max possible freq */ 157 struct work_struct dma_work; 158 struct delayed_work timeout_work; /* Timer for timeouts */ 159 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 160 unsigned int blocks; /* remaining PIO blocks */ 161 int irq; /* Device IRQ */ 162 163 u32 ns_per_fifo_word; 164 165 /* cached registers */ 166 u32 hcfg; 167 u32 cdiv; 168 169 struct mmc_request *mrq; /* Current request */ 170 struct mmc_command *cmd; /* Current command */ 171 struct mmc_data *data; /* Current data request */ 172 bool data_complete:1;/* Data finished before cmd */ 173 bool use_busy:1; /* Wait for busy interrupt */ 174 bool use_sbc:1; /* Send CMD23 */ 175 176 /* for threaded irq handler */ 177 bool irq_block; 178 bool irq_busy; 179 bool irq_data; 180 181 /* DMA part */ 182 struct dma_chan *dma_chan_rxtx; 183 struct dma_chan *dma_chan; 184 struct dma_slave_config dma_cfg_rx; 185 struct dma_slave_config dma_cfg_tx; 186 struct dma_async_tx_descriptor *dma_desc; 187 u32 dma_dir; 188 u32 drain_words; 189 struct page *drain_page; 190 u32 drain_offset; 191 bool use_dma; 192}; 193 194static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd, 195 const char *label) 196{ 197 struct device *dev = &host->pdev->dev; 198 199 if (!cmd) 200 return; 201 202 dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", 203 (cmd == host->cmd) ? '>' : ' ', 204 label, cmd->opcode, cmd->arg, cmd->flags, 205 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], 206 cmd->error); 207} 208 209static void bcm2835_dumpregs(struct bcm2835_host *host) 210{ 211 struct mmc_request *mrq = host->mrq; 212 struct device *dev = &host->pdev->dev; 213 214 if (mrq) { 215 bcm2835_dumpcmd(host, mrq->sbc, "sbc"); 216 bcm2835_dumpcmd(host, mrq->cmd, "cmd"); 217 if (mrq->data) { 218 dev_dbg(dev, "data blocks %x blksz %x - err %d\n", 219 mrq->data->blocks, 220 mrq->data->blksz, 221 mrq->data->error); 222 } 223 bcm2835_dumpcmd(host, mrq->stop, "stop"); 224 } 225 226 dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 227 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 228 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 229 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 230 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 231 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 232 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 233 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 234 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 235 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 236 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 237 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 238 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 239 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 240 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 241 dev_dbg(dev, "===========================================\n"); 242} 243 244static void bcm2835_reset_internal(struct bcm2835_host *host) 245{ 246 u32 temp; 247 248 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 249 writel(0, host->ioaddr + SDCMD); 250 writel(0, host->ioaddr + SDARG); 251 writel(0xf00000, host->ioaddr + SDTOUT); 252 writel(0, host->ioaddr + SDCDIV); 253 writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */ 254 writel(0, host->ioaddr + SDHCFG); 255 writel(0, host->ioaddr + SDHBCT); 256 writel(0, host->ioaddr + SDHBLC); 257 258 /* Limit fifo usage due to silicon bug */ 259 temp = readl(host->ioaddr + SDEDM); 260 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 261 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 262 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 263 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 264 writel(temp, host->ioaddr + SDEDM); 265 msleep(20); 266 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 267 msleep(20); 268 host->clock = 0; 269 writel(host->hcfg, host->ioaddr + SDHCFG); 270 writel(host->cdiv, host->ioaddr + SDCDIV); 271} 272 273static void bcm2835_reset(struct mmc_host *mmc) 274{ 275 struct bcm2835_host *host = mmc_priv(mmc); 276 277 if (host->dma_chan) 278 dmaengine_terminate_sync(host->dma_chan); 279 host->dma_chan = NULL; 280 bcm2835_reset_internal(host); 281} 282 283static void bcm2835_finish_command(struct bcm2835_host *host); 284 285static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) 286{ 287 int timediff; 288 u32 alternate_idle; 289 290 alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ? 291 SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; 292 293 timediff = 0; 294 295 while (1) { 296 u32 edm, fsm; 297 298 edm = readl(host->ioaddr + SDEDM); 299 fsm = edm & SDEDM_FSM_MASK; 300 301 if ((fsm == SDEDM_FSM_IDENTMODE) || 302 (fsm == SDEDM_FSM_DATAMODE)) 303 break; 304 if (fsm == alternate_idle) { 305 writel(edm | SDEDM_FORCE_DATA_MODE, 306 host->ioaddr + SDEDM); 307 break; 308 } 309 310 timediff++; 311 if (timediff == 100000) { 312 dev_err(&host->pdev->dev, 313 "wait_transfer_complete - still waiting after %d retries\n", 314 timediff); 315 bcm2835_dumpregs(host); 316 host->mrq->data->error = -ETIMEDOUT; 317 return; 318 } 319 cpu_relax(); 320 } 321} 322 323static void bcm2835_dma_complete(void *param) 324{ 325 struct bcm2835_host *host = param; 326 327 schedule_work(&host->dma_work); 328} 329 330static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 331{ 332 size_t blksize; 333 unsigned long wait_max; 334 335 blksize = host->data->blksz; 336 337 wait_max = jiffies + msecs_to_jiffies(500); 338 339 while (blksize) { 340 int copy_words; 341 u32 hsts = 0; 342 size_t len; 343 u32 *buf; 344 345 if (!sg_miter_next(&host->sg_miter)) { 346 host->data->error = -EINVAL; 347 break; 348 } 349 350 len = min(host->sg_miter.length, blksize); 351 if (len % 4) { 352 host->data->error = -EINVAL; 353 break; 354 } 355 356 blksize -= len; 357 host->sg_miter.consumed = len; 358 359 buf = (u32 *)host->sg_miter.addr; 360 361 copy_words = len / 4; 362 363 while (copy_words) { 364 int burst_words, words; 365 u32 edm; 366 367 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 368 edm = readl(host->ioaddr + SDEDM); 369 if (is_read) 370 words = ((edm >> 4) & 0x1f); 371 else 372 words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f); 373 374 if (words < burst_words) { 375 int fsm_state = (edm & SDEDM_FSM_MASK); 376 struct device *dev = &host->pdev->dev; 377 378 if ((is_read && 379 (fsm_state != SDEDM_FSM_READDATA && 380 fsm_state != SDEDM_FSM_READWAIT && 381 fsm_state != SDEDM_FSM_READCRC)) || 382 (!is_read && 383 (fsm_state != SDEDM_FSM_WRITEDATA && 384 fsm_state != SDEDM_FSM_WRITESTART1 && 385 fsm_state != SDEDM_FSM_WRITESTART2))) { 386 hsts = readl(host->ioaddr + SDHSTS); 387 dev_err(dev, "fsm %x, hsts %08x\n", 388 fsm_state, hsts); 389 if (hsts & SDHSTS_ERROR_MASK) 390 break; 391 } 392 393 if (time_after(jiffies, wait_max)) { 394 dev_err(dev, "PIO %s timeout - EDM %08x\n", 395 str_read_write(is_read), edm); 396 hsts = SDHSTS_REW_TIME_OUT; 397 break; 398 } 399 ndelay((burst_words - words) * 400 host->ns_per_fifo_word); 401 continue; 402 } else if (words > copy_words) { 403 words = copy_words; 404 } 405 406 copy_words -= words; 407 408 while (words) { 409 if (is_read) 410 *(buf++) = readl(host->ioaddr + SDDATA); 411 else 412 writel(*(buf++), host->ioaddr + SDDATA); 413 words--; 414 } 415 } 416 417 if (hsts & SDHSTS_ERROR_MASK) 418 break; 419 } 420 421 sg_miter_stop(&host->sg_miter); 422} 423 424static void bcm2835_transfer_pio(struct bcm2835_host *host) 425{ 426 struct device *dev = &host->pdev->dev; 427 u32 sdhsts; 428 bool is_read; 429 430 is_read = (host->data->flags & MMC_DATA_READ) != 0; 431 bcm2835_transfer_block_pio(host, is_read); 432 433 sdhsts = readl(host->ioaddr + SDHSTS); 434 if (sdhsts & (SDHSTS_CRC16_ERROR | 435 SDHSTS_CRC7_ERROR | 436 SDHSTS_FIFO_ERROR)) { 437 dev_err(dev, "%s transfer error - HSTS %08x\n", 438 str_read_write(is_read), sdhsts); 439 host->data->error = -EILSEQ; 440 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 441 SDHSTS_REW_TIME_OUT))) { 442 dev_err(dev, "%s timeout error - HSTS %08x\n", 443 str_read_write(is_read), sdhsts); 444 host->data->error = -ETIMEDOUT; 445 } 446} 447 448static 449void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data) 450{ 451 int sg_len, dir_data, dir_slave; 452 struct dma_async_tx_descriptor *desc = NULL; 453 struct dma_chan *dma_chan; 454 455 dma_chan = host->dma_chan_rxtx; 456 if (data->flags & MMC_DATA_READ) { 457 dir_data = DMA_FROM_DEVICE; 458 dir_slave = DMA_DEV_TO_MEM; 459 } else { 460 dir_data = DMA_TO_DEVICE; 461 dir_slave = DMA_MEM_TO_DEV; 462 } 463 464 /* The block doesn't manage the FIFO DREQs properly for 465 * multi-block transfers, so don't attempt to DMA the final 466 * few words. Unfortunately this requires the final sg entry 467 * to be trimmed. N.B. This code demands that the overspill 468 * is contained in a single sg entry. 469 */ 470 471 host->drain_words = 0; 472 if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) { 473 struct scatterlist *sg; 474 u32 len; 475 int i; 476 477 len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4, 478 (u32)data->blocks * data->blksz); 479 480 for_each_sg(data->sg, sg, data->sg_len, i) { 481 if (sg_is_last(sg)) { 482 WARN_ON(sg->length < len); 483 sg->length -= len; 484 host->drain_page = sg_page(sg); 485 host->drain_offset = sg->offset + sg->length; 486 } 487 } 488 host->drain_words = len / 4; 489 } 490 491 /* The parameters have already been validated, so this will not fail */ 492 (void)dmaengine_slave_config(dma_chan, 493 (dir_data == DMA_FROM_DEVICE) ? 494 &host->dma_cfg_rx : 495 &host->dma_cfg_tx); 496 497 sg_len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len, 498 dir_data); 499 if (!sg_len) 500 return; 501 502 desc = dmaengine_prep_slave_sg(dma_chan, data->sg, sg_len, dir_slave, 503 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 504 505 if (!desc) { 506 dma_unmap_sg(dma_chan->device->dev, data->sg, data->sg_len, 507 dir_data); 508 return; 509 } 510 511 desc->callback = bcm2835_dma_complete; 512 desc->callback_param = host; 513 host->dma_desc = desc; 514 host->dma_chan = dma_chan; 515 host->dma_dir = dir_data; 516} 517 518static void bcm2835_start_dma(struct bcm2835_host *host) 519{ 520 dmaengine_submit(host->dma_desc); 521 dma_async_issue_pending(host->dma_chan); 522} 523 524static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) 525{ 526 u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | 527 SDHCFG_BUSY_IRPT_EN; 528 529 if (host->dma_desc) { 530 host->hcfg = (host->hcfg & ~all_irqs) | 531 SDHCFG_BUSY_IRPT_EN; 532 } else { 533 host->hcfg = (host->hcfg & ~all_irqs) | 534 SDHCFG_DATA_IRPT_EN | 535 SDHCFG_BUSY_IRPT_EN; 536 } 537 538 writel(host->hcfg, host->ioaddr + SDHCFG); 539} 540 541static 542void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) 543{ 544 struct mmc_data *data = cmd->data; 545 546 WARN_ON(host->data); 547 548 host->data = data; 549 if (!data) 550 return; 551 552 host->data_complete = false; 553 host->data->bytes_xfered = 0; 554 555 if (!host->dma_desc) { 556 /* Use PIO */ 557 int flags = SG_MITER_ATOMIC; 558 559 if (data->flags & MMC_DATA_READ) 560 flags |= SG_MITER_TO_SG; 561 else 562 flags |= SG_MITER_FROM_SG; 563 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 564 host->blocks = data->blocks; 565 } 566 567 bcm2835_set_transfer_irqs(host); 568 569 writel(data->blksz, host->ioaddr + SDHBCT); 570 writel(data->blocks, host->ioaddr + SDHBLC); 571} 572 573static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms) 574{ 575 struct device *dev = &host->pdev->dev; 576 u32 value; 577 int ret; 578 579 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 580 !(value & SDCMD_NEW_FLAG), 1, 10); 581 if (ret == -ETIMEDOUT) 582 /* if it takes a while make poll interval bigger */ 583 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 584 !(value & SDCMD_NEW_FLAG), 585 10, max_ms * 1000); 586 if (ret == -ETIMEDOUT) 587 dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms); 588 589 return value; 590} 591 592static void bcm2835_finish_request(struct bcm2835_host *host) 593{ 594 struct dma_chan *terminate_chan = NULL; 595 struct mmc_request *mrq; 596 597 cancel_delayed_work(&host->timeout_work); 598 599 mrq = host->mrq; 600 601 host->mrq = NULL; 602 host->cmd = NULL; 603 host->data = NULL; 604 605 host->dma_desc = NULL; 606 terminate_chan = host->dma_chan; 607 host->dma_chan = NULL; 608 609 if (terminate_chan) { 610 int err = dmaengine_terminate_all(terminate_chan); 611 612 if (err) 613 dev_err(&host->pdev->dev, 614 "failed to terminate DMA (%d)\n", err); 615 } 616 617 mmc_request_done(mmc_from_priv(host), mrq); 618} 619 620static 621bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd) 622{ 623 struct device *dev = &host->pdev->dev; 624 u32 sdcmd, sdhsts; 625 unsigned long timeout; 626 627 WARN_ON(host->cmd); 628 629 sdcmd = bcm2835_read_wait_sdcmd(host, 100); 630 if (sdcmd & SDCMD_NEW_FLAG) { 631 dev_err(dev, "previous command never completed.\n"); 632 bcm2835_dumpregs(host); 633 cmd->error = -EILSEQ; 634 bcm2835_finish_request(host); 635 return false; 636 } 637 638 if (!cmd->data && cmd->busy_timeout > 9000) 639 timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 640 else 641 timeout = 10 * HZ; 642 schedule_delayed_work(&host->timeout_work, timeout); 643 644 host->cmd = cmd; 645 646 /* Clear any error flags */ 647 sdhsts = readl(host->ioaddr + SDHSTS); 648 if (sdhsts & SDHSTS_ERROR_MASK) 649 writel(sdhsts, host->ioaddr + SDHSTS); 650 651 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 652 dev_err(dev, "unsupported response type!\n"); 653 cmd->error = -EINVAL; 654 bcm2835_finish_request(host); 655 return false; 656 } 657 658 bcm2835_prepare_data(host, cmd); 659 660 writel(cmd->arg, host->ioaddr + SDARG); 661 662 sdcmd = cmd->opcode & SDCMD_CMD_MASK; 663 664 host->use_busy = false; 665 if (!(cmd->flags & MMC_RSP_PRESENT)) { 666 sdcmd |= SDCMD_NO_RESPONSE; 667 } else { 668 if (cmd->flags & MMC_RSP_136) 669 sdcmd |= SDCMD_LONG_RESPONSE; 670 if (cmd->flags & MMC_RSP_BUSY) { 671 sdcmd |= SDCMD_BUSYWAIT; 672 host->use_busy = true; 673 } 674 } 675 676 if (cmd->data) { 677 if (cmd->data->flags & MMC_DATA_WRITE) 678 sdcmd |= SDCMD_WRITE_CMD; 679 if (cmd->data->flags & MMC_DATA_READ) 680 sdcmd |= SDCMD_READ_CMD; 681 } 682 683 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 684 685 return true; 686} 687 688static void bcm2835_transfer_complete(struct bcm2835_host *host) 689{ 690 struct mmc_data *data; 691 692 WARN_ON(!host->data_complete); 693 694 data = host->data; 695 host->data = NULL; 696 697 /* Need to send CMD12 if - 698 * a) open-ended multiblock transfer (no CMD23) 699 * b) error in multiblock transfer 700 */ 701 if (host->mrq->stop && (data->error || !host->use_sbc)) { 702 if (bcm2835_send_command(host, host->mrq->stop)) { 703 /* No busy, so poll for completion */ 704 if (!host->use_busy) 705 bcm2835_finish_command(host); 706 } 707 } else { 708 bcm2835_wait_transfer_complete(host); 709 bcm2835_finish_request(host); 710 } 711} 712 713static void bcm2835_finish_data(struct bcm2835_host *host) 714{ 715 struct device *dev = &host->pdev->dev; 716 struct mmc_data *data; 717 718 data = host->data; 719 720 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 721 writel(host->hcfg, host->ioaddr + SDHCFG); 722 723 data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks); 724 725 host->data_complete = true; 726 727 if (host->cmd) { 728 /* Data managed to finish before the 729 * command completed. Make sure we do 730 * things in the proper order. 731 */ 732 dev_dbg(dev, "Finished early - HSTS %08x\n", 733 readl(host->ioaddr + SDHSTS)); 734 } else { 735 bcm2835_transfer_complete(host); 736 } 737} 738 739static void bcm2835_finish_command(struct bcm2835_host *host) 740{ 741 struct device *dev = &host->pdev->dev; 742 struct mmc_command *cmd = host->cmd; 743 u32 sdcmd; 744 745 sdcmd = bcm2835_read_wait_sdcmd(host, 100); 746 747 /* Check for errors */ 748 if (sdcmd & SDCMD_NEW_FLAG) { 749 dev_err(dev, "command never completed.\n"); 750 bcm2835_dumpregs(host); 751 host->cmd->error = -EIO; 752 bcm2835_finish_request(host); 753 return; 754 } else if (sdcmd & SDCMD_FAIL_FLAG) { 755 u32 sdhsts = readl(host->ioaddr + SDHSTS); 756 757 /* Clear the errors */ 758 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 759 760 if (!(sdhsts & SDHSTS_CRC7_ERROR) || 761 (host->cmd->opcode != MMC_SEND_OP_COND)) { 762 u32 edm, fsm; 763 764 if (sdhsts & SDHSTS_CMD_TIME_OUT) { 765 host->cmd->error = -ETIMEDOUT; 766 } else { 767 dev_err(dev, "unexpected command %d error\n", 768 host->cmd->opcode); 769 bcm2835_dumpregs(host); 770 host->cmd->error = -EILSEQ; 771 } 772 edm = readl(host->ioaddr + SDEDM); 773 fsm = edm & SDEDM_FSM_MASK; 774 if (fsm == SDEDM_FSM_READWAIT || 775 fsm == SDEDM_FSM_WRITESTART1) 776 /* Kick the FSM out of its wait */ 777 writel(edm | SDEDM_FORCE_DATA_MODE, 778 host->ioaddr + SDEDM); 779 bcm2835_finish_request(host); 780 return; 781 } 782 } 783 784 if (cmd->flags & MMC_RSP_PRESENT) { 785 if (cmd->flags & MMC_RSP_136) { 786 int i; 787 788 for (i = 0; i < 4; i++) { 789 cmd->resp[3 - i] = 790 readl(host->ioaddr + SDRSP0 + i * 4); 791 } 792 } else { 793 cmd->resp[0] = readl(host->ioaddr + SDRSP0); 794 } 795 } 796 797 if (cmd == host->mrq->sbc) { 798 /* Finished CMD23, now send actual command. */ 799 host->cmd = NULL; 800 if (bcm2835_send_command(host, host->mrq->cmd)) { 801 if (host->data && host->dma_desc) 802 /* DMA transfer starts now, PIO starts 803 * after irq 804 */ 805 bcm2835_start_dma(host); 806 807 if (!host->use_busy) 808 bcm2835_finish_command(host); 809 } 810 } else if (cmd == host->mrq->stop) { 811 /* Finished CMD12 */ 812 bcm2835_finish_request(host); 813 } else { 814 /* Processed actual command. */ 815 host->cmd = NULL; 816 if (!host->data) 817 bcm2835_finish_request(host); 818 else if (host->data_complete) 819 bcm2835_transfer_complete(host); 820 } 821} 822 823static void bcm2835_timeout(struct work_struct *work) 824{ 825 struct delayed_work *d = to_delayed_work(work); 826 struct bcm2835_host *host = 827 container_of(d, struct bcm2835_host, timeout_work); 828 struct device *dev = &host->pdev->dev; 829 830 mutex_lock(&host->mutex); 831 832 if (host->mrq) { 833 dev_err(dev, "timeout waiting for hardware interrupt.\n"); 834 bcm2835_dumpregs(host); 835 836 bcm2835_reset(mmc_from_priv(host)); 837 838 if (host->data) { 839 host->data->error = -ETIMEDOUT; 840 bcm2835_finish_data(host); 841 } else { 842 if (host->cmd) 843 host->cmd->error = -ETIMEDOUT; 844 else 845 host->mrq->cmd->error = -ETIMEDOUT; 846 847 bcm2835_finish_request(host); 848 } 849 } 850 851 mutex_unlock(&host->mutex); 852} 853 854static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 855{ 856 struct device *dev = &host->pdev->dev; 857 858 if (!(intmask & SDHSTS_ERROR_MASK)) 859 return false; 860 861 if (!host->cmd) 862 return true; 863 864 dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask); 865 if (intmask & SDHSTS_CRC7_ERROR) { 866 host->cmd->error = -EILSEQ; 867 } else if (intmask & (SDHSTS_CRC16_ERROR | 868 SDHSTS_FIFO_ERROR)) { 869 if (host->mrq->data) 870 host->mrq->data->error = -EILSEQ; 871 else 872 host->cmd->error = -EILSEQ; 873 } else if (intmask & SDHSTS_REW_TIME_OUT) { 874 if (host->mrq->data) 875 host->mrq->data->error = -ETIMEDOUT; 876 else 877 host->cmd->error = -ETIMEDOUT; 878 } else if (intmask & SDHSTS_CMD_TIME_OUT) { 879 host->cmd->error = -ETIMEDOUT; 880 } 881 bcm2835_dumpregs(host); 882 return true; 883} 884 885static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 886{ 887 if (!host->data) 888 return; 889 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 890 host->data->error = -EILSEQ; 891 if (intmask & SDHSTS_REW_TIME_OUT) 892 host->data->error = -ETIMEDOUT; 893} 894 895static void bcm2835_busy_irq(struct bcm2835_host *host) 896{ 897 if (WARN_ON(!host->cmd)) { 898 bcm2835_dumpregs(host); 899 return; 900 } 901 902 if (WARN_ON(!host->use_busy)) { 903 bcm2835_dumpregs(host); 904 return; 905 } 906 host->use_busy = false; 907 908 bcm2835_finish_command(host); 909} 910 911static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) 912{ 913 /* There are no dedicated data/space available interrupt 914 * status bits, so it is necessary to use the single shared 915 * data/space available FIFO status bits. It is therefore not 916 * an error to get here when there is no data transfer in 917 * progress. 918 */ 919 if (!host->data) 920 return; 921 922 bcm2835_check_data_error(host, intmask); 923 if (host->data->error) 924 goto finished; 925 926 if (host->data->flags & MMC_DATA_WRITE) { 927 /* Use the block interrupt for writes after the first block */ 928 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); 929 host->hcfg |= SDHCFG_BLOCK_IRPT_EN; 930 writel(host->hcfg, host->ioaddr + SDHCFG); 931 bcm2835_transfer_pio(host); 932 } else { 933 bcm2835_transfer_pio(host); 934 host->blocks--; 935 if ((host->blocks == 0) || host->data->error) 936 goto finished; 937 } 938 return; 939 940finished: 941 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 942 writel(host->hcfg, host->ioaddr + SDHCFG); 943} 944 945static void bcm2835_data_threaded_irq(struct bcm2835_host *host) 946{ 947 if (!host->data) 948 return; 949 if ((host->blocks == 0) || host->data->error) 950 bcm2835_finish_data(host); 951} 952 953static void bcm2835_block_irq(struct bcm2835_host *host) 954{ 955 if (WARN_ON(!host->data)) { 956 bcm2835_dumpregs(host); 957 return; 958 } 959 960 if (!host->dma_desc) { 961 WARN_ON(!host->blocks); 962 if (host->data->error || (--host->blocks == 0)) 963 bcm2835_finish_data(host); 964 else 965 bcm2835_transfer_pio(host); 966 } else if (host->data->flags & MMC_DATA_WRITE) { 967 bcm2835_finish_data(host); 968 } 969} 970 971static irqreturn_t bcm2835_irq(int irq, void *dev_id) 972{ 973 irqreturn_t result = IRQ_NONE; 974 struct bcm2835_host *host = dev_id; 975 u32 intmask; 976 977 spin_lock(&host->lock); 978 979 intmask = readl(host->ioaddr + SDHSTS); 980 981 writel(SDHSTS_BUSY_IRPT | 982 SDHSTS_BLOCK_IRPT | 983 SDHSTS_SDIO_IRPT | 984 SDHSTS_DATA_FLAG, 985 host->ioaddr + SDHSTS); 986 987 if (intmask & SDHSTS_BLOCK_IRPT) { 988 bcm2835_check_data_error(host, intmask); 989 host->irq_block = true; 990 result = IRQ_WAKE_THREAD; 991 } 992 993 if (intmask & SDHSTS_BUSY_IRPT) { 994 if (!bcm2835_check_cmd_error(host, intmask)) { 995 host->irq_busy = true; 996 result = IRQ_WAKE_THREAD; 997 } else { 998 result = IRQ_HANDLED; 999 } 1000 } 1001 1002 /* There is no true data interrupt status bit, so it is 1003 * necessary to qualify the data flag with the interrupt 1004 * enable bit. 1005 */ 1006 if ((intmask & SDHSTS_DATA_FLAG) && 1007 (host->hcfg & SDHCFG_DATA_IRPT_EN)) { 1008 bcm2835_data_irq(host, intmask); 1009 host->irq_data = true; 1010 result = IRQ_WAKE_THREAD; 1011 } 1012 1013 spin_unlock(&host->lock); 1014 1015 return result; 1016} 1017 1018static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) 1019{ 1020 struct bcm2835_host *host = dev_id; 1021 unsigned long flags; 1022 bool block, busy, data; 1023 1024 spin_lock_irqsave(&host->lock, flags); 1025 1026 block = host->irq_block; 1027 busy = host->irq_busy; 1028 data = host->irq_data; 1029 host->irq_block = false; 1030 host->irq_busy = false; 1031 host->irq_data = false; 1032 1033 spin_unlock_irqrestore(&host->lock, flags); 1034 1035 mutex_lock(&host->mutex); 1036 1037 if (block) 1038 bcm2835_block_irq(host); 1039 if (busy) 1040 bcm2835_busy_irq(host); 1041 if (data) 1042 bcm2835_data_threaded_irq(host); 1043 1044 mutex_unlock(&host->mutex); 1045 1046 return IRQ_HANDLED; 1047} 1048 1049static void bcm2835_dma_complete_work(struct work_struct *work) 1050{ 1051 struct bcm2835_host *host = 1052 container_of(work, struct bcm2835_host, dma_work); 1053 struct mmc_data *data; 1054 1055 mutex_lock(&host->mutex); 1056 1057 data = host->data; 1058 1059 if (host->dma_chan) { 1060 dma_unmap_sg(host->dma_chan->device->dev, 1061 data->sg, data->sg_len, 1062 host->dma_dir); 1063 1064 host->dma_chan = NULL; 1065 } 1066 1067 if (host->drain_words) { 1068 void *page; 1069 u32 *buf; 1070 1071 if (host->drain_offset & PAGE_MASK) { 1072 host->drain_page += host->drain_offset >> PAGE_SHIFT; 1073 host->drain_offset &= ~PAGE_MASK; 1074 } 1075 page = kmap_local_page(host->drain_page); 1076 buf = page + host->drain_offset; 1077 1078 while (host->drain_words) { 1079 u32 edm = readl(host->ioaddr + SDEDM); 1080 1081 if ((edm >> 4) & 0x1f) 1082 *(buf++) = readl(host->ioaddr + SDDATA); 1083 host->drain_words--; 1084 } 1085 1086 kunmap_local(page); 1087 } 1088 1089 bcm2835_finish_data(host); 1090 1091 mutex_unlock(&host->mutex); 1092} 1093 1094static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 1095{ 1096 struct mmc_host *mmc = mmc_from_priv(host); 1097 int div; 1098 1099 /* The SDCDIV register has 11 bits, and holds (div - 2). But 1100 * in data mode the max is 50MHz wihout a minimum, and only 1101 * the bottom 3 bits are used. Since the switch over is 1102 * automatic (unless we have marked the card as slow...), 1103 * chosen values have to make sense in both modes. Ident mode 1104 * must be 100-400KHz, so can range check the requested 1105 * clock. CMD15 must be used to return to data mode, so this 1106 * can be monitored. 1107 * 1108 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 1109 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 1110 * 1111 * 623->400KHz/27.8MHz 1112 * reset value (507)->491159/50MHz 1113 * 1114 * BUT, the 3-bit clock divisor in data mode is too small if 1115 * the core clock is higher than 250MHz, so instead use the 1116 * SLOW_CARD configuration bit to force the use of the ident 1117 * clock divisor at all times. 1118 */ 1119 1120 if (clock < 100000) { 1121 /* Can't stop the clock, but make it as slow as possible 1122 * to show willing 1123 */ 1124 host->cdiv = SDCDIV_MAX_CDIV; 1125 writel(host->cdiv, host->ioaddr + SDCDIV); 1126 return; 1127 } 1128 1129 div = host->max_clk / clock; 1130 if (div < 2) 1131 div = 2; 1132 if ((host->max_clk / div) > clock) 1133 div++; 1134 div -= 2; 1135 1136 if (div > SDCDIV_MAX_CDIV) 1137 div = SDCDIV_MAX_CDIV; 1138 1139 clock = host->max_clk / (div + 2); 1140 mmc->actual_clock = clock; 1141 1142 /* Calibrate some delays */ 1143 1144 host->ns_per_fifo_word = (1000000000 / clock) * 1145 ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32); 1146 1147 host->cdiv = div; 1148 writel(host->cdiv, host->ioaddr + SDCDIV); 1149 1150 /* Set the timeout to 500ms */ 1151 writel(mmc->actual_clock / 2, host->ioaddr + SDTOUT); 1152} 1153 1154static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq) 1155{ 1156 struct bcm2835_host *host = mmc_priv(mmc); 1157 struct device *dev = &host->pdev->dev; 1158 u32 edm, fsm; 1159 1160 /* Reset the error statuses in case this is a retry */ 1161 if (mrq->sbc) 1162 mrq->sbc->error = 0; 1163 if (mrq->cmd) 1164 mrq->cmd->error = 0; 1165 if (mrq->data) 1166 mrq->data->error = 0; 1167 if (mrq->stop) 1168 mrq->stop->error = 0; 1169 1170 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 1171 dev_err(dev, "unsupported block size (%d bytes)\n", 1172 mrq->data->blksz); 1173 1174 if (mrq->cmd) 1175 mrq->cmd->error = -EINVAL; 1176 1177 mmc_request_done(mmc, mrq); 1178 return; 1179 } 1180 1181 mutex_lock(&host->mutex); 1182 1183 WARN_ON(host->mrq); 1184 host->mrq = mrq; 1185 1186 edm = readl(host->ioaddr + SDEDM); 1187 fsm = edm & SDEDM_FSM_MASK; 1188 1189 if ((fsm != SDEDM_FSM_IDENTMODE) && 1190 (fsm != SDEDM_FSM_DATAMODE)) { 1191 dev_err(dev, "previous command (%d) not complete (EDM %08x)\n", 1192 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, 1193 edm); 1194 bcm2835_dumpregs(host); 1195 1196 if (mrq->cmd) 1197 mrq->cmd->error = -EILSEQ; 1198 1199 bcm2835_finish_request(host); 1200 mutex_unlock(&host->mutex); 1201 return; 1202 } 1203 1204 if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD)) 1205 bcm2835_prepare_dma(host, mrq->data); 1206 1207 host->use_sbc = !!mrq->sbc && host->mrq->data && 1208 (host->mrq->data->flags & MMC_DATA_READ); 1209 if (host->use_sbc) { 1210 if (bcm2835_send_command(host, mrq->sbc)) { 1211 if (!host->use_busy) 1212 bcm2835_finish_command(host); 1213 } 1214 } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) { 1215 if (host->data && host->dma_desc) { 1216 /* DMA transfer starts now, PIO starts after irq */ 1217 bcm2835_start_dma(host); 1218 } 1219 1220 if (!host->use_busy) 1221 bcm2835_finish_command(host); 1222 } 1223 1224 mutex_unlock(&host->mutex); 1225} 1226 1227static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1228{ 1229 struct bcm2835_host *host = mmc_priv(mmc); 1230 1231 mutex_lock(&host->mutex); 1232 1233 if (!ios->clock || ios->clock != host->clock) { 1234 bcm2835_set_clock(host, ios->clock); 1235 host->clock = ios->clock; 1236 } 1237 1238 /* set bus width */ 1239 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 1240 if (ios->bus_width == MMC_BUS_WIDTH_4) 1241 host->hcfg |= SDHCFG_WIDE_EXT_BUS; 1242 1243 host->hcfg |= SDHCFG_WIDE_INT_BUS; 1244 1245 /* Disable clever clock switching, to cope with fast core clocks */ 1246 host->hcfg |= SDHCFG_SLOW_CARD; 1247 1248 writel(host->hcfg, host->ioaddr + SDHCFG); 1249 1250 mutex_unlock(&host->mutex); 1251} 1252 1253static const struct mmc_host_ops bcm2835_ops = { 1254 .request = bcm2835_request, 1255 .set_ios = bcm2835_set_ios, 1256 .card_hw_reset = bcm2835_reset, 1257}; 1258 1259static int bcm2835_add_host(struct bcm2835_host *host) 1260{ 1261 struct mmc_host *mmc = mmc_from_priv(host); 1262 struct device *dev = &host->pdev->dev; 1263 char pio_limit_string[20]; 1264 int ret; 1265 1266 if (!mmc->f_max || mmc->f_max > host->max_clk) 1267 mmc->f_max = host->max_clk; 1268 mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; 1269 1270 mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000); 1271 1272 dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n", 1273 mmc->f_max, mmc->f_min, mmc->max_busy_timeout); 1274 1275 /* host controller capabilities */ 1276 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 1277 MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_CMD23; 1278 1279 spin_lock_init(&host->lock); 1280 mutex_init(&host->mutex); 1281 1282 if (!host->dma_chan_rxtx) { 1283 dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n"); 1284 host->use_dma = false; 1285 } else { 1286 host->use_dma = true; 1287 1288 host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1289 host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1290 host->dma_cfg_tx.direction = DMA_MEM_TO_DEV; 1291 host->dma_cfg_tx.src_addr = 0; 1292 host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA; 1293 1294 host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1295 host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1296 host->dma_cfg_rx.direction = DMA_DEV_TO_MEM; 1297 host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA; 1298 host->dma_cfg_rx.dst_addr = 0; 1299 1300 if (dmaengine_slave_config(host->dma_chan_rxtx, 1301 &host->dma_cfg_tx) != 0 || 1302 dmaengine_slave_config(host->dma_chan_rxtx, 1303 &host->dma_cfg_rx) != 0) 1304 host->use_dma = false; 1305 } 1306 1307 mmc->max_segs = 128; 1308 mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev)); 1309 mmc->max_seg_size = mmc->max_req_size; 1310 mmc->max_blk_size = 1024; 1311 mmc->max_blk_count = 65535; 1312 1313 /* report supported voltage ranges */ 1314 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1315 1316 INIT_WORK(&host->dma_work, bcm2835_dma_complete_work); 1317 INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout); 1318 1319 /* Set interrupt enables */ 1320 host->hcfg = SDHCFG_BUSY_IRPT_EN; 1321 1322 bcm2835_reset_internal(host); 1323 1324 ret = request_threaded_irq(host->irq, bcm2835_irq, 1325 bcm2835_threaded_irq, 1326 0, mmc_hostname(mmc), host); 1327 if (ret) { 1328 dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret); 1329 return ret; 1330 } 1331 1332 ret = mmc_add_host(mmc); 1333 if (ret) { 1334 free_irq(host->irq, host); 1335 return ret; 1336 } 1337 1338 pio_limit_string[0] = '\0'; 1339 if (host->use_dma && (PIO_THRESHOLD > 0)) 1340 sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD); 1341 dev_info(dev, "loaded - DMA %s%s\n", 1342 host->use_dma ? "enabled" : "disabled", pio_limit_string); 1343 1344 return 0; 1345} 1346 1347static int bcm2835_suspend(struct device *dev) 1348{ 1349 struct bcm2835_host *host = dev_get_drvdata(dev); 1350 1351 clk_disable_unprepare(host->clk); 1352 1353 return 0; 1354} 1355 1356static int bcm2835_resume(struct device *dev) 1357{ 1358 struct bcm2835_host *host = dev_get_drvdata(dev); 1359 1360 return clk_prepare_enable(host->clk); 1361} 1362 1363static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pm_ops, bcm2835_suspend, 1364 bcm2835_resume); 1365 1366static int bcm2835_probe(struct platform_device *pdev) 1367{ 1368 struct device *dev = &pdev->dev; 1369 struct bcm2835_host *host; 1370 struct mmc_host *mmc; 1371 const __be32 *regaddr_p; 1372 int ret; 1373 1374 dev_dbg(dev, "%s\n", __func__); 1375 mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 1376 if (!mmc) 1377 return -ENOMEM; 1378 1379 mmc->ops = &bcm2835_ops; 1380 host = mmc_priv(mmc); 1381 host->pdev = pdev; 1382 spin_lock_init(&host->lock); 1383 1384 host->ioaddr = devm_platform_ioremap_resource(pdev, 0); 1385 if (IS_ERR(host->ioaddr)) { 1386 ret = PTR_ERR(host->ioaddr); 1387 goto err; 1388 } 1389 1390 /* Parse OF address directly to get the physical address for 1391 * DMA to our registers. 1392 */ 1393 regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL); 1394 if (!regaddr_p) { 1395 dev_err(dev, "Can't get phys address\n"); 1396 ret = -EINVAL; 1397 goto err; 1398 } 1399 1400 host->phys_addr = be32_to_cpup(regaddr_p); 1401 1402 host->dma_chan = NULL; 1403 host->dma_desc = NULL; 1404 1405 host->dma_chan_rxtx = dma_request_chan(dev, "rx-tx"); 1406 if (IS_ERR(host->dma_chan_rxtx)) { 1407 ret = PTR_ERR(host->dma_chan_rxtx); 1408 host->dma_chan_rxtx = NULL; 1409 1410 if (ret == -EPROBE_DEFER) 1411 goto err; 1412 1413 /* Ignore errors to fall back to PIO mode */ 1414 } 1415 1416 host->irq = platform_get_irq(pdev, 0); 1417 if (host->irq < 0) { 1418 ret = host->irq; 1419 goto err; 1420 } 1421 1422 ret = mmc_of_parse(mmc); 1423 if (ret) 1424 goto err; 1425 1426 host->clk = devm_clk_get(dev, NULL); 1427 if (IS_ERR(host->clk)) { 1428 ret = dev_err_probe(dev, PTR_ERR(host->clk), "could not get clk\n"); 1429 goto err; 1430 } 1431 1432 ret = clk_prepare_enable(host->clk); 1433 if (ret) 1434 goto err; 1435 1436 host->max_clk = clk_get_rate(host->clk); 1437 1438 ret = bcm2835_add_host(host); 1439 if (ret) 1440 goto err_clk; 1441 1442 platform_set_drvdata(pdev, host); 1443 1444 dev_dbg(dev, "%s -> OK\n", __func__); 1445 1446 return 0; 1447 1448err_clk: 1449 clk_disable_unprepare(host->clk); 1450err: 1451 dev_dbg(dev, "%s -> err %d\n", __func__, ret); 1452 if (host->dma_chan_rxtx) 1453 dma_release_channel(host->dma_chan_rxtx); 1454 1455 return ret; 1456} 1457 1458static void bcm2835_remove(struct platform_device *pdev) 1459{ 1460 struct bcm2835_host *host = platform_get_drvdata(pdev); 1461 struct mmc_host *mmc = mmc_from_priv(host); 1462 1463 mmc_remove_host(mmc); 1464 1465 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 1466 1467 free_irq(host->irq, host); 1468 1469 cancel_work_sync(&host->dma_work); 1470 cancel_delayed_work_sync(&host->timeout_work); 1471 1472 clk_disable_unprepare(host->clk); 1473 1474 if (host->dma_chan_rxtx) 1475 dma_release_channel(host->dma_chan_rxtx); 1476} 1477 1478static const struct of_device_id bcm2835_match[] = { 1479 { .compatible = "brcm,bcm2835-sdhost" }, 1480 { } 1481}; 1482MODULE_DEVICE_TABLE(of, bcm2835_match); 1483 1484static struct platform_driver bcm2835_driver = { 1485 .probe = bcm2835_probe, 1486 .remove = bcm2835_remove, 1487 .driver = { 1488 .name = "sdhost-bcm2835", 1489 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1490 .of_match_table = bcm2835_match, 1491 .pm = pm_ptr(&bcm2835_pm_ops), 1492 }, 1493}; 1494module_platform_driver(bcm2835_driver); 1495 1496MODULE_ALIAS("platform:sdhost-bcm2835"); 1497MODULE_DESCRIPTION("BCM2835 SDHost driver"); 1498MODULE_LICENSE("GPL v2"); 1499MODULE_AUTHOR("Phil Elwell");
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