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atmel-mci.c
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linux-6.19.14/drivers/mmc/host/atmel-mci.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Atmel MultiMedia Card Interface driver 4 * 5 * Copyright (C) 2004-2008 Atmel Corporation 6 */ 7#include <linux/blkdev.h> 8#include <linux/clk.h> 9#include <linux/debugfs.h> 10#include <linux/device.h> 11#include <linux/dmaengine.h> 12#include <linux/dma-mapping.h> 13#include <linux/err.h> 14#include <linux/init.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/ioport.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/irq.h> 21#include <linux/gpio/consumer.h> 22#include <linux/platform_device.h> 23#include <linux/scatterlist.h> 24#include <linux/seq_file.h> 25#include <linux/slab.h> 26#include <linux/stat.h> 27#include <linux/types.h> 28 29#include <linux/mmc/host.h> 30#include <linux/mmc/sdio.h> 31 32#include <linux/atmel_pdc.h> 33#include <linux/pm.h> 34#include <linux/pm_runtime.h> 35#include <linux/pinctrl/consumer.h> 36#include <linux/workqueue.h> 37 38#include <asm/cacheflush.h> 39#include <asm/io.h> 40#include <linux/unaligned.h> 41#include <linux/string_choices.h> 42 43#define ATMCI_MAX_NR_SLOTS 2 44 45/* 46 * Superset of MCI IP registers integrated in Atmel AT91 Processor 47 * Registers and bitfields marked with [2] are only available in MCI2 48 */ 49 50/* MCI Register Definitions */ 51#define ATMCI_CR 0x0000 /* Control */ 52#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */ 53#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */ 54#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */ 55#define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */ 56#define ATMCI_CR_SWRST BIT(7) /* Software Reset */ 57#define ATMCI_MR 0x0004 /* Mode */ 58#define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ 59#define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */ 60#define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */ 61#define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */ 62#define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */ 63#define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */ 64#define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */ 65#define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */ 66#define ATMCI_DTOR 0x0008 /* Data Timeout */ 67#define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ 68#define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ 69#define ATMCI_SDCR 0x000c /* SD Card / SDIO */ 70#define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */ 71#define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */ 72#define ATMCI_SDCSEL_MASK (3 << 0) 73#define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */ 74#define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */ 75#define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */ 76#define ATMCI_SDCBUS_MASK (3 << 6) 77#define ATMCI_ARGR 0x0010 /* Command Argument */ 78#define ATMCI_CMDR 0x0014 /* Command */ 79#define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */ 80#define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */ 81#define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */ 82#define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */ 83#define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */ 84#define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */ 85#define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */ 86#define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */ 87#define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */ 88#define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */ 89#define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */ 90#define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */ 91#define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */ 92#define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */ 93#define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */ 94#define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */ 95#define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */ 96#define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */ 97#define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */ 98#define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */ 99#define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */ 100#define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */ 101#define ATMCI_BLKR 0x0018 /* Block */ 102#define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */ 103#define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ 104#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */ 105#define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */ 106#define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */ 107#define ATMCI_RSPR 0x0020 /* Response 0 */ 108#define ATMCI_RSPR1 0x0024 /* Response 1 */ 109#define ATMCI_RSPR2 0x0028 /* Response 2 */ 110#define ATMCI_RSPR3 0x002c /* Response 3 */ 111#define ATMCI_RDR 0x0030 /* Receive Data */ 112#define ATMCI_TDR 0x0034 /* Transmit Data */ 113#define ATMCI_SR 0x0040 /* Status */ 114#define ATMCI_IER 0x0044 /* Interrupt Enable */ 115#define ATMCI_IDR 0x0048 /* Interrupt Disable */ 116#define ATMCI_IMR 0x004c /* Interrupt Mask */ 117#define ATMCI_CMDRDY BIT(0) /* Command Ready */ 118#define ATMCI_RXRDY BIT(1) /* Receiver Ready */ 119#define ATMCI_TXRDY BIT(2) /* Transmitter Ready */ 120#define ATMCI_BLKE BIT(3) /* Data Block Ended */ 121#define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */ 122#define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */ 123#define ATMCI_ENDRX BIT(6) /* End of RX Buffer */ 124#define ATMCI_ENDTX BIT(7) /* End of TX Buffer */ 125#define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */ 126#define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */ 127#define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */ 128#define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */ 129#define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */ 130#define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */ 131#define ATMCI_RINDE BIT(16) /* Response Index Error */ 132#define ATMCI_RDIRE BIT(17) /* Response Direction Error */ 133#define ATMCI_RCRCE BIT(18) /* Response CRC Error */ 134#define ATMCI_RENDE BIT(19) /* Response End Bit Error */ 135#define ATMCI_RTOE BIT(20) /* Response Time-Out Error */ 136#define ATMCI_DCRCE BIT(21) /* Data CRC Error */ 137#define ATMCI_DTOE BIT(22) /* Data Time-Out Error */ 138#define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */ 139#define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */ 140#define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */ 141#define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */ 142#define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */ 143#define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */ 144#define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */ 145#define ATMCI_OVRE BIT(30) /* RX Overrun Error */ 146#define ATMCI_UNRE BIT(31) /* TX Underrun Error */ 147#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */ 148#define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */ 149#define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */ 150#define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */ 151#define ATMCI_CFG 0x0054 /* Configuration[2] */ 152#define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */ 153#define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */ 154#define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */ 155#define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */ 156#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */ 157#define ATMCI_WP_EN BIT(0) /* WP Enable */ 158#define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */ 159#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */ 160#define ATMCI_GET_WP_VS(x) ((x) & 0x0f) 161#define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff) 162#define ATMCI_VERSION 0x00FC /* Version */ 163#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */ 164 165/* This is not including the FIFO Aperture on MCI2 */ 166#define ATMCI_REGS_SIZE 0x100 167 168/* Register access macros */ 169#define atmci_readl(port, reg) \ 170 __raw_readl((port)->regs + reg) 171#define atmci_writel(port, reg, value) \ 172 __raw_writel((value), (port)->regs + reg) 173 174#define ATMCI_CMD_TIMEOUT_MS 2000 175#define AUTOSUSPEND_DELAY 50 176 177#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) 178#define ATMCI_DMA_THRESHOLD 16 179 180enum { 181 EVENT_CMD_RDY = 0, 182 EVENT_XFER_COMPLETE, 183 EVENT_NOTBUSY, 184 EVENT_DATA_ERROR, 185}; 186 187enum atmel_mci_state { 188 STATE_IDLE = 0, 189 STATE_SENDING_CMD, 190 STATE_DATA_XFER, 191 STATE_WAITING_NOTBUSY, 192 STATE_SENDING_STOP, 193 STATE_END_REQUEST, 194}; 195 196enum atmci_xfer_dir { 197 XFER_RECEIVE = 0, 198 XFER_TRANSMIT, 199}; 200 201enum atmci_pdc_buf { 202 PDC_FIRST_BUF = 0, 203 PDC_SECOND_BUF, 204}; 205 206/** 207 * struct mci_slot_pdata - board-specific per-slot configuration 208 * @bus_width: Number of data lines wired up the slot 209 * @detect_pin: GPIO pin wired to the card detect switch 210 * @wp_pin: GPIO pin wired to the write protect sensor 211 * @non_removable: The slot is not removable, only detect once 212 * 213 * If a given slot is not present on the board, @bus_width should be 214 * set to 0. The other fields are ignored in this case. 215 * 216 * Any pins that aren't available should be set to a negative value. 217 * 218 * Note that support for multiple slots is experimental -- some cards 219 * might get upset if we don't get the clock management exactly right. 220 * But in most cases, it should work just fine. 221 */ 222struct mci_slot_pdata { 223 unsigned int bus_width; 224 struct gpio_desc *detect_pin; 225 struct gpio_desc *wp_pin; 226 bool non_removable; 227}; 228 229struct atmel_mci_caps { 230 bool has_dma_conf_reg; 231 bool has_pdc; 232 bool has_cfg_reg; 233 bool has_cstor_reg; 234 bool has_highspeed; 235 bool has_rwproof; 236 bool has_odd_clk_div; 237 bool has_bad_data_ordering; 238 bool need_reset_after_xfer; 239 bool need_blksz_mul_4; 240 bool need_notbusy_for_read_ops; 241}; 242 243struct atmel_mci_dma { 244 struct dma_chan *chan; 245 struct dma_async_tx_descriptor *data_desc; 246}; 247 248/** 249 * struct atmel_mci - MMC controller state shared between all slots 250 * @lock: Spinlock protecting the queue and associated data. 251 * @regs: Pointer to MMIO registers. 252 * @sg: Scatterlist entry currently being processed by PIO or PDC code. 253 * @sg_len: Size of the scatterlist 254 * @pio_offset: Offset into the current scatterlist entry. 255 * @buffer: Buffer used if we don't have the r/w proof capability. We 256 * don't have the time to switch pdc buffers so we have to use only 257 * one buffer for the full transaction. 258 * @buf_size: size of the buffer. 259 * @buf_phys_addr: buffer address needed for pdc. 260 * @cur_slot: The slot which is currently using the controller. 261 * @mrq: The request currently being processed on @cur_slot, 262 * or NULL if the controller is idle. 263 * @cmd: The command currently being sent to the card, or NULL. 264 * @data: The data currently being transferred, or NULL if no data 265 * transfer is in progress. 266 * @data_size: just data->blocks * data->blksz. 267 * @dma: DMA client state. 268 * @data_chan: DMA channel being used for the current data transfer. 269 * @dma_conf: Configuration for the DMA slave 270 * @cmd_status: Snapshot of SR taken upon completion of the current 271 * command. Only valid when EVENT_CMD_COMPLETE is pending. 272 * @data_status: Snapshot of SR taken upon completion of the current 273 * data transfer. Only valid when EVENT_DATA_COMPLETE or 274 * EVENT_DATA_ERROR is pending. 275 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 276 * to be sent. 277 * @bh_work: Work running the request state machine. 278 * @pending_events: Bitmask of events flagged by the interrupt handler 279 * to be processed by the work. 280 * @completed_events: Bitmask of events which the state machine has 281 * processed. 282 * @state: Work state. 283 * @queue: List of slots waiting for access to the controller. 284 * @need_clock_update: Update the clock rate before the next request. 285 * @need_reset: Reset controller before next request. 286 * @timer: Timer to balance the data timeout error flag which cannot rise. 287 * @mode_reg: Value of the MR register. 288 * @cfg_reg: Value of the CFG register. 289 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 290 * rate and timeout calculations. 291 * @mapbase: Physical address of the MMIO registers. 292 * @mck: The peripheral bus clock hooked up to the MMC controller. 293 * @dev: Device associated with the MMC controller. 294 * @pdata: Per-slot configuration data. 295 * @slot: Slots sharing this MMC controller. 296 * @caps: MCI capabilities depending on MCI version. 297 * @prepare_data: function to setup MCI before data transfer which 298 * depends on MCI capabilities. 299 * @submit_data: function to start data transfer which depends on MCI 300 * capabilities. 301 * @stop_transfer: function to stop data transfer which depends on MCI 302 * capabilities. 303 * 304 * Locking 305 * ======= 306 * 307 * @lock is a softirq-safe spinlock protecting @queue as well as 308 * @cur_slot, @mrq and @state. These must always be updated 309 * at the same time while holding @lock. 310 * 311 * @lock also protects mode_reg and need_clock_update since these are 312 * used to synchronize mode register updates with the queue 313 * processing. 314 * 315 * The @mrq field of struct atmel_mci_slot is also protected by @lock, 316 * and must always be written at the same time as the slot is added to 317 * @queue. 318 * 319 * @pending_events and @completed_events are accessed using atomic bit 320 * operations, so they don't need any locking. 321 * 322 * None of the fields touched by the interrupt handler need any 323 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 324 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 325 * interrupts must be disabled and @data_status updated with a 326 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 327 * CMDRDY interrupt must be disabled and @cmd_status updated with a 328 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 329 * bytes_xfered field of @data must be written. This is ensured by 330 * using barriers. 331 */ 332struct atmel_mci { 333 spinlock_t lock; 334 void __iomem *regs; 335 336 struct scatterlist *sg; 337 unsigned int sg_len; 338 unsigned int pio_offset; 339 unsigned int *buffer; 340 unsigned int buf_size; 341 dma_addr_t buf_phys_addr; 342 343 struct atmel_mci_slot *cur_slot; 344 struct mmc_request *mrq; 345 struct mmc_command *cmd; 346 struct mmc_data *data; 347 unsigned int data_size; 348 349 struct atmel_mci_dma dma; 350 struct dma_chan *data_chan; 351 struct dma_slave_config dma_conf; 352 353 u32 cmd_status; 354 u32 data_status; 355 u32 stop_cmdr; 356 357 struct work_struct bh_work; 358 unsigned long pending_events; 359 unsigned long completed_events; 360 enum atmel_mci_state state; 361 struct list_head queue; 362 363 bool need_clock_update; 364 bool need_reset; 365 struct timer_list timer; 366 u32 mode_reg; 367 u32 cfg_reg; 368 unsigned long bus_hz; 369 unsigned long mapbase; 370 struct clk *mck; 371 struct device *dev; 372 373 struct mci_slot_pdata pdata[ATMCI_MAX_NR_SLOTS]; 374 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; 375 376 struct atmel_mci_caps caps; 377 378 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); 379 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); 380 void (*stop_transfer)(struct atmel_mci *host); 381}; 382 383/** 384 * struct atmel_mci_slot - MMC slot state 385 * @mmc: The mmc_host representing this slot. 386 * @host: The MMC controller this slot is using. 387 * @sdc_reg: Value of SDCR to be written before using this slot. 388 * @sdio_irq: SDIO irq mask for this slot. 389 * @mrq: mmc_request currently being processed or waiting to be 390 * processed, or NULL when the slot is idle. 391 * @queue_node: List node for placing this node in the @queue list of 392 * &struct atmel_mci. 393 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 394 * @flags: Random state bits associated with the slot. 395 * @detect_pin: GPIO pin used for card detection, or negative if not 396 * available. 397 * @wp_pin: GPIO pin used for card write protect sending, or negative 398 * if not available. 399 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 400 */ 401struct atmel_mci_slot { 402 struct mmc_host *mmc; 403 struct atmel_mci *host; 404 405 u32 sdc_reg; 406 u32 sdio_irq; 407 408 struct mmc_request *mrq; 409 struct list_head queue_node; 410 411 unsigned int clock; 412 unsigned long flags; 413#define ATMCI_CARD_PRESENT 0 414#define ATMCI_CARD_NEED_INIT 1 415#define ATMCI_SHUTDOWN 2 416 417 struct gpio_desc *detect_pin; 418 struct gpio_desc *wp_pin; 419 420 struct timer_list detect_timer; 421}; 422 423#define atmci_test_and_clear_pending(host, event) \ 424 test_and_clear_bit(event, &host->pending_events) 425#define atmci_set_completed(host, event) \ 426 set_bit(event, &host->completed_events) 427#define atmci_set_pending(host, event) \ 428 set_bit(event, &host->pending_events) 429 430/* 431 * The debugfs stuff below is mostly optimized away when 432 * CONFIG_DEBUG_FS is not set. 433 */ 434static int atmci_req_show(struct seq_file *s, void *v) 435{ 436 struct atmel_mci_slot *slot = s->private; 437 struct mmc_request *mrq; 438 struct mmc_command *cmd; 439 struct mmc_command *stop; 440 struct mmc_data *data; 441 442 /* Make sure we get a consistent snapshot */ 443 spin_lock_bh(&slot->host->lock); 444 mrq = slot->mrq; 445 446 if (mrq) { 447 cmd = mrq->cmd; 448 data = mrq->data; 449 stop = mrq->stop; 450 451 if (cmd) 452 seq_printf(s, 453 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 454 cmd->opcode, cmd->arg, cmd->flags, 455 cmd->resp[0], cmd->resp[1], cmd->resp[2], 456 cmd->resp[3], cmd->error); 457 if (data) 458 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 459 data->bytes_xfered, data->blocks, 460 data->blksz, data->flags, data->error); 461 if (stop) 462 seq_printf(s, 463 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 464 stop->opcode, stop->arg, stop->flags, 465 stop->resp[0], stop->resp[1], stop->resp[2], 466 stop->resp[3], stop->error); 467 } 468 469 spin_unlock_bh(&slot->host->lock); 470 471 return 0; 472} 473 474DEFINE_SHOW_ATTRIBUTE(atmci_req); 475 476static void atmci_show_status_reg(struct seq_file *s, 477 const char *regname, u32 value) 478{ 479 static const char *sr_bit[] = { 480 [0] = "CMDRDY", 481 [1] = "RXRDY", 482 [2] = "TXRDY", 483 [3] = "BLKE", 484 [4] = "DTIP", 485 [5] = "NOTBUSY", 486 [6] = "ENDRX", 487 [7] = "ENDTX", 488 [8] = "SDIOIRQA", 489 [9] = "SDIOIRQB", 490 [12] = "SDIOWAIT", 491 [14] = "RXBUFF", 492 [15] = "TXBUFE", 493 [16] = "RINDE", 494 [17] = "RDIRE", 495 [18] = "RCRCE", 496 [19] = "RENDE", 497 [20] = "RTOE", 498 [21] = "DCRCE", 499 [22] = "DTOE", 500 [23] = "CSTOE", 501 [24] = "BLKOVRE", 502 [25] = "DMADONE", 503 [26] = "FIFOEMPTY", 504 [27] = "XFRDONE", 505 [30] = "OVRE", 506 [31] = "UNRE", 507 }; 508 unsigned int i; 509 510 seq_printf(s, "%s:\t0x%08x", regname, value); 511 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { 512 if (value & (1 << i)) { 513 if (sr_bit[i]) 514 seq_printf(s, " %s", sr_bit[i]); 515 else 516 seq_puts(s, " UNKNOWN"); 517 } 518 } 519 seq_putc(s, '\n'); 520} 521 522static int atmci_regs_show(struct seq_file *s, void *v) 523{ 524 struct atmel_mci *host = s->private; 525 struct device *dev = host->dev; 526 u32 *buf; 527 int ret = 0; 528 529 530 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); 531 if (!buf) 532 return -ENOMEM; 533 534 pm_runtime_get_sync(dev); 535 536 /* 537 * Grab a more or less consistent snapshot. Note that we're 538 * not disabling interrupts, so IMR and SR may not be 539 * consistent. 540 */ 541 spin_lock_bh(&host->lock); 542 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 543 spin_unlock_bh(&host->lock); 544 545 pm_runtime_put_autosuspend(dev); 546 547 seq_printf(s, "MR:\t0x%08x%s%s ", 548 buf[ATMCI_MR / 4], 549 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", 550 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : ""); 551 if (host->caps.has_odd_clk_div) 552 seq_printf(s, "{CLKDIV,CLKODD}=%u\n", 553 ((buf[ATMCI_MR / 4] & 0xff) << 1) 554 | ((buf[ATMCI_MR / 4] >> 16) & 1)); 555 else 556 seq_printf(s, "CLKDIV=%u\n", 557 (buf[ATMCI_MR / 4] & 0xff)); 558 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); 559 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); 560 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); 561 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 562 buf[ATMCI_BLKR / 4], 563 buf[ATMCI_BLKR / 4] & 0xffff, 564 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); 565 if (host->caps.has_cstor_reg) 566 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); 567 568 /* Don't read RSPR and RDR; it will consume the data there */ 569 570 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); 571 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); 572 573 if (host->caps.has_dma_conf_reg) { 574 u32 val; 575 576 val = buf[ATMCI_DMA / 4]; 577 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 578 val, val & 3, 579 ((val >> 4) & 3) ? 580 1 << (((val >> 4) & 3) + 1) : 1, 581 val & ATMCI_DMAEN ? " DMAEN" : ""); 582 } 583 if (host->caps.has_cfg_reg) { 584 u32 val; 585 586 val = buf[ATMCI_CFG / 4]; 587 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 588 val, 589 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 590 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 591 val & ATMCI_CFG_HSMODE ? " HSMODE" : "", 592 val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); 593 } 594 595 kfree(buf); 596 597 return ret; 598} 599 600DEFINE_SHOW_ATTRIBUTE(atmci_regs); 601 602static void atmci_init_debugfs(struct atmel_mci_slot *slot) 603{ 604 struct mmc_host *mmc = slot->mmc; 605 struct atmel_mci *host = slot->host; 606 struct dentry *root; 607 608 root = mmc->debugfs_root; 609 if (!root) 610 return; 611 612 debugfs_create_file("regs", 0400, root, host, &atmci_regs_fops); 613 debugfs_create_file("req", 0400, root, slot, &atmci_req_fops); 614 debugfs_create_u32("state", 0400, root, &host->state); 615 debugfs_create_xul("pending_events", 0400, root, 616 &host->pending_events); 617 debugfs_create_xul("completed_events", 0400, root, 618 &host->completed_events); 619} 620 621static const struct of_device_id atmci_dt_ids[] = { 622 { .compatible = "atmel,hsmci" }, 623 { /* sentinel */ } 624}; 625 626MODULE_DEVICE_TABLE(of, atmci_dt_ids); 627 628static int atmci_of_init(struct atmel_mci *host) 629{ 630 struct device *dev = host->dev; 631 struct device_node *np = dev->of_node; 632 struct device_node *cnp; 633 u32 slot_id; 634 int err; 635 636 if (!np) 637 return dev_err_probe(dev, -EINVAL, "device node not found\n"); 638 639 for_each_child_of_node(np, cnp) { 640 if (of_property_read_u32(cnp, "reg", &slot_id)) { 641 dev_warn(dev, "reg property is missing for %pOF\n", cnp); 642 continue; 643 } 644 645 if (slot_id >= ATMCI_MAX_NR_SLOTS) { 646 dev_warn(dev, "can't have more than %d slots\n", 647 ATMCI_MAX_NR_SLOTS); 648 of_node_put(cnp); 649 break; 650 } 651 652 if (of_property_read_u32(cnp, "bus-width", 653 &host->pdata[slot_id].bus_width)) 654 host->pdata[slot_id].bus_width = 1; 655 656 host->pdata[slot_id].detect_pin = 657 devm_fwnode_gpiod_get(dev, of_fwnode_handle(cnp), 658 "cd", GPIOD_IN, "cd-gpios"); 659 err = PTR_ERR_OR_ZERO(host->pdata[slot_id].detect_pin); 660 if (err) { 661 if (err != -ENOENT) { 662 of_node_put(cnp); 663 return err; 664 } 665 host->pdata[slot_id].detect_pin = NULL; 666 } 667 668 host->pdata[slot_id].non_removable = 669 of_property_read_bool(cnp, "non-removable"); 670 671 host->pdata[slot_id].wp_pin = 672 devm_fwnode_gpiod_get(dev, of_fwnode_handle(cnp), 673 "wp", GPIOD_IN, "wp-gpios"); 674 err = PTR_ERR_OR_ZERO(host->pdata[slot_id].wp_pin); 675 if (err) { 676 if (err != -ENOENT) { 677 of_node_put(cnp); 678 return err; 679 } 680 host->pdata[slot_id].wp_pin = NULL; 681 } 682 } 683 684 return 0; 685} 686 687static inline unsigned int atmci_get_version(struct atmel_mci *host) 688{ 689 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; 690} 691 692/* 693 * Fix sconfig's burst size according to atmel MCI. We need to convert them as: 694 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. 695 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2, 696 * 8 -> 3, 16 -> 4. 697 * 698 * This can be done by finding most significant bit set. 699 */ 700static inline unsigned int atmci_convert_chksize(struct atmel_mci *host, 701 unsigned int maxburst) 702{ 703 unsigned int version = atmci_get_version(host); 704 unsigned int offset = 2; 705 706 if (version >= 0x600) 707 offset = 1; 708 709 if (maxburst > 1) 710 return fls(maxburst) - offset; 711 else 712 return 0; 713} 714 715static void atmci_timeout_timer(struct timer_list *t) 716{ 717 struct atmel_mci *host = timer_container_of(host, t, timer); 718 struct device *dev = host->dev; 719 720 dev_dbg(dev, "software timeout\n"); 721 722 if (host->mrq->cmd->data) { 723 host->mrq->cmd->data->error = -ETIMEDOUT; 724 host->data = NULL; 725 /* 726 * With some SDIO modules, sometimes DMA transfer hangs. If 727 * stop_transfer() is not called then the DMA request is not 728 * removed, following ones are queued and never computed. 729 */ 730 if (host->state == STATE_DATA_XFER) 731 host->stop_transfer(host); 732 } else { 733 host->mrq->cmd->error = -ETIMEDOUT; 734 host->cmd = NULL; 735 } 736 host->need_reset = 1; 737 host->state = STATE_END_REQUEST; 738 smp_wmb(); 739 queue_work(system_bh_wq, &host->bh_work); 740} 741 742static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, 743 unsigned int ns) 744{ 745 /* 746 * It is easier here to use us instead of ns for the timeout, 747 * it prevents from overflows during calculation. 748 */ 749 unsigned int us = DIV_ROUND_UP(ns, 1000); 750 751 /* Maximum clock frequency is host->bus_hz/2 */ 752 return us * (DIV_ROUND_UP(host->bus_hz, 2000000)); 753} 754 755static void atmci_set_timeout(struct atmel_mci *host, 756 struct atmel_mci_slot *slot, struct mmc_data *data) 757{ 758 static unsigned dtomul_to_shift[] = { 759 0, 4, 7, 8, 10, 12, 16, 20 760 }; 761 unsigned timeout; 762 unsigned dtocyc; 763 unsigned dtomul; 764 765 timeout = atmci_ns_to_clocks(host, data->timeout_ns) 766 + data->timeout_clks; 767 768 for (dtomul = 0; dtomul < 8; dtomul++) { 769 unsigned shift = dtomul_to_shift[dtomul]; 770 dtocyc = (timeout + (1 << shift) - 1) >> shift; 771 if (dtocyc < 15) 772 break; 773 } 774 775 if (dtomul >= 8) { 776 dtomul = 7; 777 dtocyc = 15; 778 } 779 780 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 781 dtocyc << dtomul_to_shift[dtomul]); 782 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); 783} 784 785/* 786 * Return mask with command flags to be enabled for this command. 787 */ 788static u32 atmci_prepare_command(struct mmc_host *mmc, 789 struct mmc_command *cmd) 790{ 791 struct mmc_data *data; 792 u32 cmdr; 793 794 cmd->error = -EINPROGRESS; 795 796 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); 797 798 if (cmd->flags & MMC_RSP_PRESENT) { 799 if (cmd->flags & MMC_RSP_136) 800 cmdr |= ATMCI_CMDR_RSPTYP_136BIT; 801 else 802 cmdr |= ATMCI_CMDR_RSPTYP_48BIT; 803 } 804 805 /* 806 * This should really be MAXLAT_5 for CMD2 and ACMD41, but 807 * it's too difficult to determine whether this is an ACMD or 808 * not. Better make it 64. 809 */ 810 cmdr |= ATMCI_CMDR_MAXLAT_64CYC; 811 812 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 813 cmdr |= ATMCI_CMDR_OPDCMD; 814 815 data = cmd->data; 816 if (data) { 817 cmdr |= ATMCI_CMDR_START_XFER; 818 819 if (cmd->opcode == SD_IO_RW_EXTENDED) { 820 cmdr |= ATMCI_CMDR_SDIO_BLOCK; 821 } else { 822 if (data->blocks > 1) 823 cmdr |= ATMCI_CMDR_MULTI_BLOCK; 824 else 825 cmdr |= ATMCI_CMDR_BLOCK; 826 } 827 828 if (data->flags & MMC_DATA_READ) 829 cmdr |= ATMCI_CMDR_TRDIR_READ; 830 } 831 832 return cmdr; 833} 834 835static void atmci_send_command(struct atmel_mci *host, 836 struct mmc_command *cmd, u32 cmd_flags) 837{ 838 struct device *dev = host->dev; 839 unsigned int timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : 840 ATMCI_CMD_TIMEOUT_MS; 841 842 WARN_ON(host->cmd); 843 host->cmd = cmd; 844 845 dev_vdbg(dev, "start command: ARGR=0x%08x CMDR=0x%08x\n", cmd->arg, cmd_flags); 846 847 atmci_writel(host, ATMCI_ARGR, cmd->arg); 848 atmci_writel(host, ATMCI_CMDR, cmd_flags); 849 850 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms)); 851} 852 853static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 854{ 855 struct device *dev = host->dev; 856 857 dev_dbg(dev, "send stop command\n"); 858 atmci_send_command(host, data->stop, host->stop_cmdr); 859 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 860} 861 862/* 863 * Configure given PDC buffer taking care of alignment issues. 864 * Update host->data_size and host->sg. 865 */ 866static void atmci_pdc_set_single_buf(struct atmel_mci *host, 867 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) 868{ 869 u32 pointer_reg, counter_reg; 870 unsigned int buf_size; 871 872 if (dir == XFER_RECEIVE) { 873 pointer_reg = ATMEL_PDC_RPR; 874 counter_reg = ATMEL_PDC_RCR; 875 } else { 876 pointer_reg = ATMEL_PDC_TPR; 877 counter_reg = ATMEL_PDC_TCR; 878 } 879 880 if (buf_nb == PDC_SECOND_BUF) { 881 pointer_reg += ATMEL_PDC_SCND_BUF_OFF; 882 counter_reg += ATMEL_PDC_SCND_BUF_OFF; 883 } 884 885 if (!host->caps.has_rwproof) { 886 buf_size = host->buf_size; 887 atmci_writel(host, pointer_reg, host->buf_phys_addr); 888 } else { 889 buf_size = sg_dma_len(host->sg); 890 atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); 891 } 892 893 if (host->data_size <= buf_size) { 894 if (host->data_size & 0x3) { 895 /* If size is different from modulo 4, transfer bytes */ 896 atmci_writel(host, counter_reg, host->data_size); 897 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); 898 } else { 899 /* Else transfer 32-bits words */ 900 atmci_writel(host, counter_reg, host->data_size / 4); 901 } 902 host->data_size = 0; 903 } else { 904 /* We assume the size of a page is 32-bits aligned */ 905 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); 906 host->data_size -= sg_dma_len(host->sg); 907 if (host->data_size) 908 host->sg = sg_next(host->sg); 909 } 910} 911 912/* 913 * Configure PDC buffer according to the data size ie configuring one or two 914 * buffers. Don't use this function if you want to configure only the second 915 * buffer. In this case, use atmci_pdc_set_single_buf. 916 */ 917static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) 918{ 919 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); 920 if (host->data_size) 921 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); 922} 923 924/* 925 * Unmap sg lists, called when transfer is finished. 926 */ 927static void atmci_pdc_cleanup(struct atmel_mci *host) 928{ 929 struct mmc_data *data = host->data; 930 struct device *dev = host->dev; 931 932 if (data) 933 dma_unmap_sg(dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); 934} 935 936/* 937 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after 938 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY 939 * interrupt needed for both transfer directions. 940 */ 941static void atmci_pdc_complete(struct atmel_mci *host) 942{ 943 struct device *dev = host->dev; 944 int transfer_size = host->data->blocks * host->data->blksz; 945 int i; 946 947 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 948 949 if ((!host->caps.has_rwproof) 950 && (host->data->flags & MMC_DATA_READ)) { 951 if (host->caps.has_bad_data_ordering) 952 for (i = 0; i < transfer_size; i++) 953 host->buffer[i] = swab32(host->buffer[i]); 954 sg_copy_from_buffer(host->data->sg, host->data->sg_len, 955 host->buffer, transfer_size); 956 } 957 958 atmci_pdc_cleanup(host); 959 960 dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 961 atmci_set_pending(host, EVENT_XFER_COMPLETE); 962 queue_work(system_bh_wq, &host->bh_work); 963} 964 965static void atmci_dma_cleanup(struct atmel_mci *host) 966{ 967 struct mmc_data *data = host->data; 968 969 if (data) 970 dma_unmap_sg(host->dma.chan->device->dev, 971 data->sg, data->sg_len, 972 mmc_get_dma_dir(data)); 973} 974 975/* 976 * This function is called by the DMA driver from bh context. 977 */ 978static void atmci_dma_complete(void *arg) 979{ 980 struct atmel_mci *host = arg; 981 struct mmc_data *data = host->data; 982 struct device *dev = host->dev; 983 984 dev_vdbg(dev, "DMA complete\n"); 985 986 if (host->caps.has_dma_conf_reg) 987 /* Disable DMA hardware handshaking on MCI */ 988 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); 989 990 atmci_dma_cleanup(host); 991 992 /* 993 * If the card was removed, data will be NULL. No point trying 994 * to send the stop command or waiting for NBUSY in this case. 995 */ 996 if (data) { 997 dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 998 atmci_set_pending(host, EVENT_XFER_COMPLETE); 999 queue_work(system_bh_wq, &host->bh_work); 1000 1001 /* 1002 * Regardless of what the documentation says, we have 1003 * to wait for NOTBUSY even after block read 1004 * operations. 1005 * 1006 * When the DMA transfer is complete, the controller 1007 * may still be reading the CRC from the card, i.e. 1008 * the data transfer is still in progress and we 1009 * haven't seen all the potential error bits yet. 1010 * 1011 * The interrupt handler will schedule a different 1012 * bh work to finish things up when the data transfer 1013 * is completely done. 1014 * 1015 * We may not complete the mmc request here anyway 1016 * because the mmc layer may call back and cause us to 1017 * violate the "don't submit new operations from the 1018 * completion callback" rule of the dma engine 1019 * framework. 1020 */ 1021 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1022 } 1023} 1024 1025/* 1026 * Returns a mask of interrupt flags to be enabled after the whole 1027 * request has been prepared. 1028 */ 1029static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) 1030{ 1031 u32 iflags; 1032 1033 data->error = -EINPROGRESS; 1034 1035 host->sg = data->sg; 1036 host->sg_len = data->sg_len; 1037 host->data = data; 1038 host->data_chan = NULL; 1039 1040 iflags = ATMCI_DATA_ERROR_FLAGS; 1041 1042 /* 1043 * Errata: MMC data write operation with less than 12 1044 * bytes is impossible. 1045 * 1046 * Errata: MCI Transmit Data Register (TDR) FIFO 1047 * corruption when length is not multiple of 4. 1048 */ 1049 if (data->blocks * data->blksz < 12 1050 || (data->blocks * data->blksz) & 3) 1051 host->need_reset = true; 1052 1053 host->pio_offset = 0; 1054 if (data->flags & MMC_DATA_READ) 1055 iflags |= ATMCI_RXRDY; 1056 else 1057 iflags |= ATMCI_TXRDY; 1058 1059 return iflags; 1060} 1061 1062/* 1063 * Set interrupt flags and set block length into the MCI mode register even 1064 * if this value is also accessible in the MCI block register. It seems to be 1065 * necessary before the High Speed MCI version. It also map sg and configure 1066 * PDC registers. 1067 */ 1068static u32 1069atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1070{ 1071 struct device *dev = host->dev; 1072 u32 iflags, tmp; 1073 int i; 1074 1075 data->error = -EINPROGRESS; 1076 1077 host->data = data; 1078 host->sg = data->sg; 1079 iflags = ATMCI_DATA_ERROR_FLAGS; 1080 1081 /* Enable pdc mode */ 1082 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); 1083 1084 if (data->flags & MMC_DATA_READ) 1085 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; 1086 else 1087 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE; 1088 1089 /* Set BLKLEN */ 1090 tmp = atmci_readl(host, ATMCI_MR); 1091 tmp &= 0x0000ffff; 1092 tmp |= ATMCI_BLKLEN(data->blksz); 1093 atmci_writel(host, ATMCI_MR, tmp); 1094 1095 /* Configure PDC */ 1096 host->data_size = data->blocks * data->blksz; 1097 dma_map_sg(dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); 1098 1099 if ((!host->caps.has_rwproof) 1100 && (host->data->flags & MMC_DATA_WRITE)) { 1101 sg_copy_to_buffer(host->data->sg, host->data->sg_len, 1102 host->buffer, host->data_size); 1103 if (host->caps.has_bad_data_ordering) 1104 for (i = 0; i < host->data_size; i++) 1105 host->buffer[i] = swab32(host->buffer[i]); 1106 } 1107 1108 if (host->data_size) 1109 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ? 1110 XFER_RECEIVE : XFER_TRANSMIT); 1111 return iflags; 1112} 1113 1114static u32 1115atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 1116{ 1117 struct dma_chan *chan; 1118 struct dma_async_tx_descriptor *desc; 1119 struct scatterlist *sg; 1120 unsigned int i; 1121 enum dma_transfer_direction slave_dirn; 1122 unsigned int sglen; 1123 u32 maxburst; 1124 u32 iflags; 1125 1126 data->error = -EINPROGRESS; 1127 1128 WARN_ON(host->data); 1129 host->sg = NULL; 1130 host->data = data; 1131 1132 iflags = ATMCI_DATA_ERROR_FLAGS; 1133 1134 /* 1135 * We don't do DMA on "complex" transfers, i.e. with 1136 * non-word-aligned buffers or lengths. Also, we don't bother 1137 * with all the DMA setup overhead for short transfers. 1138 */ 1139 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 1140 return atmci_prepare_data(host, data); 1141 if (data->blksz & 3) 1142 return atmci_prepare_data(host, data); 1143 1144 for_each_sg(data->sg, sg, data->sg_len, i) { 1145 if (sg->offset & 3 || sg->length & 3) 1146 return atmci_prepare_data(host, data); 1147 } 1148 1149 /* If we don't have a channel, we can't do DMA */ 1150 if (!host->dma.chan) 1151 return -ENODEV; 1152 1153 chan = host->dma.chan; 1154 host->data_chan = chan; 1155 1156 if (data->flags & MMC_DATA_READ) { 1157 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM; 1158 maxburst = atmci_convert_chksize(host, 1159 host->dma_conf.src_maxburst); 1160 } else { 1161 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV; 1162 maxburst = atmci_convert_chksize(host, 1163 host->dma_conf.dst_maxburst); 1164 } 1165 1166 if (host->caps.has_dma_conf_reg) 1167 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | 1168 ATMCI_DMAEN); 1169 1170 sglen = dma_map_sg(chan->device->dev, data->sg, 1171 data->sg_len, mmc_get_dma_dir(data)); 1172 1173 dmaengine_slave_config(chan, &host->dma_conf); 1174 desc = dmaengine_prep_slave_sg(chan, 1175 data->sg, sglen, slave_dirn, 1176 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1177 if (!desc) 1178 goto unmap_exit; 1179 1180 host->dma.data_desc = desc; 1181 desc->callback = atmci_dma_complete; 1182 desc->callback_param = host; 1183 1184 return iflags; 1185unmap_exit: 1186 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 1187 mmc_get_dma_dir(data)); 1188 return -ENOMEM; 1189} 1190 1191static void 1192atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) 1193{ 1194 return; 1195} 1196 1197/* 1198 * Start PDC according to transfer direction. 1199 */ 1200static void 1201atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1202{ 1203 if (data->flags & MMC_DATA_READ) 1204 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1205 else 1206 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1207} 1208 1209static void 1210atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 1211{ 1212 struct dma_chan *chan = host->data_chan; 1213 struct dma_async_tx_descriptor *desc = host->dma.data_desc; 1214 1215 if (chan) { 1216 dmaengine_submit(desc); 1217 dma_async_issue_pending(chan); 1218 } 1219} 1220 1221static void atmci_stop_transfer(struct atmel_mci *host) 1222{ 1223 struct device *dev = host->dev; 1224 1225 dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 1226 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1227 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1228} 1229 1230/* 1231 * Stop data transfer because error(s) occurred. 1232 */ 1233static void atmci_stop_transfer_pdc(struct atmel_mci *host) 1234{ 1235 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 1236} 1237 1238static void atmci_stop_transfer_dma(struct atmel_mci *host) 1239{ 1240 struct dma_chan *chan = host->data_chan; 1241 struct device *dev = host->dev; 1242 1243 if (chan) { 1244 dmaengine_terminate_all(chan); 1245 atmci_dma_cleanup(host); 1246 } else { 1247 /* Data transfer was stopped by the interrupt handler */ 1248 dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 1249 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1250 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1251 } 1252} 1253 1254/* 1255 * Start a request: prepare data if needed, prepare the command and activate 1256 * interrupts. 1257 */ 1258static void atmci_start_request(struct atmel_mci *host, 1259 struct atmel_mci_slot *slot) 1260{ 1261 struct device *dev = host->dev; 1262 struct mmc_request *mrq; 1263 struct mmc_command *cmd; 1264 struct mmc_data *data; 1265 u32 iflags; 1266 u32 cmdflags; 1267 1268 mrq = slot->mrq; 1269 host->cur_slot = slot; 1270 host->mrq = mrq; 1271 1272 host->pending_events = 0; 1273 host->completed_events = 0; 1274 host->cmd_status = 0; 1275 host->data_status = 0; 1276 1277 dev_dbg(dev, "start request: cmd %u\n", mrq->cmd->opcode); 1278 1279 if (host->need_reset || host->caps.need_reset_after_xfer) { 1280 iflags = atmci_readl(host, ATMCI_IMR); 1281 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB); 1282 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1283 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1284 atmci_writel(host, ATMCI_MR, host->mode_reg); 1285 if (host->caps.has_cfg_reg) 1286 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1287 atmci_writel(host, ATMCI_IER, iflags); 1288 host->need_reset = false; 1289 } 1290 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); 1291 1292 iflags = atmci_readl(host, ATMCI_IMR); 1293 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 1294 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 1295 iflags); 1296 1297 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 1298 /* Send init sequence (74 clock cycles) */ 1299 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); 1300 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) 1301 cpu_relax(); 1302 } 1303 iflags = 0; 1304 data = mrq->data; 1305 if (data) { 1306 atmci_set_timeout(host, slot, data); 1307 1308 /* Must set block count/size before sending command */ 1309 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) 1310 | ATMCI_BLKLEN(data->blksz)); 1311 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 1312 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); 1313 1314 iflags |= host->prepare_data(host, data); 1315 } 1316 1317 iflags |= ATMCI_CMDRDY; 1318 cmd = mrq->cmd; 1319 cmdflags = atmci_prepare_command(slot->mmc, cmd); 1320 1321 /* 1322 * DMA transfer should be started before sending the command to avoid 1323 * unexpected errors especially for read operations in SDIO mode. 1324 * Unfortunately, in PDC mode, command has to be sent before starting 1325 * the transfer. 1326 */ 1327 if (host->submit_data != &atmci_submit_data_dma) 1328 atmci_send_command(host, cmd, cmdflags); 1329 1330 if (data) 1331 host->submit_data(host, data); 1332 1333 if (host->submit_data == &atmci_submit_data_dma) 1334 atmci_send_command(host, cmd, cmdflags); 1335 1336 if (mrq->stop) { 1337 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 1338 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; 1339 if (!(data->flags & MMC_DATA_WRITE)) 1340 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; 1341 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; 1342 } 1343 1344 /* 1345 * We could have enabled interrupts earlier, but I suspect 1346 * that would open up a nice can of interesting race 1347 * conditions (e.g. command and data complete, but stop not 1348 * prepared yet.) 1349 */ 1350 atmci_writel(host, ATMCI_IER, iflags); 1351} 1352 1353static void atmci_queue_request(struct atmel_mci *host, 1354 struct atmel_mci_slot *slot, struct mmc_request *mrq) 1355{ 1356 struct device *dev = host->dev; 1357 1358 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1359 host->state); 1360 1361 spin_lock_bh(&host->lock); 1362 slot->mrq = mrq; 1363 if (host->state == STATE_IDLE) { 1364 host->state = STATE_SENDING_CMD; 1365 atmci_start_request(host, slot); 1366 } else { 1367 dev_dbg(dev, "queue request\n"); 1368 list_add_tail(&slot->queue_node, &host->queue); 1369 } 1370 spin_unlock_bh(&host->lock); 1371} 1372 1373static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1374{ 1375 struct atmel_mci_slot *slot = mmc_priv(mmc); 1376 struct atmel_mci *host = slot->host; 1377 struct device *dev = host->dev; 1378 struct mmc_data *data; 1379 1380 WARN_ON(slot->mrq); 1381 dev_dbg(dev, "MRQ: cmd %u\n", mrq->cmd->opcode); 1382 1383 /* 1384 * We may "know" the card is gone even though there's still an 1385 * electrical connection. If so, we really need to communicate 1386 * this to the MMC core since there won't be any more 1387 * interrupts as the card is completely removed. Otherwise, 1388 * the MMC core might believe the card is still there even 1389 * though the card was just removed very slowly. 1390 */ 1391 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 1392 mrq->cmd->error = -ENOMEDIUM; 1393 mmc_request_done(mmc, mrq); 1394 return; 1395 } 1396 1397 /* We don't support multiple blocks of weird lengths. */ 1398 data = mrq->data; 1399 if (data && data->blocks > 1 && data->blksz & 3) { 1400 mrq->cmd->error = -EINVAL; 1401 mmc_request_done(mmc, mrq); 1402 } 1403 1404 atmci_queue_request(host, slot, mrq); 1405} 1406 1407static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1408{ 1409 struct atmel_mci_slot *slot = mmc_priv(mmc); 1410 struct atmel_mci *host = slot->host; 1411 unsigned int i; 1412 1413 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; 1414 switch (ios->bus_width) { 1415 case MMC_BUS_WIDTH_1: 1416 slot->sdc_reg |= ATMCI_SDCBUS_1BIT; 1417 break; 1418 case MMC_BUS_WIDTH_4: 1419 slot->sdc_reg |= ATMCI_SDCBUS_4BIT; 1420 break; 1421 case MMC_BUS_WIDTH_8: 1422 slot->sdc_reg |= ATMCI_SDCBUS_8BIT; 1423 break; 1424 } 1425 1426 if (ios->clock) { 1427 unsigned int clock_min = ~0U; 1428 int clkdiv; 1429 1430 spin_lock_bh(&host->lock); 1431 if (!host->mode_reg) { 1432 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1433 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1434 if (host->caps.has_cfg_reg) 1435 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1436 } 1437 1438 /* 1439 * Use mirror of ios->clock to prevent race with mmc 1440 * core ios update when finding the minimum. 1441 */ 1442 slot->clock = ios->clock; 1443 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1444 if (host->slot[i] && host->slot[i]->clock 1445 && host->slot[i]->clock < clock_min) 1446 clock_min = host->slot[i]->clock; 1447 } 1448 1449 /* Calculate clock divider */ 1450 if (host->caps.has_odd_clk_div) { 1451 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; 1452 if (clkdiv < 0) { 1453 dev_warn(&mmc->class_dev, 1454 "clock %u too fast; using %lu\n", 1455 clock_min, host->bus_hz / 2); 1456 clkdiv = 0; 1457 } else if (clkdiv > 511) { 1458 dev_warn(&mmc->class_dev, 1459 "clock %u too slow; using %lu\n", 1460 clock_min, host->bus_hz / (511 + 2)); 1461 clkdiv = 511; 1462 } 1463 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) 1464 | ATMCI_MR_CLKODD(clkdiv & 1); 1465 } else { 1466 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 1467 if (clkdiv > 255) { 1468 dev_warn(&mmc->class_dev, 1469 "clock %u too slow; using %lu\n", 1470 clock_min, host->bus_hz / (2 * 256)); 1471 clkdiv = 255; 1472 } 1473 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); 1474 } 1475 1476 /* 1477 * WRPROOF and RDPROOF prevent overruns/underruns by 1478 * stopping the clock when the FIFO is full/empty. 1479 * This state is not expected to last for long. 1480 */ 1481 if (host->caps.has_rwproof) 1482 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); 1483 1484 if (host->caps.has_cfg_reg) { 1485 /* setup High Speed mode in relation with card capacity */ 1486 if (ios->timing == MMC_TIMING_SD_HS) 1487 host->cfg_reg |= ATMCI_CFG_HSMODE; 1488 else 1489 host->cfg_reg &= ~ATMCI_CFG_HSMODE; 1490 } 1491 1492 if (list_empty(&host->queue)) { 1493 atmci_writel(host, ATMCI_MR, host->mode_reg); 1494 if (host->caps.has_cfg_reg) 1495 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1496 } else { 1497 host->need_clock_update = true; 1498 } 1499 1500 spin_unlock_bh(&host->lock); 1501 } else { 1502 bool any_slot_active = false; 1503 1504 spin_lock_bh(&host->lock); 1505 slot->clock = 0; 1506 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1507 if (host->slot[i] && host->slot[i]->clock) { 1508 any_slot_active = true; 1509 break; 1510 } 1511 } 1512 if (!any_slot_active) { 1513 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 1514 if (host->mode_reg) { 1515 atmci_readl(host, ATMCI_MR); 1516 } 1517 host->mode_reg = 0; 1518 } 1519 spin_unlock_bh(&host->lock); 1520 } 1521 1522 switch (ios->power_mode) { 1523 case MMC_POWER_OFF: 1524 if (!IS_ERR(mmc->supply.vmmc)) 1525 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1526 break; 1527 case MMC_POWER_UP: 1528 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 1529 if (!IS_ERR(mmc->supply.vmmc)) 1530 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1531 break; 1532 default: 1533 break; 1534 } 1535} 1536 1537static int atmci_get_ro(struct mmc_host *mmc) 1538{ 1539 int read_only = -ENOSYS; 1540 struct atmel_mci_slot *slot = mmc_priv(mmc); 1541 1542 if (slot->wp_pin) { 1543 read_only = gpiod_get_value(slot->wp_pin); 1544 dev_dbg(&mmc->class_dev, "card is %s\n", 1545 read_only ? "read-only" : "read-write"); 1546 } 1547 1548 return read_only; 1549} 1550 1551static int atmci_get_cd(struct mmc_host *mmc) 1552{ 1553 int present = -ENOSYS; 1554 struct atmel_mci_slot *slot = mmc_priv(mmc); 1555 1556 if (slot->detect_pin) { 1557 present = gpiod_get_value_cansleep(slot->detect_pin); 1558 dev_dbg(&mmc->class_dev, "card is %spresent\n", 1559 present ? "" : "not "); 1560 } 1561 1562 return present; 1563} 1564 1565static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1566{ 1567 struct atmel_mci_slot *slot = mmc_priv(mmc); 1568 struct atmel_mci *host = slot->host; 1569 1570 if (enable) 1571 atmci_writel(host, ATMCI_IER, slot->sdio_irq); 1572 else 1573 atmci_writel(host, ATMCI_IDR, slot->sdio_irq); 1574} 1575 1576static const struct mmc_host_ops atmci_ops = { 1577 .request = atmci_request, 1578 .set_ios = atmci_set_ios, 1579 .get_ro = atmci_get_ro, 1580 .get_cd = atmci_get_cd, 1581 .enable_sdio_irq = atmci_enable_sdio_irq, 1582}; 1583 1584/* Called with host->lock held */ 1585static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 1586 __releases(&host->lock) 1587 __acquires(&host->lock) 1588{ 1589 struct atmel_mci_slot *slot = NULL; 1590 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1591 struct device *dev = host->dev; 1592 1593 WARN_ON(host->cmd || host->data); 1594 1595 timer_delete(&host->timer); 1596 1597 /* 1598 * Update the MMC clock rate if necessary. This may be 1599 * necessary if set_ios() is called when a different slot is 1600 * busy transferring data. 1601 */ 1602 if (host->need_clock_update) { 1603 atmci_writel(host, ATMCI_MR, host->mode_reg); 1604 if (host->caps.has_cfg_reg) 1605 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1606 } 1607 1608 host->cur_slot->mrq = NULL; 1609 host->mrq = NULL; 1610 if (!list_empty(&host->queue)) { 1611 slot = list_entry(host->queue.next, 1612 struct atmel_mci_slot, queue_node); 1613 list_del(&slot->queue_node); 1614 dev_vdbg(dev, "list not empty: %s is next\n", mmc_hostname(slot->mmc)); 1615 host->state = STATE_SENDING_CMD; 1616 atmci_start_request(host, slot); 1617 } else { 1618 dev_vdbg(dev, "list empty\n"); 1619 host->state = STATE_IDLE; 1620 } 1621 1622 spin_unlock(&host->lock); 1623 mmc_request_done(prev_mmc, mrq); 1624 spin_lock(&host->lock); 1625} 1626 1627static void atmci_command_complete(struct atmel_mci *host, 1628 struct mmc_command *cmd) 1629{ 1630 u32 status = host->cmd_status; 1631 1632 /* Read the response from the card (up to 16 bytes) */ 1633 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); 1634 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); 1635 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); 1636 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); 1637 1638 if (status & ATMCI_RTOE) 1639 cmd->error = -ETIMEDOUT; 1640 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) 1641 cmd->error = -EILSEQ; 1642 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) 1643 cmd->error = -EIO; 1644 else if (host->mrq->data && (host->mrq->data->blksz & 3)) { 1645 if (host->caps.need_blksz_mul_4) { 1646 cmd->error = -EINVAL; 1647 host->need_reset = 1; 1648 } 1649 } else 1650 cmd->error = 0; 1651} 1652 1653static void atmci_detect_change(struct timer_list *t) 1654{ 1655 struct atmel_mci_slot *slot = timer_container_of(slot, t, 1656 detect_timer); 1657 bool present; 1658 bool present_old; 1659 1660 /* 1661 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 1662 * freeing the interrupt. We must not re-enable the interrupt 1663 * if it has been freed, and if we're shutting down, it 1664 * doesn't really matter whether the card is present or not. 1665 */ 1666 smp_rmb(); 1667 if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1668 return; 1669 1670 enable_irq(gpiod_to_irq(slot->detect_pin)); 1671 present = gpiod_get_value_cansleep(slot->detect_pin); 1672 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1673 1674 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1675 present, present_old); 1676 1677 if (present != present_old) { 1678 struct atmel_mci *host = slot->host; 1679 struct mmc_request *mrq; 1680 1681 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1682 present ? "inserted" : "removed"); 1683 1684 spin_lock(&host->lock); 1685 1686 if (!present) 1687 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1688 else 1689 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1690 1691 /* Clean up queue if present */ 1692 mrq = slot->mrq; 1693 if (mrq) { 1694 if (mrq == host->mrq) { 1695 /* 1696 * Reset controller to terminate any ongoing 1697 * commands or data transfers. 1698 */ 1699 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1700 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1701 atmci_writel(host, ATMCI_MR, host->mode_reg); 1702 if (host->caps.has_cfg_reg) 1703 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1704 1705 host->data = NULL; 1706 host->cmd = NULL; 1707 1708 switch (host->state) { 1709 case STATE_IDLE: 1710 break; 1711 case STATE_SENDING_CMD: 1712 mrq->cmd->error = -ENOMEDIUM; 1713 if (mrq->data) 1714 host->stop_transfer(host); 1715 break; 1716 case STATE_DATA_XFER: 1717 mrq->data->error = -ENOMEDIUM; 1718 host->stop_transfer(host); 1719 break; 1720 case STATE_WAITING_NOTBUSY: 1721 mrq->data->error = -ENOMEDIUM; 1722 break; 1723 case STATE_SENDING_STOP: 1724 mrq->stop->error = -ENOMEDIUM; 1725 break; 1726 case STATE_END_REQUEST: 1727 break; 1728 } 1729 1730 atmci_request_end(host, mrq); 1731 } else { 1732 list_del(&slot->queue_node); 1733 mrq->cmd->error = -ENOMEDIUM; 1734 if (mrq->data) 1735 mrq->data->error = -ENOMEDIUM; 1736 if (mrq->stop) 1737 mrq->stop->error = -ENOMEDIUM; 1738 1739 spin_unlock(&host->lock); 1740 mmc_request_done(slot->mmc, mrq); 1741 spin_lock(&host->lock); 1742 } 1743 } 1744 spin_unlock(&host->lock); 1745 1746 mmc_detect_change(slot->mmc, 0); 1747 } 1748} 1749 1750static void atmci_work_func(struct work_struct *t) 1751{ 1752 struct atmel_mci *host = from_work(host, t, bh_work); 1753 struct mmc_request *mrq = host->mrq; 1754 struct mmc_data *data = host->data; 1755 struct device *dev = host->dev; 1756 enum atmel_mci_state state = host->state; 1757 enum atmel_mci_state prev_state; 1758 u32 status; 1759 1760 spin_lock(&host->lock); 1761 1762 state = host->state; 1763 1764 dev_vdbg(dev, "bh_work: state %u pending/completed/mask %lx/%lx/%x\n", 1765 state, host->pending_events, host->completed_events, 1766 atmci_readl(host, ATMCI_IMR)); 1767 1768 do { 1769 prev_state = state; 1770 dev_dbg(dev, "FSM: state=%d\n", state); 1771 1772 switch (state) { 1773 case STATE_IDLE: 1774 break; 1775 1776 case STATE_SENDING_CMD: 1777 /* 1778 * Command has been sent, we are waiting for command 1779 * ready. Then we have three next states possible: 1780 * END_REQUEST by default, WAITING_NOTBUSY if it's a 1781 * command needing it or DATA_XFER if there is data. 1782 */ 1783 dev_dbg(dev, "FSM: cmd ready?\n"); 1784 if (!atmci_test_and_clear_pending(host, 1785 EVENT_CMD_RDY)) 1786 break; 1787 1788 dev_dbg(dev, "set completed cmd ready\n"); 1789 host->cmd = NULL; 1790 atmci_set_completed(host, EVENT_CMD_RDY); 1791 atmci_command_complete(host, mrq->cmd); 1792 if (mrq->data) { 1793 dev_dbg(dev, "command with data transfer\n"); 1794 /* 1795 * If there is a command error don't start 1796 * data transfer. 1797 */ 1798 if (mrq->cmd->error) { 1799 host->stop_transfer(host); 1800 host->data = NULL; 1801 atmci_writel(host, ATMCI_IDR, 1802 ATMCI_TXRDY | ATMCI_RXRDY 1803 | ATMCI_DATA_ERROR_FLAGS); 1804 state = STATE_END_REQUEST; 1805 } else 1806 state = STATE_DATA_XFER; 1807 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { 1808 dev_dbg(dev, "command response need waiting notbusy\n"); 1809 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1810 state = STATE_WAITING_NOTBUSY; 1811 } else 1812 state = STATE_END_REQUEST; 1813 1814 break; 1815 1816 case STATE_DATA_XFER: 1817 if (atmci_test_and_clear_pending(host, 1818 EVENT_DATA_ERROR)) { 1819 dev_dbg(dev, "set completed data error\n"); 1820 atmci_set_completed(host, EVENT_DATA_ERROR); 1821 state = STATE_END_REQUEST; 1822 break; 1823 } 1824 1825 /* 1826 * A data transfer is in progress. The event expected 1827 * to move to the next state depends of data transfer 1828 * type (PDC or DMA). Once transfer done we can move 1829 * to the next step which is WAITING_NOTBUSY in write 1830 * case and directly SENDING_STOP in read case. 1831 */ 1832 dev_dbg(dev, "FSM: xfer complete?\n"); 1833 if (!atmci_test_and_clear_pending(host, 1834 EVENT_XFER_COMPLETE)) 1835 break; 1836 1837 dev_dbg(dev, "(%s) set completed xfer complete\n", __func__); 1838 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1839 1840 if (host->caps.need_notbusy_for_read_ops || 1841 (host->data->flags & MMC_DATA_WRITE)) { 1842 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1843 state = STATE_WAITING_NOTBUSY; 1844 } else if (host->mrq->stop) { 1845 atmci_send_stop_cmd(host, data); 1846 state = STATE_SENDING_STOP; 1847 } else { 1848 host->data = NULL; 1849 data->bytes_xfered = data->blocks * data->blksz; 1850 data->error = 0; 1851 state = STATE_END_REQUEST; 1852 } 1853 break; 1854 1855 case STATE_WAITING_NOTBUSY: 1856 /* 1857 * We can be in the state for two reasons: a command 1858 * requiring waiting not busy signal (stop command 1859 * included) or a write operation. In the latest case, 1860 * we need to send a stop command. 1861 */ 1862 dev_dbg(dev, "FSM: not busy?\n"); 1863 if (!atmci_test_and_clear_pending(host, 1864 EVENT_NOTBUSY)) 1865 break; 1866 1867 dev_dbg(dev, "set completed not busy\n"); 1868 atmci_set_completed(host, EVENT_NOTBUSY); 1869 1870 if (host->data) { 1871 /* 1872 * For some commands such as CMD53, even if 1873 * there is data transfer, there is no stop 1874 * command to send. 1875 */ 1876 if (host->mrq->stop) { 1877 atmci_send_stop_cmd(host, data); 1878 state = STATE_SENDING_STOP; 1879 } else { 1880 host->data = NULL; 1881 data->bytes_xfered = data->blocks 1882 * data->blksz; 1883 data->error = 0; 1884 state = STATE_END_REQUEST; 1885 } 1886 } else 1887 state = STATE_END_REQUEST; 1888 break; 1889 1890 case STATE_SENDING_STOP: 1891 /* 1892 * In this state, it is important to set host->data to 1893 * NULL (which is tested in the waiting notbusy state) 1894 * in order to go to the end request state instead of 1895 * sending stop again. 1896 */ 1897 dev_dbg(dev, "FSM: cmd ready?\n"); 1898 if (!atmci_test_and_clear_pending(host, 1899 EVENT_CMD_RDY)) 1900 break; 1901 1902 dev_dbg(dev, "FSM: cmd ready\n"); 1903 host->cmd = NULL; 1904 data->bytes_xfered = data->blocks * data->blksz; 1905 data->error = 0; 1906 atmci_command_complete(host, mrq->stop); 1907 if (mrq->stop->error) { 1908 host->stop_transfer(host); 1909 atmci_writel(host, ATMCI_IDR, 1910 ATMCI_TXRDY | ATMCI_RXRDY 1911 | ATMCI_DATA_ERROR_FLAGS); 1912 state = STATE_END_REQUEST; 1913 } else { 1914 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1915 state = STATE_WAITING_NOTBUSY; 1916 } 1917 host->data = NULL; 1918 break; 1919 1920 case STATE_END_REQUEST: 1921 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY 1922 | ATMCI_DATA_ERROR_FLAGS); 1923 status = host->data_status; 1924 if (unlikely(status)) { 1925 host->stop_transfer(host); 1926 host->data = NULL; 1927 if (data) { 1928 if (status & ATMCI_DTOE) { 1929 data->error = -ETIMEDOUT; 1930 } else if (status & ATMCI_DCRCE) { 1931 data->error = -EILSEQ; 1932 } else { 1933 data->error = -EIO; 1934 } 1935 } 1936 } 1937 1938 atmci_request_end(host, host->mrq); 1939 goto unlock; /* atmci_request_end() sets host->state */ 1940 break; 1941 } 1942 } while (state != prev_state); 1943 1944 host->state = state; 1945 1946unlock: 1947 spin_unlock(&host->lock); 1948} 1949 1950static void atmci_read_data_pio(struct atmel_mci *host) 1951{ 1952 struct scatterlist *sg = host->sg; 1953 unsigned int offset = host->pio_offset; 1954 struct mmc_data *data = host->data; 1955 u32 value; 1956 u32 status; 1957 unsigned int nbytes = 0; 1958 1959 do { 1960 value = atmci_readl(host, ATMCI_RDR); 1961 if (likely(offset + 4 <= sg->length)) { 1962 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset); 1963 1964 offset += 4; 1965 nbytes += 4; 1966 1967 if (offset == sg->length) { 1968 flush_dcache_page(sg_page(sg)); 1969 host->sg = sg = sg_next(sg); 1970 host->sg_len--; 1971 if (!sg || !host->sg_len) 1972 goto done; 1973 1974 offset = 0; 1975 } 1976 } else { 1977 unsigned int remaining = sg->length - offset; 1978 1979 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset); 1980 nbytes += remaining; 1981 1982 flush_dcache_page(sg_page(sg)); 1983 host->sg = sg = sg_next(sg); 1984 host->sg_len--; 1985 if (!sg || !host->sg_len) 1986 goto done; 1987 1988 offset = 4 - remaining; 1989 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining, 1990 offset, 0); 1991 nbytes += offset; 1992 } 1993 1994 status = atmci_readl(host, ATMCI_SR); 1995 if (status & ATMCI_DATA_ERROR_FLAGS) { 1996 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY 1997 | ATMCI_DATA_ERROR_FLAGS)); 1998 host->data_status = status; 1999 data->bytes_xfered += nbytes; 2000 return; 2001 } 2002 } while (status & ATMCI_RXRDY); 2003 2004 host->pio_offset = offset; 2005 data->bytes_xfered += nbytes; 2006 2007 return; 2008 2009done: 2010 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); 2011 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 2012 data->bytes_xfered += nbytes; 2013 smp_wmb(); 2014 atmci_set_pending(host, EVENT_XFER_COMPLETE); 2015} 2016 2017static void atmci_write_data_pio(struct atmel_mci *host) 2018{ 2019 struct scatterlist *sg = host->sg; 2020 unsigned int offset = host->pio_offset; 2021 struct mmc_data *data = host->data; 2022 u32 value; 2023 u32 status; 2024 unsigned int nbytes = 0; 2025 2026 do { 2027 if (likely(offset + 4 <= sg->length)) { 2028 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset); 2029 atmci_writel(host, ATMCI_TDR, value); 2030 2031 offset += 4; 2032 nbytes += 4; 2033 if (offset == sg->length) { 2034 host->sg = sg = sg_next(sg); 2035 host->sg_len--; 2036 if (!sg || !host->sg_len) 2037 goto done; 2038 2039 offset = 0; 2040 } 2041 } else { 2042 unsigned int remaining = sg->length - offset; 2043 2044 value = 0; 2045 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset); 2046 nbytes += remaining; 2047 2048 host->sg = sg = sg_next(sg); 2049 host->sg_len--; 2050 if (!sg || !host->sg_len) { 2051 atmci_writel(host, ATMCI_TDR, value); 2052 goto done; 2053 } 2054 2055 offset = 4 - remaining; 2056 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining, 2057 offset, 0); 2058 atmci_writel(host, ATMCI_TDR, value); 2059 nbytes += offset; 2060 } 2061 2062 status = atmci_readl(host, ATMCI_SR); 2063 if (status & ATMCI_DATA_ERROR_FLAGS) { 2064 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY 2065 | ATMCI_DATA_ERROR_FLAGS)); 2066 host->data_status = status; 2067 data->bytes_xfered += nbytes; 2068 return; 2069 } 2070 } while (status & ATMCI_TXRDY); 2071 2072 host->pio_offset = offset; 2073 data->bytes_xfered += nbytes; 2074 2075 return; 2076 2077done: 2078 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); 2079 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 2080 data->bytes_xfered += nbytes; 2081 smp_wmb(); 2082 atmci_set_pending(host, EVENT_XFER_COMPLETE); 2083} 2084 2085static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) 2086{ 2087 int i; 2088 2089 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2090 struct atmel_mci_slot *slot = host->slot[i]; 2091 if (slot && (status & slot->sdio_irq)) { 2092 mmc_signal_sdio_irq(slot->mmc); 2093 } 2094 } 2095} 2096 2097 2098static irqreturn_t atmci_interrupt(int irq, void *dev_id) 2099{ 2100 struct atmel_mci *host = dev_id; 2101 struct device *dev = host->dev; 2102 u32 status, mask, pending; 2103 unsigned int pass_count = 0; 2104 2105 do { 2106 status = atmci_readl(host, ATMCI_SR); 2107 mask = atmci_readl(host, ATMCI_IMR); 2108 pending = status & mask; 2109 if (!pending) 2110 break; 2111 2112 if (pending & ATMCI_DATA_ERROR_FLAGS) { 2113 dev_dbg(dev, "IRQ: data error\n"); 2114 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS 2115 | ATMCI_RXRDY | ATMCI_TXRDY 2116 | ATMCI_ENDRX | ATMCI_ENDTX 2117 | ATMCI_RXBUFF | ATMCI_TXBUFE); 2118 2119 host->data_status = status; 2120 dev_dbg(dev, "set pending data error\n"); 2121 smp_wmb(); 2122 atmci_set_pending(host, EVENT_DATA_ERROR); 2123 queue_work(system_bh_wq, &host->bh_work); 2124 } 2125 2126 if (pending & ATMCI_TXBUFE) { 2127 dev_dbg(dev, "IRQ: tx buffer empty\n"); 2128 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); 2129 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2130 /* 2131 * We can receive this interruption before having configured 2132 * the second pdc buffer, so we need to reconfigure first and 2133 * second buffers again 2134 */ 2135 if (host->data_size) { 2136 atmci_pdc_set_both_buf(host, XFER_TRANSMIT); 2137 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2138 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); 2139 } else { 2140 atmci_pdc_complete(host); 2141 } 2142 } else if (pending & ATMCI_ENDTX) { 2143 dev_dbg(dev, "IRQ: end of tx buffer\n"); 2144 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2145 2146 if (host->data_size) { 2147 atmci_pdc_set_single_buf(host, 2148 XFER_TRANSMIT, PDC_SECOND_BUF); 2149 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2150 } 2151 } 2152 2153 if (pending & ATMCI_RXBUFF) { 2154 dev_dbg(dev, "IRQ: rx buffer full\n"); 2155 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); 2156 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2157 /* 2158 * We can receive this interruption before having configured 2159 * the second pdc buffer, so we need to reconfigure first and 2160 * second buffers again 2161 */ 2162 if (host->data_size) { 2163 atmci_pdc_set_both_buf(host, XFER_RECEIVE); 2164 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2165 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); 2166 } else { 2167 atmci_pdc_complete(host); 2168 } 2169 } else if (pending & ATMCI_ENDRX) { 2170 dev_dbg(dev, "IRQ: end of rx buffer\n"); 2171 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2172 2173 if (host->data_size) { 2174 atmci_pdc_set_single_buf(host, 2175 XFER_RECEIVE, PDC_SECOND_BUF); 2176 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2177 } 2178 } 2179 2180 /* 2181 * First mci IPs, so mainly the ones having pdc, have some 2182 * issues with the notbusy signal. You can't get it after 2183 * data transmission if you have not sent a stop command. 2184 * The appropriate workaround is to use the BLKE signal. 2185 */ 2186 if (pending & ATMCI_BLKE) { 2187 dev_dbg(dev, "IRQ: blke\n"); 2188 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); 2189 smp_wmb(); 2190 dev_dbg(dev, "set pending notbusy\n"); 2191 atmci_set_pending(host, EVENT_NOTBUSY); 2192 queue_work(system_bh_wq, &host->bh_work); 2193 } 2194 2195 if (pending & ATMCI_NOTBUSY) { 2196 dev_dbg(dev, "IRQ: not_busy\n"); 2197 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); 2198 smp_wmb(); 2199 dev_dbg(dev, "set pending notbusy\n"); 2200 atmci_set_pending(host, EVENT_NOTBUSY); 2201 queue_work(system_bh_wq, &host->bh_work); 2202 } 2203 2204 if (pending & ATMCI_RXRDY) 2205 atmci_read_data_pio(host); 2206 if (pending & ATMCI_TXRDY) 2207 atmci_write_data_pio(host); 2208 2209 if (pending & ATMCI_CMDRDY) { 2210 dev_dbg(dev, "IRQ: cmd ready\n"); 2211 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); 2212 host->cmd_status = status; 2213 smp_wmb(); 2214 dev_dbg(dev, "set pending cmd rdy\n"); 2215 atmci_set_pending(host, EVENT_CMD_RDY); 2216 queue_work(system_bh_wq, &host->bh_work); 2217 } 2218 2219 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 2220 atmci_sdio_interrupt(host, status); 2221 2222 } while (pass_count++ < 5); 2223 2224 return pass_count ? IRQ_HANDLED : IRQ_NONE; 2225} 2226 2227static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 2228{ 2229 struct atmel_mci_slot *slot = dev_id; 2230 2231 /* 2232 * Disable interrupts until the pin has stabilized and check 2233 * the state then. Use mod_timer() since we may be in the 2234 * middle of the timer routine when this interrupt triggers. 2235 */ 2236 disable_irq_nosync(irq); 2237 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 2238 2239 return IRQ_HANDLED; 2240} 2241 2242static int atmci_init_slot(struct atmel_mci *host, 2243 struct mci_slot_pdata *slot_data, unsigned int id, 2244 u32 sdc_reg, u32 sdio_irq) 2245{ 2246 struct device *dev = host->dev; 2247 struct mmc_host *mmc; 2248 struct atmel_mci_slot *slot; 2249 int ret; 2250 2251 mmc = devm_mmc_alloc_host(dev, sizeof(*slot)); 2252 if (!mmc) 2253 return -ENOMEM; 2254 2255 slot = mmc_priv(mmc); 2256 slot->mmc = mmc; 2257 slot->host = host; 2258 slot->detect_pin = slot_data->detect_pin; 2259 slot->wp_pin = slot_data->wp_pin; 2260 slot->sdc_reg = sdc_reg; 2261 slot->sdio_irq = sdio_irq; 2262 2263 dev_dbg(&mmc->class_dev, 2264 "slot[%u]: bus_width=%u, detect_pin=%d, " 2265 "detect_is_active_high=%s, wp_pin=%d\n", 2266 id, slot_data->bus_width, desc_to_gpio(slot_data->detect_pin), 2267 str_true_false(!gpiod_is_active_low(slot_data->detect_pin)), 2268 desc_to_gpio(slot_data->wp_pin)); 2269 2270 mmc->ops = &atmci_ops; 2271 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 2272 mmc->f_max = host->bus_hz / 2; 2273 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2274 if (sdio_irq) 2275 mmc->caps |= MMC_CAP_SDIO_IRQ; 2276 if (host->caps.has_highspeed) 2277 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2278 /* 2279 * Without the read/write proof capability, it is strongly suggested to 2280 * use only one bit for data to prevent fifo underruns and overruns 2281 * which will corrupt data. 2282 */ 2283 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) { 2284 mmc->caps |= MMC_CAP_4_BIT_DATA; 2285 if (slot_data->bus_width >= 8) 2286 mmc->caps |= MMC_CAP_8_BIT_DATA; 2287 } 2288 2289 if (atmci_get_version(host) < 0x200) { 2290 mmc->max_segs = 256; 2291 mmc->max_blk_size = 4095; 2292 mmc->max_blk_count = 256; 2293 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2294 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs; 2295 } else { 2296 mmc->max_segs = 64; 2297 mmc->max_req_size = 32768 * 512; 2298 mmc->max_blk_size = 32768; 2299 mmc->max_blk_count = 512; 2300 } 2301 2302 /* Assume card is present initially */ 2303 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 2304 if (slot->detect_pin) { 2305 if (!gpiod_get_value_cansleep(slot->detect_pin)) 2306 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 2307 } else { 2308 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 2309 } 2310 2311 if (!slot->detect_pin) { 2312 if (slot_data->non_removable) 2313 mmc->caps |= MMC_CAP_NONREMOVABLE; 2314 else 2315 mmc->caps |= MMC_CAP_NEEDS_POLL; 2316 } 2317 2318 if (!slot->wp_pin) 2319 dev_dbg(&mmc->class_dev, "no WP pin available\n"); 2320 2321 host->slot[id] = slot; 2322 mmc_regulator_get_supply(mmc); 2323 ret = mmc_add_host(mmc); 2324 if (ret) 2325 return ret; 2326 2327 if (slot->detect_pin) { 2328 timer_setup(&slot->detect_timer, atmci_detect_change, 0); 2329 2330 ret = request_irq(gpiod_to_irq(slot->detect_pin), 2331 atmci_detect_interrupt, 2332 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 2333 "mmc-detect", slot); 2334 if (ret) { 2335 dev_dbg(&mmc->class_dev, 2336 "could not request IRQ %d for detect pin\n", 2337 gpiod_to_irq(slot->detect_pin)); 2338 slot->detect_pin = NULL; 2339 } 2340 } 2341 2342 atmci_init_debugfs(slot); 2343 2344 return 0; 2345} 2346 2347static void atmci_cleanup_slot(struct atmel_mci_slot *slot, 2348 unsigned int id) 2349{ 2350 /* Debugfs stuff is cleaned up by mmc core */ 2351 2352 set_bit(ATMCI_SHUTDOWN, &slot->flags); 2353 smp_wmb(); 2354 2355 mmc_remove_host(slot->mmc); 2356 2357 if (slot->detect_pin) { 2358 free_irq(gpiod_to_irq(slot->detect_pin), slot); 2359 timer_delete_sync(&slot->detect_timer); 2360 } 2361 2362 slot->host->slot[id] = NULL; 2363} 2364 2365static int atmci_configure_dma(struct atmel_mci *host) 2366{ 2367 struct device *dev = host->dev; 2368 2369 host->dma.chan = dma_request_chan(dev, "rxtx"); 2370 if (IS_ERR(host->dma.chan)) 2371 return PTR_ERR(host->dma.chan); 2372 2373 dev_info(dev, "using %s for DMA transfers\n", dma_chan_name(host->dma.chan)); 2374 2375 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; 2376 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2377 host->dma_conf.src_maxburst = 1; 2378 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR; 2379 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2380 host->dma_conf.dst_maxburst = 1; 2381 host->dma_conf.device_fc = false; 2382 2383 return 0; 2384} 2385 2386/* 2387 * HSMCI (High Speed MCI) module is not fully compatible with MCI module. 2388 * HSMCI provides DMA support and a new config register but no more supports 2389 * PDC. 2390 */ 2391static void atmci_get_cap(struct atmel_mci *host) 2392{ 2393 struct device *dev = host->dev; 2394 unsigned int version; 2395 2396 version = atmci_get_version(host); 2397 dev_info(dev, "version: 0x%x\n", version); 2398 2399 host->caps.has_dma_conf_reg = false; 2400 host->caps.has_pdc = true; 2401 host->caps.has_cfg_reg = false; 2402 host->caps.has_cstor_reg = false; 2403 host->caps.has_highspeed = false; 2404 host->caps.has_rwproof = false; 2405 host->caps.has_odd_clk_div = false; 2406 host->caps.has_bad_data_ordering = true; 2407 host->caps.need_reset_after_xfer = true; 2408 host->caps.need_blksz_mul_4 = true; 2409 host->caps.need_notbusy_for_read_ops = false; 2410 2411 /* keep only major version number */ 2412 switch (version & 0xf00) { 2413 case 0x600: 2414 case 0x500: 2415 host->caps.has_odd_clk_div = true; 2416 fallthrough; 2417 case 0x400: 2418 case 0x300: 2419 host->caps.has_dma_conf_reg = true; 2420 host->caps.has_pdc = false; 2421 host->caps.has_cfg_reg = true; 2422 host->caps.has_cstor_reg = true; 2423 host->caps.has_highspeed = true; 2424 fallthrough; 2425 case 0x200: 2426 host->caps.has_rwproof = true; 2427 host->caps.need_blksz_mul_4 = false; 2428 host->caps.need_notbusy_for_read_ops = true; 2429 fallthrough; 2430 case 0x100: 2431 host->caps.has_bad_data_ordering = false; 2432 host->caps.need_reset_after_xfer = false; 2433 fallthrough; 2434 case 0x0: 2435 break; 2436 default: 2437 host->caps.has_pdc = false; 2438 dev_warn(dev, "Unmanaged mci version, set minimum capabilities\n"); 2439 break; 2440 } 2441} 2442 2443static int atmci_probe(struct platform_device *pdev) 2444{ 2445 struct device *dev = &pdev->dev; 2446 struct atmel_mci *host; 2447 struct resource *regs; 2448 unsigned int nr_slots; 2449 int irq; 2450 int ret, i; 2451 2452 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2453 if (!regs) 2454 return -ENXIO; 2455 2456 irq = platform_get_irq(pdev, 0); 2457 if (irq < 0) 2458 return irq; 2459 2460 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 2461 if (!host) 2462 return -ENOMEM; 2463 2464 host->dev = dev; 2465 spin_lock_init(&host->lock); 2466 INIT_LIST_HEAD(&host->queue); 2467 2468 ret = atmci_of_init(host); 2469 if (ret) 2470 return dev_err_probe(dev, ret, "Slot information not available\n"); 2471 2472 host->mck = devm_clk_get(dev, "mci_clk"); 2473 if (IS_ERR(host->mck)) 2474 return PTR_ERR(host->mck); 2475 2476 host->regs = devm_ioremap(dev, regs->start, resource_size(regs)); 2477 if (!host->regs) 2478 return -ENOMEM; 2479 2480 ret = clk_prepare_enable(host->mck); 2481 if (ret) 2482 return ret; 2483 2484 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 2485 host->bus_hz = clk_get_rate(host->mck); 2486 2487 host->mapbase = regs->start; 2488 2489 INIT_WORK(&host->bh_work, atmci_work_func); 2490 2491 ret = request_irq(irq, atmci_interrupt, 0, dev_name(dev), host); 2492 if (ret) { 2493 clk_disable_unprepare(host->mck); 2494 return ret; 2495 } 2496 2497 /* Get MCI capabilities and set operations according to it */ 2498 atmci_get_cap(host); 2499 ret = atmci_configure_dma(host); 2500 if (ret == -EPROBE_DEFER) { 2501 clk_disable_unprepare(host->mck); 2502 goto err_dma_probe_defer; 2503 } 2504 if (ret == 0) { 2505 host->prepare_data = &atmci_prepare_data_dma; 2506 host->submit_data = &atmci_submit_data_dma; 2507 host->stop_transfer = &atmci_stop_transfer_dma; 2508 } else if (host->caps.has_pdc) { 2509 dev_info(dev, "using PDC\n"); 2510 host->prepare_data = &atmci_prepare_data_pdc; 2511 host->submit_data = &atmci_submit_data_pdc; 2512 host->stop_transfer = &atmci_stop_transfer_pdc; 2513 } else { 2514 dev_info(dev, "using PIO\n"); 2515 host->prepare_data = &atmci_prepare_data; 2516 host->submit_data = &atmci_submit_data; 2517 host->stop_transfer = &atmci_stop_transfer; 2518 } 2519 2520 platform_set_drvdata(pdev, host); 2521 2522 timer_setup(&host->timer, atmci_timeout_timer, 0); 2523 2524 pm_runtime_get_noresume(dev); 2525 pm_runtime_set_active(dev); 2526 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_DELAY); 2527 pm_runtime_use_autosuspend(dev); 2528 pm_runtime_enable(dev); 2529 2530 /* We need at least one slot to succeed */ 2531 nr_slots = 0; 2532 ret = -ENODEV; 2533 if (host->pdata[0].bus_width) { 2534 ret = atmci_init_slot(host, &host->pdata[0], 2535 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); 2536 if (!ret) { 2537 nr_slots++; 2538 host->buf_size = host->slot[0]->mmc->max_req_size; 2539 } 2540 } 2541 if (host->pdata[1].bus_width) { 2542 ret = atmci_init_slot(host, &host->pdata[1], 2543 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); 2544 if (!ret) { 2545 nr_slots++; 2546 if (host->slot[1]->mmc->max_req_size > host->buf_size) 2547 host->buf_size = 2548 host->slot[1]->mmc->max_req_size; 2549 } 2550 } 2551 2552 if (!nr_slots) { 2553 dev_err_probe(dev, ret, "init failed: no slot defined\n"); 2554 goto err_init_slot; 2555 } 2556 2557 if (!host->caps.has_rwproof) { 2558 host->buffer = dma_alloc_coherent(dev, host->buf_size, 2559 &host->buf_phys_addr, 2560 GFP_KERNEL); 2561 if (!host->buffer) { 2562 ret = dev_err_probe(dev, -ENOMEM, "buffer allocation failed\n"); 2563 goto err_dma_alloc; 2564 } 2565 } 2566 2567 dev_info(dev, "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2568 host->mapbase, irq, nr_slots); 2569 2570 pm_runtime_put_autosuspend(dev); 2571 2572 return 0; 2573 2574err_dma_alloc: 2575 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2576 if (host->slot[i]) 2577 atmci_cleanup_slot(host->slot[i], i); 2578 } 2579err_init_slot: 2580 clk_disable_unprepare(host->mck); 2581 2582 pm_runtime_disable(dev); 2583 pm_runtime_put_noidle(dev); 2584 2585 timer_delete_sync(&host->timer); 2586 if (!IS_ERR(host->dma.chan)) 2587 dma_release_channel(host->dma.chan); 2588err_dma_probe_defer: 2589 free_irq(irq, host); 2590 return ret; 2591} 2592 2593static void atmci_remove(struct platform_device *pdev) 2594{ 2595 struct atmel_mci *host = platform_get_drvdata(pdev); 2596 struct device *dev = &pdev->dev; 2597 unsigned int i; 2598 2599 pm_runtime_get_sync(dev); 2600 2601 if (host->buffer) 2602 dma_free_coherent(dev, host->buf_size, host->buffer, host->buf_phys_addr); 2603 2604 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2605 if (host->slot[i]) 2606 atmci_cleanup_slot(host->slot[i], i); 2607 } 2608 2609 atmci_writel(host, ATMCI_IDR, ~0UL); 2610 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 2611 atmci_readl(host, ATMCI_SR); 2612 2613 timer_delete_sync(&host->timer); 2614 if (!IS_ERR(host->dma.chan)) 2615 dma_release_channel(host->dma.chan); 2616 2617 free_irq(platform_get_irq(pdev, 0), host); 2618 2619 clk_disable_unprepare(host->mck); 2620 2621 pm_runtime_disable(dev); 2622 pm_runtime_put_noidle(dev); 2623} 2624 2625static int atmci_runtime_suspend(struct device *dev) 2626{ 2627 struct atmel_mci *host = dev_get_drvdata(dev); 2628 2629 clk_disable_unprepare(host->mck); 2630 2631 pinctrl_pm_select_sleep_state(dev); 2632 2633 return 0; 2634} 2635 2636static int atmci_runtime_resume(struct device *dev) 2637{ 2638 struct atmel_mci *host = dev_get_drvdata(dev); 2639 2640 pinctrl_select_default_state(dev); 2641 2642 return clk_prepare_enable(host->mck); 2643} 2644 2645static const struct dev_pm_ops atmci_dev_pm_ops = { 2646 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 2647 RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL) 2648}; 2649 2650static struct platform_driver atmci_driver = { 2651 .probe = atmci_probe, 2652 .remove = atmci_remove, 2653 .driver = { 2654 .name = "atmel_mci", 2655 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2656 .of_match_table = atmci_dt_ids, 2657 .pm = pm_ptr(&atmci_dev_pm_ops), 2658 }, 2659}; 2660module_platform_driver(atmci_driver); 2661 2662MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); 2663MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2664MODULE_LICENSE("GPL v2");
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