pci-me.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
  4 * Intel Management Engine Interface (Intel MEI) Linux driver
  5 */
  6
  7#include <linux/module.h>
  8#include <linux/kernel.h>
  9#include <linux/device.h>
 10#include <linux/errno.h>
 11#include <linux/types.h>
 12#include <linux/pci.h>
 13#include <linux/dma-mapping.h>
 14#include <linux/sched.h>
 15#include <linux/interrupt.h>
 16
 17#include <linux/pm_domain.h>
 18#include <linux/pm_runtime.h>
 19
 20#include <linux/mei.h>
 21
 22#include "mei_dev.h"
 23#include "client.h"
 24#include "hw-me-regs.h"
 25#include "hw-me.h"
 26
 27/* mei_pci_tbl - PCI Device ID Table */
 28static const struct pci_device_id mei_me_pci_tbl[] = {
 29	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
 30	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
 31	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
 32	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
 33	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
 34	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
 35	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
 36	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
 37	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
 38	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
 39	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
 40
 41	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
 42	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
 43	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
 44	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
 45	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
 46	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
 47	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
 48	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
 49	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
 50
 51	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
 52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
 53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
 54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
 55
 56	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
 57	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
 58	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
 59	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
 60	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
 61	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
 62	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
 63	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
 64	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
 65	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
 66	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
 67	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
 68	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
 69
 70	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
 71	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
 72	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
 73	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
 74	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
 75	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
 76
 77	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
 78	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
 79
 80	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
 81
 82	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
 83
 84	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
 85	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
 86	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
 87
 88	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
 89	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
 90	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
 91	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
 92
 93	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
 94	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
 95	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
 96	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
 97	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
 98
 99	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
100	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
101
102	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
103	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
104
105	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
106
107	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
108	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
109
110	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
111
112	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
113
114	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
115	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
116	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
117	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
118
119	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},
120
121	{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
122	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
123	{MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
124
125	{MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},
126
127	{MEI_PCI_DEVICE(MEI_DEV_ID_PTL_H, MEI_ME_PCH15_CFG)},
128	{MEI_PCI_DEVICE(MEI_DEV_ID_PTL_P, MEI_ME_PCH15_CFG)},
129
130	{MEI_PCI_DEVICE(MEI_DEV_ID_WCL_P, MEI_ME_PCH15_CFG)},
131
132	{MEI_PCI_DEVICE(MEI_DEV_ID_NVL_S, MEI_ME_PCH15_CFG)},
133
134	/* required last entry */
135	{0, }
136};
137
138MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
139
140#ifdef CONFIG_PM
141static inline void mei_me_set_pm_domain(struct mei_device *dev);
142static inline void mei_me_unset_pm_domain(struct mei_device *dev);
143#else
144static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
145static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
146#endif /* CONFIG_PM */
147
148static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
149{
150	struct pci_dev *pdev = to_pci_dev(dev->parent);
151
152	return pci_read_config_dword(pdev, where, val);
153}
154
155/**
156 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
157 *
158 * @pdev: PCI device structure
159 * @cfg: per generation config
160 *
161 * Return: true if ME Interface is valid, false otherwise
162 */
163static bool mei_me_quirk_probe(struct pci_dev *pdev,
164				const struct mei_cfg *cfg)
165{
166	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
167		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
168		return false;
169	}
170
171	return true;
172}
173
174/**
175 * mei_me_probe - Device Initialization Routine
176 *
177 * @pdev: PCI device structure
178 * @ent: entry in kcs_pci_tbl
179 *
180 * Return: 0 on success, <0 on failure.
181 */
182static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
183{
184	const struct mei_cfg *cfg;
185	struct mei_device *dev;
186	struct mei_me_hw *hw;
187	unsigned int irqflags;
188	int err;
189
190	cfg = mei_me_get_cfg(ent->driver_data);
191	if (!cfg)
192		return -ENODEV;
193
194	if (!mei_me_quirk_probe(pdev, cfg))
195		return -ENODEV;
196
197	/* enable pci dev */
198	err = pcim_enable_device(pdev);
199	if (err) {
200		dev_err(&pdev->dev, "failed to enable pci device.\n");
201		goto end;
202	}
203	/* set PCI host mastering  */
204	pci_set_master(pdev);
205	/* pci request regions and mapping IO device memory for mei driver */
206	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
207	if (err) {
208		dev_err(&pdev->dev, "failed to get pci regions.\n");
209		goto end;
210	}
211
212	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
213	if (err) {
214		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
215		goto end;
216	}
217
218	/* allocates and initializes the mei dev structure */
219	dev = mei_me_dev_init(&pdev->dev, cfg, false);
220	if (!dev) {
221		err = -ENOMEM;
222		goto end;
223	}
224	hw = to_me_hw(dev);
225	hw->mem_addr = pcim_iomap_table(pdev)[0];
226	hw->read_fws = mei_me_read_fws;
227
228	err = mei_register(dev, &pdev->dev);
229	if (err)
230		goto end;
231
232	pci_enable_msi(pdev);
233
234	hw->irq = pdev->irq;
235
236	 /* request and enable interrupt */
237	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
238
239	err = request_threaded_irq(pdev->irq,
240			mei_me_irq_quick_handler,
241			mei_me_irq_thread_handler,
242			irqflags, KBUILD_MODNAME, dev);
243	if (err) {
244		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
245		       pdev->irq);
246		goto deregister;
247	}
248
249	if (mei_start(dev)) {
250		dev_err(&pdev->dev, "init hw failure.\n");
251		err = -ENODEV;
252		goto deregister;
253	}
254
255	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
256	pm_runtime_use_autosuspend(&pdev->dev);
257
258	pci_set_drvdata(pdev, dev);
259
260	/*
261	 * MEI requires to resume from runtime suspend mode
262	 * in order to perform link reset flow upon system suspend.
263	 */
264	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
265
266	/*
267	 * ME maps runtime suspend/resume to D0i states,
268	 * hence we need to go around native PCI runtime service which
269	 * eventually brings the device into D3cold/hot state,
270	 * but the mei device cannot wake up from D3 unlike from D0i3.
271	 * To get around the PCI device native runtime pm,
272	 * ME uses runtime pm domain handlers which take precedence
273	 * over the driver's pm handlers.
274	 */
275	mei_me_set_pm_domain(dev);
276
277	if (mei_pg_is_enabled(dev)) {
278		pm_runtime_put_noidle(&pdev->dev);
279		if (hw->d0i3_supported)
280			pm_runtime_allow(&pdev->dev);
281	}
282
283	dev_dbg(&pdev->dev, "initialization successful.\n");
284
285	return 0;
286
287deregister:
288	mei_cancel_work(dev);
289	mei_disable_interrupts(dev);
290	free_irq(pdev->irq, dev);
291	mei_deregister(dev);
292end:
293	dev_err(&pdev->dev, "initialization failed.\n");
294	return err;
295}
296
297/**
298 * mei_me_shutdown - Device Removal Routine
299 *
300 * @pdev: PCI device structure
301 *
302 * mei_me_shutdown is called from the reboot notifier
303 * it's a simplified version of remove so we go down
304 * faster.
305 */
306static void mei_me_shutdown(struct pci_dev *pdev)
307{
308	struct mei_device *dev = pci_get_drvdata(pdev);
309
310	dev_dbg(&pdev->dev, "shutdown\n");
311	mei_stop(dev);
312
313	mei_me_unset_pm_domain(dev);
314
315	mei_disable_interrupts(dev);
316	free_irq(pdev->irq, dev);
317}
318
319/**
320 * mei_me_remove - Device Removal Routine
321 *
322 * @pdev: PCI device structure
323 *
324 * mei_me_remove is called by the PCI subsystem to alert the driver
325 * that it should release a PCI device.
326 */
327static void mei_me_remove(struct pci_dev *pdev)
328{
329	struct mei_device *dev = pci_get_drvdata(pdev);
330
331	if (mei_pg_is_enabled(dev))
332		pm_runtime_get_noresume(&pdev->dev);
333
334	dev_dbg(&pdev->dev, "stop\n");
335	mei_stop(dev);
336
337	mei_me_unset_pm_domain(dev);
338
339	mei_disable_interrupts(dev);
340
341	free_irq(pdev->irq, dev);
342
343	mei_deregister(dev);
344}
345
346#ifdef CONFIG_PM_SLEEP
347static int mei_me_pci_prepare(struct device *device)
348{
349	pm_runtime_resume(device);
350	return 0;
351}
352
353static int mei_me_pci_suspend(struct device *device)
354{
355	struct pci_dev *pdev = to_pci_dev(device);
356	struct mei_device *dev = pci_get_drvdata(pdev);
357
358	dev_dbg(&pdev->dev, "suspend\n");
359
360	mei_stop(dev);
361
362	mei_disable_interrupts(dev);
363
364	free_irq(pdev->irq, dev);
365	pci_disable_msi(pdev);
366
367	return 0;
368}
369
370static int mei_me_pci_resume(struct device *device)
371{
372	struct pci_dev *pdev = to_pci_dev(device);
373	struct mei_device *dev = pci_get_drvdata(pdev);
374	unsigned int irqflags;
375	int err;
376
377	pci_enable_msi(pdev);
378
379	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
380
381	/* request and enable interrupt */
382	err = request_threaded_irq(pdev->irq,
383			mei_me_irq_quick_handler,
384			mei_me_irq_thread_handler,
385			irqflags, KBUILD_MODNAME, dev);
386
387	if (err) {
388		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
389				pdev->irq);
390		return err;
391	}
392
393	err = mei_restart(dev);
394	if (err) {
395		free_irq(pdev->irq, dev);
396		return err;
397	}
398
399	/* Start timer if stopped in suspend */
400	schedule_delayed_work(&dev->timer_work, HZ);
401
402	return 0;
403}
404
405static void mei_me_pci_complete(struct device *device)
406{
407	pm_runtime_suspend(device);
408}
409#else /* CONFIG_PM_SLEEP */
410
411#define mei_me_pci_prepare NULL
412#define mei_me_pci_complete NULL
413
414#endif /* !CONFIG_PM_SLEEP */
415
416#ifdef CONFIG_PM
417static int mei_me_pm_runtime_idle(struct device *device)
418{
419	struct mei_device *dev = dev_get_drvdata(device);
420
421	dev_dbg(device, "rpm: me: runtime_idle\n");
422
423	if (mei_write_is_idle(dev))
424		pm_runtime_autosuspend(device);
425
426	return -EBUSY;
427}
428
429static int mei_me_pm_runtime_suspend(struct device *device)
430{
431	struct mei_device *dev = dev_get_drvdata(device);
432	int ret;
433
434	dev_dbg(device, "rpm: me: runtime suspend\n");
435
436	mutex_lock(&dev->device_lock);
437
438	if (mei_write_is_idle(dev))
439		ret = mei_me_pg_enter_sync(dev);
440	else
441		ret = -EAGAIN;
442
443	mutex_unlock(&dev->device_lock);
444
445	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
446
447	if (ret && ret != -EAGAIN)
448		schedule_work(&dev->reset_work);
449
450	return ret;
451}
452
453static int mei_me_pm_runtime_resume(struct device *device)
454{
455	struct mei_device *dev = dev_get_drvdata(device);
456	int ret;
457
458	dev_dbg(device, "rpm: me: runtime resume\n");
459
460	mutex_lock(&dev->device_lock);
461
462	ret = mei_me_pg_exit_sync(dev);
463
464	mutex_unlock(&dev->device_lock);
465
466	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
467
468	if (ret)
469		schedule_work(&dev->reset_work);
470
471	return ret;
472}
473
474/**
475 * mei_me_set_pm_domain - fill and set pm domain structure for device
476 *
477 * @dev: mei_device
478 */
479static inline void mei_me_set_pm_domain(struct mei_device *dev)
480{
481	struct pci_dev *pdev  = to_pci_dev(dev->parent);
482
483	if (pdev->dev.bus && pdev->dev.bus->pm) {
484		dev->pg_domain.ops = *pdev->dev.bus->pm;
485
486		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
487		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
488		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
489
490		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
491	}
492}
493
494/**
495 * mei_me_unset_pm_domain - clean pm domain structure for device
496 *
497 * @dev: mei_device
498 */
499static inline void mei_me_unset_pm_domain(struct mei_device *dev)
500{
501	/* stop using pm callbacks if any */
502	dev_pm_domain_set(dev->parent, NULL);
503}
504
505static const struct dev_pm_ops mei_me_pm_ops = {
506	.prepare = mei_me_pci_prepare,
507	.complete = mei_me_pci_complete,
508	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
509				mei_me_pci_resume)
510	SET_RUNTIME_PM_OPS(
511		mei_me_pm_runtime_suspend,
512		mei_me_pm_runtime_resume,
513		mei_me_pm_runtime_idle)
514};
515
516#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
517#else
518#define MEI_ME_PM_OPS	NULL
519#endif /* CONFIG_PM */
520/*
521 *  PCI driver structure
522 */
523static struct pci_driver mei_me_driver = {
524	.name = KBUILD_MODNAME,
525	.id_table = mei_me_pci_tbl,
526	.probe = mei_me_probe,
527	.remove = mei_me_remove,
528	.shutdown = mei_me_shutdown,
529	.driver.pm = MEI_ME_PM_OPS,
530	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
531};
532
533module_pci_driver(mei_me_driver);
534
535MODULE_AUTHOR("Intel Corporation");
536MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
537MODULE_LICENSE("GPL v2");