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cp500.c
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linux-6.19.14/drivers/misc/keba/cp500.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) KEBA Industrial Automation Gmbh 2024 4 * 5 * Driver for KEBA system FPGA 6 * 7 * The KEBA system FPGA implements various devices. This driver registers 8 * auxiliary devices for every device within the FPGA. 9 */ 10 11#include <linux/device.h> 12#include <linux/i2c.h> 13#include <linux/misc/keba.h> 14#include <linux/module.h> 15#include <linux/mtd/partitions.h> 16#include <linux/nvmem-consumer.h> 17#include <linux/nvmem-provider.h> 18#include <linux/pci.h> 19#include <linux/spi/flash.h> 20#include <linux/spi/spi.h> 21 22#define CP500 "cp500" 23 24#define PCI_VENDOR_ID_KEBA 0xCEBA 25#define PCI_DEVICE_ID_KEBA_CP035 0x2706 26#define PCI_DEVICE_ID_KEBA_CP505 0x2703 27#define PCI_DEVICE_ID_KEBA_CP520 0x2696 28 29#define CP500_SYS_BAR 0 30#define CP500_ECM_BAR 1 31 32/* BAR 0 registers */ 33#define CP500_VERSION_REG 0x00 34#define CP500_RECONFIG_REG 0x11 /* upper 8-bits of STARTUP register */ 35#define CP500_PRESENT_REG 0x20 36#define CP500_AXI_REG 0x40 37 38/* Bits in BUILD_REG */ 39#define CP500_BUILD_TEST 0x8000 /* FPGA test version */ 40 41/* Bits in RECONFIG_REG */ 42#define CP500_RECFG_REQ 0x01 /* reconfigure FPGA on next reset */ 43 44/* Bits in PRESENT_REG */ 45#define CP500_PRESENT_FAN0 0x01 46 47/* MSIX */ 48#define CP500_AXI_MSIX 3 49#define CP500_RFB_UART_MSIX 4 50#define CP500_DEBUG_UART_MSIX 5 51#define CP500_SI1_UART_MSIX 6 52#define CP500_NUM_MSIX 8 53#define CP500_NUM_MSIX_NO_MMI 2 54#define CP500_NUM_MSIX_NO_AXI 3 55 56/* EEPROM */ 57#define CP500_EEPROM_DA_OFFSET 0x016F 58#define CP500_EEPROM_DA_ESC_TYPE_MASK 0x01 59#define CP500_EEPROM_ESC_LAN9252 0x00 60#define CP500_EEPROM_ESC_ET1100 0x01 61#define CP500_EEPROM_CPU_NAME "cpu_eeprom" 62#define CP500_EEPROM_CPU_OFFSET 0 63#define CP500_EEPROM_CPU_SIZE 3072 64#define CP500_EEPROM_USER_NAME "user_eeprom" 65#define CP500_EEPROM_USER_OFFSET 3072 66#define CP500_EEPROM_USER_SIZE 1024 67 68/* SPI flash running at full speed */ 69#define CP500_FLASH_HZ (33 * 1000 * 1000) 70 71/* LAN9252 */ 72#define CP500_LAN9252_HZ (10 * 1000 * 1000) 73 74#define CP500_IS_CP035(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP035) 75#define CP500_IS_CP505(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP505) 76#define CP500_IS_CP520(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP520) 77 78struct cp500_dev_info { 79 off_t offset; 80 size_t size; 81 unsigned int msix; 82}; 83 84struct cp500_devs { 85 struct cp500_dev_info startup; 86 struct cp500_dev_info spi; 87 struct cp500_dev_info i2c; 88 struct cp500_dev_info fan; 89 struct cp500_dev_info batt; 90 struct cp500_dev_info uart0_rfb; 91 struct cp500_dev_info uart1_dbg; 92 struct cp500_dev_info uart2_si1; 93}; 94 95/* list of devices within FPGA of CP035 family (CP035, CP056, CP057) */ 96static struct cp500_devs cp035_devices = { 97 .startup = { 0x0000, SZ_4K }, 98 .spi = { 0x1000, SZ_4K }, 99 .i2c = { 0x4000, SZ_4K }, 100 .fan = { 0x9000, SZ_4K }, 101 .batt = { 0xA000, SZ_4K }, 102 .uart0_rfb = { 0xB000, SZ_4K, CP500_RFB_UART_MSIX }, 103 .uart2_si1 = { 0xD000, SZ_4K, CP500_SI1_UART_MSIX }, 104}; 105 106/* list of devices within FPGA of CP505 family (CP503, CP505, CP507) */ 107static struct cp500_devs cp505_devices = { 108 .startup = { 0x0000, SZ_4K }, 109 .spi = { 0x4000, SZ_4K }, 110 .i2c = { 0x5000, SZ_4K }, 111 .fan = { 0x9000, SZ_4K }, 112 .batt = { 0xA000, SZ_4K }, 113 .uart0_rfb = { 0xB000, SZ_4K, CP500_RFB_UART_MSIX }, 114 .uart2_si1 = { 0xD000, SZ_4K, CP500_SI1_UART_MSIX }, 115}; 116 117/* list of devices within FPGA of CP520 family (CP520, CP530) */ 118static struct cp500_devs cp520_devices = { 119 .startup = { 0x0000, SZ_4K }, 120 .spi = { 0x4000, SZ_4K }, 121 .i2c = { 0x5000, SZ_4K }, 122 .fan = { 0x8000, SZ_4K }, 123 .batt = { 0x9000, SZ_4K }, 124 .uart0_rfb = { 0xC000, SZ_4K, CP500_RFB_UART_MSIX }, 125 .uart1_dbg = { 0xD000, SZ_4K, CP500_DEBUG_UART_MSIX }, 126}; 127 128struct cp500_nvmem { 129 struct nvmem_device *base_nvmem; 130 unsigned int offset; 131 struct nvmem_device *nvmem; 132}; 133 134struct cp500 { 135 struct pci_dev *pci_dev; 136 struct cp500_devs *devs; 137 int msix_num; 138 struct { 139 int major; 140 int minor; 141 int build; 142 } version; 143 struct notifier_block nvmem_notifier; 144 atomic_t nvmem_notified; 145 146 /* system FPGA BAR */ 147 resource_size_t sys_hwbase; 148 struct keba_spi_auxdev *spi; 149 struct keba_i2c_auxdev *i2c; 150 struct keba_fan_auxdev *fan; 151 struct keba_batt_auxdev *batt; 152 struct keba_uart_auxdev *uart0_rfb; 153 struct keba_uart_auxdev *uart1_dbg; 154 struct keba_uart_auxdev *uart2_si1; 155 156 /* ECM EtherCAT BAR */ 157 resource_size_t ecm_hwbase; 158 159 /* NVMEM devices */ 160 struct cp500_nvmem nvmem_cpu; 161 struct cp500_nvmem nvmem_user; 162 163 void __iomem *system_startup_addr; 164}; 165 166/* I2C devices */ 167#define CP500_EEPROM_ADDR 0x50 168static struct i2c_board_info cp500_i2c_info[] = { 169 { /* temperature sensor */ 170 I2C_BOARD_INFO("emc1403", 0x4c), 171 }, 172 { /* 173 * CPU EEPROM 174 * CP035 family: CPU board 175 * CP505 family: bridge board 176 * CP520 family: carrier board 177 */ 178 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR), 179 }, 180 { /* interface board EEPROM */ 181 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 1), 182 }, 183 { /* 184 * EEPROM (optional) 185 * CP505 family: CPU board 186 * CP520 family: MMI board 187 */ 188 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 2), 189 }, 190 { /* extension module 0 EEPROM (optional) */ 191 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 3), 192 }, 193 { /* extension module 1 EEPROM (optional) */ 194 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 4), 195 }, 196 { /* extension module 2 EEPROM (optional) */ 197 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 5), 198 }, 199 { /* extension module 3 EEPROM (optional) */ 200 I2C_BOARD_INFO("24c32", CP500_EEPROM_ADDR + 6), 201 } 202}; 203 204/* SPI devices */ 205static struct mtd_partition cp500_partitions[] = { 206 { 207 .name = "system-flash-parts", 208 .size = MTDPART_SIZ_FULL, 209 .offset = 0, 210 .mask_flags = 0 211 } 212}; 213static const struct flash_platform_data cp500_w25q32 = { 214 .type = "w25q32", 215 .name = "system-flash", 216 .parts = cp500_partitions, 217 .nr_parts = ARRAY_SIZE(cp500_partitions), 218}; 219static const struct flash_platform_data cp500_m25p16 = { 220 .type = "m25p16", 221 .name = "system-flash", 222 .parts = cp500_partitions, 223 .nr_parts = ARRAY_SIZE(cp500_partitions), 224}; 225static struct spi_board_info cp500_spi_info[] = { 226 { /* system FPGA configuration bitstream flash */ 227 .modalias = "m25p80", 228 .platform_data = &cp500_m25p16, 229 .max_speed_hz = CP500_FLASH_HZ, 230 .chip_select = 0, 231 .mode = SPI_MODE_3, 232 }, { /* LAN9252 EtherCAT slave controller */ 233 .modalias = "lan9252", 234 .platform_data = NULL, 235 .max_speed_hz = CP500_LAN9252_HZ, 236 .chip_select = 1, 237 .mode = SPI_MODE_3, 238 } 239}; 240 241static ssize_t cp500_get_fpga_version(struct cp500 *cp500, char *buf, 242 size_t max_len) 243{ 244 int n; 245 246 if (CP500_IS_CP035(cp500)) 247 n = scnprintf(buf, max_len, "CP035"); 248 else if (CP500_IS_CP505(cp500)) 249 n = scnprintf(buf, max_len, "CP505"); 250 else 251 n = scnprintf(buf, max_len, "CP500"); 252 253 n += scnprintf(buf + n, max_len - n, "_FPGA_%d.%02d", 254 cp500->version.major, cp500->version.minor); 255 256 /* test versions have test bit set */ 257 if (cp500->version.build & CP500_BUILD_TEST) 258 n += scnprintf(buf + n, max_len - n, "Test%d", 259 cp500->version.build & ~CP500_BUILD_TEST); 260 261 n += scnprintf(buf + n, max_len - n, "\n"); 262 263 return n; 264} 265 266static ssize_t version_show(struct device *dev, struct device_attribute *attr, 267 char *buf) 268{ 269 struct cp500 *cp500 = dev_get_drvdata(dev); 270 271 return cp500_get_fpga_version(cp500, buf, PAGE_SIZE); 272} 273static DEVICE_ATTR_RO(version); 274 275static ssize_t keep_cfg_show(struct device *dev, struct device_attribute *attr, 276 char *buf) 277{ 278 struct cp500 *cp500 = dev_get_drvdata(dev); 279 unsigned long keep_cfg = 1; 280 281 /* 282 * FPGA configuration stream is kept during reset when RECONFIG bit is 283 * zero 284 */ 285 if (ioread8(cp500->system_startup_addr + CP500_RECONFIG_REG) & 286 CP500_RECFG_REQ) 287 keep_cfg = 0; 288 289 return sysfs_emit(buf, "%lu\n", keep_cfg); 290} 291 292static ssize_t keep_cfg_store(struct device *dev, struct device_attribute *attr, 293 const char *buf, size_t count) 294{ 295 struct cp500 *cp500 = dev_get_drvdata(dev); 296 unsigned long keep_cfg; 297 298 if (kstrtoul(buf, 10, &keep_cfg) < 0) 299 return -EINVAL; 300 301 /* 302 * In normal operation "keep_cfg" is "1". This means that the FPGA keeps 303 * its configuration stream during a reset. 304 * In case of a firmware update of the FPGA, the configuration stream 305 * needs to be reloaded. This can be done without a powercycle by 306 * writing a "0" into the "keep_cfg" attribute. After a reset/reboot th 307 * new configuration stream will be loaded. 308 */ 309 if (keep_cfg) 310 iowrite8(0, cp500->system_startup_addr + CP500_RECONFIG_REG); 311 else 312 iowrite8(CP500_RECFG_REQ, 313 cp500->system_startup_addr + CP500_RECONFIG_REG); 314 315 return count; 316} 317static DEVICE_ATTR_RW(keep_cfg); 318 319static struct attribute *cp500_attrs[] = { 320 &dev_attr_version.attr, 321 &dev_attr_keep_cfg.attr, 322 NULL 323}; 324ATTRIBUTE_GROUPS(cp500); 325 326static void cp500_i2c_release(struct device *dev) 327{ 328 struct keba_i2c_auxdev *i2c = 329 container_of(dev, struct keba_i2c_auxdev, auxdev.dev); 330 331 kfree(i2c); 332} 333 334static int cp500_register_i2c(struct cp500 *cp500) 335{ 336 int ret; 337 338 cp500->i2c = kzalloc(sizeof(*cp500->i2c), GFP_KERNEL); 339 if (!cp500->i2c) 340 return -ENOMEM; 341 342 cp500->i2c->auxdev.name = "i2c"; 343 cp500->i2c->auxdev.id = 0; 344 cp500->i2c->auxdev.dev.release = cp500_i2c_release; 345 cp500->i2c->auxdev.dev.parent = &cp500->pci_dev->dev; 346 cp500->i2c->io = (struct resource) { 347 /* I2C register area */ 348 .start = (resource_size_t) cp500->sys_hwbase + 349 cp500->devs->i2c.offset, 350 .end = (resource_size_t) cp500->sys_hwbase + 351 cp500->devs->i2c.offset + 352 cp500->devs->i2c.size - 1, 353 .flags = IORESOURCE_MEM, 354 }; 355 cp500->i2c->info_size = ARRAY_SIZE(cp500_i2c_info); 356 cp500->i2c->info = cp500_i2c_info; 357 358 ret = auxiliary_device_init(&cp500->i2c->auxdev); 359 if (ret) { 360 kfree(cp500->i2c); 361 cp500->i2c = NULL; 362 363 return ret; 364 } 365 ret = __auxiliary_device_add(&cp500->i2c->auxdev, "keba"); 366 if (ret) { 367 auxiliary_device_uninit(&cp500->i2c->auxdev); 368 cp500->i2c = NULL; 369 370 return ret; 371 } 372 373 return 0; 374} 375 376static void cp500_spi_release(struct device *dev) 377{ 378 struct keba_spi_auxdev *spi = 379 container_of(dev, struct keba_spi_auxdev, auxdev.dev); 380 381 kfree(spi); 382} 383 384static int cp500_register_spi(struct cp500 *cp500, u8 esc_type) 385{ 386 int info_size; 387 int ret; 388 389 cp500->spi = kzalloc(sizeof(*cp500->spi), GFP_KERNEL); 390 if (!cp500->spi) 391 return -ENOMEM; 392 393 if (CP500_IS_CP035(cp500)) 394 cp500_spi_info[0].platform_data = &cp500_w25q32; 395 if (esc_type == CP500_EEPROM_ESC_LAN9252) 396 info_size = ARRAY_SIZE(cp500_spi_info); 397 else 398 info_size = ARRAY_SIZE(cp500_spi_info) - 1; 399 400 cp500->spi->auxdev.name = "spi"; 401 cp500->spi->auxdev.id = 0; 402 cp500->spi->auxdev.dev.release = cp500_spi_release; 403 cp500->spi->auxdev.dev.parent = &cp500->pci_dev->dev; 404 cp500->spi->io = (struct resource) { 405 /* SPI register area */ 406 .start = (resource_size_t) cp500->sys_hwbase + 407 cp500->devs->spi.offset, 408 .end = (resource_size_t) cp500->sys_hwbase + 409 cp500->devs->spi.offset + 410 cp500->devs->spi.size - 1, 411 .flags = IORESOURCE_MEM, 412 }; 413 cp500->spi->info_size = info_size; 414 cp500->spi->info = cp500_spi_info; 415 416 ret = auxiliary_device_init(&cp500->spi->auxdev); 417 if (ret) { 418 kfree(cp500->spi); 419 cp500->spi = NULL; 420 421 return ret; 422 } 423 ret = __auxiliary_device_add(&cp500->spi->auxdev, "keba"); 424 if (ret) { 425 auxiliary_device_uninit(&cp500->spi->auxdev); 426 cp500->spi = NULL; 427 428 return ret; 429 } 430 431 return 0; 432} 433 434static void cp500_fan_release(struct device *dev) 435{ 436 struct keba_fan_auxdev *fan = 437 container_of(dev, struct keba_fan_auxdev, auxdev.dev); 438 439 kfree(fan); 440} 441 442static int cp500_register_fan(struct cp500 *cp500) 443{ 444 int ret; 445 446 cp500->fan = kzalloc(sizeof(*cp500->fan), GFP_KERNEL); 447 if (!cp500->fan) 448 return -ENOMEM; 449 450 cp500->fan->auxdev.name = "fan"; 451 cp500->fan->auxdev.id = 0; 452 cp500->fan->auxdev.dev.release = cp500_fan_release; 453 cp500->fan->auxdev.dev.parent = &cp500->pci_dev->dev; 454 cp500->fan->io = (struct resource) { 455 /* fan register area */ 456 .start = (resource_size_t) cp500->sys_hwbase + 457 cp500->devs->fan.offset, 458 .end = (resource_size_t) cp500->sys_hwbase + 459 cp500->devs->fan.offset + 460 cp500->devs->fan.size - 1, 461 .flags = IORESOURCE_MEM, 462 }; 463 464 ret = auxiliary_device_init(&cp500->fan->auxdev); 465 if (ret) { 466 kfree(cp500->fan); 467 cp500->fan = NULL; 468 469 return ret; 470 } 471 ret = __auxiliary_device_add(&cp500->fan->auxdev, "keba"); 472 if (ret) { 473 auxiliary_device_uninit(&cp500->fan->auxdev); 474 cp500->fan = NULL; 475 476 return ret; 477 } 478 479 return 0; 480} 481 482static void cp500_batt_release(struct device *dev) 483{ 484 struct keba_batt_auxdev *fan = 485 container_of(dev, struct keba_batt_auxdev, auxdev.dev); 486 487 kfree(fan); 488} 489 490static int cp500_register_batt(struct cp500 *cp500) 491{ 492 int ret; 493 494 cp500->batt = kzalloc(sizeof(*cp500->batt), GFP_KERNEL); 495 if (!cp500->batt) 496 return -ENOMEM; 497 498 cp500->batt->auxdev.name = "batt"; 499 cp500->batt->auxdev.id = 0; 500 cp500->batt->auxdev.dev.release = cp500_batt_release; 501 cp500->batt->auxdev.dev.parent = &cp500->pci_dev->dev; 502 cp500->batt->io = (struct resource) { 503 /* battery register area */ 504 .start = (resource_size_t) cp500->sys_hwbase + 505 cp500->devs->batt.offset, 506 .end = (resource_size_t) cp500->sys_hwbase + 507 cp500->devs->batt.offset + 508 cp500->devs->batt.size - 1, 509 .flags = IORESOURCE_MEM, 510 }; 511 512 ret = auxiliary_device_init(&cp500->batt->auxdev); 513 if (ret) { 514 kfree(cp500->batt); 515 cp500->batt = NULL; 516 517 return ret; 518 } 519 ret = __auxiliary_device_add(&cp500->batt->auxdev, "keba"); 520 if (ret) { 521 auxiliary_device_uninit(&cp500->batt->auxdev); 522 cp500->batt = NULL; 523 524 return ret; 525 } 526 527 return 0; 528} 529 530static void cp500_uart_release(struct device *dev) 531{ 532 struct keba_uart_auxdev *uart = 533 container_of(dev, struct keba_uart_auxdev, auxdev.dev); 534 535 kfree(uart); 536} 537 538static int cp500_register_uart(struct cp500 *cp500, 539 struct keba_uart_auxdev **uart, const char *name, 540 struct cp500_dev_info *info, unsigned int irq) 541{ 542 int ret; 543 544 *uart = kzalloc(sizeof(**uart), GFP_KERNEL); 545 if (!*uart) 546 return -ENOMEM; 547 548 (*uart)->auxdev.name = name; 549 (*uart)->auxdev.id = 0; 550 (*uart)->auxdev.dev.release = cp500_uart_release; 551 (*uart)->auxdev.dev.parent = &cp500->pci_dev->dev; 552 (*uart)->io = (struct resource) { 553 /* UART register area */ 554 .start = (resource_size_t) cp500->sys_hwbase + info->offset, 555 .end = (resource_size_t) cp500->sys_hwbase + info->offset + 556 info->size - 1, 557 .flags = IORESOURCE_MEM, 558 }; 559 (*uart)->irq = irq; 560 561 ret = auxiliary_device_init(&(*uart)->auxdev); 562 if (ret) { 563 kfree(*uart); 564 *uart = NULL; 565 566 return ret; 567 } 568 ret = __auxiliary_device_add(&(*uart)->auxdev, "keba"); 569 if (ret) { 570 auxiliary_device_uninit(&(*uart)->auxdev); 571 *uart = NULL; 572 573 return ret; 574 } 575 576 return 0; 577} 578 579static int cp500_nvmem_read(void *priv, unsigned int offset, void *val, 580 size_t bytes) 581{ 582 struct cp500_nvmem *nvmem = priv; 583 int ret; 584 585 ret = nvmem_device_read(nvmem->base_nvmem, nvmem->offset + offset, 586 bytes, val); 587 if (ret != bytes) 588 return ret; 589 590 return 0; 591} 592 593static int cp500_nvmem_write(void *priv, unsigned int offset, void *val, 594 size_t bytes) 595{ 596 struct cp500_nvmem *nvmem = priv; 597 int ret; 598 599 ret = nvmem_device_write(nvmem->base_nvmem, nvmem->offset + offset, 600 bytes, val); 601 if (ret != bytes) 602 return ret; 603 604 return 0; 605} 606 607static int cp500_nvmem_register(struct cp500 *cp500, 608 struct nvmem_device *base_nvmem) 609{ 610 struct device *dev = &cp500->pci_dev->dev; 611 struct nvmem_config nvmem_config = {}; 612 struct nvmem_device *tmp; 613 614 /* 615 * The main EEPROM of CP500 devices is logically split into two EEPROMs. 616 * The first logical EEPROM with 3 kB contains the type label which is 617 * programmed during production of the device. The second logical EEPROM 618 * with 1 kB is not programmed during production and can be used for 619 * arbitrary user data. 620 */ 621 622 nvmem_config.dev = dev; 623 nvmem_config.owner = THIS_MODULE; 624 nvmem_config.id = NVMEM_DEVID_NONE; 625 nvmem_config.type = NVMEM_TYPE_EEPROM; 626 nvmem_config.root_only = true; 627 nvmem_config.reg_read = cp500_nvmem_read; 628 nvmem_config.reg_write = cp500_nvmem_write; 629 630 cp500->nvmem_cpu.base_nvmem = base_nvmem; 631 cp500->nvmem_cpu.offset = CP500_EEPROM_CPU_OFFSET; 632 nvmem_config.name = CP500_EEPROM_CPU_NAME; 633 nvmem_config.size = CP500_EEPROM_CPU_SIZE; 634 nvmem_config.priv = &cp500->nvmem_cpu; 635 tmp = nvmem_register(&nvmem_config); 636 if (IS_ERR(tmp)) 637 return PTR_ERR(tmp); 638 cp500->nvmem_cpu.nvmem = tmp; 639 640 cp500->nvmem_user.base_nvmem = base_nvmem; 641 cp500->nvmem_user.offset = CP500_EEPROM_USER_OFFSET; 642 nvmem_config.name = CP500_EEPROM_USER_NAME; 643 nvmem_config.size = CP500_EEPROM_USER_SIZE; 644 nvmem_config.priv = &cp500->nvmem_user; 645 tmp = nvmem_register(&nvmem_config); 646 if (IS_ERR(tmp)) { 647 nvmem_unregister(cp500->nvmem_cpu.nvmem); 648 cp500->nvmem_cpu.nvmem = NULL; 649 650 return PTR_ERR(tmp); 651 } 652 cp500->nvmem_user.nvmem = tmp; 653 654 return 0; 655} 656 657static void cp500_nvmem_unregister(struct cp500 *cp500) 658{ 659 int notified; 660 661 if (cp500->nvmem_user.nvmem) { 662 nvmem_unregister(cp500->nvmem_user.nvmem); 663 cp500->nvmem_user.nvmem = NULL; 664 } 665 if (cp500->nvmem_cpu.nvmem) { 666 nvmem_unregister(cp500->nvmem_cpu.nvmem); 667 cp500->nvmem_cpu.nvmem = NULL; 668 } 669 670 /* CPU and user nvmem use the same base_nvmem, put only once */ 671 notified = atomic_read(&cp500->nvmem_notified); 672 if (notified) 673 nvmem_device_put(cp500->nvmem_cpu.base_nvmem); 674} 675 676static int cp500_nvmem_match(struct device *dev, const void *data) 677{ 678 const struct cp500 *cp500 = data; 679 struct i2c_client *client; 680 681 /* match only CPU EEPROM below the cp500 device */ 682 dev = dev->parent; 683 client = i2c_verify_client(dev); 684 if (!client || client->addr != CP500_EEPROM_ADDR) 685 return 0; 686 while ((dev = dev->parent)) 687 if (dev == &cp500->pci_dev->dev) 688 return 1; 689 690 return 0; 691} 692 693static int cp500_nvmem(struct notifier_block *nb, unsigned long action, 694 void *data) 695{ 696 struct nvmem_device *nvmem; 697 struct cp500 *cp500; 698 struct device *dev; 699 int notified; 700 u8 esc_type; 701 int ret; 702 703 if (action != NVMEM_ADD) 704 return NOTIFY_DONE; 705 cp500 = container_of(nb, struct cp500, nvmem_notifier); 706 dev = &cp500->pci_dev->dev; 707 708 /* process CPU EEPROM content only once */ 709 notified = atomic_read(&cp500->nvmem_notified); 710 if (notified) 711 return NOTIFY_DONE; 712 nvmem = nvmem_device_find(cp500, cp500_nvmem_match); 713 if (IS_ERR_OR_NULL(nvmem)) 714 return NOTIFY_DONE; 715 if (!atomic_try_cmpxchg_relaxed(&cp500->nvmem_notified, ¬ified, 1)) { 716 nvmem_device_put(nvmem); 717 718 return NOTIFY_DONE; 719 } 720 721 ret = cp500_nvmem_register(cp500, nvmem); 722 if (ret) 723 return ret; 724 725 ret = nvmem_device_read(nvmem, CP500_EEPROM_DA_OFFSET, sizeof(esc_type), 726 (void *)&esc_type); 727 if (ret != sizeof(esc_type)) { 728 dev_warn(dev, "Failed to read device assembly!\n"); 729 730 return NOTIFY_DONE; 731 } 732 esc_type &= CP500_EEPROM_DA_ESC_TYPE_MASK; 733 734 if (cp500_register_spi(cp500, esc_type)) 735 dev_warn(dev, "Failed to register SPI!\n"); 736 737 return NOTIFY_OK; 738} 739 740static void cp500_register_auxiliary_devs(struct cp500 *cp500) 741{ 742 struct device *dev = &cp500->pci_dev->dev; 743 u8 present = ioread8(cp500->system_startup_addr + CP500_PRESENT_REG); 744 745 if (cp500_register_i2c(cp500)) 746 dev_warn(dev, "Failed to register I2C!\n"); 747 if (present & CP500_PRESENT_FAN0) 748 if (cp500_register_fan(cp500)) 749 dev_warn(dev, "Failed to register fan!\n"); 750 if (cp500_register_batt(cp500)) 751 dev_warn(dev, "Failed to register battery!\n"); 752 if (cp500->devs->uart0_rfb.size && 753 cp500->devs->uart0_rfb.msix < cp500->msix_num) { 754 int irq = pci_irq_vector(cp500->pci_dev, 755 cp500->devs->uart0_rfb.msix); 756 757 if (cp500_register_uart(cp500, &cp500->uart0_rfb, "rs485-uart", 758 &cp500->devs->uart0_rfb, irq)) 759 dev_warn(dev, "Failed to register RFB UART!\n"); 760 } 761 if (cp500->devs->uart1_dbg.size && 762 cp500->devs->uart1_dbg.msix < cp500->msix_num) { 763 int irq = pci_irq_vector(cp500->pci_dev, 764 cp500->devs->uart1_dbg.msix); 765 766 if (cp500_register_uart(cp500, &cp500->uart1_dbg, "rs232-uart", 767 &cp500->devs->uart1_dbg, irq)) 768 dev_warn(dev, "Failed to register debug UART!\n"); 769 } 770 if (cp500->devs->uart2_si1.size && 771 cp500->devs->uart2_si1.msix < cp500->msix_num) { 772 int irq = pci_irq_vector(cp500->pci_dev, 773 cp500->devs->uart2_si1.msix); 774 775 if (cp500_register_uart(cp500, &cp500->uart2_si1, "uart", 776 &cp500->devs->uart2_si1, irq)) 777 dev_warn(dev, "Failed to register SI1 UART!\n"); 778 } 779} 780 781static void cp500_unregister_dev(struct auxiliary_device *auxdev) 782{ 783 auxiliary_device_delete(auxdev); 784 auxiliary_device_uninit(auxdev); 785} 786 787static void cp500_unregister_auxiliary_devs(struct cp500 *cp500) 788{ 789 if (cp500->spi) { 790 cp500_unregister_dev(&cp500->spi->auxdev); 791 cp500->spi = NULL; 792 } 793 if (cp500->i2c) { 794 cp500_unregister_dev(&cp500->i2c->auxdev); 795 cp500->i2c = NULL; 796 } 797 if (cp500->fan) { 798 cp500_unregister_dev(&cp500->fan->auxdev); 799 cp500->fan = NULL; 800 } 801 if (cp500->batt) { 802 cp500_unregister_dev(&cp500->batt->auxdev); 803 cp500->batt = NULL; 804 } 805 if (cp500->uart0_rfb) { 806 cp500_unregister_dev(&cp500->uart0_rfb->auxdev); 807 cp500->uart0_rfb = NULL; 808 } 809 if (cp500->uart1_dbg) { 810 cp500_unregister_dev(&cp500->uart1_dbg->auxdev); 811 cp500->uart1_dbg = NULL; 812 } 813 if (cp500->uart2_si1) { 814 cp500_unregister_dev(&cp500->uart2_si1->auxdev); 815 cp500->uart2_si1 = NULL; 816 } 817} 818 819static irqreturn_t cp500_axi_handler(int irq, void *dev) 820{ 821 struct cp500 *cp500 = dev; 822 u32 axi_address = ioread32(cp500->system_startup_addr + CP500_AXI_REG); 823 824 /* 825 * FPGA signals AXI response error, print AXI address to indicate which 826 * IP core was affected 827 */ 828 dev_err(&cp500->pci_dev->dev, "AXI response error at 0x%08x\n", 829 axi_address); 830 831 return IRQ_HANDLED; 832} 833 834static int cp500_enable(struct cp500 *cp500) 835{ 836 int axi_irq = -1; 837 int ret; 838 839 if (cp500->msix_num > CP500_NUM_MSIX_NO_AXI) { 840 axi_irq = pci_irq_vector(cp500->pci_dev, CP500_AXI_MSIX); 841 ret = request_irq(axi_irq, cp500_axi_handler, 0, 842 CP500, cp500); 843 if (ret != 0) { 844 dev_err(&cp500->pci_dev->dev, 845 "Failed to register AXI response error!\n"); 846 return ret; 847 } 848 } 849 850 return 0; 851} 852 853static void cp500_disable(struct cp500 *cp500) 854{ 855 int axi_irq; 856 857 if (cp500->msix_num > CP500_NUM_MSIX_NO_AXI) { 858 axi_irq = pci_irq_vector(cp500->pci_dev, CP500_AXI_MSIX); 859 free_irq(axi_irq, cp500); 860 } 861} 862 863static int cp500_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) 864{ 865 struct device *dev = &pci_dev->dev; 866 struct resource startup; 867 struct cp500 *cp500; 868 u32 cp500_vers; 869 char buf[64]; 870 int ret; 871 872 cp500 = devm_kzalloc(dev, sizeof(*cp500), GFP_KERNEL); 873 if (!cp500) 874 return -ENOMEM; 875 cp500->pci_dev = pci_dev; 876 cp500->sys_hwbase = pci_resource_start(pci_dev, CP500_SYS_BAR); 877 cp500->ecm_hwbase = pci_resource_start(pci_dev, CP500_ECM_BAR); 878 if (!cp500->sys_hwbase || !cp500->ecm_hwbase) 879 return -ENODEV; 880 881 if (CP500_IS_CP035(cp500)) 882 cp500->devs = &cp035_devices; 883 else if (CP500_IS_CP505(cp500)) 884 cp500->devs = &cp505_devices; 885 else if (CP500_IS_CP520(cp500)) 886 cp500->devs = &cp520_devices; 887 else 888 return -ENODEV; 889 890 ret = pci_enable_device(pci_dev); 891 if (ret) 892 return ret; 893 pci_set_master(pci_dev); 894 895 startup = *pci_resource_n(pci_dev, CP500_SYS_BAR); 896 startup.end = startup.start + cp500->devs->startup.size - 1; 897 cp500->system_startup_addr = devm_ioremap_resource(&pci_dev->dev, 898 &startup); 899 if (IS_ERR(cp500->system_startup_addr)) { 900 ret = PTR_ERR(cp500->system_startup_addr); 901 goto out_disable; 902 } 903 904 cp500->msix_num = pci_alloc_irq_vectors(pci_dev, CP500_NUM_MSIX_NO_MMI, 905 CP500_NUM_MSIX, PCI_IRQ_MSIX); 906 if (cp500->msix_num < CP500_NUM_MSIX_NO_MMI) { 907 dev_err(&pci_dev->dev, 908 "Hardware does not support enough MSI-X interrupts\n"); 909 ret = -ENODEV; 910 goto out_disable; 911 } 912 913 cp500_vers = ioread32(cp500->system_startup_addr + CP500_VERSION_REG); 914 cp500->version.major = (cp500_vers & 0xff); 915 cp500->version.minor = (cp500_vers >> 8) & 0xff; 916 cp500->version.build = (cp500_vers >> 16) & 0xffff; 917 cp500_get_fpga_version(cp500, buf, sizeof(buf)); 918 919 dev_info(&pci_dev->dev, "FPGA version %s", buf); 920 921 pci_set_drvdata(pci_dev, cp500); 922 923 cp500->nvmem_notifier.notifier_call = cp500_nvmem; 924 ret = nvmem_register_notifier(&cp500->nvmem_notifier); 925 if (ret != 0) 926 goto out_free_irq; 927 928 ret = cp500_enable(cp500); 929 if (ret != 0) 930 goto out_unregister_nvmem; 931 932 cp500_register_auxiliary_devs(cp500); 933 934 return 0; 935 936out_unregister_nvmem: 937 nvmem_unregister_notifier(&cp500->nvmem_notifier); 938out_free_irq: 939 pci_free_irq_vectors(pci_dev); 940out_disable: 941 pci_clear_master(pci_dev); 942 pci_disable_device(pci_dev); 943 944 return ret; 945} 946 947static void cp500_remove(struct pci_dev *pci_dev) 948{ 949 struct cp500 *cp500 = pci_get_drvdata(pci_dev); 950 951 /* 952 * unregister CPU and user nvmem and put base_nvmem before parent 953 * auxiliary device of base_nvmem is unregistered 954 */ 955 nvmem_unregister_notifier(&cp500->nvmem_notifier); 956 cp500_nvmem_unregister(cp500); 957 958 cp500_unregister_auxiliary_devs(cp500); 959 960 cp500_disable(cp500); 961 962 pci_set_drvdata(pci_dev, 0); 963 964 pci_free_irq_vectors(pci_dev); 965 966 pci_clear_master(pci_dev); 967 pci_disable_device(pci_dev); 968} 969 970static struct pci_device_id cp500_ids[] = { 971 { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP035) }, 972 { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP505) }, 973 { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP520) }, 974 { } 975}; 976MODULE_DEVICE_TABLE(pci, cp500_ids); 977 978static struct pci_driver cp500_driver = { 979 .name = CP500, 980 .id_table = cp500_ids, 981 .probe = cp500_probe, 982 .remove = cp500_remove, 983 .dev_groups = cp500_groups, 984}; 985module_pci_driver(cp500_driver); 986 987MODULE_AUTHOR("Gerhard Engleder <eg@keba.com>"); 988MODULE_DESCRIPTION("KEBA CP500 system FPGA driver"); 989MODULE_LICENSE("GPL");
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