eeprom_93xx46.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Driver for 93xx46 EEPROMs
  4 *
  5 * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
  6 */
  7
  8#include <linux/array_size.h>
  9#include <linux/bits.h>
 10#include <linux/delay.h>
 11#include <linux/device.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/kstrtox.h>
 14#include <linux/log2.h>
 15#include <linux/mod_devicetable.h>
 16#include <linux/module.h>
 17#include <linux/mutex.h>
 18#include <linux/property.h>
 19#include <linux/slab.h>
 20#include <linux/spi/spi.h>
 21#include <linux/string_choices.h>
 22
 23#include <linux/nvmem-provider.h>
 24
 25struct eeprom_93xx46_platform_data {
 26	unsigned char	flags;
 27#define EE_ADDR8	0x01		/*  8 bit addr. cfg */
 28#define EE_ADDR16	0x02		/* 16 bit addr. cfg */
 29#define EE_READONLY	0x08		/* forbid writing */
 30#define EE_SIZE1K	0x10		/* 1 kb of data, that is a 93xx46 */
 31#define EE_SIZE2K	0x20		/* 2 kb of data, that is a 93xx56 */
 32#define EE_SIZE4K	0x40		/* 4 kb of data, that is a 93xx66 */
 33
 34	unsigned int	quirks;
 35/* Single word read transfers only; no sequential read. */
 36#define EEPROM_93XX46_QUIRK_SINGLE_WORD_READ		(1 << 0)
 37/* Instructions such as EWEN are (addrlen + 2) in length. */
 38#define EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH		(1 << 1)
 39/* Add extra cycle after address during a read */
 40#define EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE		BIT(2)
 41
 42	struct gpio_desc *select;
 43};
 44
 45#define OP_START	0x4
 46#define OP_WRITE	(OP_START | 0x1)
 47#define OP_READ		(OP_START | 0x2)
 48/* The following addresses are offset for the 1K EEPROM variant in 16-bit mode */
 49#define ADDR_EWDS	0x00
 50#define ADDR_ERAL	0x20
 51#define ADDR_EWEN	0x30
 52
 53struct eeprom_93xx46_devtype_data {
 54	unsigned int quirks;
 55	unsigned char flags;
 56};
 57
 58static const struct eeprom_93xx46_devtype_data at93c46_data = {
 59	.flags = EE_SIZE1K,
 60};
 61
 62static const struct eeprom_93xx46_devtype_data at93c56_data = {
 63	.flags = EE_SIZE2K,
 64};
 65
 66static const struct eeprom_93xx46_devtype_data at93c66_data = {
 67	.flags = EE_SIZE4K,
 68};
 69
 70static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
 71	.flags = EE_SIZE1K,
 72	.quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
 73		  EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
 74};
 75
 76static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = {
 77	.flags = EE_SIZE1K,
 78	.quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE,
 79};
 80
 81struct eeprom_93xx46_dev {
 82	struct spi_device *spi;
 83	struct eeprom_93xx46_platform_data *pdata;
 84	struct mutex lock;
 85	struct nvmem_config nvmem_config;
 86	struct nvmem_device *nvmem;
 87	int addrlen;
 88	int size;
 89};
 90
 91static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
 92{
 93	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
 94}
 95
 96static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
 97{
 98	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
 99}
100
101static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
102{
103	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
104}
105
106static int eeprom_93xx46_read(void *priv, unsigned int off,
107			      void *val, size_t count)
108{
109	struct eeprom_93xx46_dev *edev = priv;
110	char *buf = val;
111	int err = 0;
112	int bits;
113
114	if (unlikely(off >= edev->size))
115		return 0;
116	if ((off + count) > edev->size)
117		count = edev->size - off;
118	if (unlikely(!count))
119		return count;
120
121	mutex_lock(&edev->lock);
122
123	gpiod_set_value_cansleep(edev->pdata->select, 1);
124
125	/* The opcode in front of the address is three bits. */
126	bits = edev->addrlen + 3;
127
128	while (count) {
129		struct spi_message m;
130		struct spi_transfer t[2] = {};
131		u16 cmd_addr = OP_READ << edev->addrlen;
132		size_t nbytes = count;
133
134		if (edev->pdata->flags & EE_ADDR8) {
135			cmd_addr |= off;
136			if (has_quirk_single_word_read(edev))
137				nbytes = 1;
138		} else {
139			cmd_addr |= (off >> 1);
140			if (has_quirk_single_word_read(edev))
141				nbytes = 2;
142		}
143
144		dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
145			cmd_addr, edev->spi->max_speed_hz);
146
147		if (has_quirk_extra_read_cycle(edev)) {
148			cmd_addr <<= 1;
149			bits += 1;
150		}
151
152		t[0].tx_buf = (char *)&cmd_addr;
153		t[0].len = 2;
154		t[0].bits_per_word = bits;
155
156		t[1].rx_buf = buf;
157		t[1].len = count;
158		t[1].bits_per_word = 8;
159
160		spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
161
162		err = spi_sync(edev->spi, &m);
163		/* have to wait at least Tcsl ns */
164		ndelay(250);
165
166		if (err) {
167			dev_err(&edev->spi->dev, "read %zu bytes at %u: err. %d\n",
168				nbytes, off, err);
169			break;
170		}
171
172		buf += nbytes;
173		off += nbytes;
174		count -= nbytes;
175	}
176
177	gpiod_set_value_cansleep(edev->pdata->select, 0);
178
179	mutex_unlock(&edev->lock);
180
181	return err;
182}
183
184static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
185{
186	struct spi_message m;
187	struct spi_transfer t = {};
188	int bits, ret;
189	u16 cmd_addr;
190
191	/* The opcode in front of the address is three bits. */
192	bits = edev->addrlen + 3;
193
194	cmd_addr = OP_START << edev->addrlen;
195	cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << (edev->addrlen - 6);
196
197	if (has_quirk_instruction_length(edev)) {
198		cmd_addr <<= 2;
199		bits += 2;
200	}
201
202	dev_dbg(&edev->spi->dev, "ew %s cmd 0x%04x, %d bits\n",
203		str_enable_disable(is_on), cmd_addr, bits);
204
205	t.tx_buf = &cmd_addr;
206	t.len = 2;
207	t.bits_per_word = bits;
208
209	spi_message_init_with_transfers(&m, &t, 1);
210
211	mutex_lock(&edev->lock);
212
213	gpiod_set_value_cansleep(edev->pdata->select, 1);
214
215	ret = spi_sync(edev->spi, &m);
216	/* have to wait at least Tcsl ns */
217	ndelay(250);
218	if (ret)
219		dev_err(&edev->spi->dev, "erase/write %s error %d\n",
220			str_enable_disable(is_on), ret);
221
222	gpiod_set_value_cansleep(edev->pdata->select, 0);
223
224	mutex_unlock(&edev->lock);
225	return ret;
226}
227
228static ssize_t
229eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
230			 const char *buf, unsigned int off)
231{
232	struct spi_message m;
233	struct spi_transfer t[2] = {};
234	int bits, data_len, ret;
235	u16 cmd_addr;
236
237	if (unlikely(off >= edev->size))
238		return -EINVAL;
239
240	/* The opcode in front of the address is three bits. */
241	bits = edev->addrlen + 3;
242
243	cmd_addr = OP_WRITE << edev->addrlen;
244
245	if (edev->pdata->flags & EE_ADDR8) {
246		cmd_addr |= off;
247		data_len = 1;
248	} else {
249		cmd_addr |= (off >> 1);
250		data_len = 2;
251	}
252
253	dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
254
255	t[0].tx_buf = (char *)&cmd_addr;
256	t[0].len = 2;
257	t[0].bits_per_word = bits;
258
259	t[1].tx_buf = buf;
260	t[1].len = data_len;
261	t[1].bits_per_word = 8;
262
263	spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
264
265	ret = spi_sync(edev->spi, &m);
266	/* have to wait program cycle time Twc ms */
267	mdelay(6);
268	return ret;
269}
270
271static int eeprom_93xx46_write(void *priv, unsigned int off,
272				   void *val, size_t count)
273{
274	struct eeprom_93xx46_dev *edev = priv;
275	char *buf = val;
276	int ret, step = 1;
277	unsigned int i;
278
279	if (unlikely(off >= edev->size))
280		return -EFBIG;
281	if ((off + count) > edev->size)
282		count = edev->size - off;
283	if (unlikely(!count))
284		return count;
285
286	/* only write even number of bytes on 16-bit devices */
287	if (edev->pdata->flags & EE_ADDR16) {
288		step = 2;
289		count &= ~1;
290	}
291
292	/* erase/write enable */
293	ret = eeprom_93xx46_ew(edev, 1);
294	if (ret)
295		return ret;
296
297	mutex_lock(&edev->lock);
298
299	gpiod_set_value_cansleep(edev->pdata->select, 1);
300
301	for (i = 0; i < count; i += step) {
302		ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
303		if (ret) {
304			dev_err(&edev->spi->dev, "write failed at %u: %d\n", off + i, ret);
305			break;
306		}
307	}
308
309	gpiod_set_value_cansleep(edev->pdata->select, 0);
310
311	mutex_unlock(&edev->lock);
312
313	/* erase/write disable */
314	eeprom_93xx46_ew(edev, 0);
315	return ret;
316}
317
318static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
319{
320	struct spi_message m;
321	struct spi_transfer t = {};
322	int bits, ret;
323	u16 cmd_addr;
324
325	/* The opcode in front of the address is three bits. */
326	bits = edev->addrlen + 3;
327
328	cmd_addr = OP_START << edev->addrlen;
329	cmd_addr |= ADDR_ERAL << (edev->addrlen - 6);
330
331	if (has_quirk_instruction_length(edev)) {
332		cmd_addr <<= 2;
333		bits += 2;
334	}
335
336	dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
337
338	t.tx_buf = &cmd_addr;
339	t.len = 2;
340	t.bits_per_word = bits;
341
342	spi_message_init_with_transfers(&m, &t, 1);
343
344	mutex_lock(&edev->lock);
345
346	gpiod_set_value_cansleep(edev->pdata->select, 1);
347
348	ret = spi_sync(edev->spi, &m);
349	if (ret)
350		dev_err(&edev->spi->dev, "erase error %d\n", ret);
351	/* have to wait erase cycle time Tec ms */
352	mdelay(6);
353
354	gpiod_set_value_cansleep(edev->pdata->select, 0);
355
356	mutex_unlock(&edev->lock);
357	return ret;
358}
359
360static ssize_t erase_store(struct device *dev, struct device_attribute *attr,
361			   const char *buf, size_t count)
362{
363	struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
364	bool erase;
365	int ret;
366
367	ret = kstrtobool(buf, &erase);
368	if (ret)
369		return ret;
370
371	if (erase) {
372		ret = eeprom_93xx46_ew(edev, 1);
373		if (ret)
374			return ret;
375		ret = eeprom_93xx46_eral(edev);
376		if (ret)
377			return ret;
378		ret = eeprom_93xx46_ew(edev, 0);
379		if (ret)
380			return ret;
381	}
382	return count;
383}
384static DEVICE_ATTR_WO(erase);
385
386static const struct of_device_id eeprom_93xx46_of_table[] = {
387	{ .compatible = "eeprom-93xx46", .data = &at93c46_data, },
388	{ .compatible = "atmel,at93c46", .data = &at93c46_data, },
389	{ .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
390	{ .compatible = "atmel,at93c56", .data = &at93c56_data, },
391	{ .compatible = "atmel,at93c66", .data = &at93c66_data, },
392	{ .compatible = "microchip,93lc46b", .data = &microchip_93lc46b_data, },
393	{}
394};
395MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
396
397static const struct spi_device_id eeprom_93xx46_spi_ids[] = {
398	{ .name = "eeprom-93xx46",
399	  .driver_data = (kernel_ulong_t)&at93c46_data, },
400	{ .name = "at93c46",
401	  .driver_data = (kernel_ulong_t)&at93c46_data, },
402	{ .name = "at93c46d",
403	  .driver_data = (kernel_ulong_t)&atmel_at93c46d_data, },
404	{ .name = "at93c56",
405	  .driver_data = (kernel_ulong_t)&at93c56_data, },
406	{ .name = "at93c66",
407	  .driver_data = (kernel_ulong_t)&at93c66_data, },
408	{ .name = "93lc46b",
409	  .driver_data = (kernel_ulong_t)&microchip_93lc46b_data, },
410	{}
411};
412MODULE_DEVICE_TABLE(spi, eeprom_93xx46_spi_ids);
413
414static int eeprom_93xx46_probe_fw(struct device *dev)
415{
416	const struct eeprom_93xx46_devtype_data *data;
417	struct eeprom_93xx46_platform_data *pd;
418	u32 tmp;
419	int ret;
420
421	pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
422	if (!pd)
423		return -ENOMEM;
424
425	ret = device_property_read_u32(dev, "data-size", &tmp);
426	if (ret < 0) {
427		dev_err(dev, "data-size property not found\n");
428		return ret;
429	}
430
431	if (tmp == 8) {
432		pd->flags |= EE_ADDR8;
433	} else if (tmp == 16) {
434		pd->flags |= EE_ADDR16;
435	} else {
436		dev_err(dev, "invalid data-size (%d)\n", tmp);
437		return -EINVAL;
438	}
439
440	if (device_property_read_bool(dev, "read-only"))
441		pd->flags |= EE_READONLY;
442
443	pd->select = devm_gpiod_get_optional(dev, "select", GPIOD_OUT_LOW);
444	if (IS_ERR(pd->select))
445		return PTR_ERR(pd->select);
446	gpiod_set_consumer_name(pd->select, "93xx46 EEPROMs OE");
447
448	data = spi_get_device_match_data(to_spi_device(dev));
449	if (data) {
450		pd->quirks = data->quirks;
451		pd->flags |= data->flags;
452	}
453
454	dev->platform_data = pd;
455
456	return 0;
457}
458
459static int eeprom_93xx46_probe(struct spi_device *spi)
460{
461	struct eeprom_93xx46_platform_data *pd;
462	struct eeprom_93xx46_dev *edev;
463	struct device *dev = &spi->dev;
464	int err;
465
466	err = eeprom_93xx46_probe_fw(dev);
467	if (err < 0)
468		return err;
469
470	pd = spi->dev.platform_data;
471	if (!pd) {
472		dev_err(&spi->dev, "missing platform data\n");
473		return -ENODEV;
474	}
475
476	edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
477	if (!edev)
478		return -ENOMEM;
479
480	if (pd->flags & EE_SIZE1K)
481		edev->size = 128;
482	else if (pd->flags & EE_SIZE2K)
483		edev->size = 256;
484	else if (pd->flags & EE_SIZE4K)
485		edev->size = 512;
486	else {
487		dev_err(&spi->dev, "unspecified size\n");
488		return -EINVAL;
489	}
490
491	if (pd->flags & EE_ADDR8)
492		edev->addrlen = ilog2(edev->size);
493	else if (pd->flags & EE_ADDR16)
494		edev->addrlen = ilog2(edev->size) - 1;
495	else {
496		dev_err(&spi->dev, "unspecified address type\n");
497		return -EINVAL;
498	}
499
500	mutex_init(&edev->lock);
501
502	edev->spi = spi;
503	edev->pdata = pd;
504
505	edev->nvmem_config.type = NVMEM_TYPE_EEPROM;
506	edev->nvmem_config.name = dev_name(&spi->dev);
507	edev->nvmem_config.dev = &spi->dev;
508	edev->nvmem_config.read_only = pd->flags & EE_READONLY;
509	edev->nvmem_config.root_only = true;
510	edev->nvmem_config.owner = THIS_MODULE;
511	edev->nvmem_config.compat = true;
512	edev->nvmem_config.base_dev = &spi->dev;
513	edev->nvmem_config.reg_read = eeprom_93xx46_read;
514	edev->nvmem_config.reg_write = eeprom_93xx46_write;
515	edev->nvmem_config.priv = edev;
516	edev->nvmem_config.stride = 4;
517	edev->nvmem_config.word_size = 1;
518	edev->nvmem_config.size = edev->size;
519
520	edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
521	if (IS_ERR(edev->nvmem))
522		return PTR_ERR(edev->nvmem);
523
524	dev_info(&spi->dev, "%d-bit eeprom containing %d bytes %s\n",
525		(pd->flags & EE_ADDR8) ? 8 : 16,
526		edev->size,
527		(pd->flags & EE_READONLY) ? "(readonly)" : "");
528
529	if (!(pd->flags & EE_READONLY)) {
530		if (device_create_file(&spi->dev, &dev_attr_erase))
531			dev_err(&spi->dev, "can't create erase interface\n");
532	}
533
534	spi_set_drvdata(spi, edev);
535	return 0;
536}
537
538static void eeprom_93xx46_remove(struct spi_device *spi)
539{
540	struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
541
542	if (!(edev->pdata->flags & EE_READONLY))
543		device_remove_file(&spi->dev, &dev_attr_erase);
544}
545
546static struct spi_driver eeprom_93xx46_driver = {
547	.driver = {
548		.name	= "93xx46",
549		.of_match_table = eeprom_93xx46_of_table,
550	},
551	.probe		= eeprom_93xx46_probe,
552	.remove		= eeprom_93xx46_remove,
553	.id_table	= eeprom_93xx46_spi_ids,
554};
555
556module_spi_driver(eeprom_93xx46_driver);
557
558MODULE_LICENSE("GPL");
559MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs");
560MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
561MODULE_ALIAS("spi:93xx46");