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at24.c
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linux-6.19.14/drivers/misc/eeprom/at24.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * at24.c - handle most I2C EEPROMs 4 * 5 * Copyright (C) 2005-2007 David Brownell 6 * Copyright (C) 2008 Wolfram Sang, Pengutronix 7 */ 8 9#include <linux/acpi.h> 10#include <linux/bitops.h> 11#include <linux/capability.h> 12#include <linux/delay.h> 13#include <linux/i2c.h> 14#include <linux/init.h> 15#include <linux/jiffies.h> 16#include <linux/kernel.h> 17#include <linux/mod_devicetable.h> 18#include <linux/module.h> 19#include <linux/mutex.h> 20#include <linux/nvmem-provider.h> 21#include <linux/pm_runtime.h> 22#include <linux/property.h> 23#include <linux/regmap.h> 24#include <linux/regulator/consumer.h> 25#include <linux/slab.h> 26 27/* Address pointer is 16 bit. */ 28#define AT24_FLAG_ADDR16 BIT(7) 29/* sysfs-entry will be read-only. */ 30#define AT24_FLAG_READONLY BIT(6) 31/* sysfs-entry will be world-readable. */ 32#define AT24_FLAG_IRUGO BIT(5) 33/* Take always 8 addresses (24c00). */ 34#define AT24_FLAG_TAKE8ADDR BIT(4) 35/* Factory-programmed serial number. */ 36#define AT24_FLAG_SERIAL BIT(3) 37/* Factory-programmed mac address. */ 38#define AT24_FLAG_MAC BIT(2) 39/* Does not auto-rollover reads to the next slave address. */ 40#define AT24_FLAG_NO_RDROL BIT(1) 41 42/* 43 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable. 44 * Differences between different vendor product lines (like Atmel AT24C or 45 * MicroChip 24LC, etc) won't much matter for typical read/write access. 46 * There are also I2C RAM chips, likewise interchangeable. One example 47 * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes). 48 * 49 * However, misconfiguration can lose data. "Set 16-bit memory address" 50 * to a part with 8-bit addressing will overwrite data. Writing with too 51 * big a page size also loses data. And it's not safe to assume that the 52 * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC 53 * uses 0x51, for just one example. 54 * 55 * Accordingly, explicit board-specific configuration data should be used 56 * in almost all cases. (One partial exception is an SMBus used to access 57 * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.) 58 * 59 * So this driver uses "new style" I2C driver binding, expecting to be 60 * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or 61 * similar kernel-resident tables; or, configuration data coming from 62 * a bootloader. 63 * 64 * Other than binding model, current differences from "eeprom" driver are 65 * that this one handles write access and isn't restricted to 24c02 devices. 66 * It also handles larger devices (32 kbit and up) with two-byte addresses, 67 * which won't work on pure SMBus systems. 68 */ 69 70struct at24_data { 71 /* 72 * Lock protects against activities from other Linux tasks, 73 * but not from changes by other I2C masters. 74 */ 75 struct mutex lock; 76 77 unsigned int write_max; 78 unsigned int num_addresses; 79 unsigned int offset_adj; 80 81 u32 byte_len; 82 u16 page_size; 83 u8 flags; 84 85 struct nvmem_device *nvmem; 86 struct regulator *vcc_reg; 87 void (*read_post)(unsigned int off, char *buf, size_t count); 88 89 /* 90 * Some chips tie up multiple I2C addresses; dummy devices reserve 91 * them for us. 92 */ 93 u8 bank_addr_shift; 94 struct regmap *client_regmaps[] __counted_by(num_addresses); 95}; 96 97/* 98 * This parameter is to help this driver avoid blocking other drivers out 99 * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C 100 * clock, one 256 byte read takes about 1/43 second which is excessive; 101 * but the 1/170 second it takes at 400 kHz may be quite reasonable; and 102 * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible. 103 * 104 * This value is forced to be a power of two so that writes align on pages. 105 */ 106static unsigned int at24_io_limit = 128; 107module_param_named(io_limit, at24_io_limit, uint, 0); 108MODULE_PARM_DESC(at24_io_limit, "Maximum bytes per I/O (default 128)"); 109 110/* 111 * Specs often allow 5 msec for a page write, sometimes 20 msec; 112 * it's important to recover from write timeouts. 113 */ 114static unsigned int at24_write_timeout = 25; 115module_param_named(write_timeout, at24_write_timeout, uint, 0); 116MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)"); 117 118struct at24_chip_data { 119 u32 byte_len; 120 u8 flags; 121 u8 bank_addr_shift; 122 void (*read_post)(unsigned int off, char *buf, size_t count); 123}; 124 125#define AT24_CHIP_DATA(_name, _len, _flags) \ 126 static const struct at24_chip_data _name = { \ 127 .byte_len = _len, .flags = _flags, \ 128 } 129 130#define AT24_CHIP_DATA_CB(_name, _len, _flags, _read_post) \ 131 static const struct at24_chip_data _name = { \ 132 .byte_len = _len, .flags = _flags, \ 133 .read_post = _read_post, \ 134 } 135 136#define AT24_CHIP_DATA_BS(_name, _len, _flags, _bank_addr_shift) \ 137 static const struct at24_chip_data _name = { \ 138 .byte_len = _len, .flags = _flags, \ 139 .bank_addr_shift = _bank_addr_shift \ 140 } 141 142static void at24_read_post_vaio(unsigned int off, char *buf, size_t count) 143{ 144 int i; 145 146 if (capable(CAP_SYS_ADMIN)) 147 return; 148 149 /* 150 * Hide VAIO private settings to regular users: 151 * - BIOS passwords: bytes 0x00 to 0x0f 152 * - UUID: bytes 0x10 to 0x1f 153 * - Serial number: 0xc0 to 0xdf 154 */ 155 for (i = 0; i < count; i++) { 156 if ((off + i <= 0x1f) || 157 (off + i >= 0xc0 && off + i <= 0xdf)) 158 buf[i] = 0; 159 } 160} 161 162/* needs 8 addresses as A0-A2 are ignored */ 163AT24_CHIP_DATA(at24_data_24c00, 128 / 8, AT24_FLAG_TAKE8ADDR); 164/* old variants can't be handled with this generic entry! */ 165AT24_CHIP_DATA(at24_data_24c01, 1024 / 8, 0); 166AT24_CHIP_DATA(at24_data_24cs01, 16, 167 AT24_FLAG_SERIAL | AT24_FLAG_READONLY); 168AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, 0); 169AT24_CHIP_DATA(at24_data_24cs02, 16, 170 AT24_FLAG_SERIAL | AT24_FLAG_READONLY); 171AT24_CHIP_DATA(at24_data_24mac402, 48 / 8, 172 AT24_FLAG_MAC | AT24_FLAG_READONLY); 173AT24_CHIP_DATA(at24_data_24mac602, 64 / 8, 174 AT24_FLAG_MAC | AT24_FLAG_READONLY); 175AT24_CHIP_DATA(at24_data_24aa025e48, 48 / 8, 176 AT24_FLAG_READONLY); 177AT24_CHIP_DATA(at24_data_24aa025e64, 64 / 8, 178 AT24_FLAG_READONLY); 179/* spd is a 24c02 in memory DIMMs */ 180AT24_CHIP_DATA(at24_data_spd, 2048 / 8, 181 AT24_FLAG_READONLY | AT24_FLAG_IRUGO); 182/* 24c02_vaio is a 24c02 on some Sony laptops */ 183AT24_CHIP_DATA_CB(at24_data_24c02_vaio, 2048 / 8, 184 AT24_FLAG_READONLY | AT24_FLAG_IRUGO, 185 at24_read_post_vaio); 186AT24_CHIP_DATA(at24_data_24c04, 4096 / 8, 0); 187AT24_CHIP_DATA(at24_data_24cs04, 16, 188 AT24_FLAG_SERIAL | AT24_FLAG_READONLY); 189/* 24rf08 quirk is handled at i2c-core */ 190AT24_CHIP_DATA(at24_data_24c08, 8192 / 8, 0); 191AT24_CHIP_DATA(at24_data_24cs08, 16, 192 AT24_FLAG_SERIAL | AT24_FLAG_READONLY); 193AT24_CHIP_DATA(at24_data_24c16, 16384 / 8, 0); 194AT24_CHIP_DATA(at24_data_24cs16, 16, 195 AT24_FLAG_SERIAL | AT24_FLAG_READONLY); 196AT24_CHIP_DATA(at24_data_24c32, 32768 / 8, AT24_FLAG_ADDR16); 197/* M24C32-D Additional Write lockable page (M24C32-D order codes) */ 198AT24_CHIP_DATA(at24_data_24c32d_wlp, 32, AT24_FLAG_ADDR16); 199AT24_CHIP_DATA(at24_data_24cs32, 16, 200 AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY); 201AT24_CHIP_DATA(at24_data_24c64, 65536 / 8, AT24_FLAG_ADDR16); 202/* M24C64-D Additional Write lockable page (M24C64-D order codes) */ 203AT24_CHIP_DATA(at24_data_24c64d_wlp, 32, AT24_FLAG_ADDR16); 204AT24_CHIP_DATA(at24_data_24cs64, 16, 205 AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY); 206AT24_CHIP_DATA(at24_data_24c128, 131072 / 8, AT24_FLAG_ADDR16); 207AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16); 208/* M24256E Additional Write lockable page (M24256E-F order codes) */ 209AT24_CHIP_DATA(at24_data_24256e_wlp, 64, AT24_FLAG_ADDR16); 210AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16); 211AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16); 212AT24_CHIP_DATA_BS(at24_data_24c1025, 1048576 / 8, AT24_FLAG_ADDR16, 2); 213AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16); 214/* identical to 24c08 ? */ 215AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0); 216 217static const struct i2c_device_id at24_ids[] = { 218 { "24c00", (kernel_ulong_t)&at24_data_24c00 }, 219 { "24c01", (kernel_ulong_t)&at24_data_24c01 }, 220 { "24cs01", (kernel_ulong_t)&at24_data_24cs01 }, 221 { "24c02", (kernel_ulong_t)&at24_data_24c02 }, 222 { "24cs02", (kernel_ulong_t)&at24_data_24cs02 }, 223 { "24mac402", (kernel_ulong_t)&at24_data_24mac402 }, 224 { "24mac602", (kernel_ulong_t)&at24_data_24mac602 }, 225 { "24aa025e48", (kernel_ulong_t)&at24_data_24aa025e48 }, 226 { "24aa025e64", (kernel_ulong_t)&at24_data_24aa025e64 }, 227 { "spd", (kernel_ulong_t)&at24_data_spd }, 228 { "24c02-vaio", (kernel_ulong_t)&at24_data_24c02_vaio }, 229 { "24c04", (kernel_ulong_t)&at24_data_24c04 }, 230 { "24cs04", (kernel_ulong_t)&at24_data_24cs04 }, 231 { "24c08", (kernel_ulong_t)&at24_data_24c08 }, 232 { "24cs08", (kernel_ulong_t)&at24_data_24cs08 }, 233 { "24c16", (kernel_ulong_t)&at24_data_24c16 }, 234 { "24cs16", (kernel_ulong_t)&at24_data_24cs16 }, 235 { "24c32", (kernel_ulong_t)&at24_data_24c32 }, 236 { "24c32d-wl", (kernel_ulong_t)&at24_data_24c32d_wlp }, 237 { "24cs32", (kernel_ulong_t)&at24_data_24cs32 }, 238 { "24c64", (kernel_ulong_t)&at24_data_24c64 }, 239 { "24c64-wl", (kernel_ulong_t)&at24_data_24c64d_wlp }, 240 { "24cs64", (kernel_ulong_t)&at24_data_24cs64 }, 241 { "24c128", (kernel_ulong_t)&at24_data_24c128 }, 242 { "24c256", (kernel_ulong_t)&at24_data_24c256 }, 243 { "24256e-wl", (kernel_ulong_t)&at24_data_24256e_wlp }, 244 { "24c512", (kernel_ulong_t)&at24_data_24c512 }, 245 { "24c1024", (kernel_ulong_t)&at24_data_24c1024 }, 246 { "24c1025", (kernel_ulong_t)&at24_data_24c1025 }, 247 { "24c2048", (kernel_ulong_t)&at24_data_24c2048 }, 248 { "at24", 0 }, 249 { /* END OF LIST */ } 250}; 251MODULE_DEVICE_TABLE(i2c, at24_ids); 252 253static const struct of_device_id at24_of_match[] = { 254 { .compatible = "atmel,24c00", .data = &at24_data_24c00 }, 255 { .compatible = "atmel,24c01", .data = &at24_data_24c01 }, 256 { .compatible = "atmel,24cs01", .data = &at24_data_24cs01 }, 257 { .compatible = "atmel,24c02", .data = &at24_data_24c02 }, 258 { .compatible = "atmel,24cs02", .data = &at24_data_24cs02 }, 259 { .compatible = "atmel,24mac402", .data = &at24_data_24mac402 }, 260 { .compatible = "atmel,24mac602", .data = &at24_data_24mac602 }, 261 { .compatible = "atmel,spd", .data = &at24_data_spd }, 262 { .compatible = "atmel,24c04", .data = &at24_data_24c04 }, 263 { .compatible = "atmel,24cs04", .data = &at24_data_24cs04 }, 264 { .compatible = "atmel,24c08", .data = &at24_data_24c08 }, 265 { .compatible = "atmel,24cs08", .data = &at24_data_24cs08 }, 266 { .compatible = "atmel,24c16", .data = &at24_data_24c16 }, 267 { .compatible = "atmel,24cs16", .data = &at24_data_24cs16 }, 268 { .compatible = "atmel,24c32", .data = &at24_data_24c32 }, 269 { .compatible = "atmel,24c32d-wl", .data = &at24_data_24c32d_wlp }, 270 { .compatible = "atmel,24cs32", .data = &at24_data_24cs32 }, 271 { .compatible = "atmel,24c64", .data = &at24_data_24c64 }, 272 { .compatible = "atmel,24c64d-wl", .data = &at24_data_24c64d_wlp }, 273 { .compatible = "atmel,24cs64", .data = &at24_data_24cs64 }, 274 { .compatible = "atmel,24c128", .data = &at24_data_24c128 }, 275 { .compatible = "atmel,24c256", .data = &at24_data_24c256 }, 276 { .compatible = "atmel,24c512", .data = &at24_data_24c512 }, 277 { .compatible = "atmel,24c1024", .data = &at24_data_24c1024 }, 278 { .compatible = "atmel,24c1025", .data = &at24_data_24c1025 }, 279 { .compatible = "atmel,24c2048", .data = &at24_data_24c2048 }, 280 { .compatible = "microchip,24aa025e48", .data = &at24_data_24aa025e48 }, 281 { .compatible = "microchip,24aa025e64", .data = &at24_data_24aa025e64 }, 282 { .compatible = "st,24256e-wl", .data = &at24_data_24256e_wlp }, 283 { /* END OF LIST */ }, 284}; 285MODULE_DEVICE_TABLE(of, at24_of_match); 286 287static const struct acpi_device_id at24_acpi_ids[] = { 288 { "INT3499", (kernel_ulong_t)&at24_data_INT3499 }, 289 { "TPF0001", (kernel_ulong_t)&at24_data_24c1024 }, 290 { /* END OF LIST */ } 291}; 292MODULE_DEVICE_TABLE(acpi, at24_acpi_ids); 293 294/* 295 * This routine supports chips which consume multiple I2C addresses. It 296 * computes the addressing information to be used for a given r/w request. 297 * Assumes that sanity checks for offset happened at sysfs-layer. 298 * 299 * Slave address and byte offset derive from the offset. Always 300 * set the byte address; on a multi-master board, another master 301 * may have changed the chip's "current" address pointer. 302 */ 303static struct regmap *at24_translate_offset(struct at24_data *at24, 304 unsigned int *offset) 305{ 306 unsigned int i; 307 308 if (at24->flags & AT24_FLAG_ADDR16) { 309 i = *offset >> 16; 310 *offset &= 0xffff; 311 } else { 312 i = *offset >> 8; 313 *offset &= 0xff; 314 } 315 316 return at24->client_regmaps[i]; 317} 318 319static struct device *at24_base_client_dev(struct at24_data *at24) 320{ 321 return regmap_get_device(at24->client_regmaps[0]); 322} 323 324static size_t at24_adjust_read_count(struct at24_data *at24, 325 unsigned int offset, size_t count) 326{ 327 unsigned int bits; 328 size_t remainder; 329 330 /* 331 * In case of multi-address chips that don't rollover reads to 332 * the next slave address: truncate the count to the slave boundary, 333 * so that the read never straddles slaves. 334 */ 335 if (at24->flags & AT24_FLAG_NO_RDROL) { 336 bits = (at24->flags & AT24_FLAG_ADDR16) ? 16 : 8; 337 remainder = BIT(bits) - offset; 338 if (count > remainder) 339 count = remainder; 340 } 341 342 if (count > at24_io_limit) 343 count = at24_io_limit; 344 345 return count; 346} 347 348static ssize_t at24_regmap_read(struct at24_data *at24, char *buf, 349 unsigned int offset, size_t count) 350{ 351 unsigned long timeout, read_time; 352 struct regmap *regmap; 353 int ret; 354 355 regmap = at24_translate_offset(at24, &offset); 356 count = at24_adjust_read_count(at24, offset, count); 357 358 /* adjust offset for mac and serial read ops */ 359 offset += at24->offset_adj; 360 361 timeout = jiffies + msecs_to_jiffies(at24_write_timeout); 362 do { 363 /* 364 * The timestamp shall be taken before the actual operation 365 * to avoid a premature timeout in case of high CPU load. 366 */ 367 read_time = jiffies; 368 369 ret = regmap_bulk_read(regmap, offset, buf, count); 370 dev_dbg(regmap_get_device(regmap), "read %zu@%d --> %d (%ld)\n", 371 count, offset, ret, jiffies); 372 if (!ret) 373 return count; 374 375 usleep_range(1000, 1500); 376 } while (time_before(read_time, timeout)); 377 378 return -ETIMEDOUT; 379} 380 381/* 382 * Note that if the hardware write-protect pin is pulled high, the whole 383 * chip is normally write protected. But there are plenty of product 384 * variants here, including OTP fuses and partial chip protect. 385 * 386 * We only use page mode writes; the alternative is sloooow. These routines 387 * write at most one page. 388 */ 389 390static size_t at24_adjust_write_count(struct at24_data *at24, 391 unsigned int offset, size_t count) 392{ 393 unsigned int next_page; 394 395 /* write_max is at most a page */ 396 if (count > at24->write_max) 397 count = at24->write_max; 398 399 /* Never roll over backwards, to the start of this page */ 400 next_page = roundup(offset + 1, at24->page_size); 401 if (offset + count > next_page) 402 count = next_page - offset; 403 404 return count; 405} 406 407static ssize_t at24_regmap_write(struct at24_data *at24, const char *buf, 408 unsigned int offset, size_t count) 409{ 410 unsigned long timeout, write_time; 411 struct regmap *regmap; 412 int ret; 413 414 regmap = at24_translate_offset(at24, &offset); 415 count = at24_adjust_write_count(at24, offset, count); 416 timeout = jiffies + msecs_to_jiffies(at24_write_timeout); 417 418 do { 419 /* 420 * The timestamp shall be taken before the actual operation 421 * to avoid a premature timeout in case of high CPU load. 422 */ 423 write_time = jiffies; 424 425 ret = regmap_bulk_write(regmap, offset, buf, count); 426 dev_dbg(regmap_get_device(regmap), "write %zu@%d --> %d (%ld)\n", 427 count, offset, ret, jiffies); 428 if (!ret) 429 return count; 430 431 usleep_range(1000, 1500); 432 } while (time_before(write_time, timeout)); 433 434 return -ETIMEDOUT; 435} 436 437static int at24_read(void *priv, unsigned int off, void *val, size_t count) 438{ 439 struct at24_data *at24; 440 struct device *dev; 441 char *buf = val; 442 int i, ret; 443 444 at24 = priv; 445 dev = at24_base_client_dev(at24); 446 447 if (unlikely(!count)) 448 return count; 449 450 if (off + count > at24->byte_len) 451 return -EINVAL; 452 453 ret = pm_runtime_resume_and_get(dev); 454 if (ret) 455 return ret; 456 /* 457 * Read data from chip, protecting against concurrent updates 458 * from this host, but not from other I2C masters. 459 */ 460 mutex_lock(&at24->lock); 461 462 for (i = 0; count; i += ret, count -= ret) { 463 ret = at24_regmap_read(at24, buf + i, off + i, count); 464 if (ret < 0) { 465 mutex_unlock(&at24->lock); 466 pm_runtime_put(dev); 467 return ret; 468 } 469 } 470 471 mutex_unlock(&at24->lock); 472 473 pm_runtime_put(dev); 474 475 if (unlikely(at24->read_post)) 476 at24->read_post(off, buf, i); 477 478 return 0; 479} 480 481static int at24_write(void *priv, unsigned int off, void *val, size_t count) 482{ 483 struct at24_data *at24; 484 struct device *dev; 485 char *buf = val; 486 int ret; 487 488 at24 = priv; 489 dev = at24_base_client_dev(at24); 490 491 if (unlikely(!count)) 492 return -EINVAL; 493 494 if (off + count > at24->byte_len) 495 return -EINVAL; 496 497 ret = pm_runtime_resume_and_get(dev); 498 if (ret) 499 return ret; 500 /* 501 * Write data to chip, protecting against concurrent updates 502 * from this host, but not from other I2C masters. 503 */ 504 mutex_lock(&at24->lock); 505 506 while (count) { 507 ret = at24_regmap_write(at24, buf, off, count); 508 if (ret < 0) { 509 mutex_unlock(&at24->lock); 510 pm_runtime_put(dev); 511 return ret; 512 } 513 buf += ret; 514 off += ret; 515 count -= ret; 516 } 517 518 mutex_unlock(&at24->lock); 519 520 pm_runtime_put(dev); 521 522 return 0; 523} 524 525static int at24_make_dummy_client(struct at24_data *at24, unsigned int index, 526 struct i2c_client *base_client, 527 struct regmap_config *regmap_config) 528{ 529 struct i2c_client *dummy_client; 530 struct regmap *regmap; 531 532 dummy_client = devm_i2c_new_dummy_device(&base_client->dev, 533 base_client->adapter, 534 base_client->addr + 535 (index << at24->bank_addr_shift)); 536 if (IS_ERR(dummy_client)) 537 return PTR_ERR(dummy_client); 538 539 regmap = devm_regmap_init_i2c(dummy_client, regmap_config); 540 if (IS_ERR(regmap)) 541 return PTR_ERR(regmap); 542 543 at24->client_regmaps[index] = regmap; 544 545 return 0; 546} 547 548static unsigned int at24_get_offset_adj(u8 flags, unsigned int byte_len) 549{ 550 if (flags & AT24_FLAG_MAC) { 551 /* EUI-48 starts from 0x9a, EUI-64 from 0x98 */ 552 return 0xa0 - byte_len; 553 } else if (flags & AT24_FLAG_SERIAL && flags & AT24_FLAG_ADDR16) { 554 /* 555 * For 16 bit address pointers, the word address must contain 556 * a '10' sequence in bits 11 and 10 regardless of the 557 * intended position of the address pointer. 558 */ 559 return 0x0800; 560 } else if (flags & AT24_FLAG_SERIAL) { 561 /* 562 * Otherwise the word address must begin with a '10' sequence, 563 * regardless of the intended address. 564 */ 565 return 0x0080; 566 } else { 567 return 0; 568 } 569} 570 571static void at24_probe_temp_sensor(struct i2c_client *client) 572{ 573 struct at24_data *at24 = i2c_get_clientdata(client); 574 struct i2c_board_info info = { .type = "jc42" }; 575 int ret; 576 u8 val; 577 578 /* 579 * Byte 2 has value 11 for DDR3, earlier versions don't 580 * support the thermal sensor present flag 581 */ 582 ret = at24_read(at24, 2, &val, 1); 583 if (ret || val != 11) 584 return; 585 586 /* Byte 32, bit 7 is set if temp sensor is present */ 587 ret = at24_read(at24, 32, &val, 1); 588 if (ret || !(val & BIT(7))) 589 return; 590 591 info.addr = 0x18 | (client->addr & 7); 592 593 i2c_new_client_device(client->adapter, &info); 594} 595 596static int at24_probe(struct i2c_client *client) 597{ 598 struct regmap_config regmap_config = { }; 599 struct nvmem_config nvmem_config = { }; 600 u32 byte_len, page_size, flags, addrw; 601 const struct at24_chip_data *cdata; 602 struct device *dev = &client->dev; 603 bool i2c_fn_i2c, i2c_fn_block; 604 unsigned int i, num_addresses; 605 struct at24_data *at24; 606 bool full_power; 607 struct regmap *regmap; 608 bool writable; 609 u8 test_byte; 610 int err; 611 612 i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C); 613 i2c_fn_block = i2c_check_functionality(client->adapter, 614 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK); 615 616 cdata = i2c_get_match_data(client); 617 if (!cdata) 618 return -ENODEV; 619 620 err = device_property_read_u32(dev, "pagesize", &page_size); 621 if (err) 622 /* 623 * This is slow, but we can't know all eeproms, so we better 624 * play safe. Specifying custom eeprom-types via device tree 625 * or properties is recommended anyhow. 626 */ 627 page_size = 1; 628 629 flags = cdata->flags; 630 if (device_property_present(dev, "read-only")) 631 flags |= AT24_FLAG_READONLY; 632 if (device_property_present(dev, "no-read-rollover")) 633 flags |= AT24_FLAG_NO_RDROL; 634 635 err = device_property_read_u32(dev, "address-width", &addrw); 636 if (!err) { 637 switch (addrw) { 638 case 8: 639 if (flags & AT24_FLAG_ADDR16) 640 dev_warn(dev, 641 "Override address width to be 8, while default is 16\n"); 642 flags &= ~AT24_FLAG_ADDR16; 643 break; 644 case 16: 645 flags |= AT24_FLAG_ADDR16; 646 break; 647 default: 648 dev_warn(dev, "Bad \"address-width\" property: %u\n", 649 addrw); 650 } 651 } 652 653 err = device_property_read_u32(dev, "size", &byte_len); 654 if (err) 655 byte_len = cdata->byte_len; 656 657 if (!i2c_fn_i2c && !i2c_fn_block) 658 page_size = 1; 659 660 if (!page_size) { 661 dev_err(dev, "page_size must not be 0!\n"); 662 return -EINVAL; 663 } 664 665 if (!is_power_of_2(page_size)) 666 dev_warn(dev, "page_size looks suspicious (no power of 2)!\n"); 667 668 err = device_property_read_u32(dev, "num-addresses", &num_addresses); 669 if (err) { 670 if (flags & AT24_FLAG_TAKE8ADDR) 671 num_addresses = 8; 672 else 673 num_addresses = DIV_ROUND_UP(byte_len, 674 (flags & AT24_FLAG_ADDR16) ? 65536 : 256); 675 } 676 677 if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) { 678 dev_err(dev, 679 "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC."); 680 return -EINVAL; 681 } 682 683 regmap_config.val_bits = 8; 684 regmap_config.reg_bits = (flags & AT24_FLAG_ADDR16) ? 16 : 8; 685 regmap_config.disable_locking = true; 686 687 regmap = devm_regmap_init_i2c(client, ®map_config); 688 if (IS_ERR(regmap)) 689 return PTR_ERR(regmap); 690 691 at24 = devm_kzalloc(dev, struct_size(at24, client_regmaps, num_addresses), 692 GFP_KERNEL); 693 if (!at24) 694 return -ENOMEM; 695 696 mutex_init(&at24->lock); 697 at24->byte_len = byte_len; 698 at24->page_size = page_size; 699 at24->flags = flags; 700 at24->read_post = cdata->read_post; 701 at24->bank_addr_shift = cdata->bank_addr_shift; 702 at24->num_addresses = num_addresses; 703 at24->offset_adj = at24_get_offset_adj(flags, byte_len); 704 at24->client_regmaps[0] = regmap; 705 706 at24->vcc_reg = devm_regulator_get(dev, "vcc"); 707 if (IS_ERR(at24->vcc_reg)) 708 return PTR_ERR(at24->vcc_reg); 709 710 writable = !(flags & AT24_FLAG_READONLY); 711 if (writable) { 712 at24->write_max = min_t(unsigned int, 713 page_size, at24_io_limit); 714 if (!i2c_fn_i2c && at24->write_max > I2C_SMBUS_BLOCK_MAX) 715 at24->write_max = I2C_SMBUS_BLOCK_MAX; 716 } 717 718 /* use dummy devices for multiple-address chips */ 719 for (i = 1; i < num_addresses; i++) { 720 err = at24_make_dummy_client(at24, i, client, ®map_config); 721 if (err) 722 return err; 723 } 724 725 /* 726 * We initialize nvmem_config.id to NVMEM_DEVID_AUTO even if the 727 * label property is set as some platform can have multiple eeproms 728 * with same label and we can not register each of those with same 729 * label. Failing to register those eeproms trigger cascade failure 730 * on such platform. 731 */ 732 nvmem_config.id = NVMEM_DEVID_AUTO; 733 734 if (device_property_present(dev, "label")) { 735 err = device_property_read_string(dev, "label", 736 &nvmem_config.name); 737 if (err) 738 return err; 739 } else { 740 nvmem_config.name = dev_name(dev); 741 } 742 743 nvmem_config.type = NVMEM_TYPE_EEPROM; 744 nvmem_config.dev = dev; 745 nvmem_config.read_only = !writable; 746 nvmem_config.root_only = !(flags & AT24_FLAG_IRUGO); 747 nvmem_config.owner = THIS_MODULE; 748 nvmem_config.compat = true; 749 nvmem_config.base_dev = dev; 750 nvmem_config.reg_read = at24_read; 751 nvmem_config.reg_write = at24_write; 752 nvmem_config.priv = at24; 753 nvmem_config.stride = 1; 754 nvmem_config.word_size = 1; 755 nvmem_config.size = byte_len; 756 757 i2c_set_clientdata(client, at24); 758 759 full_power = acpi_dev_state_d0(&client->dev); 760 if (full_power) { 761 err = regulator_enable(at24->vcc_reg); 762 if (err) { 763 dev_err(dev, "Failed to enable vcc regulator\n"); 764 return err; 765 } 766 767 pm_runtime_set_active(dev); 768 } 769 pm_runtime_enable(dev); 770 771 /* 772 * Perform a one-byte test read to verify that the chip is functional, 773 * unless powering on the device is to be avoided during probe (i.e. 774 * it's powered off right now). 775 */ 776 if (full_power) { 777 err = at24_read(at24, 0, &test_byte, 1); 778 if (err) { 779 pm_runtime_disable(dev); 780 if (!pm_runtime_status_suspended(dev)) 781 regulator_disable(at24->vcc_reg); 782 return -ENODEV; 783 } 784 } 785 786 at24->nvmem = devm_nvmem_register(dev, &nvmem_config); 787 if (IS_ERR(at24->nvmem)) { 788 pm_runtime_disable(dev); 789 if (!pm_runtime_status_suspended(dev)) 790 regulator_disable(at24->vcc_reg); 791 return dev_err_probe(dev, PTR_ERR(at24->nvmem), 792 "failed to register nvmem\n"); 793 } 794 795 /* If this a SPD EEPROM, probe for DDR3 thermal sensor */ 796 if (cdata == &at24_data_spd) 797 at24_probe_temp_sensor(client); 798 799 pm_runtime_idle(dev); 800 801 if (writable) 802 dev_info(dev, "%u byte %s EEPROM, writable, %u bytes/write\n", 803 byte_len, client->name, at24->write_max); 804 else 805 dev_info(dev, "%u byte %s EEPROM, read-only\n", 806 byte_len, client->name); 807 808 return 0; 809} 810 811static void at24_remove(struct i2c_client *client) 812{ 813 struct at24_data *at24 = i2c_get_clientdata(client); 814 815 pm_runtime_disable(&client->dev); 816 if (acpi_dev_state_d0(&client->dev)) { 817 if (!pm_runtime_status_suspended(&client->dev)) 818 regulator_disable(at24->vcc_reg); 819 pm_runtime_set_suspended(&client->dev); 820 } 821} 822 823static int __maybe_unused at24_suspend(struct device *dev) 824{ 825 struct i2c_client *client = to_i2c_client(dev); 826 struct at24_data *at24 = i2c_get_clientdata(client); 827 828 return regulator_disable(at24->vcc_reg); 829} 830 831static int __maybe_unused at24_resume(struct device *dev) 832{ 833 struct i2c_client *client = to_i2c_client(dev); 834 struct at24_data *at24 = i2c_get_clientdata(client); 835 836 return regulator_enable(at24->vcc_reg); 837} 838 839static const struct dev_pm_ops at24_pm_ops = { 840 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 841 pm_runtime_force_resume) 842 SET_RUNTIME_PM_OPS(at24_suspend, at24_resume, NULL) 843}; 844 845static struct i2c_driver at24_driver = { 846 .driver = { 847 .name = "at24", 848 .pm = &at24_pm_ops, 849 .of_match_table = at24_of_match, 850 .acpi_match_table = at24_acpi_ids, 851 }, 852 .probe = at24_probe, 853 .remove = at24_remove, 854 .id_table = at24_ids, 855 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 856}; 857 858static int __init at24_init(void) 859{ 860 if (!at24_io_limit) { 861 pr_err("at24: at24_io_limit must not be 0!\n"); 862 return -EINVAL; 863 } 864 865 at24_io_limit = rounddown_pow_of_two(at24_io_limit); 866 return i2c_add_driver(&at24_driver); 867} 868module_init(at24_init); 869 870static void __exit at24_exit(void) 871{ 872 i2c_del_driver(&at24_driver); 873} 874module_exit(at24_exit); 875 876MODULE_DESCRIPTION("Driver for most I2C EEPROMs"); 877MODULE_AUTHOR("David Brownell and Wolfram Sang"); 878MODULE_LICENSE("GPL");
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