rts5264.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Driver for Realtek PCI-Express card reader
  3 *
  4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
  5 *
  6 * Author:
  7 *   Ricky Wu <ricky_wu@realtek.com>
  8 */
  9#ifndef RTS5264_H
 10#define RTS5264_H
 11
 12/*New add*/
 13#define rts5264_vendor_setting_valid(reg)	((reg) & 0x010000)
 14#define rts5264_reg_to_aspm(reg) \
 15	(((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01))
 16#define rts5264_reg_check_reverse_socket(reg)	((reg) & 0x04)
 17#define rts5264_reg_check_wp_reverse(reg)		((reg) & 0x8000)
 18#define rts5264_reg_to_sd30_drive_sel_1v8(reg)	(((reg) >> 22) & 0x03)
 19#define rts5264_reg_to_sd30_drive_sel_3v3(reg)	(((reg) >> 16) & 0x03)
 20#define rts5264_reg_to_rtd3(reg)		((reg) & 0x08)
 21
 22#define RTS5264_AUTOLOAD_CFG0		0xFF7B
 23#define RTS5264_AUTOLOAD_CFG1		0xFF7C
 24#define RTS5264_AUTOLOAD_CFG3		0xFF7E
 25#define RTS5264_AUTOLOAD_CFG4		0xFF7F
 26#define RTS5264_FORCE_PRSNT_LOW		(1 << 6)
 27#define RTS5264_AUX_CLK_16M_EN		(1 << 5)
 28#define RTS5264_F_HIGH_RC_MASK		(1 << 4)
 29#define RTS5264_F_HIGH_RC_1_6M		(1 << 4)
 30#define RTS5264_F_HIGH_RC_400K		(0 << 4)
 31
 32/* SSC_CTL2 0xFC12 */
 33#define RTS5264_SSC_DEPTH_MASK		0x07
 34#define RTS5264_SSC_DEPTH_DISALBE	0x00
 35#define RTS5264_SSC_DEPTH_8M		0x01
 36#define RTS5264_SSC_DEPTH_4M		0x02
 37#define RTS5264_SSC_DEPTH_2M		0x03
 38#define RTS5264_SSC_DEPTH_1M		0x04
 39#define RTS5264_SSC_DEPTH_512K		0x05
 40#define RTS5264_SSC_DEPTH_256K		0x06
 41#define RTS5264_SSC_DEPTH_128K		0x07
 42
 43#define RTS5264_CARD_CLK_SRC2		0xFC2F
 44#define RTS5264_REG_BIG_KVCO_A		0x20
 45
 46/* efuse control register*/
 47#define RTS5264_EFUSE_CTL		0xFC30
 48#define RTS5264_EFUSE_ENABLE		0x80
 49/* EFUSE_MODE: 0=READ 1=PROGRAM */
 50#define RTS5264_EFUSE_MODE_MASK		0x40
 51#define RTS5264_EFUSE_PROGRAM		0x40
 52
 53#define RTS5264_EFUSE_ADDR		0xFC31
 54#define	RTS5264_EFUSE_ADDR_MASK		0x3F
 55
 56#define RTS5264_EFUSE_WRITE_DATA	0xFC32
 57#define RTS5264_EFUSE_READ_DATA		0xFC34
 58
 59#define RTS5264_SYS_DUMMY_1		0xFC35
 60#define RTS5264_REG_BIG_KVCO		0x04
 61
 62/* DMACTL 0xFE2C */
 63#define RTS5264_DMA_PACK_SIZE_MASK	0x70
 64
 65#define RTS5264_FW_CFG_INFO2	0xFF52
 66
 67#define RTS5264_FW_CFG1			0xFF55
 68#define RTS5264_SYS_CLK_SEL_MCU_CLK	(0x01<<7)
 69#define RTS5264_CRC_CLK_SEL_MCU_CLK	(0x01<<6)
 70#define RTS5264_FAKE_MCU_CLOCK_GATING	(0x01<<5)
 71#define RTS5264_MCU_BUS_SEL_MASK	(0x01<<4)
 72
 73/* FW status register */
 74#define RTS5264_FW_STATUS		0xFF56
 75#define RTS5264_EXPRESS_LINK_FAIL_MASK	(0x01<<7)
 76
 77/* FW control register */
 78#define RTS5264_FW_CTL			0xFF5F
 79#define RTS5264_INFORM_RTD3_COLD	(0x01<<5)
 80
 81#define RTS5264_REG_FPDCTL		0xFF60
 82
 83#define RTS5264_REG_LDO12_CFG		0xFF6E
 84#define RTS5264_LDO12_SR_MASK		(0x03<<6)
 85#define RTS5264_LDO12_SR_1_0_MS		(0x03<<6)
 86#define RTS5264_LDO12_SR_0_5_MS		(0x02<<6)
 87#define RTS5264_LDO12_SR_0_2_5_MS	(0x01<<6)
 88#define RTS5264_LDO12_SR_0_0_MS		(0x00<<6)
 89#define RTS5264_LDO12_VO_TUNE_MASK	(0x07<<1)
 90#define RTS5264_LDO12_115		(0x03<<1)
 91#define RTS5264_LDO12_120		(0x04<<1)
 92#define RTS5264_LDO12_125		(0x05<<1)
 93#define RTS5264_LDO12_130		(0x06<<1)
 94#define RTS5264_LDO12_135		(0x07<<1)
 95
 96/* LDO control register */
 97#define RTS5264_CARD_PWR_CTL		0xFD50
 98#define RTS5264_SD_CLK_ISO		(0x01<<7)
 99#define RTS5264_PAD_SD_DAT_FW_CTRL	(0x01<<6)
100#define RTS5264_PUPDC			(0x01<<5)
101#define RTS5264_SD_CMD_ISO		(0x01<<4)
102
103#define RTS5264_OCP_VDD3_CTL		0xFD89
104#define SD_VDD3_DETECT_EN		0x08
105#define SD_VDD3_OCP_INT_EN		0x04
106#define SD_VDD3_OCP_INT_CLR		0x02
107#define SD_VDD3_OC_CLR			0x01
108
109#define RTS5264_OCP_VDD3_STS		0xFD8A
110#define SD_VDD3_OCP_DETECT		0x08
111#define SD_VDD3_OC_NOW			0x04
112#define SD_VDD3_OC_EVER			0x02
113
114#define RTS5264_OVP_CTL			0xFD8D
115#define RTS5264_OVP_TIME_MASK		0xF0
116#define RTS5264_OVP_TIME_DFT		0x50
117#define RTS5264_OVP_DETECT_EN		0x08
118#define RTS5264_OVP_INT_EN		0x04
119#define RTS5264_OVP_INT_CLR		0x02
120#define RTS5264_OVP_CLR			0x01
121
122#define RTS5264_OVP_STS			0xFD8E
123#define RTS5264_OVP_GLTCH_TIME_MASK	0xF0
124#define RTS5264_OVP_GLTCH_TIME_DFT	0x50
125#define RTS5264_VOVER_DET		0x08
126#define RTS5264_OVP_NOW			0x04
127#define RTS5264_OVP_EVER		0x02
128
129#define RTS5264_CMD_OE_START_EARLY		0xFDCB
130#define RTS5264_CMD_OE_EARLY_LEAVE		0x08
131#define RTS5264_CMD_OE_EARLY_CYCLE_MASK		0x06
132#define RTS5264_CMD_OE_EARLY_4CYCLE		0x06
133#define RTS5264_CMD_OE_EARLY_3CYCLE		0x04
134#define RTS5264_CMD_OE_EARLY_2CYCLE		0x02
135#define RTS5264_CMD_OE_EARLY_1CYCLE		0x00
136#define RTS5264_CMD_OE_EARLY_EN			0x01
137
138#define RTS5264_DAT_OE_START_EARLY		0xFDCC
139#define RTS5264_DAT_OE_EARLY_LEAVE		0x08
140#define RTS5264_DAT_OE_EARLY_CYCLE_MASK		0x06
141#define RTS5264_DAT_OE_EARLY_4CYCLE		0x06
142#define RTS5264_DAT_OE_EARLY_3CYCLE		0x04
143#define RTS5264_DAT_OE_EARLY_2CYCLE		0x02
144#define RTS5264_DAT_OE_EARLY_1CYCLE		0x00
145#define RTS5264_DAT_OE_EARLY_EN			0x01
146
147#define RTS5264_LDO1233318_POW_CTL	0xFF70
148#define RTS5264_TUNE_REF_LDO3318	(0x03<<6)
149#define RTS5264_TUNE_REF_LDO3318_DFT	(0x02<<6)
150#define RTS5264_LDO3318_POWERON		(0x01<<3)
151#define RTS5264_LDO3_POWERON		(0x01<<2)
152#define RTS5264_LDO2_POWERON		(0x01<<1)
153#define RTS5264_LDO1_POWERON		(0x01<<0)
154#define RTS5264_LDO_POWERON_MASK	(0x0F<<0)
155
156#define RTS5264_DV3318_CFG		0xFF71
157#define RTS5264_DV3318_TUNE_MASK	(0x07<<4)
158#define RTS5264_DV3318_18		(0x02<<4)
159#define RTS5264_DV3318_19		(0x04<<4)
160#define RTS5264_DV3318_33		(0x07<<4)
161
162#define RTS5264_LDO1_CFG0		0xFF72
163#define RTS5264_LDO1_OCP_THD_MASK	(0x07 << 5)
164#define RTS5264_LDO1_OCP_EN		(0x01 << 4)
165#define RTS5264_LDO1_OCP_LMT_THD_MASK	(0x03 << 2)
166#define RTS5264_LDO1_OCP_LMT_EN		(0x01 << 1)
167
168#define RTS5264_LDO1_OCP_THD_850	(0x00<<5)
169#define RTS5264_LDO1_OCP_THD_950	(0x01<<5)
170#define RTS5264_LDO1_OCP_THD_1050	(0x02<<5)
171#define RTS5264_LDO1_OCP_THD_1100	(0x03<<5)
172#define RTS5264_LDO1_OCP_THD_1150	(0x04<<5)
173#define RTS5264_LDO1_OCP_THD_1200	(0x05<<5)
174#define RTS5264_LDO1_OCP_THD_1300	(0x06<<5)
175#define RTS5264_LDO1_OCP_THD_1350	(0x07<<5)
176
177#define RTS5264_LDO1_LMT_THD_1700	(0x00<<2)
178#define RTS5264_LDO1_LMT_THD_1800	(0x01<<2)
179#define RTS5264_LDO1_LMT_THD_1900	(0x02<<2)
180#define RTS5264_LDO1_LMT_THD_2000	(0x03<<2)
181
182#define RTS5264_LDO1_CFG1		0xFF73
183#define RTS5264_LDO1_TUNE_MASK		(0x07<<1)
184#define RTS5264_LDO1_18			(0x05<<1)
185#define RTS5264_LDO1_33			(0x07<<1)
186#define RTS5264_LDO1_PWD_MASK		(0x01<<0)
187
188#define RTS5264_LDO2_CFG0		0xFF74
189#define RTS5264_LDO2_OCP_THD_MASK	(0x07<<5)
190#define RTS5264_LDO2_OCP_EN		(0x01<<4)
191#define RTS5264_LDO2_OCP_LMT_THD_MASK	(0x03<<2)
192#define RTS5264_LDO2_OCP_LMT_EN		(0x01<<1)
193
194#define RTS5264_LDO2_OCP_THD_750	(0x00<<5)
195#define RTS5264_LDO2_OCP_THD_850	(0x01<<5)
196#define RTS5264_LDO2_OCP_THD_900	(0x02<<5)
197#define RTS5264_LDO2_OCP_THD_950	(0x03<<5)
198#define RTS5264_LDO2_OCP_THD_1050	(0x04<<5)
199#define RTS5264_LDO2_OCP_THD_1100	(0x05<<5)
200#define RTS5264_LDO2_OCP_THD_1150	(0x06<<5)
201#define RTS5264_LDO2_OCP_THD_1200	(0x07<<5)
202
203#define RTS5264_LDO2_LMT_THD_1700	(0x00<<2)
204#define RTS5264_LDO2_LMT_THD_1800	(0x01<<2)
205#define RTS5264_LDO2_LMT_THD_1900	(0x02<<2)
206#define RTS5264_LDO2_LMT_THD_2000	(0x03<<2)
207
208#define RTS5264_LDO2_CFG1		0xFF75
209#define RTS5264_LDO2_TUNE_MASK		(0x07<<1)
210#define RTS5264_LDO2_18			(0x02<<1)
211#define RTS5264_LDO2_185		(0x03<<1)
212#define RTS5264_LDO2_19			(0x04<<1)
213#define RTS5264_LDO2_195		(0x05<<1)
214#define RTS5264_LDO2_33			(0x07<<1)
215#define RTS5264_LDO2_PWD_MASK		(0x01<<0)
216
217#define RTS5264_LDO3_CFG0		0xFF76
218#define RTS5264_LDO3_OCP_THD_MASK	(0x07<<5)
219#define RTS5264_LDO3_OCP_EN		(0x01<<4)
220#define RTS5264_LDO3_OCP_LMT_THD_MASK	(0x03<<2)
221#define RTS5264_LDO3_OCP_LMT_EN		(0x01<<1)
222
223#define RTS5264_LDO3_OCP_THD_610	(0x00<<5)
224#define RTS5264_LDO3_OCP_THD_630	(0x01<<5)
225#define RTS5264_LDO3_OCP_THD_670	(0x02<<5)
226#define RTS5264_LDO3_OCP_THD_710	(0x03<<5)
227#define RTS5264_LDO3_OCP_THD_750	(0x04<<5)
228#define RTS5264_LDO3_OCP_THD_770	(0x05<<5)
229#define RTS5264_LDO3_OCP_THD_810	(0x06<<5)
230#define RTS5264_LDO3_OCP_THD_850	(0x07<<5)
231
232#define RTS5264_LDO3_LMT_THD_1200	(0x00<<2)
233#define RTS5264_LDO3_LMT_THD_1300	(0x01<<2)
234#define RTS5264_LDO3_LMT_THD_1400	(0x02<<2)
235#define RTS5264_LDO3_LMT_THD_1500	(0x03<<2)
236
237#define RTS5264_LDO3_CFG1		0xFF77
238#define RTS5264_LDO3_TUNE_MASK		(0x07<<1)
239#define RTS5264_LDO3_12			(0x02<<1)
240#define RTS5264_LDO3_125		(0x03<<1)
241#define RTS5264_LDO3_13			(0x04<<1)
242#define RTS5264_LDO3_135		(0x05<<1)
243#define RTS5264_LDO3_33			(0x07<<1)
244#define RTS5264_LDO3_PWD_MASK		(0x01<<0)
245
246#define RTS5264_REG_PME_FORCE_CTL	0xFF78
247#define FORCE_PM_CONTROL		0x20
248#define FORCE_PM_VALUE			0x10
249#define REG_EFUSE_BYPASS		0x08
250#define REG_EFUSE_POR			0x04
251#define REG_EFUSE_POWER_MASK		0x03
252#define REG_EFUSE_POWERON		0x03
253#define REG_EFUSE_POWEROFF		0x00
254
255#define RTS5264_PWR_CUT			0xFF81
256#define RTS5264_CFG_MEM_PD		0xF0
257
258#define RTS5264_OVP_DET			0xFF8A
259#define RTS5264_POW_VDET		0x04
260#define RTS5264_TUNE_VROV_MASK		0x03
261#define RTS5264_TUNE_VROV_2V		0x03
262#define RTS5264_TUNE_VROV_1V8		0x02
263#define RTS5264_TUNE_VROV_1V6		0x01
264#define RTS5264_TUNE_VROV_1V4		0x00
265
266#define RTS5264_CKMUX_MBIAS_PWR		0xFF8B
267#define RTS5264_NON_XTAL_SEL		0x80
268#define RTS5264_POW_CKMUX		0x40
269#define RTS5264_LVD_MASK		0x04
270#define RTS5264_POW_PSW_MASK		0x03
271#define RTS5264_POW_PSW_DFT		0x03
272
273/* Single LUN, support SD/SD EXPRESS */
274#define DEFAULT_SINGLE		0
275#define SD_LUN			1
276#define SD_EXPRESS_LUN		2
277
278#define RTS5264_IC_VER_A		0
279#define RTS5264_IC_VER_B		2
280#define RTS5264_IC_VER_C		3
281
282int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
283		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
284
285#endif /* RTS5264_H */