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rts5264.c
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linux-6.19.14/drivers/misc/cardreader/rts5264.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Ricky Wu <ricky_wu@realtek.com> 8 */ 9 10#include <linux/module.h> 11#include <linux/delay.h> 12#include <linux/rtsx_pci.h> 13 14#include "rts5264.h" 15#include "rtsx_pcr.h" 16 17static u8 rts5264_get_ic_version(struct rtsx_pcr *pcr) 18{ 19 u8 val; 20 21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 22 return val & 0x0F; 23} 24 25static void rts5264_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 26{ 27 u8 driving_3v3[4][3] = { 28 {0x88, 0x88, 0x88}, 29 {0x77, 0x77, 0x77}, 30 {0x99, 0x99, 0x99}, 31 {0x66, 0x66, 0x66}, 32 }; 33 u8 driving_1v8[4][3] = { 34 {0x99, 0x99, 0x99}, 35 {0x77, 0x77, 0x77}, 36 {0xBB, 0xBB, 0xBB}, 37 {0x65, 0x65, 0x65}, 38 }; 39 u8 (*driving)[3], drive_sel; 40 41 if (voltage == OUTPUT_3V3) { 42 driving = driving_3v3; 43 drive_sel = pcr->sd30_drive_sel_3v3; 44 } else { 45 driving = driving_1v8; 46 drive_sel = pcr->sd30_drive_sel_1v8; 47 } 48 49 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, 50 0xFF, driving[drive_sel][0]); 51 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, 52 0xFF, driving[drive_sel][1]); 53 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, 54 0xFF, driving[drive_sel][2]); 55} 56 57static void rts5264_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) 58{ 59 /* Set relink_time to 0 */ 60 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); 61 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); 62 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 63 RELINK_TIME_MASK, 0); 64 65 if (pm_state == HOST_ENTER_S3) 66 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 67 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 68 69 if (!runtime) { 70 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1, 71 CD_RESUME_EN_MASK, 0); 72 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); 73 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, 74 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); 75 } else { 76 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, 77 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0); 78 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01); 79 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 80 D3_DELINK_MODE_EN, 0); 81 rtsx_pci_write_register(pcr, RTS5264_FW_CTL, 82 RTS5264_INFORM_RTD3_COLD, RTS5264_INFORM_RTD3_COLD); 83 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, 84 RTS5264_FORCE_PRSNT_LOW, RTS5264_FORCE_PRSNT_LOW); 85 } 86 87 rtsx_pci_write_register(pcr, RTS5264_REG_FPDCTL, 88 SSC_POWER_DOWN, SSC_POWER_DOWN); 89} 90 91static int rts5264_enable_auto_blink(struct rtsx_pcr *pcr) 92{ 93 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 94 LED_SHINE_MASK, LED_SHINE_EN); 95} 96 97static int rts5264_disable_auto_blink(struct rtsx_pcr *pcr) 98{ 99 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 100 LED_SHINE_MASK, LED_SHINE_DISABLE); 101} 102 103static int rts5264_turn_on_led(struct rtsx_pcr *pcr) 104{ 105 return rtsx_pci_write_register(pcr, GPIO_CTL, 106 0x02, 0x02); 107} 108 109static int rts5264_turn_off_led(struct rtsx_pcr *pcr) 110{ 111 return rtsx_pci_write_register(pcr, GPIO_CTL, 112 0x02, 0x00); 113} 114 115/* SD Pull Control Enable: 116 * SD_DAT[3:0] ==> pull up 117 * SD_CD ==> pull up 118 * SD_WP ==> pull up 119 * SD_CMD ==> pull up 120 * SD_CLK ==> pull down 121 */ 122static const u32 rts5264_sd_pull_ctl_enable_tbl[] = { 123 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 124 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 125 0, 126}; 127 128/* SD Pull Control Disable: 129 * SD_DAT[3:0] ==> pull down 130 * SD_CD ==> pull up 131 * SD_WP ==> pull down 132 * SD_CMD ==> pull down 133 * SD_CLK ==> pull down 134 */ 135static const u32 rts5264_sd_pull_ctl_disable_tbl[] = { 136 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 137 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 138 0, 139}; 140 141static int rts5264_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) 142{ 143 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK 144 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 145 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); 146 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, 147 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 148 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 149 150 return 0; 151} 152 153static int rts5264_card_power_on(struct rtsx_pcr *pcr, int card) 154{ 155 struct rtsx_cr_option *option = &pcr->option; 156 157 if (option->ocp_en) 158 rtsx_pci_enable_ocp(pcr); 159 160 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, 161 CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD); 162 163 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG1, 164 RTS5264_LDO1_TUNE_MASK, RTS5264_LDO1_33); 165 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, 166 RTS5264_LDO1_POWERON, RTS5264_LDO1_POWERON); 167 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, 168 RTS5264_LDO3318_POWERON, RTS5264_LDO3318_POWERON); 169 170 msleep(20); 171 172 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 173 174 /* Initialize SD_CFG1 register */ 175 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF, 176 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT); 177 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, 178 0xFF, SD20_RX_POS_EDGE); 179 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0); 180 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, 181 SD_STOP | SD_CLR_ERR); 182 183 /* Reset SD_CFG3 register */ 184 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); 185 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, 186 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 | 187 SD30_CLK_STOP_CFG0, 0); 188 189 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || 190 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 191 rts5264_sd_set_sample_push_timing_sd30(pcr); 192 193 return 0; 194} 195 196static int rts5264_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 197{ 198 rtsx_pci_write_register(pcr, RTS5264_CARD_PWR_CTL, 199 RTS5264_PUPDC, RTS5264_PUPDC); 200 201 switch (voltage) { 202 case OUTPUT_3V3: 203 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, 204 RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318); 205 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG, 206 RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_33); 207 rtsx_pci_write_register(pcr, SD_PAD_CTL, 208 SD_IO_USING_1V8, 0); 209 break; 210 case OUTPUT_1V8: 211 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, 212 RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318_DFT); 213 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG, 214 RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_18); 215 rtsx_pci_write_register(pcr, SD_PAD_CTL, 216 SD_IO_USING_1V8, SD_IO_USING_1V8); 217 break; 218 default: 219 return -EINVAL; 220 } 221 222 /* set pad drive */ 223 rts5264_fill_driving(pcr, voltage); 224 225 return 0; 226} 227 228static void rts5264_stop_cmd(struct rtsx_pcr *pcr) 229{ 230 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); 231 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); 232 rtsx_pci_write_register(pcr, DMACTL, DMA_RST, DMA_RST); 233 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); 234} 235 236static void rts5264_card_before_power_off(struct rtsx_pcr *pcr) 237{ 238 rts5264_stop_cmd(pcr); 239 rts5264_switch_output_voltage(pcr, OUTPUT_3V3); 240} 241 242static int rts5264_card_power_off(struct rtsx_pcr *pcr, int card) 243{ 244 int err = 0; 245 246 rts5264_card_before_power_off(pcr); 247 err = rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, 248 RTS5264_LDO_POWERON_MASK, 0); 249 250 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, 251 CFG_SD_POW_AUTO_PD, 0); 252 if (pcr->option.ocp_en) 253 rtsx_pci_disable_ocp(pcr); 254 255 return err; 256} 257 258static void rts5264_enable_ocp(struct rtsx_pcr *pcr) 259{ 260 u8 mask = 0; 261 u8 val = 0; 262 263 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, 264 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 265 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN); 266 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, 267 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 268 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN); 269 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, 270 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 271 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN); 272 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, 273 RTS5264_POW_VDET, RTS5264_POW_VDET); 274 275 mask = SD_OCP_INT_EN | SD_DETECT_EN; 276 mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN; 277 val = mask; 278 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 279 280 mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN; 281 val = mask; 282 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, val); 283 284 mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN; 285 val = mask; 286 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, val); 287} 288 289static void rts5264_disable_ocp(struct rtsx_pcr *pcr) 290{ 291 u8 mask = 0; 292 293 mask = SD_OCP_INT_EN | SD_DETECT_EN; 294 mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN; 295 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 296 297 mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN; 298 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, 0); 299 300 mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN; 301 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, 0); 302 303 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, 304 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0); 305 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, 306 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0); 307 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, 308 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0); 309 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, RTS5264_POW_VDET, 0); 310} 311 312static void rts5264_init_ocp(struct rtsx_pcr *pcr) 313{ 314 struct rtsx_cr_option *option = &pcr->option; 315 316 if (option->ocp_en) { 317 u8 mask, val; 318 319 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, 320 RTS5264_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd); 321 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, 322 RTS5264_LDO1_OCP_LMT_THD_MASK, 323 RTS5264_LDO1_LMT_THD_2000); 324 325 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, 326 RTS5264_LDO2_OCP_THD_MASK, RTS5264_LDO2_OCP_THD_950); 327 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, 328 RTS5264_LDO2_OCP_LMT_THD_MASK, 329 RTS5264_LDO2_LMT_THD_2000); 330 331 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, 332 RTS5264_LDO3_OCP_THD_MASK, RTS5264_LDO3_OCP_THD_710); 333 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, 334 RTS5264_LDO3_OCP_LMT_THD_MASK, 335 RTS5264_LDO3_LMT_THD_1500); 336 337 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, 338 RTS5264_TUNE_VROV_MASK, RTS5264_TUNE_VROV_1V6); 339 340 mask = SD_OCP_GLITCH_MASK | SDVIO_OCP_GLITCH_MASK; 341 val = pcr->hw_param.ocp_glitch; 342 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); 343 344 } else { 345 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, 346 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0); 347 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, 348 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0); 349 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, 350 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0); 351 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, 352 RTS5264_POW_VDET, 0); 353 } 354} 355 356static int rts5264_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val) 357{ 358 return rtsx_pci_read_register(pcr, RTS5264_OCP_VDD3_STS, val); 359} 360 361static int rts5264_get_ovpstat(struct rtsx_pcr *pcr, u8 *val) 362{ 363 return rtsx_pci_read_register(pcr, RTS5264_OVP_STS, val); 364} 365 366static void rts5264_clear_ocpstat(struct rtsx_pcr *pcr) 367{ 368 u8 mask = 0; 369 u8 val = 0; 370 371 mask = SD_OCP_INT_CLR | SD_OC_CLR; 372 mask |= SDVIO_OCP_INT_CLR | SDVIO_OC_CLR; 373 val = mask; 374 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 375 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, 376 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR, 377 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR); 378 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, 379 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR, 380 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR); 381 382 udelay(1000); 383 384 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 385 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, 386 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR, 0); 387 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, 388 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR, 0); 389} 390 391static void rts5264_process_ocp(struct rtsx_pcr *pcr) 392{ 393 if (!pcr->option.ocp_en) 394 return; 395 396 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); 397 rts5264_get_ocpstat2(pcr, &pcr->ocp_stat2); 398 rts5264_get_ovpstat(pcr, &pcr->ovp_stat); 399 400 if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER | SDVIO_OC_NOW | SDVIO_OC_EVER)) || 401 (pcr->ocp_stat2 & (SD_VDD3_OC_NOW | SD_VDD3_OC_EVER)) || 402 (pcr->ovp_stat & (RTS5264_OVP_NOW | RTS5264_OVP_EVER))) { 403 rts5264_clear_ocpstat(pcr); 404 rts5264_card_power_off(pcr, RTSX_SD_CARD); 405 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 406 pcr->ocp_stat = 0; 407 pcr->ocp_stat2 = 0; 408 pcr->ovp_stat = 0; 409 } 410} 411 412static void rts5264_init_from_hw(struct rtsx_pcr *pcr) 413{ 414 struct pci_dev *pdev = pcr->pci; 415 u32 lval1, lval2, i; 416 u16 setting_reg1, setting_reg2, phy_val; 417 u8 valid, efuse_valid, tmp, efuse_len; 418 419 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, 420 REG_EFUSE_POR | REG_EFUSE_POWER_MASK, 421 REG_EFUSE_POR | REG_EFUSE_POWERON); 422 udelay(1); 423 rtsx_pci_write_register(pcr, RTS5264_EFUSE_ADDR, 424 RTS5264_EFUSE_ADDR_MASK, 0x00); 425 rtsx_pci_write_register(pcr, RTS5264_EFUSE_CTL, 426 RTS5264_EFUSE_ENABLE | RTS5264_EFUSE_MODE_MASK, 427 RTS5264_EFUSE_ENABLE); 428 429 /* Wait transfer end */ 430 for (i = 0; i < MAX_RW_REG_CNT; i++) { 431 rtsx_pci_read_register(pcr, RTS5264_EFUSE_CTL, &tmp); 432 if ((tmp & 0x80) == 0) 433 break; 434 } 435 rtsx_pci_read_register(pcr, RTS5264_EFUSE_READ_DATA, &tmp); 436 efuse_len = ((tmp & 0x70) >> 4); 437 pcr_dbg(pcr, "Load efuse len: 0x%x\n", efuse_len); 438 efuse_valid = ((tmp & 0x0C) >> 2); 439 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid); 440 441 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2); 442 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2); 443 /* 0x816 */ 444 valid = (u8)((lval2 >> 16) & 0x03); 445 446 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, 447 REG_EFUSE_POR, 0); 448 pcr_dbg(pcr, "Disable efuse por!\n"); 449 450 if (is_version(pcr, PID_5264, RTS5264_IC_VER_B)) { 451 pci_write_config_dword(pdev, 0x718, 0x0007C000); 452 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE, 0xFF, 0x88); 453 rtsx_pci_read_phy_register(pcr, _PHY_REV0, &phy_val); 454 phy_val &= 0xFFFD; 455 456 if (efuse_len == 0) { 457 rtsx_pci_write_register(pcr, RTS5264_FW_CFG_INFO2, 0x0F, 0x0F); 458 rtsx_pci_write_register(pcr, 0xFF14, 0xFF, 0x79); 459 rtsx_pci_write_register(pcr, 0xFF15, 0xFF, 0xFF); 460 rtsx_pci_write_register(pcr, 0xFF16, 0xFF, 0x3D); 461 rtsx_pci_write_register(pcr, 0xFF17, 0xFF, 0xFE); 462 463 rtsx_pci_write_register(pcr, 0xFF18, 0xFF, 0x5B); 464 rtsx_pci_write_register(pcr, 0xFF19, 0xFF, 0xFF); 465 rtsx_pci_write_register(pcr, 0xFF1A, 0xFF, 0x3E); 466 rtsx_pci_write_register(pcr, 0xFF1B, 0xFF, 0xFE); 467 468 rtsx_pci_write_register(pcr, 0xFF1C, 0xFF, 0x00); 469 rtsx_pci_write_register(pcr, 0xFF1D, 0xFF, 0xFF); 470 rtsx_pci_write_register(pcr, 0xFF1E, 0xFF, 0x3F); 471 rtsx_pci_write_register(pcr, 0xFF1F, 0xFF, 0xFE); 472 473 rtsx_pci_write_register(pcr, 0xFF20, 0xFF, 0x81); 474 rtsx_pci_write_register(pcr, 0xFF21, 0xFF, 0xFF); 475 rtsx_pci_write_register(pcr, 0xFF22, 0xFF, 0x3C); 476 rtsx_pci_write_register(pcr, 0xFF23, 0xFF, 0xFE); 477 } 478 479 rtsx_pci_write_register(pcr, 0xFF24, 0xFF, 0x79); 480 rtsx_pci_write_register(pcr, 0xFF25, 0xFF, 0x5B); 481 rtsx_pci_write_register(pcr, 0xFF26, 0xFF, 0x00); 482 rtsx_pci_write_register(pcr, 0xFF27, 0xFF, 0x40); 483 484 rtsx_pci_write_register(pcr, 0xFF28, 0xFF, (u8)phy_val); 485 rtsx_pci_write_register(pcr, 0xFF29, 0xFF, (u8)(phy_val >> 8)); 486 rtsx_pci_write_register(pcr, 0xFF2A, 0xFF, 0x19); 487 rtsx_pci_write_register(pcr, 0xFF2B, 0xFF, 0x40); 488 489 rtsx_pci_write_register(pcr, 0xFF2C, 0xFF, 0x20); 490 rtsx_pci_write_register(pcr, 0xFF2D, 0xFF, 0xDA); 491 rtsx_pci_write_register(pcr, 0xFF2E, 0xFF, 0x0A); 492 rtsx_pci_write_register(pcr, 0xFF2F, 0xFF, 0x40); 493 494 rtsx_pci_write_register(pcr, 0xFF30, 0xFF, 0x20); 495 rtsx_pci_write_register(pcr, 0xFF31, 0xFF, 0xD2); 496 rtsx_pci_write_register(pcr, 0xFF32, 0xFF, 0x0A); 497 rtsx_pci_write_register(pcr, 0xFF33, 0xFF, 0x40); 498 } else { 499 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE, 0x80, 0x80); 500 } 501 502 if (efuse_valid == 2 || efuse_valid == 3) { 503 if (valid == 3) { 504 /* Bypass efuse */ 505 setting_reg1 = PCR_SETTING_REG1; 506 setting_reg2 = PCR_SETTING_REG2; 507 } else { 508 /* Use efuse data */ 509 setting_reg1 = PCR_SETTING_REG4; 510 setting_reg2 = PCR_SETTING_REG5; 511 } 512 } else if (efuse_valid == 0) { 513 // default 514 setting_reg1 = PCR_SETTING_REG1; 515 setting_reg2 = PCR_SETTING_REG2; 516 } else { 517 return; 518 } 519 520 pci_read_config_dword(pdev, setting_reg2, &lval2); 521 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2); 522 523 if (!rts5264_vendor_setting_valid(lval2)) { 524 pcr_dbg(pcr, "skip fetch vendor setting\n"); 525 return; 526 } 527 528 pcr->rtd3_en = rts5264_reg_to_rtd3(lval2); 529 530 if (rts5264_reg_check_reverse_socket(lval2)) { 531 if (is_version_higher_than(pcr, PID_5264, RTS5264_IC_VER_B)) 532 pcr->option.sd_cd_reverse_en = 1; 533 else 534 pcr->flags |= PCR_REVERSE_SOCKET; 535 } 536 537 if (rts5264_reg_check_wp_reverse(lval2) && 538 is_version_higher_than(pcr, PID_5264, RTS5264_IC_VER_B)) 539 pcr->option.sd_wp_reverse_en = 1; 540 541 pci_read_config_dword(pdev, setting_reg1, &lval1); 542 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1); 543 544 pcr->aspm_en = rts5264_reg_to_aspm(lval1); 545 pcr->sd30_drive_sel_1v8 = rts5264_reg_to_sd30_drive_sel_1v8(lval1); 546 pcr->sd30_drive_sel_3v3 = rts5264_reg_to_sd30_drive_sel_3v3(lval1); 547 548 if (setting_reg1 == PCR_SETTING_REG1) { 549 /* store setting */ 550 rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF)); 551 rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF)); 552 rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF)); 553 rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF)); 554 rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF)); 555 rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF)); 556 rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF)); 557 558 pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1); 559 lval2 = lval2 & 0x00FFFFFF; 560 pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2); 561 } 562} 563 564static void rts5264_init_from_cfg(struct rtsx_pcr *pcr) 565{ 566 struct rtsx_cr_option *option = &pcr->option; 567 568 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 569 | PM_L1_1_EN | PM_L1_2_EN)) 570 rtsx_pci_disable_oobs_polling(pcr); 571 else 572 rtsx_pci_enable_oobs_polling(pcr); 573 574 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); 575 576 if (option->ltr_en) { 577 if (option->ltr_enabled) 578 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 579 } 580} 581 582static int rts5264_extra_init_hw(struct rtsx_pcr *pcr) 583{ 584 struct rtsx_cr_option *option = &pcr->option; 585 586 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1, 587 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); 588 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); 589 590 rts5264_init_from_cfg(pcr); 591 rts5264_init_from_hw(pcr); 592 593 /* power off efuse */ 594 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, 595 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF); 596 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2, 597 RTS5264_CHIP_RST_N_SEL, 0); 598 rtsx_pci_write_register(pcr, RTS5264_REG_LDO12_CFG, 599 RTS5264_LDO12_SR_MASK, RTS5264_LDO12_SR_0_0_MS); 600 rtsx_pci_write_register(pcr, CDGW, 0xFF, 0x01); 601 rtsx_pci_write_register(pcr, RTS5264_CKMUX_MBIAS_PWR, 602 RTS5264_POW_CKMUX, RTS5264_POW_CKMUX); 603 rtsx_pci_write_register(pcr, RTS5264_CMD_OE_START_EARLY, 604 RTS5264_CMD_OE_EARLY_EN | RTS5264_CMD_OE_EARLY_CYCLE_MASK, 605 RTS5264_CMD_OE_EARLY_EN); 606 rtsx_pci_write_register(pcr, RTS5264_DAT_OE_START_EARLY, 607 RTS5264_DAT_OE_EARLY_EN | RTS5264_DAT_OE_EARLY_CYCLE_MASK, 608 RTS5264_DAT_OE_EARLY_EN); 609 rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D); 610 611 rtsx_pci_write_register(pcr, RTS5264_PWR_CUT, 612 RTS5264_CFG_MEM_PD, RTS5264_CFG_MEM_PD); 613 rtsx_pci_write_register(pcr, L1SUB_CONFIG1, 614 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE); 615 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0); 616 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, 617 RTS5264_AUX_CLK_16M_EN, 0); 618 619 /* Release PRSNT# */ 620 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, 621 RTS5264_FORCE_PRSNT_LOW, 0); 622 rtsx_pci_write_register(pcr, PCLK_CTL, 623 PCLK_MODE_SEL, PCLK_MODE_SEL); 624 625 /* LED shine disabled, set initial shine cycle period */ 626 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02); 627 628 /* Configure driving */ 629 rts5264_fill_driving(pcr, OUTPUT_3V3); 630 631 if (pcr->flags & PCR_REVERSE_SOCKET) 632 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); 633 else { 634 rtsx_pci_write_register(pcr, PETXCFG, 0x20, option->sd_cd_reverse_en << 5); 635 rtsx_pci_write_register(pcr, PETXCFG, 0x10, option->sd_wp_reverse_en << 4); 636 } 637 638 /* 639 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 640 * to drive low, and we forcibly request clock. 641 */ 642 if (option->force_clkreq_0) 643 rtsx_pci_write_register(pcr, PETXCFG, 644 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 645 else 646 rtsx_pci_write_register(pcr, PETXCFG, 647 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 648 649 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFF); 650 rtsx_pci_write_register(pcr, RBCTL, U_AUTO_DMA_EN_MASK, 0); 651 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, 652 RTS5264_F_HIGH_RC_MASK, RTS5264_F_HIGH_RC_400K); 653 654 if (pcr->rtd3_en) { 655 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); 656 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, 657 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0); 658 } else { 659 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); 660 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, 661 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); 662 } 663 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00); 664 665 /* Clear Enter RTD3_cold Information*/ 666 rtsx_pci_write_register(pcr, RTS5264_FW_CTL, 667 RTS5264_INFORM_RTD3_COLD, 0); 668 669 return 0; 670} 671 672static int rts5264_optimize_phy(struct rtsx_pcr *pcr) 673{ 674 u16 subvendor, subdevice, val; 675 676 subvendor = pcr->pci->subsystem_vendor; 677 subdevice = pcr->pci->subsystem_device; 678 679 if ((subvendor == 0x1028) && (subdevice == 0x0CE1)) { 680 rtsx_pci_read_phy_register(pcr, _PHY_REV0, &val); 681 if ((val & 0xFE00) > 0x3800) 682 rtsx_pci_update_phy(pcr, _PHY_REV0, 0x1FF, 0x3800); 683 } 684 685 if (is_version(pcr, PID_5264, RTS5264_IC_VER_B)) 686 rtsx_pci_write_phy_register(pcr, 0x00, 0x5B79); 687 688 return 0; 689} 690 691static void rts5264_enable_aspm(struct rtsx_pcr *pcr, bool enable) 692{ 693 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 694 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 695 696 if (pcr->aspm_enabled == enable) 697 return; 698 699 val |= (pcr->aspm_en & 0x02); 700 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 701 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 702 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); 703 pcr->aspm_enabled = enable; 704} 705 706static void rts5264_disable_aspm(struct rtsx_pcr *pcr, bool enable) 707{ 708 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 709 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 710 711 if (pcr->aspm_enabled == enable) 712 return; 713 714 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 715 PCI_EXP_LNKCTL_ASPMC, 0); 716 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 717 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 718 udelay(10); 719 pcr->aspm_enabled = enable; 720} 721 722static void rts5264_set_aspm(struct rtsx_pcr *pcr, bool enable) 723{ 724 if (enable) 725 rts5264_enable_aspm(pcr, true); 726 else 727 rts5264_disable_aspm(pcr, false); 728} 729 730static void rts5264_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 731{ 732 struct rtsx_cr_option *option = &(pcr->option); 733 734 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); 735 int card_exist = (interrupt & SD_EXIST); 736 int aspm_L1_1, aspm_L1_2; 737 u8 val = 0; 738 739 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 740 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 741 742 if (active) { 743 /* Run, latency: 60us */ 744 if (aspm_L1_1) 745 val = option->ltr_l1off_snooze_sspwrgate; 746 } else { 747 /* L1off, latency: 300us */ 748 if (aspm_L1_2) 749 val = option->ltr_l1off_sspwrgate; 750 } 751 752 if (aspm_L1_1 || aspm_L1_2) { 753 if (rtsx_check_dev_flag(pcr, 754 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) { 755 if (card_exist) 756 val &= ~L1OFF_MBIAS2_EN_5250; 757 else 758 val |= L1OFF_MBIAS2_EN_5250; 759 } 760 } 761 rtsx_set_l1off_sub(pcr, val); 762} 763 764static const struct pcr_ops rts5264_pcr_ops = { 765 .turn_on_led = rts5264_turn_on_led, 766 .turn_off_led = rts5264_turn_off_led, 767 .extra_init_hw = rts5264_extra_init_hw, 768 .optimize_phy = rts5264_optimize_phy, 769 .enable_auto_blink = rts5264_enable_auto_blink, 770 .disable_auto_blink = rts5264_disable_auto_blink, 771 .card_power_on = rts5264_card_power_on, 772 .card_power_off = rts5264_card_power_off, 773 .switch_output_voltage = rts5264_switch_output_voltage, 774 .force_power_down = rts5264_force_power_down, 775 .stop_cmd = rts5264_stop_cmd, 776 .set_aspm = rts5264_set_aspm, 777 .set_l1off_cfg_sub_d0 = rts5264_set_l1off_cfg_sub_d0, 778 .enable_ocp = rts5264_enable_ocp, 779 .disable_ocp = rts5264_disable_ocp, 780 .init_ocp = rts5264_init_ocp, 781 .process_ocp = rts5264_process_ocp, 782 .clear_ocpstat = rts5264_clear_ocpstat, 783}; 784 785static inline u8 double_ssc_depth(u8 depth) 786{ 787 return ((depth > 1) ? (depth - 1) : depth); 788} 789 790int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 791 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) 792{ 793 int err, clk; 794 u16 n; 795 u8 clk_divider, mcu_cnt, div; 796 static const u8 depth[] = { 797 [RTSX_SSC_DEPTH_4M] = RTS5264_SSC_DEPTH_4M, 798 [RTSX_SSC_DEPTH_2M] = RTS5264_SSC_DEPTH_2M, 799 [RTSX_SSC_DEPTH_1M] = RTS5264_SSC_DEPTH_1M, 800 [RTSX_SSC_DEPTH_500K] = RTS5264_SSC_DEPTH_512K, 801 }; 802 803 if (initial_mode) { 804 /* We use 250k(around) here, in initial stage */ 805 clk_divider = SD_CLK_DIVIDE_128; 806 card_clock = 30000000; 807 } else { 808 clk_divider = SD_CLK_DIVIDE_0; 809 } 810 err = rtsx_pci_write_register(pcr, SD_CFG1, 811 SD_CLK_DIVIDE_MASK, clk_divider); 812 if (err < 0) 813 return err; 814 815 card_clock /= 1000000; 816 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); 817 818 clk = card_clock; 819 if (!initial_mode && double_clk) 820 clk = card_clock * 2; 821 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", 822 clk, pcr->cur_clock); 823 824 if (clk == pcr->cur_clock) 825 return 0; 826 827 if (pcr->ops->conv_clk_and_div_n) 828 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); 829 else 830 n = clk - 4; 831 if ((clk <= 4) || (n > 396)) 832 return -EINVAL; 833 834 mcu_cnt = 125/clk + 3; 835 if (mcu_cnt > 15) 836 mcu_cnt = 15; 837 838 div = CLK_DIV_1; 839 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { 840 if (pcr->ops->conv_clk_and_div_n) { 841 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, 842 DIV_N_TO_CLK) * 2; 843 n = pcr->ops->conv_clk_and_div_n(dbl_clk, 844 CLK_TO_DIV_N); 845 } else { 846 n = (n + 4) * 2 - 4; 847 } 848 div++; 849 } 850 851 n = (n / 2) - 1; 852 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); 853 854 ssc_depth = depth[ssc_depth]; 855 if (double_clk) 856 ssc_depth = double_ssc_depth(ssc_depth); 857 858 if (ssc_depth) { 859 if (div == CLK_DIV_2) { 860 if (ssc_depth > 1) 861 ssc_depth -= 1; 862 else 863 ssc_depth = RTS5264_SSC_DEPTH_8M; 864 } else if (div == CLK_DIV_4) { 865 if (ssc_depth > 2) 866 ssc_depth -= 2; 867 else 868 ssc_depth = RTS5264_SSC_DEPTH_8M; 869 } else if (div == CLK_DIV_8) { 870 if (ssc_depth > 3) 871 ssc_depth -= 3; 872 else 873 ssc_depth = RTS5264_SSC_DEPTH_8M; 874 } 875 } else { 876 ssc_depth = 0; 877 } 878 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); 879 880 rtsx_pci_init_cmd(pcr); 881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 882 CHANGE_CLK, CHANGE_CLK); 883 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 884 0xFF, (div << 4) | mcu_cnt); 885 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 886 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 887 SSC_DEPTH_MASK, ssc_depth); 888 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 889 890 if (is_version(pcr, PID_5264, RTS5264_IC_VER_A)) { 891 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 892 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_CARD_CLK_SRC2, 893 RTS5264_REG_BIG_KVCO_A, 0); 894 } else { 895 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 896 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_SYS_DUMMY_1, 897 RTS5264_REG_BIG_KVCO, 0); 898 } 899 900 if (vpclk) { 901 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 902 PHASE_NOT_RESET, 0); 903 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 904 PHASE_NOT_RESET, 0); 905 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 906 PHASE_NOT_RESET, PHASE_NOT_RESET); 907 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 908 PHASE_NOT_RESET, PHASE_NOT_RESET); 909 } 910 911 err = rtsx_pci_send_cmd(pcr, 2000); 912 if (err < 0) 913 return err; 914 915 /* Wait SSC clock stable */ 916 udelay(SSC_CLOCK_STABLE_WAIT); 917 err = rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); 918 if (err < 0) 919 return err; 920 921 pcr->cur_clock = clk; 922 return 0; 923} 924 925void rts5264_init_params(struct rtsx_pcr *pcr) 926{ 927 struct rtsx_cr_option *option = &pcr->option; 928 struct rtsx_hw_param *hw_param = &pcr->hw_param; 929 u8 val; 930 931 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 932 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; 933 rtsx_pci_read_register(pcr, RTS5264_FW_STATUS, &val); 934 if (!(val & RTS5264_EXPRESS_LINK_FAIL_MASK)) 935 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS; 936 pcr->num_slots = 1; 937 pcr->ops = &rts5264_pcr_ops; 938 939 pcr->flags = 0; 940 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 941 pcr->sd30_drive_sel_1v8 = 0x00; 942 pcr->sd30_drive_sel_3v3 = 0x00; 943 pcr->aspm_en = ASPM_L1_EN; 944 pcr->aspm_mode = ASPM_MODE_REG; 945 pcr->tx_initial_phase = SET_CLOCK_PHASE(24, 24, 11); 946 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 947 948 pcr->ic_version = rts5264_get_ic_version(pcr); 949 pcr->sd_pull_ctl_enable_tbl = rts5264_sd_pull_ctl_enable_tbl; 950 pcr->sd_pull_ctl_disable_tbl = rts5264_sd_pull_ctl_disable_tbl; 951 952 pcr->reg_pm_ctrl3 = RTS5264_AUTOLOAD_CFG3; 953 954 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 955 | LTR_L1SS_PWR_GATE_EN); 956 option->ltr_en = true; 957 958 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 959 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 960 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 961 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 962 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 963 option->ltr_l1off_sspwrgate = 0x7F; 964 option->ltr_l1off_snooze_sspwrgate = 0x78; 965 966 option->ocp_en = 1; 967 hw_param->interrupt_en |= (SD_OC_INT_EN | SD_OVP_INT_EN); 968 hw_param->ocp_glitch = SD_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U; 969 option->sd_800mA_ocp_thd = RTS5264_LDO1_OCP_THD_1150; 970 option->sd_cd_reverse_en = 0; 971 option->sd_wp_reverse_en = 0; 972}
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