twl6030-irq.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * twl6030-irq.c - TWL6030 irq support
  4 *
  5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
  6 *
  7 * Modifications to defer interrupt handling to a kernel thread:
  8 * Copyright (C) 2006 MontaVista Software, Inc.
  9 *
 10 * Based on tlv320aic23.c:
 11 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
 12 *
 13 * Code cleanup and modifications to IRQ handler.
 14 * by syed khasim <x0khasim@ti.com>
 15 *
 16 * TWL6030 specific code and IRQ handling changes by
 17 * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
 18 * Balaji T K <balajitk@ti.com>
 19 */
 20
 21#include <linux/export.h>
 22#include <linux/interrupt.h>
 23#include <linux/irq.h>
 24#include <linux/kthread.h>
 25#include <linux/mfd/twl.h>
 26#include <linux/platform_device.h>
 27#include <linux/suspend.h>
 28#include <linux/of.h>
 29#include <linux/irqdomain.h>
 30#include <linux/of_device.h>
 31
 32#include "twl-core.h"
 33
 34/*
 35 * TWL6030 (unlike its predecessors, which had two level interrupt handling)
 36 * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
 37 * It exposes status bits saying who has raised an interrupt. There are
 38 * three mask registers that corresponds to these status registers, that
 39 * enables/disables these interrupts.
 40 *
 41 * We set up IRQs starting at a platform-specified base. An interrupt map table,
 42 * specifies mapping between interrupt number and the associated module.
 43 */
 44#define TWL6030_NR_IRQS    20
 45
 46static int twl6030_interrupt_mapping[24] = {
 47	PWR_INTR_OFFSET,	/* Bit 0	PWRON			*/
 48	PWR_INTR_OFFSET,	/* Bit 1	RPWRON			*/
 49	PWR_INTR_OFFSET,	/* Bit 2	BAT_VLOW		*/
 50	RTC_INTR_OFFSET,	/* Bit 3	RTC_ALARM		*/
 51	RTC_INTR_OFFSET,	/* Bit 4	RTC_PERIOD		*/
 52	HOTDIE_INTR_OFFSET,	/* Bit 5	HOT_DIE			*/
 53	SMPSLDO_INTR_OFFSET,	/* Bit 6	VXXX_SHORT		*/
 54	SMPSLDO_INTR_OFFSET,	/* Bit 7	VMMC_SHORT		*/
 55
 56	SMPSLDO_INTR_OFFSET,	/* Bit 8	VUSIM_SHORT		*/
 57	BATDETECT_INTR_OFFSET,	/* Bit 9	BAT			*/
 58	SIMDETECT_INTR_OFFSET,	/* Bit 10	SIM			*/
 59	MMCDETECT_INTR_OFFSET,	/* Bit 11	MMC			*/
 60	RSV_INTR_OFFSET,	/* Bit 12	Reserved		*/
 61	MADC_INTR_OFFSET,	/* Bit 13	GPADC_RT_EOC		*/
 62	MADC_INTR_OFFSET,	/* Bit 14	GPADC_SW_EOC		*/
 63	GASGAUGE_INTR_OFFSET,	/* Bit 15	CC_AUTOCAL		*/
 64
 65	USBOTG_INTR_OFFSET,	/* Bit 16	ID_WKUP			*/
 66	USBOTG_INTR_OFFSET,	/* Bit 17	VBUS_WKUP		*/
 67	USBOTG_INTR_OFFSET,	/* Bit 18	ID			*/
 68	USB_PRES_INTR_OFFSET,	/* Bit 19	VBUS			*/
 69	CHARGER_INTR_OFFSET,	/* Bit 20	CHRG_CTRL		*/
 70	CHARGERFAULT_INTR_OFFSET,	/* Bit 21	EXT_CHRG	*/
 71	CHARGERFAULT_INTR_OFFSET,	/* Bit 22	INT_CHRG	*/
 72	RSV_INTR_OFFSET,	/* Bit 23	Reserved		*/
 73};
 74
 75static int twl6032_interrupt_mapping[24] = {
 76	PWR_INTR_OFFSET,	/* Bit 0	PWRON			*/
 77	PWR_INTR_OFFSET,	/* Bit 1	RPWRON			*/
 78	PWR_INTR_OFFSET,	/* Bit 2	SYS_VLOW		*/
 79	RTC_INTR_OFFSET,	/* Bit 3	RTC_ALARM		*/
 80	RTC_INTR_OFFSET,	/* Bit 4	RTC_PERIOD		*/
 81	HOTDIE_INTR_OFFSET,	/* Bit 5	HOT_DIE			*/
 82	SMPSLDO_INTR_OFFSET,	/* Bit 6	VXXX_SHORT		*/
 83	PWR_INTR_OFFSET,	/* Bit 7	SPDURATION		*/
 84
 85	PWR_INTR_OFFSET,	/* Bit 8	WATCHDOG		*/
 86	BATDETECT_INTR_OFFSET,	/* Bit 9	BAT			*/
 87	SIMDETECT_INTR_OFFSET,	/* Bit 10	SIM			*/
 88	MMCDETECT_INTR_OFFSET,	/* Bit 11	MMC			*/
 89	MADC_INTR_OFFSET,	/* Bit 12	GPADC_RT_EOC		*/
 90	MADC_INTR_OFFSET,	/* Bit 13	GPADC_SW_EOC		*/
 91	GASGAUGE_INTR_OFFSET,	/* Bit 14	CC_EOC			*/
 92	GASGAUGE_INTR_OFFSET,	/* Bit 15	CC_AUTOCAL		*/
 93
 94	USBOTG_INTR_OFFSET,	/* Bit 16	ID_WKUP			*/
 95	USBOTG_INTR_OFFSET,	/* Bit 17	VBUS_WKUP		*/
 96	USBOTG_INTR_OFFSET,	/* Bit 18	ID			*/
 97	USB_PRES_INTR_OFFSET,	/* Bit 19	VBUS			*/
 98	CHARGER_INTR_OFFSET,	/* Bit 20	CHRG_CTRL		*/
 99	CHARGERFAULT_INTR_OFFSET,	/* Bit 21	EXT_CHRG	*/
100	CHARGERFAULT_INTR_OFFSET,	/* Bit 22	INT_CHRG	*/
101	RSV_INTR_OFFSET,	/* Bit 23	Reserved		*/
102};
103
104/*----------------------------------------------------------------------*/
105
106struct twl6030_irq {
107	unsigned int		irq_base;
108	int			twl_irq;
109	bool			irq_wake_enabled;
110	atomic_t		wakeirqs;
111	struct notifier_block	pm_nb;
112	struct irq_chip		irq_chip;
113	struct irq_domain	*irq_domain;
114	const int		*irq_mapping_tbl;
115};
116
117static struct twl6030_irq *twl6030_irq;
118
119static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
120				   unsigned long pm_event, void *unused)
121{
122	int chained_wakeups;
123	struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
124						  pm_nb);
125
126	switch (pm_event) {
127	case PM_SUSPEND_PREPARE:
128		chained_wakeups = atomic_read(&pdata->wakeirqs);
129
130		if (chained_wakeups && !pdata->irq_wake_enabled) {
131			if (enable_irq_wake(pdata->twl_irq))
132				pr_err("twl6030 IRQ wake enable failed\n");
133			else
134				pdata->irq_wake_enabled = true;
135		} else if (!chained_wakeups && pdata->irq_wake_enabled) {
136			disable_irq_wake(pdata->twl_irq);
137			pdata->irq_wake_enabled = false;
138		}
139
140		disable_irq(pdata->twl_irq);
141		break;
142
143	case PM_POST_SUSPEND:
144		enable_irq(pdata->twl_irq);
145		break;
146
147	default:
148		break;
149	}
150
151	return NOTIFY_DONE;
152}
153
154/*
155* Threaded irq handler for the twl6030 interrupt.
156* We query the interrupt controller in the twl6030 to determine
157* which module is generating the interrupt request and call
158* handle_nested_irq for that module.
159*/
160static irqreturn_t twl6030_irq_thread(int irq, void *data)
161{
162	int i, ret;
163	union {
164		u8 bytes[4];
165		__le32 int_sts;
166	} sts;
167	u32 int_sts; /* sts.int_sts converted to CPU endianness */
168	struct twl6030_irq *pdata = data;
169
170	/* read INT_STS_A, B and C in one shot using a burst read */
171	ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
172	if (ret) {
173		pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
174		return IRQ_HANDLED;
175	}
176
177	sts.bytes[3] = 0; /* Only 24 bits are valid*/
178
179	/*
180	 * Since VBUS status bit is not reliable for VBUS disconnect
181	 * use CHARGER VBUS detection status bit instead.
182	 */
183	if (sts.bytes[2] & 0x10)
184		sts.bytes[2] |= 0x08;
185
186	int_sts = le32_to_cpu(sts.int_sts);
187	for (i = 0; int_sts; int_sts >>= 1, i++)
188		if (int_sts & 0x1) {
189			int module_irq =
190				irq_find_mapping(pdata->irq_domain,
191						 pdata->irq_mapping_tbl[i]);
192			if (module_irq)
193				handle_nested_irq(module_irq);
194			else
195				pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
196				       i);
197			pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
198				 i, module_irq);
199		}
200
201	/*
202	 * NOTE:
203	 * Simulation confirms that documentation is wrong w.r.t the
204	 * interrupt status clear operation. A single *byte* write to
205	 * any one of STS_A to STS_C register results in all three
206	 * STS registers being reset. Since it does not matter which
207	 * value is written, all three registers are cleared on a
208	 * single byte write, so we just use 0x0 to clear.
209	 */
210	ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
211	if (ret)
212		pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
213
214	return IRQ_HANDLED;
215}
216
217/*----------------------------------------------------------------------*/
218
219static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
220{
221	struct twl6030_irq *pdata = irq_data_get_irq_chip_data(d);
222
223	if (on)
224		atomic_inc(&pdata->wakeirqs);
225	else
226		atomic_dec(&pdata->wakeirqs);
227
228	return 0;
229}
230
231int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
232{
233	int ret;
234	u8 unmask_value;
235
236	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
237			REG_INT_STS_A + offset);
238	unmask_value &= (~(bit_mask));
239	ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
240			REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
241	return ret;
242}
243EXPORT_SYMBOL(twl6030_interrupt_unmask);
244
245int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
246{
247	int ret;
248	u8 mask_value;
249
250	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
251			REG_INT_STS_A + offset);
252	mask_value |= (bit_mask);
253	ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
254			REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
255	return ret;
256}
257EXPORT_SYMBOL(twl6030_interrupt_mask);
258
259static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
260			      irq_hw_number_t hwirq)
261{
262	struct twl6030_irq *pdata = d->host_data;
263
264	irq_set_chip_data(virq, pdata);
265	irq_set_chip_and_handler(virq,  &pdata->irq_chip, handle_simple_irq);
266	irq_set_nested_thread(virq, true);
267	irq_set_parent(virq, pdata->twl_irq);
268	irq_set_noprobe(virq);
269
270	return 0;
271}
272
273static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
274{
275	irq_set_chip_and_handler(virq, NULL, NULL);
276	irq_set_chip_data(virq, NULL);
277}
278
279static const struct irq_domain_ops twl6030_irq_domain_ops = {
280	.map	= twl6030_irq_map,
281	.unmap	= twl6030_irq_unmap,
282	.xlate	= irq_domain_xlate_onetwocell,
283};
284
285static const struct of_device_id twl6030_of_match[] __maybe_unused = {
286	{.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
287	{.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
288	{ },
289};
290
291int twl6030_init_irq(struct device *dev, int irq_num)
292{
293	int			nr_irqs;
294	int			status;
295	u8			mask[3];
296	const struct of_device_id *of_id;
297
298	of_id = of_match_device(twl6030_of_match, dev);
299	if (!of_id || !of_id->data) {
300		dev_err(dev, "Unknown TWL device model\n");
301		return -EINVAL;
302	}
303
304	nr_irqs = TWL6030_NR_IRQS;
305
306	twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
307	if (!twl6030_irq)
308		return -ENOMEM;
309
310	mask[0] = 0xFF;
311	mask[1] = 0xFF;
312	mask[2] = 0xFF;
313
314	/* mask all int lines */
315	status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
316	/* mask all int sts */
317	status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
318	/* clear INT_STS_A,B,C */
319	status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
320
321	if (status < 0) {
322		dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
323		return status;
324	}
325
326	/*
327	 * install an irq handler for each of the modules;
328	 * clone dummy irq_chip since PIH can't *do* anything
329	 */
330	twl6030_irq->irq_chip = dummy_irq_chip;
331	twl6030_irq->irq_chip.name = "twl6030";
332	twl6030_irq->irq_chip.irq_set_type = NULL;
333	twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
334
335	twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
336	atomic_set(&twl6030_irq->wakeirqs, 0);
337	twl6030_irq->irq_mapping_tbl = of_id->data;
338
339	twl6030_irq->irq_domain = irq_domain_create_linear(dev_fwnode(dev), nr_irqs,
340							   &twl6030_irq_domain_ops, twl6030_irq);
341	if (!twl6030_irq->irq_domain) {
342		dev_err(dev, "Can't add irq_domain\n");
343		return -ENOMEM;
344	}
345
346	dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
347
348	/* install an irq handler to demultiplex the TWL6030 interrupt */
349	status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
350				      IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
351	if (status < 0) {
352		dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
353		goto fail_irq;
354	}
355
356	twl6030_irq->twl_irq = irq_num;
357	register_pm_notifier(&twl6030_irq->pm_nb);
358	return 0;
359
360fail_irq:
361	irq_domain_remove(twl6030_irq->irq_domain);
362	return status;
363}
364
365void twl6030_exit_irq(void)
366{
367	if (twl6030_irq && twl6030_irq->twl_irq) {
368		unregister_pm_notifier(&twl6030_irq->pm_nb);
369		free_irq(twl6030_irq->twl_irq, NULL);
370		/*
371		 * TODO: IRQ domain and allocated nested IRQ descriptors
372		 * should be freed somehow here. Now It can't be done, because
373		 * child devices will not be deleted during removing of
374		 * TWL Core driver and they will still contain allocated
375		 * virt IRQs in their Resources tables.
376		 * The same prevents us from using devm_request_threaded_irq()
377		 * in this module.
378		 */
379	}
380}
381