FILE
tps6594-core.c
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linux-6.19.14/drivers/mfd/tps6594-core.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Core functions for following TI PMICs: 4 * - LP8764 5 * - TPS65224 6 * - TPS652G1 7 * - TPS6593 8 * - TPS6594 9 * 10 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ 11 */ 12 13#include <linux/bitfield.h> 14#include <linux/completion.h> 15#include <linux/delay.h> 16#include <linux/interrupt.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/reboot.h> 20 21#include <linux/mfd/core.h> 22#include <linux/mfd/tps6594.h> 23 24#define TPS6594_CRC_SYNC_TIMEOUT_MS 150 25#define TPS65224_EN_SEL_PB 1 26#define TPS65224_GPIO3_SEL_PB 3 27 28/* Completion to synchronize CRC feature enabling on all PMICs */ 29static DECLARE_COMPLETION(tps6594_crc_comp); 30 31static const struct resource tps6594_regulator_resources[] = { 32 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_OV, TPS6594_IRQ_NAME_BUCK1_OV), 33 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_UV, TPS6594_IRQ_NAME_BUCK1_UV), 34 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_SC, TPS6594_IRQ_NAME_BUCK1_SC), 35 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_ILIM, TPS6594_IRQ_NAME_BUCK1_ILIM), 36 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_OV, TPS6594_IRQ_NAME_BUCK2_OV), 37 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_UV, TPS6594_IRQ_NAME_BUCK2_UV), 38 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_SC, TPS6594_IRQ_NAME_BUCK2_SC), 39 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_ILIM, TPS6594_IRQ_NAME_BUCK2_ILIM), 40 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_OV, TPS6594_IRQ_NAME_BUCK3_OV), 41 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_UV, TPS6594_IRQ_NAME_BUCK3_UV), 42 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_SC, TPS6594_IRQ_NAME_BUCK3_SC), 43 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_ILIM, TPS6594_IRQ_NAME_BUCK3_ILIM), 44 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_OV, TPS6594_IRQ_NAME_BUCK4_OV), 45 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_UV, TPS6594_IRQ_NAME_BUCK4_UV), 46 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_SC, TPS6594_IRQ_NAME_BUCK4_SC), 47 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_ILIM, TPS6594_IRQ_NAME_BUCK4_ILIM), 48 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_OV, TPS6594_IRQ_NAME_BUCK5_OV), 49 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_UV, TPS6594_IRQ_NAME_BUCK5_UV), 50 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_SC, TPS6594_IRQ_NAME_BUCK5_SC), 51 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_ILIM, TPS6594_IRQ_NAME_BUCK5_ILIM), 52 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_OV, TPS6594_IRQ_NAME_LDO1_OV), 53 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_UV, TPS6594_IRQ_NAME_LDO1_UV), 54 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_SC, TPS6594_IRQ_NAME_LDO1_SC), 55 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_ILIM, TPS6594_IRQ_NAME_LDO1_ILIM), 56 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_OV, TPS6594_IRQ_NAME_LDO2_OV), 57 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_UV, TPS6594_IRQ_NAME_LDO2_UV), 58 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_SC, TPS6594_IRQ_NAME_LDO2_SC), 59 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_ILIM, TPS6594_IRQ_NAME_LDO2_ILIM), 60 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_OV, TPS6594_IRQ_NAME_LDO3_OV), 61 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_UV, TPS6594_IRQ_NAME_LDO3_UV), 62 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_SC, TPS6594_IRQ_NAME_LDO3_SC), 63 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_ILIM, TPS6594_IRQ_NAME_LDO3_ILIM), 64 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_OV, TPS6594_IRQ_NAME_LDO4_OV), 65 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_UV, TPS6594_IRQ_NAME_LDO4_UV), 66 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_SC, TPS6594_IRQ_NAME_LDO4_SC), 67 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_ILIM, TPS6594_IRQ_NAME_LDO4_ILIM), 68 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OV, TPS6594_IRQ_NAME_VCCA_OV), 69 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_UV, TPS6594_IRQ_NAME_VCCA_UV), 70 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_OV, TPS6594_IRQ_NAME_VMON1_OV), 71 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_UV, TPS6594_IRQ_NAME_VMON1_UV), 72 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_RV, TPS6594_IRQ_NAME_VMON1_RV), 73 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_OV, TPS6594_IRQ_NAME_VMON2_OV), 74 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_UV, TPS6594_IRQ_NAME_VMON2_UV), 75 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_RV, TPS6594_IRQ_NAME_VMON2_RV), 76}; 77 78static const struct resource tps6594_pinctrl_resources[] = { 79 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO9, TPS6594_IRQ_NAME_GPIO9), 80 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO10, TPS6594_IRQ_NAME_GPIO10), 81 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO11, TPS6594_IRQ_NAME_GPIO11), 82 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO1, TPS6594_IRQ_NAME_GPIO1), 83 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO2, TPS6594_IRQ_NAME_GPIO2), 84 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO3, TPS6594_IRQ_NAME_GPIO3), 85 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO4, TPS6594_IRQ_NAME_GPIO4), 86 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO5, TPS6594_IRQ_NAME_GPIO5), 87 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO6, TPS6594_IRQ_NAME_GPIO6), 88 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO7, TPS6594_IRQ_NAME_GPIO7), 89 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO8, TPS6594_IRQ_NAME_GPIO8), 90}; 91 92static const struct resource tps6594_pfsm_resources[] = { 93 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_START, TPS6594_IRQ_NAME_NPWRON_START), 94 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ENABLE, TPS6594_IRQ_NAME_ENABLE), 95 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_FSD, TPS6594_IRQ_NAME_FSD), 96 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOFT_REBOOT, TPS6594_IRQ_NAME_SOFT_REBOOT), 97 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_PASS, TPS6594_IRQ_NAME_BIST_PASS), 98 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EXT_CLK, TPS6594_IRQ_NAME_EXT_CLK), 99 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TWARN, TPS6594_IRQ_NAME_TWARN), 100 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_ORD, TPS6594_IRQ_NAME_TSD_ORD), 101 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_FAIL, TPS6594_IRQ_NAME_BIST_FAIL), 102 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_REG_CRC_ERR, TPS6594_IRQ_NAME_REG_CRC_ERR), 103 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_RECOV_CNT, TPS6594_IRQ_NAME_RECOV_CNT), 104 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SPMI_ERR, TPS6594_IRQ_NAME_SPMI_ERR), 105 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_LONG, TPS6594_IRQ_NAME_NPWRON_LONG), 106 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NINT_READBACK, TPS6594_IRQ_NAME_NINT_READBACK), 107 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_READBACK, TPS6594_IRQ_NAME_NRSTOUT_READBACK), 108 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_IMM, TPS6594_IRQ_NAME_TSD_IMM), 109 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OVP, TPS6594_IRQ_NAME_VCCA_OVP), 110 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_PFSM_ERR, TPS6594_IRQ_NAME_PFSM_ERR), 111 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_IMM_SHUTDOWN, TPS6594_IRQ_NAME_IMM_SHUTDOWN), 112 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ORD_SHUTDOWN, TPS6594_IRQ_NAME_ORD_SHUTDOWN), 113 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_MCU_PWR_ERR, TPS6594_IRQ_NAME_MCU_PWR_ERR), 114 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOC_PWR_ERR, TPS6594_IRQ_NAME_SOC_PWR_ERR), 115 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_FRM_ERR, TPS6594_IRQ_NAME_COMM_FRM_ERR), 116 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_CRC_ERR, TPS6594_IRQ_NAME_COMM_CRC_ERR), 117 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_ADR_ERR, TPS6594_IRQ_NAME_COMM_ADR_ERR), 118 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EN_DRV_READBACK, TPS6594_IRQ_NAME_EN_DRV_READBACK), 119 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_SOC_READBACK, 120 TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK), 121}; 122 123static const struct resource tps6594_esm_resources[] = { 124 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_PIN, TPS6594_IRQ_NAME_ESM_SOC_PIN), 125 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_FAIL, TPS6594_IRQ_NAME_ESM_SOC_FAIL), 126 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_RST, TPS6594_IRQ_NAME_ESM_SOC_RST), 127}; 128 129static const struct resource tps6594_rtc_resources[] = { 130 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TIMER, TPS6594_IRQ_NAME_TIMER), 131 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ALARM, TPS6594_IRQ_NAME_ALARM), 132 DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_POWER_UP, TPS6594_IRQ_NAME_POWERUP), 133}; 134 135static const struct resource tps6594_pwrbutton_resources[] = { 136 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_FALL, TPS65224_IRQ_NAME_PB_FALL), 137 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_RISE, TPS65224_IRQ_NAME_PB_RISE), 138 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_SHORT, TPS65224_IRQ_NAME_PB_SHORT), 139}; 140 141static const struct mfd_cell tps6594_common_cells[] = { 142 MFD_CELL_RES("tps6594-regulator", tps6594_regulator_resources), 143 MFD_CELL_RES("tps6594-pinctrl", tps6594_pinctrl_resources), 144 MFD_CELL_RES("tps6594-pfsm", tps6594_pfsm_resources), 145 MFD_CELL_RES("tps6594-esm", tps6594_esm_resources), 146}; 147 148static const struct mfd_cell tps6594_rtc_cells[] = { 149 MFD_CELL_RES("tps6594-rtc", tps6594_rtc_resources), 150}; 151 152static const struct regmap_irq tps6594_irqs[] = { 153 /* INT_BUCK1_2 register */ 154 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_OV, 0, TPS6594_BIT_BUCKX_OV_INT(0)), 155 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_UV, 0, TPS6594_BIT_BUCKX_UV_INT(0)), 156 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_SC, 0, TPS6594_BIT_BUCKX_SC_INT(0)), 157 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(0)), 158 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_OV, 0, TPS6594_BIT_BUCKX_OV_INT(1)), 159 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_UV, 0, TPS6594_BIT_BUCKX_UV_INT(1)), 160 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_SC, 0, TPS6594_BIT_BUCKX_SC_INT(1)), 161 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(1)), 162 163 /* INT_BUCK3_4 register */ 164 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_OV, 1, TPS6594_BIT_BUCKX_OV_INT(2)), 165 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_UV, 1, TPS6594_BIT_BUCKX_UV_INT(2)), 166 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_SC, 1, TPS6594_BIT_BUCKX_SC_INT(2)), 167 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(2)), 168 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_OV, 1, TPS6594_BIT_BUCKX_OV_INT(3)), 169 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_UV, 1, TPS6594_BIT_BUCKX_UV_INT(3)), 170 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_SC, 1, TPS6594_BIT_BUCKX_SC_INT(3)), 171 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(3)), 172 173 /* INT_BUCK5 register */ 174 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_OV, 2, TPS6594_BIT_BUCKX_OV_INT(4)), 175 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_UV, 2, TPS6594_BIT_BUCKX_UV_INT(4)), 176 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_SC, 2, TPS6594_BIT_BUCKX_SC_INT(4)), 177 REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_ILIM, 2, TPS6594_BIT_BUCKX_ILIM_INT(4)), 178 179 /* INT_LDO1_2 register */ 180 REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_OV, 3, TPS6594_BIT_LDOX_OV_INT(0)), 181 REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_UV, 3, TPS6594_BIT_LDOX_UV_INT(0)), 182 REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_SC, 3, TPS6594_BIT_LDOX_SC_INT(0)), 183 REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(0)), 184 REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_OV, 3, TPS6594_BIT_LDOX_OV_INT(1)), 185 REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_UV, 3, TPS6594_BIT_LDOX_UV_INT(1)), 186 REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_SC, 3, TPS6594_BIT_LDOX_SC_INT(1)), 187 REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(1)), 188 189 /* INT_LDO3_4 register */ 190 REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_OV, 4, TPS6594_BIT_LDOX_OV_INT(2)), 191 REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_UV, 4, TPS6594_BIT_LDOX_UV_INT(2)), 192 REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_SC, 4, TPS6594_BIT_LDOX_SC_INT(2)), 193 REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(2)), 194 REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_OV, 4, TPS6594_BIT_LDOX_OV_INT(3)), 195 REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_UV, 4, TPS6594_BIT_LDOX_UV_INT(3)), 196 REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_SC, 4, TPS6594_BIT_LDOX_SC_INT(3)), 197 REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(3)), 198 199 /* INT_VMON register */ 200 REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OV, 5, TPS6594_BIT_VCCA_OV_INT), 201 REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_UV, 5, TPS6594_BIT_VCCA_UV_INT), 202 REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_OV, 5, TPS6594_BIT_VMON1_OV_INT), 203 REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_UV, 5, TPS6594_BIT_VMON1_UV_INT), 204 REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_RV, 5, TPS6594_BIT_VMON1_RV_INT), 205 REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_OV, 5, TPS6594_BIT_VMON2_OV_INT), 206 REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_UV, 5, TPS6594_BIT_VMON2_UV_INT), 207 REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_RV, 5, TPS6594_BIT_VMON2_RV_INT), 208 209 /* INT_GPIO register */ 210 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO9, 6, TPS6594_BIT_GPIO9_INT), 211 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO10, 6, TPS6594_BIT_GPIO10_INT), 212 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO11, 6, TPS6594_BIT_GPIO11_INT), 213 214 /* INT_GPIO1_8 register */ 215 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO1, 7, TPS6594_BIT_GPIOX_INT(0)), 216 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO2, 7, TPS6594_BIT_GPIOX_INT(1)), 217 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO3, 7, TPS6594_BIT_GPIOX_INT(2)), 218 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO4, 7, TPS6594_BIT_GPIOX_INT(3)), 219 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO5, 7, TPS6594_BIT_GPIOX_INT(4)), 220 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO6, 7, TPS6594_BIT_GPIOX_INT(5)), 221 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO7, 7, TPS6594_BIT_GPIOX_INT(6)), 222 REGMAP_IRQ_REG(TPS6594_IRQ_GPIO8, 7, TPS6594_BIT_GPIOX_INT(7)), 223 224 /* INT_STARTUP register */ 225 REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_START, 8, TPS6594_BIT_NPWRON_START_INT), 226 REGMAP_IRQ_REG(TPS6594_IRQ_ENABLE, 8, TPS6594_BIT_ENABLE_INT), 227 REGMAP_IRQ_REG(TPS6594_IRQ_FSD, 8, TPS6594_BIT_FSD_INT), 228 REGMAP_IRQ_REG(TPS6594_IRQ_SOFT_REBOOT, 8, TPS6594_BIT_SOFT_REBOOT_INT), 229 230 /* INT_MISC register */ 231 REGMAP_IRQ_REG(TPS6594_IRQ_BIST_PASS, 9, TPS6594_BIT_BIST_PASS_INT), 232 REGMAP_IRQ_REG(TPS6594_IRQ_EXT_CLK, 9, TPS6594_BIT_EXT_CLK_INT), 233 REGMAP_IRQ_REG(TPS6594_IRQ_TWARN, 9, TPS6594_BIT_TWARN_INT), 234 235 /* INT_MODERATE_ERR register */ 236 REGMAP_IRQ_REG(TPS6594_IRQ_TSD_ORD, 10, TPS6594_BIT_TSD_ORD_INT), 237 REGMAP_IRQ_REG(TPS6594_IRQ_BIST_FAIL, 10, TPS6594_BIT_BIST_FAIL_INT), 238 REGMAP_IRQ_REG(TPS6594_IRQ_REG_CRC_ERR, 10, TPS6594_BIT_REG_CRC_ERR_INT), 239 REGMAP_IRQ_REG(TPS6594_IRQ_RECOV_CNT, 10, TPS6594_BIT_RECOV_CNT_INT), 240 REGMAP_IRQ_REG(TPS6594_IRQ_SPMI_ERR, 10, TPS6594_BIT_SPMI_ERR_INT), 241 REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_LONG, 10, TPS6594_BIT_NPWRON_LONG_INT), 242 REGMAP_IRQ_REG(TPS6594_IRQ_NINT_READBACK, 10, TPS6594_BIT_NINT_READBACK_INT), 243 REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_READBACK, 10, TPS6594_BIT_NRSTOUT_READBACK_INT), 244 245 /* INT_SEVERE_ERR register */ 246 REGMAP_IRQ_REG(TPS6594_IRQ_TSD_IMM, 11, TPS6594_BIT_TSD_IMM_INT), 247 REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OVP, 11, TPS6594_BIT_VCCA_OVP_INT), 248 REGMAP_IRQ_REG(TPS6594_IRQ_PFSM_ERR, 11, TPS6594_BIT_PFSM_ERR_INT), 249 250 /* INT_FSM_ERR register */ 251 REGMAP_IRQ_REG(TPS6594_IRQ_IMM_SHUTDOWN, 12, TPS6594_BIT_IMM_SHUTDOWN_INT), 252 REGMAP_IRQ_REG(TPS6594_IRQ_ORD_SHUTDOWN, 12, TPS6594_BIT_ORD_SHUTDOWN_INT), 253 REGMAP_IRQ_REG(TPS6594_IRQ_MCU_PWR_ERR, 12, TPS6594_BIT_MCU_PWR_ERR_INT), 254 REGMAP_IRQ_REG(TPS6594_IRQ_SOC_PWR_ERR, 12, TPS6594_BIT_SOC_PWR_ERR_INT), 255 256 /* INT_COMM_ERR register */ 257 REGMAP_IRQ_REG(TPS6594_IRQ_COMM_FRM_ERR, 13, TPS6594_BIT_COMM_FRM_ERR_INT), 258 REGMAP_IRQ_REG(TPS6594_IRQ_COMM_CRC_ERR, 13, TPS6594_BIT_COMM_CRC_ERR_INT), 259 REGMAP_IRQ_REG(TPS6594_IRQ_COMM_ADR_ERR, 13, TPS6594_BIT_COMM_ADR_ERR_INT), 260 261 /* INT_READBACK_ERR register */ 262 REGMAP_IRQ_REG(TPS6594_IRQ_EN_DRV_READBACK, 14, TPS6594_BIT_EN_DRV_READBACK_INT), 263 REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_SOC_READBACK, 14, TPS6594_BIT_NRSTOUT_SOC_READBACK_INT), 264 265 /* INT_ESM register */ 266 REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_PIN, 15, TPS6594_BIT_ESM_SOC_PIN_INT), 267 REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_FAIL, 15, TPS6594_BIT_ESM_SOC_FAIL_INT), 268 REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_RST, 15, TPS6594_BIT_ESM_SOC_RST_INT), 269 270 /* RTC_STATUS register */ 271 REGMAP_IRQ_REG(TPS6594_IRQ_TIMER, 16, TPS6594_BIT_TIMER), 272 REGMAP_IRQ_REG(TPS6594_IRQ_ALARM, 16, TPS6594_BIT_ALARM), 273 REGMAP_IRQ_REG(TPS6594_IRQ_POWER_UP, 16, TPS6594_BIT_POWER_UP), 274}; 275 276static const unsigned int tps6594_irq_reg[] = { 277 TPS6594_REG_INT_BUCK1_2, 278 TPS6594_REG_INT_BUCK3_4, 279 TPS6594_REG_INT_BUCK5, 280 TPS6594_REG_INT_LDO1_2, 281 TPS6594_REG_INT_LDO3_4, 282 TPS6594_REG_INT_VMON, 283 TPS6594_REG_INT_GPIO, 284 TPS6594_REG_INT_GPIO1_8, 285 TPS6594_REG_INT_STARTUP, 286 TPS6594_REG_INT_MISC, 287 TPS6594_REG_INT_MODERATE_ERR, 288 TPS6594_REG_INT_SEVERE_ERR, 289 TPS6594_REG_INT_FSM_ERR, 290 TPS6594_REG_INT_COMM_ERR, 291 TPS6594_REG_INT_READBACK_ERR, 292 TPS6594_REG_INT_ESM, 293 TPS6594_REG_RTC_STATUS, 294}; 295 296/* TPS65224 Resources */ 297 298static const struct resource tps65224_regulator_resources[] = { 299 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK1_UVOV, TPS65224_IRQ_NAME_BUCK1_UVOV), 300 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK2_UVOV, TPS65224_IRQ_NAME_BUCK2_UVOV), 301 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK3_UVOV, TPS65224_IRQ_NAME_BUCK3_UVOV), 302 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK4_UVOV, TPS65224_IRQ_NAME_BUCK4_UVOV), 303 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_LDO1_UVOV, TPS65224_IRQ_NAME_LDO1_UVOV), 304 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_LDO2_UVOV, TPS65224_IRQ_NAME_LDO2_UVOV), 305 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_LDO3_UVOV, TPS65224_IRQ_NAME_LDO3_UVOV), 306 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VCCA_UVOV, TPS65224_IRQ_NAME_VCCA_UVOV), 307 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VMON1_UVOV, TPS65224_IRQ_NAME_VMON1_UVOV), 308 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VMON2_UVOV, TPS65224_IRQ_NAME_VMON2_UVOV), 309}; 310 311static const struct resource tps65224_pinctrl_resources[] = { 312 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO1, TPS65224_IRQ_NAME_GPIO1), 313 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO2, TPS65224_IRQ_NAME_GPIO2), 314 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO3, TPS65224_IRQ_NAME_GPIO3), 315 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO4, TPS65224_IRQ_NAME_GPIO4), 316 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO5, TPS65224_IRQ_NAME_GPIO5), 317 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO6, TPS65224_IRQ_NAME_GPIO6), 318}; 319 320static const struct resource tps65224_pfsm_resources[] = { 321 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VSENSE, TPS65224_IRQ_NAME_VSENSE), 322 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_ENABLE, TPS65224_IRQ_NAME_ENABLE), 323 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_SHORT, TPS65224_IRQ_NAME_PB_SHORT), 324 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_FSD, TPS65224_IRQ_NAME_FSD), 325 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_SOFT_REBOOT, TPS65224_IRQ_NAME_SOFT_REBOOT), 326 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BIST_PASS, TPS65224_IRQ_NAME_BIST_PASS), 327 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_EXT_CLK, TPS65224_IRQ_NAME_EXT_CLK), 328 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_REG_UNLOCK, TPS65224_IRQ_NAME_REG_UNLOCK), 329 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_TWARN, TPS65224_IRQ_NAME_TWARN), 330 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_LONG, TPS65224_IRQ_NAME_PB_LONG), 331 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_TSD_ORD, TPS65224_IRQ_NAME_TSD_ORD), 332 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BIST_FAIL, TPS65224_IRQ_NAME_BIST_FAIL), 333 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_REG_CRC_ERR, TPS65224_IRQ_NAME_REG_CRC_ERR), 334 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_RECOV_CNT, TPS65224_IRQ_NAME_RECOV_CNT), 335 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_TSD_IMM, TPS65224_IRQ_NAME_TSD_IMM), 336 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VCCA_OVP, TPS65224_IRQ_NAME_VCCA_OVP), 337 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PFSM_ERR, TPS65224_IRQ_NAME_PFSM_ERR), 338 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BG_XMON, TPS65224_IRQ_NAME_BG_XMON), 339 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_IMM_SHUTDOWN, TPS65224_IRQ_NAME_IMM_SHUTDOWN), 340 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_ORD_SHUTDOWN, TPS65224_IRQ_NAME_ORD_SHUTDOWN), 341 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_MCU_PWR_ERR, TPS65224_IRQ_NAME_MCU_PWR_ERR), 342 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_SOC_PWR_ERR, TPS65224_IRQ_NAME_SOC_PWR_ERR), 343 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_COMM_ERR, TPS65224_IRQ_NAME_COMM_ERR), 344 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_I2C2_ERR, TPS65224_IRQ_NAME_I2C2_ERR), 345}; 346 347static const struct resource tps65224_adc_resources[] = { 348 DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_ADC_CONV_READY, TPS65224_IRQ_NAME_ADC_CONV_READY), 349}; 350 351static const struct mfd_cell tps65224_common_cells[] = { 352 MFD_CELL_RES("tps65224-adc", tps65224_adc_resources), 353 MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources), 354 MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources), 355 MFD_CELL_RES("tps6594-regulator", tps65224_regulator_resources), 356}; 357 358static const struct mfd_cell tps6594_pwrbutton_cell = { 359 .name = "tps6594-pwrbutton", 360 .resources = tps6594_pwrbutton_resources, 361 .num_resources = ARRAY_SIZE(tps6594_pwrbutton_resources), 362}; 363 364static const struct regmap_irq tps65224_irqs[] = { 365 /* INT_BUCK register */ 366 REGMAP_IRQ_REG(TPS65224_IRQ_BUCK1_UVOV, 0, TPS65224_BIT_BUCK1_UVOV_INT), 367 REGMAP_IRQ_REG(TPS65224_IRQ_BUCK2_UVOV, 0, TPS65224_BIT_BUCK2_UVOV_INT), 368 REGMAP_IRQ_REG(TPS65224_IRQ_BUCK3_UVOV, 0, TPS65224_BIT_BUCK3_UVOV_INT), 369 REGMAP_IRQ_REG(TPS65224_IRQ_BUCK4_UVOV, 0, TPS65224_BIT_BUCK4_UVOV_INT), 370 371 /* INT_VMON_LDO register */ 372 REGMAP_IRQ_REG(TPS65224_IRQ_LDO1_UVOV, 1, TPS65224_BIT_LDO1_UVOV_INT), 373 REGMAP_IRQ_REG(TPS65224_IRQ_LDO2_UVOV, 1, TPS65224_BIT_LDO2_UVOV_INT), 374 REGMAP_IRQ_REG(TPS65224_IRQ_LDO3_UVOV, 1, TPS65224_BIT_LDO3_UVOV_INT), 375 REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_UVOV, 1, TPS65224_BIT_VCCA_UVOV_INT), 376 REGMAP_IRQ_REG(TPS65224_IRQ_VMON1_UVOV, 1, TPS65224_BIT_VMON1_UVOV_INT), 377 REGMAP_IRQ_REG(TPS65224_IRQ_VMON2_UVOV, 1, TPS65224_BIT_VMON2_UVOV_INT), 378 379 /* INT_GPIO register */ 380 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO1, 2, TPS65224_BIT_GPIO1_INT), 381 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO2, 2, TPS65224_BIT_GPIO2_INT), 382 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO3, 2, TPS65224_BIT_GPIO3_INT), 383 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO4, 2, TPS65224_BIT_GPIO4_INT), 384 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO5, 2, TPS65224_BIT_GPIO5_INT), 385 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO6, 2, TPS65224_BIT_GPIO6_INT), 386 387 /* INT_STARTUP register */ 388 REGMAP_IRQ_REG(TPS65224_IRQ_VSENSE, 3, TPS65224_BIT_VSENSE_INT), 389 REGMAP_IRQ_REG(TPS65224_IRQ_ENABLE, 3, TPS6594_BIT_ENABLE_INT), 390 REGMAP_IRQ_REG(TPS65224_IRQ_PB_SHORT, 3, TPS65224_BIT_PB_SHORT_INT), 391 REGMAP_IRQ_REG(TPS65224_IRQ_FSD, 3, TPS6594_BIT_FSD_INT), 392 REGMAP_IRQ_REG(TPS65224_IRQ_SOFT_REBOOT, 3, TPS6594_BIT_SOFT_REBOOT_INT), 393 394 /* INT_MISC register */ 395 REGMAP_IRQ_REG(TPS65224_IRQ_BIST_PASS, 4, TPS6594_BIT_BIST_PASS_INT), 396 REGMAP_IRQ_REG(TPS65224_IRQ_EXT_CLK, 4, TPS6594_BIT_EXT_CLK_INT), 397 REGMAP_IRQ_REG(TPS65224_IRQ_REG_UNLOCK, 4, TPS65224_BIT_REG_UNLOCK_INT), 398 REGMAP_IRQ_REG(TPS65224_IRQ_TWARN, 4, TPS6594_BIT_TWARN_INT), 399 REGMAP_IRQ_REG(TPS65224_IRQ_PB_LONG, 4, TPS65224_BIT_PB_LONG_INT), 400 REGMAP_IRQ_REG(TPS65224_IRQ_PB_FALL, 4, TPS65224_BIT_PB_FALL_INT), 401 REGMAP_IRQ_REG(TPS65224_IRQ_PB_RISE, 4, TPS65224_BIT_PB_RISE_INT), 402 REGMAP_IRQ_REG(TPS65224_IRQ_ADC_CONV_READY, 4, TPS65224_BIT_ADC_CONV_READY_INT), 403 404 /* INT_MODERATE_ERR register */ 405 REGMAP_IRQ_REG(TPS65224_IRQ_TSD_ORD, 5, TPS6594_BIT_TSD_ORD_INT), 406 REGMAP_IRQ_REG(TPS65224_IRQ_BIST_FAIL, 5, TPS6594_BIT_BIST_FAIL_INT), 407 REGMAP_IRQ_REG(TPS65224_IRQ_REG_CRC_ERR, 5, TPS6594_BIT_REG_CRC_ERR_INT), 408 REGMAP_IRQ_REG(TPS65224_IRQ_RECOV_CNT, 5, TPS6594_BIT_RECOV_CNT_INT), 409 410 /* INT_SEVERE_ERR register */ 411 REGMAP_IRQ_REG(TPS65224_IRQ_TSD_IMM, 6, TPS6594_BIT_TSD_IMM_INT), 412 REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_OVP, 6, TPS6594_BIT_VCCA_OVP_INT), 413 REGMAP_IRQ_REG(TPS65224_IRQ_PFSM_ERR, 6, TPS6594_BIT_PFSM_ERR_INT), 414 REGMAP_IRQ_REG(TPS65224_IRQ_BG_XMON, 6, TPS65224_BIT_BG_XMON_INT), 415 416 /* INT_FSM_ERR register */ 417 REGMAP_IRQ_REG(TPS65224_IRQ_IMM_SHUTDOWN, 7, TPS6594_BIT_IMM_SHUTDOWN_INT), 418 REGMAP_IRQ_REG(TPS65224_IRQ_ORD_SHUTDOWN, 7, TPS6594_BIT_ORD_SHUTDOWN_INT), 419 REGMAP_IRQ_REG(TPS65224_IRQ_MCU_PWR_ERR, 7, TPS6594_BIT_MCU_PWR_ERR_INT), 420 REGMAP_IRQ_REG(TPS65224_IRQ_SOC_PWR_ERR, 7, TPS6594_BIT_SOC_PWR_ERR_INT), 421 REGMAP_IRQ_REG(TPS65224_IRQ_COMM_ERR, 7, TPS6594_BIT_COMM_ERR_INT), 422 REGMAP_IRQ_REG(TPS65224_IRQ_I2C2_ERR, 7, TPS65224_BIT_I2C2_ERR_INT), 423}; 424 425static const unsigned int tps65224_irq_reg[] = { 426 TPS6594_REG_INT_BUCK, 427 TPS6594_REG_INT_LDO_VMON, 428 TPS6594_REG_INT_GPIO, 429 TPS6594_REG_INT_STARTUP, 430 TPS6594_REG_INT_MISC, 431 TPS6594_REG_INT_MODERATE_ERR, 432 TPS6594_REG_INT_SEVERE_ERR, 433 TPS6594_REG_INT_FSM_ERR, 434}; 435 436/* TPS652G1 Resources */ 437 438static const struct mfd_cell tps652g1_common_cells[] = { 439 MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources), 440 MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources), 441 MFD_CELL_NAME("tps6594-regulator"), 442}; 443 444static const struct regmap_irq tps652g1_irqs[] = { 445 /* INT_GPIO register */ 446 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO1, 2, TPS65224_BIT_GPIO1_INT), 447 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO2, 2, TPS65224_BIT_GPIO2_INT), 448 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO3, 2, TPS65224_BIT_GPIO3_INT), 449 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO4, 2, TPS65224_BIT_GPIO4_INT), 450 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO5, 2, TPS65224_BIT_GPIO5_INT), 451 REGMAP_IRQ_REG(TPS65224_IRQ_GPIO6, 2, TPS65224_BIT_GPIO6_INT), 452 453 /* INT_STARTUP register */ 454 REGMAP_IRQ_REG(TPS65224_IRQ_VSENSE, 3, TPS65224_BIT_VSENSE_INT), 455 REGMAP_IRQ_REG(TPS65224_IRQ_ENABLE, 3, TPS6594_BIT_ENABLE_INT), 456 REGMAP_IRQ_REG(TPS65224_IRQ_PB_SHORT, 3, TPS65224_BIT_PB_SHORT_INT), 457 REGMAP_IRQ_REG(TPS65224_IRQ_FSD, 3, TPS6594_BIT_FSD_INT), 458 REGMAP_IRQ_REG(TPS65224_IRQ_SOFT_REBOOT, 3, TPS6594_BIT_SOFT_REBOOT_INT), 459 460 /* INT_MISC register */ 461 REGMAP_IRQ_REG(TPS65224_IRQ_BIST_PASS, 4, TPS6594_BIT_BIST_PASS_INT), 462 REGMAP_IRQ_REG(TPS65224_IRQ_EXT_CLK, 4, TPS6594_BIT_EXT_CLK_INT), 463 REGMAP_IRQ_REG(TPS65224_IRQ_REG_UNLOCK, 4, TPS65224_BIT_REG_UNLOCK_INT), 464 REGMAP_IRQ_REG(TPS65224_IRQ_TWARN, 4, TPS6594_BIT_TWARN_INT), 465 REGMAP_IRQ_REG(TPS65224_IRQ_PB_LONG, 4, TPS65224_BIT_PB_LONG_INT), 466 REGMAP_IRQ_REG(TPS65224_IRQ_PB_FALL, 4, TPS65224_BIT_PB_FALL_INT), 467 REGMAP_IRQ_REG(TPS65224_IRQ_PB_RISE, 4, TPS65224_BIT_PB_RISE_INT), 468 REGMAP_IRQ_REG(TPS65224_IRQ_ADC_CONV_READY, 4, TPS65224_BIT_ADC_CONV_READY_INT), 469 470 /* INT_MODERATE_ERR register */ 471 REGMAP_IRQ_REG(TPS65224_IRQ_TSD_ORD, 5, TPS6594_BIT_TSD_ORD_INT), 472 REGMAP_IRQ_REG(TPS65224_IRQ_BIST_FAIL, 5, TPS6594_BIT_BIST_FAIL_INT), 473 REGMAP_IRQ_REG(TPS65224_IRQ_REG_CRC_ERR, 5, TPS6594_BIT_REG_CRC_ERR_INT), 474 REGMAP_IRQ_REG(TPS65224_IRQ_RECOV_CNT, 5, TPS6594_BIT_RECOV_CNT_INT), 475 476 /* INT_SEVERE_ERR register */ 477 REGMAP_IRQ_REG(TPS65224_IRQ_TSD_IMM, 6, TPS6594_BIT_TSD_IMM_INT), 478 REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_OVP, 6, TPS6594_BIT_VCCA_OVP_INT), 479 REGMAP_IRQ_REG(TPS65224_IRQ_PFSM_ERR, 6, TPS6594_BIT_PFSM_ERR_INT), 480 REGMAP_IRQ_REG(TPS65224_IRQ_BG_XMON, 6, TPS65224_BIT_BG_XMON_INT), 481 482 /* INT_FSM_ERR register */ 483 REGMAP_IRQ_REG(TPS65224_IRQ_IMM_SHUTDOWN, 7, TPS6594_BIT_IMM_SHUTDOWN_INT), 484 REGMAP_IRQ_REG(TPS65224_IRQ_ORD_SHUTDOWN, 7, TPS6594_BIT_ORD_SHUTDOWN_INT), 485 REGMAP_IRQ_REG(TPS65224_IRQ_MCU_PWR_ERR, 7, TPS6594_BIT_MCU_PWR_ERR_INT), 486 REGMAP_IRQ_REG(TPS65224_IRQ_SOC_PWR_ERR, 7, TPS6594_BIT_SOC_PWR_ERR_INT), 487 REGMAP_IRQ_REG(TPS65224_IRQ_COMM_ERR, 7, TPS6594_BIT_COMM_ERR_INT), 488 REGMAP_IRQ_REG(TPS65224_IRQ_I2C2_ERR, 7, TPS65224_BIT_I2C2_ERR_INT), 489}; 490 491static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data, 492 unsigned int base, int index) 493{ 494 return tps6594_irq_reg[index]; 495}; 496 497static inline unsigned int tps65224_get_irq_reg(struct regmap_irq_chip_data *data, 498 unsigned int base, int index) 499{ 500 return tps65224_irq_reg[index]; 501}; 502 503static int tps6594_handle_post_irq(void *irq_drv_data) 504{ 505 struct tps6594 *tps = irq_drv_data; 506 int ret = 0; 507 unsigned int regmap_reg, mask_val; 508 509 /* 510 * When CRC is enabled, writing to a read-only bit triggers an error, 511 * and COMM_ADR_ERR_INT bit is set. Besides, bits indicating interrupts 512 * (that must be cleared) and read-only bits are sometimes grouped in 513 * the same register. 514 * Since regmap clears interrupts by doing a write per register, clearing 515 * an interrupt bit in a register containing also a read-only bit makes 516 * COMM_ADR_ERR_INT bit set. Clear immediately this bit to avoid raising 517 * a new interrupt. 518 */ 519 if (tps->use_crc) { 520 if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) { 521 regmap_reg = TPS6594_REG_INT_FSM_ERR; 522 mask_val = TPS6594_BIT_COMM_ERR_INT; 523 } else { 524 regmap_reg = TPS6594_REG_INT_COMM_ERR; 525 mask_val = TPS6594_BIT_COMM_ADR_ERR_INT; 526 } 527 528 ret = regmap_write_bits(tps->regmap, regmap_reg, mask_val, mask_val); 529 } 530 531 return ret; 532}; 533 534static struct regmap_irq_chip tps6594_irq_chip = { 535 .ack_base = TPS6594_REG_INT_BUCK1_2, 536 .ack_invert = 1, 537 .clear_ack = 1, 538 .init_ack_masked = 1, 539 .num_regs = ARRAY_SIZE(tps6594_irq_reg), 540 .irqs = tps6594_irqs, 541 .num_irqs = ARRAY_SIZE(tps6594_irqs), 542 .get_irq_reg = tps6594_get_irq_reg, 543 .handle_post_irq = tps6594_handle_post_irq, 544}; 545 546static struct regmap_irq_chip tps65224_irq_chip = { 547 .ack_base = TPS6594_REG_INT_BUCK, 548 .ack_invert = 1, 549 .clear_ack = 1, 550 .init_ack_masked = 1, 551 .num_regs = ARRAY_SIZE(tps65224_irq_reg), 552 .irqs = tps65224_irqs, 553 .num_irqs = ARRAY_SIZE(tps65224_irqs), 554 .get_irq_reg = tps65224_get_irq_reg, 555 .handle_post_irq = tps6594_handle_post_irq, 556}; 557 558static struct regmap_irq_chip tps652g1_irq_chip = { 559 .ack_base = TPS6594_REG_INT_BUCK, 560 .ack_invert = 1, 561 .clear_ack = 1, 562 .init_ack_masked = 1, 563 .num_regs = ARRAY_SIZE(tps65224_irq_reg), 564 .irqs = tps652g1_irqs, 565 .num_irqs = ARRAY_SIZE(tps652g1_irqs), 566 .get_irq_reg = tps65224_get_irq_reg, 567 .handle_post_irq = tps6594_handle_post_irq, 568}; 569 570static const struct regmap_range tps6594_volatile_ranges[] = { 571 regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_READBACK_ERR), 572 regmap_reg_range(TPS6594_REG_RTC_STATUS, TPS6594_REG_RTC_STATUS), 573}; 574 575const struct regmap_access_table tps6594_volatile_table = { 576 .yes_ranges = tps6594_volatile_ranges, 577 .n_yes_ranges = ARRAY_SIZE(tps6594_volatile_ranges), 578}; 579EXPORT_SYMBOL_GPL(tps6594_volatile_table); 580 581static const struct regmap_range tps65224_volatile_ranges[] = { 582 regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_SEVERE_ERR), 583}; 584 585const struct regmap_access_table tps65224_volatile_table = { 586 .yes_ranges = tps65224_volatile_ranges, 587 .n_yes_ranges = ARRAY_SIZE(tps65224_volatile_ranges), 588}; 589EXPORT_SYMBOL_GPL(tps65224_volatile_table); 590 591static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic) 592{ 593 int ret; 594 unsigned int regmap_reg, mask_val; 595 596 if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) { 597 regmap_reg = TPS6594_REG_CONFIG_2; 598 mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN; 599 } else { 600 regmap_reg = TPS6594_REG_SERIAL_IF_CONFIG; 601 mask_val = TPS6594_BIT_I2C1_SPI_CRC_EN; 602 } 603 604 /* 605 * Check if CRC is enabled. 606 * Once CRC is enabled, it can't be disabled until next power cycle. 607 */ 608 tps->use_crc = true; 609 ret = regmap_test_bits(tps->regmap, regmap_reg, mask_val); 610 if (ret == 0) { 611 ret = -EIO; 612 } else if (ret > 0) { 613 dev_info(tps->dev, "CRC feature enabled on %s PMIC", 614 primary_pmic ? "primary" : "secondary"); 615 ret = 0; 616 } 617 618 return ret; 619} 620 621static int tps6594_set_crc_feature(struct tps6594 *tps) 622{ 623 int ret; 624 unsigned int regmap_reg, mask_val; 625 626 if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) { 627 regmap_reg = TPS6594_REG_CONFIG_2; 628 mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN; 629 } else { 630 regmap_reg = TPS6594_REG_FSM_I2C_TRIGGERS; 631 mask_val = TPS6594_BIT_TRIGGER_I2C(2); 632 } 633 634 ret = tps6594_check_crc_mode(tps, true); 635 if (ret) { 636 /* 637 * If CRC is not already enabled, force PFSM I2C_2 trigger to enable it 638 * on primary PMIC. 639 */ 640 tps->use_crc = false; 641 ret = regmap_write_bits(tps->regmap, regmap_reg, mask_val, mask_val); 642 if (ret) 643 return ret; 644 645 /* 646 * Wait for PFSM to process trigger. 647 * The datasheet indicates 2 ms, and clock specification is +/-5%. 648 * 4 ms should provide sufficient margin. 649 */ 650 usleep_range(4000, 5000); 651 652 ret = tps6594_check_crc_mode(tps, true); 653 } 654 655 return ret; 656} 657 658static int tps6594_enable_crc(struct tps6594 *tps) 659{ 660 struct device *dev = tps->dev; 661 unsigned int is_primary; 662 unsigned long timeout = msecs_to_jiffies(TPS6594_CRC_SYNC_TIMEOUT_MS); 663 int ret; 664 665 /* 666 * CRC mode can be used with I2C or SPI protocols. 667 * If this mode is specified for primary PMIC, it will also be applied to secondary PMICs 668 * through SPMI serial interface. 669 * In this multi-PMIC synchronization scheme, the primary PMIC is the controller device 670 * on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. 671 */ 672 is_primary = of_property_read_bool(dev->of_node, "ti,primary-pmic"); 673 if (is_primary) { 674 /* Enable CRC feature on primary PMIC */ 675 ret = tps6594_set_crc_feature(tps); 676 if (ret) 677 return ret; 678 679 /* Notify secondary PMICs that CRC feature is enabled */ 680 complete_all(&tps6594_crc_comp); 681 } else { 682 /* Wait for CRC feature enabling event from primary PMIC */ 683 ret = wait_for_completion_interruptible_timeout(&tps6594_crc_comp, timeout); 684 if (ret == 0) 685 ret = -ETIMEDOUT; 686 else if (ret > 0) 687 ret = tps6594_check_crc_mode(tps, false); 688 } 689 690 return ret; 691} 692 693static int tps6594_power_off_handler(struct sys_off_data *data) 694{ 695 struct tps6594 *tps = data->cb_data; 696 int ret; 697 698 ret = regmap_update_bits(tps->regmap, TPS6594_REG_FSM_I2C_TRIGGERS, 699 TPS6594_BIT_TRIGGER_I2C(0), TPS6594_BIT_TRIGGER_I2C(0)); 700 if (ret) 701 return notifier_from_errno(ret); 702 703 return NOTIFY_DONE; 704} 705 706int tps6594_device_init(struct tps6594 *tps, bool enable_crc) 707{ 708 struct device *dev = tps->dev; 709 int ret; 710 struct regmap_irq_chip *irq_chip; 711 unsigned int pwr_on, gpio3_cfg; 712 const struct mfd_cell *cells; 713 int n_cells; 714 715 if (enable_crc) { 716 ret = tps6594_enable_crc(tps); 717 if (ret) 718 return dev_err_probe(dev, ret, "Failed to enable CRC\n"); 719 } 720 721 /* Keep PMIC in ACTIVE state */ 722 ret = regmap_set_bits(tps->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS, 723 TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B); 724 if (ret) 725 return dev_err_probe(dev, ret, "Failed to set PMIC state\n"); 726 727 if (tps->chip_id == TPS65224) { 728 irq_chip = &tps65224_irq_chip; 729 n_cells = ARRAY_SIZE(tps65224_common_cells); 730 cells = tps65224_common_cells; 731 } else if (tps->chip_id == TPS652G1) { 732 irq_chip = &tps652g1_irq_chip; 733 n_cells = ARRAY_SIZE(tps652g1_common_cells); 734 cells = tps652g1_common_cells; 735 } else { 736 irq_chip = &tps6594_irq_chip; 737 n_cells = ARRAY_SIZE(tps6594_common_cells); 738 cells = tps6594_common_cells; 739 } 740 741 irq_chip->irq_drv_data = tps; 742 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%ld-0x%02x", 743 dev->driver->name, tps->chip_id, tps->reg); 744 745 if (!irq_chip->name) 746 return -ENOMEM; 747 748 ret = devm_regmap_add_irq_chip(dev, tps->regmap, tps->irq, IRQF_SHARED | IRQF_ONESHOT, 749 0, irq_chip, &tps->irq_data); 750 if (ret) 751 return dev_err_probe(dev, ret, "Failed to add regmap IRQ\n"); 752 753 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, n_cells, NULL, 0, 754 regmap_irq_get_domain(tps->irq_data)); 755 if (ret) 756 return dev_err_probe(dev, ret, "Failed to add common child devices\n"); 757 758 /* If either the PB/EN/VSENSE or GPIO3 is configured as PB, register a driver for it */ 759 if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) { 760 ret = regmap_read(tps->regmap, TPS6594_REG_NPWRON_CONF, &pwr_on); 761 if (ret) 762 return dev_err_probe(dev, ret, "Failed to read PB/EN/VSENSE config\n"); 763 764 ret = regmap_read(tps->regmap, TPS6594_REG_GPIOX_CONF(2), &gpio3_cfg); 765 if (ret) 766 return dev_err_probe(dev, ret, "Failed to read GPIO3 config\n"); 767 768 if (FIELD_GET(TPS65224_MASK_EN_PB_VSENSE_CONFIG, pwr_on) == TPS65224_EN_SEL_PB || 769 FIELD_GET(TPS65224_MASK_GPIO_SEL, gpio3_cfg) == TPS65224_GPIO3_SEL_PB) { 770 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, 771 &tps6594_pwrbutton_cell, 1, NULL, 0, 772 regmap_irq_get_domain(tps->irq_data)); 773 if (ret) 774 return dev_err_probe(dev, ret, 775 "Failed to add power button device.\n"); 776 } 777 } 778 779 /* No RTC for LP8764, TPS65224 and TPS652G1 */ 780 if (tps->chip_id != LP8764 && tps->chip_id != TPS65224 && tps->chip_id != TPS652G1) { 781 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells, 782 ARRAY_SIZE(tps6594_rtc_cells), NULL, 0, 783 regmap_irq_get_domain(tps->irq_data)); 784 if (ret) 785 return dev_err_probe(dev, ret, "Failed to add RTC child device\n"); 786 } 787 788 if (of_device_is_system_power_controller(dev->of_node)) { 789 ret = devm_register_power_off_handler(tps->dev, tps6594_power_off_handler, tps); 790 if (ret) 791 return dev_err_probe(dev, ret, "Failed to register power-off handler\n"); 792 } 793 794 return 0; 795} 796EXPORT_SYMBOL_GPL(tps6594_device_init); 797 798MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>"); 799MODULE_AUTHOR("Bhargav Raviprakash <bhargav.r@ltts.com"); 800MODULE_DESCRIPTION("TPS6594 Driver"); 801MODULE_LICENSE("GPL");
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