stm32-timers.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) STMicroelectronics 2016
  4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
  5 */
  6
  7#include <linux/bitfield.h>
  8#include <linux/export.h>
  9#include <linux/mfd/stm32-timers.h>
 10#include <linux/module.h>
 11#include <linux/of_platform.h>
 12#include <linux/platform_device.h>
 13#include <linux/property.h>
 14#include <linux/reset.h>
 15
 16#define STM32_TIMERS_MAX_REGISTERS	0x3fc
 17
 18/* DIER register DMA enable bits */
 19static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {
 20	TIM_DIER_CC1DE,
 21	TIM_DIER_CC2DE,
 22	TIM_DIER_CC3DE,
 23	TIM_DIER_CC4DE,
 24	TIM_DIER_UIE,
 25	TIM_DIER_TDE,
 26	TIM_DIER_COMDE
 27};
 28
 29static void stm32_timers_dma_done(void *p)
 30{
 31	struct stm32_timers_dma *dma = p;
 32	struct dma_tx_state state;
 33	enum dma_status status;
 34
 35	status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);
 36	if (status == DMA_COMPLETE)
 37		complete(&dma->completion);
 38}
 39
 40/**
 41 * stm32_timers_dma_burst_read - Read from timers registers using DMA.
 42 *
 43 * Read from STM32 timers registers using DMA on a single event.
 44 * @dev: reference to stm32_timers MFD device
 45 * @buf: DMA'able destination buffer
 46 * @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)
 47 * @reg: registers start offset for DMA to read from (like CCRx for capture)
 48 * @num_reg: number of registers to read upon each DMA request, starting @reg.
 49 * @bursts: number of bursts to read (e.g. like two for pwm period capture)
 50 * @tmo_ms: timeout (milliseconds)
 51 */
 52int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
 53				enum stm32_timers_dmas id, u32 reg,
 54				unsigned int num_reg, unsigned int bursts,
 55				unsigned long tmo_ms)
 56{
 57	struct stm32_timers *ddata = dev_get_drvdata(dev);
 58	unsigned long timeout = msecs_to_jiffies(tmo_ms);
 59	struct regmap *regmap = ddata->regmap;
 60	struct stm32_timers_dma *dma = &ddata->dma;
 61	size_t len = num_reg * bursts * sizeof(u32);
 62	struct dma_async_tx_descriptor *desc;
 63	struct dma_slave_config config;
 64	dma_cookie_t cookie;
 65	dma_addr_t dma_buf;
 66	u32 dbl, dba;
 67	long err;
 68	int ret;
 69
 70	/* Sanity check */
 71	if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)
 72		return -EINVAL;
 73
 74	if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||
 75	    (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)
 76		return -EINVAL;
 77
 78	if (!dma->chans[id])
 79		return -ENODEV;
 80	mutex_lock(&dma->lock);
 81
 82	/* Select DMA channel in use */
 83	dma->chan = dma->chans[id];
 84	dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
 85	if (dma_mapping_error(dev, dma_buf)) {
 86		ret = -ENOMEM;
 87		goto unlock;
 88	}
 89
 90	/* Prepare DMA read from timer registers, using DMA burst mode */
 91	memset(&config, 0, sizeof(config));
 92	config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;
 93	config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 94	ret = dmaengine_slave_config(dma->chan, &config);
 95	if (ret)
 96		goto unmap;
 97
 98	desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len,
 99					   DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
100	if (!desc) {
101		ret = -EBUSY;
102		goto unmap;
103	}
104
105	desc->callback = stm32_timers_dma_done;
106	desc->callback_param = dma;
107	cookie = dmaengine_submit(desc);
108	ret = dma_submit_error(cookie);
109	if (ret)
110		goto dma_term;
111
112	reinit_completion(&dma->completion);
113	dma_async_issue_pending(dma->chan);
114
115	/* Setup and enable timer DMA burst mode */
116	dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1);
117	dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2);
118	ret = regmap_write(regmap, TIM_DCR, dbl | dba);
119	if (ret)
120		goto dma_term;
121
122	/* Clear pending flags before enabling DMA request */
123	ret = regmap_write(regmap, TIM_SR, 0);
124	if (ret)
125		goto dcr_clr;
126
127	ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id],
128				 stm32_timers_dier_dmaen[id]);
129	if (ret)
130		goto dcr_clr;
131
132	err = wait_for_completion_interruptible_timeout(&dma->completion,
133							timeout);
134	if (err == 0)
135		ret = -ETIMEDOUT;
136	else if (err < 0)
137		ret = err;
138
139	regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0);
140	regmap_write(regmap, TIM_SR, 0);
141dcr_clr:
142	regmap_write(regmap, TIM_DCR, 0);
143dma_term:
144	dmaengine_terminate_all(dma->chan);
145unmap:
146	dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE);
147unlock:
148	dma->chan = NULL;
149	mutex_unlock(&dma->lock);
150
151	return ret;
152}
153EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read);
154
155static const struct regmap_config stm32_timers_regmap_cfg = {
156	.reg_bits = 32,
157	.val_bits = 32,
158	.reg_stride = sizeof(u32),
159	.max_register = STM32_TIMERS_MAX_REGISTERS,
160};
161
162static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
163{
164	u32 arr;
165
166	/* Backup ARR to restore it after getting the maximum value */
167	regmap_read(ddata->regmap, TIM_ARR, &arr);
168
169	/*
170	 * Only the available bits will be written so when readback
171	 * we get the maximum value of auto reload register
172	 */
173	regmap_write(ddata->regmap, TIM_ARR, ~0L);
174	regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
175	regmap_write(ddata->regmap, TIM_ARR, arr);
176}
177
178static int stm32_timers_probe_hwcfgr(struct device *dev, struct stm32_timers *ddata)
179{
180	u32 val;
181
182	ddata->ipidr = (uintptr_t)device_get_match_data(dev);
183	if (!ddata->ipidr) {
184		/* Fallback to legacy method for probing counter width */
185		stm32_timers_get_arr_size(ddata);
186		return 0;
187	}
188
189	regmap_read(ddata->regmap, TIM_IPIDR, &val);
190	if (val != ddata->ipidr) {
191		dev_err(dev, "Unsupported device detected: %u\n", val);
192		return -EINVAL;
193	}
194
195	regmap_read(ddata->regmap, TIM_HWCFGR2, &val);
196
197	/* Counter width in bits, max reload value is BIT(width) - 1 */
198	ddata->max_arr = BIT(FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)) - 1;
199
200	return 0;
201}
202
203static int stm32_timers_dma_probe(struct device *dev,
204				   struct stm32_timers *ddata)
205{
206	int i;
207	int ret = 0;
208	char name[4];
209
210	init_completion(&ddata->dma.completion);
211	mutex_init(&ddata->dma.lock);
212
213	/* Optional DMA support: get valid DMA channel(s) or NULL */
214	for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) {
215		snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1);
216		ddata->dma.chans[i] = dma_request_chan(dev, name);
217	}
218	ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up");
219	ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig");
220	ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com");
221
222	for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) {
223		if (IS_ERR(ddata->dma.chans[i])) {
224			/* Save the first error code to return */
225			if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret)
226				ret = PTR_ERR(ddata->dma.chans[i]);
227
228			ddata->dma.chans[i] = NULL;
229		}
230	}
231
232	return ret;
233}
234
235static void stm32_timers_dma_remove(struct device *dev,
236				    struct stm32_timers *ddata)
237{
238	int i;
239
240	for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++)
241		if (ddata->dma.chans[i])
242			dma_release_channel(ddata->dma.chans[i]);
243}
244
245static const char * const stm32_timers_irq_name[STM32_TIMERS_MAX_IRQS] = {
246	"brk", "up", "trg-com", "cc"
247};
248
249static int stm32_timers_irq_probe(struct platform_device *pdev,
250				  struct stm32_timers *ddata)
251{
252	int i, ret;
253
254	/*
255	 * STM32 Timer may have either:
256	 * - a unique global interrupt line
257	 * - four dedicated interrupt lines that may be handled separately.
258	 * Optionally get them here, to be used by child devices.
259	 */
260	ret = platform_get_irq_byname_optional(pdev, "global");
261	if (ret < 0 && ret != -ENXIO) {
262		return ret;
263	} else if (ret != -ENXIO) {
264		ddata->irq[STM32_TIMERS_IRQ_GLOBAL_BRK] = ret;
265		ddata->nr_irqs = 1;
266		return 0;
267	}
268
269	for (i = 0; i < STM32_TIMERS_MAX_IRQS; i++) {
270		ret = platform_get_irq_byname_optional(pdev, stm32_timers_irq_name[i]);
271		if (ret < 0 && ret != -ENXIO) {
272			return ret;
273		} else if (ret != -ENXIO) {
274			ddata->irq[i] = ret;
275			ddata->nr_irqs++;
276		}
277	}
278
279	if (ddata->nr_irqs && ddata->nr_irqs != STM32_TIMERS_MAX_IRQS) {
280		dev_err(&pdev->dev, "Invalid number of IRQs %d\n", ddata->nr_irqs);
281		return -EINVAL;
282	}
283
284	return 0;
285}
286
287static int stm32_timers_probe(struct platform_device *pdev)
288{
289	struct device *dev = &pdev->dev;
290	struct stm32_timers *ddata;
291	struct resource *res;
292	void __iomem *mmio;
293	int ret;
294
295	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
296	if (!ddata)
297		return -ENOMEM;
298
299	mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
300	if (IS_ERR(mmio))
301		return PTR_ERR(mmio);
302
303	/* Timer physical addr for DMA */
304	ddata->dma.phys_base = res->start;
305
306	ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
307						  &stm32_timers_regmap_cfg);
308	if (IS_ERR(ddata->regmap))
309		return PTR_ERR(ddata->regmap);
310
311	ddata->clk = devm_clk_get(dev, NULL);
312	if (IS_ERR(ddata->clk))
313		return PTR_ERR(ddata->clk);
314
315	ret = stm32_timers_probe_hwcfgr(dev, ddata);
316	if (ret)
317		return ret;
318
319	ret = stm32_timers_irq_probe(pdev, ddata);
320	if (ret)
321		return ret;
322
323	ret = stm32_timers_dma_probe(dev, ddata);
324	if (ret) {
325		stm32_timers_dma_remove(dev, ddata);
326		return ret;
327	}
328
329	platform_set_drvdata(pdev, ddata);
330
331	ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
332	if (ret)
333		stm32_timers_dma_remove(dev, ddata);
334
335	return ret;
336}
337
338static void stm32_timers_remove(struct platform_device *pdev)
339{
340	struct stm32_timers *ddata = platform_get_drvdata(pdev);
341
342	/*
343	 * Don't use devm_ here: enfore of_platform_depopulate() happens before
344	 * DMA are released, to avoid race on DMA.
345	 */
346	of_platform_depopulate(&pdev->dev);
347	stm32_timers_dma_remove(&pdev->dev, ddata);
348}
349
350static const struct of_device_id stm32_timers_of_match[] = {
351	{ .compatible = "st,stm32-timers", },
352	{ .compatible = "st,stm32mp25-timers", .data = (void *)STM32MP25_TIM_IPIDR },
353	{ /* end node */ },
354};
355MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
356
357static struct platform_driver stm32_timers_driver = {
358	.probe = stm32_timers_probe,
359	.remove = stm32_timers_remove,
360	.driver	= {
361		.name = "stm32-timers",
362		.of_match_table = stm32_timers_of_match,
363	},
364};
365module_platform_driver(stm32_timers_driver);
366
367MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
368MODULE_LICENSE("GPL v2");