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sm501.c
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linux-6.19.14/drivers/mfd/sm501.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* linux/drivers/mfd/sm501.c 3 * 4 * Copyright (C) 2006 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * Vincent Sanders <vince@simtec.co.uk> 7 * 8 * SM501 MFD driver 9*/ 10 11#include <linux/kernel.h> 12#include <linux/module.h> 13#include <linux/delay.h> 14#include <linux/init.h> 15#include <linux/list.h> 16#include <linux/device.h> 17#include <linux/platform_device.h> 18#include <linux/pci.h> 19#include <linux/platform_data/i2c-gpio.h> 20#include <linux/gpio/driver.h> 21#include <linux/gpio/machine.h> 22#include <linux/slab.h> 23 24#include <linux/sm501.h> 25#include <linux/sm501-regs.h> 26#include <linux/serial_8250.h> 27 28#include <linux/io.h> 29 30struct sm501_device { 31 struct list_head list; 32 struct platform_device pdev; 33}; 34 35struct sm501_gpio; 36 37#ifdef CONFIG_MFD_SM501_GPIO 38#include <linux/gpio.h> 39 40struct sm501_gpio_chip { 41 struct gpio_chip gpio; 42 struct sm501_gpio *ourgpio; /* to get back to parent. */ 43 void __iomem *regbase; 44 void __iomem *control; /* address of control reg. */ 45}; 46 47struct sm501_gpio { 48 struct sm501_gpio_chip low; 49 struct sm501_gpio_chip high; 50 spinlock_t lock; 51 52 unsigned int registered : 1; 53 void __iomem *regs; 54 struct resource *regs_res; 55}; 56#else 57struct sm501_gpio { 58 /* no gpio support, empty definition for sm501_devdata. */ 59}; 60#endif 61 62struct sm501_devdata { 63 spinlock_t reg_lock; 64 struct mutex clock_lock; 65 struct list_head devices; 66 struct sm501_gpio gpio; 67 68 struct device *dev; 69 struct resource *io_res; 70 struct resource *mem_res; 71 struct resource *regs_claim; 72 struct sm501_platdata *platdata; 73 74 75 unsigned int in_suspend; 76 unsigned long pm_misc; 77 78 int unit_power[20]; 79 unsigned int pdev_id; 80 unsigned int irq; 81 void __iomem *regs; 82 unsigned int rev; 83}; 84 85 86#define MHZ (1000 * 1000) 87 88#ifdef DEBUG 89static const unsigned int div_tab[] = { 90 [0] = 1, 91 [1] = 2, 92 [2] = 4, 93 [3] = 8, 94 [4] = 16, 95 [5] = 32, 96 [6] = 64, 97 [7] = 128, 98 [8] = 3, 99 [9] = 6, 100 [10] = 12, 101 [11] = 24, 102 [12] = 48, 103 [13] = 96, 104 [14] = 192, 105 [15] = 384, 106 [16] = 5, 107 [17] = 10, 108 [18] = 20, 109 [19] = 40, 110 [20] = 80, 111 [21] = 160, 112 [22] = 320, 113 [23] = 604, 114}; 115 116static unsigned long decode_div(unsigned long pll2, unsigned long val, 117 unsigned int lshft, unsigned int selbit, 118 unsigned long mask) 119{ 120 if (val & selbit) 121 pll2 = 288 * MHZ; 122 123 return pll2 / div_tab[(val >> lshft) & mask]; 124} 125 126#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x) 127 128/* sm501_dump_clk 129 * 130 * Print out the current clock configuration for the device 131*/ 132 133static void sm501_dump_clk(struct sm501_devdata *sm) 134{ 135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); 136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); 137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); 138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 139 unsigned long sdclk0, sdclk1; 140 unsigned long pll2 = 0; 141 142 switch (misct & 0x30) { 143 case 0x00: 144 pll2 = 336 * MHZ; 145 break; 146 case 0x10: 147 pll2 = 288 * MHZ; 148 break; 149 case 0x20: 150 pll2 = 240 * MHZ; 151 break; 152 case 0x30: 153 pll2 = 192 * MHZ; 154 break; 155 } 156 157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; 158 sdclk0 /= div_tab[((misct >> 8) & 0xf)]; 159 160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; 161 sdclk1 /= div_tab[((misct >> 16) & 0xf)]; 162 163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", 164 misct, pm0, pm1); 165 166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", 167 fmt_freq(pll2), sdclk0, sdclk1); 168 169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); 170 171 dev_dbg(sm->dev, "PM0[%c]: " 172 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 174 (pmc & 3 ) == 0 ? '*' : '-', 175 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), 176 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), 177 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), 178 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); 179 180 dev_dbg(sm->dev, "PM1[%c]: " 181 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 183 (pmc & 3 ) == 1 ? '*' : '-', 184 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), 185 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), 186 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), 187 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); 188} 189 190static void sm501_dump_regs(struct sm501_devdata *sm) 191{ 192 void __iomem *regs = sm->regs; 193 194 dev_info(sm->dev, "System Control %08x\n", 195 smc501_readl(regs + SM501_SYSTEM_CONTROL)); 196 dev_info(sm->dev, "Misc Control %08x\n", 197 smc501_readl(regs + SM501_MISC_CONTROL)); 198 dev_info(sm->dev, "GPIO Control Low %08x\n", 199 smc501_readl(regs + SM501_GPIO31_0_CONTROL)); 200 dev_info(sm->dev, "GPIO Control Hi %08x\n", 201 smc501_readl(regs + SM501_GPIO63_32_CONTROL)); 202 dev_info(sm->dev, "DRAM Control %08x\n", 203 smc501_readl(regs + SM501_DRAM_CONTROL)); 204 dev_info(sm->dev, "Arbitration Ctrl %08x\n", 205 smc501_readl(regs + SM501_ARBTRTN_CONTROL)); 206 dev_info(sm->dev, "Misc Timing %08x\n", 207 smc501_readl(regs + SM501_MISC_TIMING)); 208} 209 210static void sm501_dump_gate(struct sm501_devdata *sm) 211{ 212 dev_info(sm->dev, "CurrentGate %08x\n", 213 smc501_readl(sm->regs + SM501_CURRENT_GATE)); 214 dev_info(sm->dev, "CurrentClock %08x\n", 215 smc501_readl(sm->regs + SM501_CURRENT_CLOCK)); 216 dev_info(sm->dev, "PowerModeControl %08x\n", 217 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL)); 218} 219 220#else 221static inline void sm501_dump_gate(struct sm501_devdata *sm) { } 222static inline void sm501_dump_regs(struct sm501_devdata *sm) { } 223static inline void sm501_dump_clk(struct sm501_devdata *sm) { } 224#endif 225 226/* sm501_sync_regs 227 * 228 * ensure the 229*/ 230 231static void sm501_sync_regs(struct sm501_devdata *sm) 232{ 233 smc501_readl(sm->regs); 234} 235 236static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) 237{ 238 /* during suspend/resume, we are currently not allowed to sleep, 239 * so change to using mdelay() instead of msleep() if we 240 * are in one of these paths */ 241 242 if (sm->in_suspend) 243 mdelay(delay); 244 else 245 msleep(delay); 246} 247 248/* sm501_misc_control 249 * 250 * alters the miscellaneous control parameters 251*/ 252 253int sm501_misc_control(struct device *dev, 254 unsigned long set, unsigned long clear) 255{ 256 struct sm501_devdata *sm = dev_get_drvdata(dev); 257 unsigned long misc; 258 unsigned long save; 259 unsigned long to; 260 261 spin_lock_irqsave(&sm->reg_lock, save); 262 263 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 264 to = (misc & ~clear) | set; 265 266 if (to != misc) { 267 smc501_writel(to, sm->regs + SM501_MISC_CONTROL); 268 sm501_sync_regs(sm); 269 270 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); 271 } 272 273 spin_unlock_irqrestore(&sm->reg_lock, save); 274 return to; 275} 276 277EXPORT_SYMBOL_GPL(sm501_misc_control); 278 279/* sm501_modify_reg 280 * 281 * Modify a register in the SM501 which may be shared with other 282 * drivers. 283*/ 284 285unsigned long sm501_modify_reg(struct device *dev, 286 unsigned long reg, 287 unsigned long set, 288 unsigned long clear) 289{ 290 struct sm501_devdata *sm = dev_get_drvdata(dev); 291 unsigned long data; 292 unsigned long save; 293 294 spin_lock_irqsave(&sm->reg_lock, save); 295 296 data = smc501_readl(sm->regs + reg); 297 data |= set; 298 data &= ~clear; 299 300 smc501_writel(data, sm->regs + reg); 301 sm501_sync_regs(sm); 302 303 spin_unlock_irqrestore(&sm->reg_lock, save); 304 305 return data; 306} 307 308EXPORT_SYMBOL_GPL(sm501_modify_reg); 309 310/* sm501_unit_power 311 * 312 * alters the power active gate to set specific units on or off 313 */ 314 315int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) 316{ 317 struct sm501_devdata *sm = dev_get_drvdata(dev); 318 unsigned long mode; 319 unsigned long gate; 320 unsigned long clock; 321 322 mutex_lock(&sm->clock_lock); 323 324 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 325 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 326 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 327 328 mode &= 3; /* get current power mode */ 329 330 if (unit >= ARRAY_SIZE(sm->unit_power)) { 331 dev_err(dev, "%s: bad unit %d\n", __func__, unit); 332 goto already; 333 } 334 335 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit, 336 sm->unit_power[unit], to); 337 338 if (to == 0 && sm->unit_power[unit] == 0) { 339 dev_err(sm->dev, "unit %d is already shutdown\n", unit); 340 goto already; 341 } 342 343 sm->unit_power[unit] += to ? 1 : -1; 344 to = sm->unit_power[unit] ? 1 : 0; 345 346 if (to) { 347 if (gate & (1 << unit)) 348 goto already; 349 gate |= (1 << unit); 350 } else { 351 if (!(gate & (1 << unit))) 352 goto already; 353 gate &= ~(1 << unit); 354 } 355 356 switch (mode) { 357 case 1: 358 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 359 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 360 mode = 0; 361 break; 362 case 2: 363 case 0: 364 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 365 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 366 mode = 1; 367 break; 368 369 default: 370 gate = -1; 371 goto already; 372 } 373 374 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 375 sm501_sync_regs(sm); 376 377 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 378 gate, clock, mode); 379 380 sm501_mdelay(sm, 16); 381 382 already: 383 mutex_unlock(&sm->clock_lock); 384 return gate; 385} 386 387EXPORT_SYMBOL_GPL(sm501_unit_power); 388 389/* clock value structure. */ 390struct sm501_clock { 391 unsigned long mclk; 392 int divider; 393 int shift; 394 unsigned int m, n, k; 395}; 396 397/* sm501_calc_clock 398 * 399 * Calculates the nearest discrete clock frequency that 400 * can be achieved with the specified input clock. 401 * the maximum divisor is 3 or 5 402 */ 403 404static int sm501_calc_clock(unsigned long freq, 405 struct sm501_clock *clock, 406 int max_div, 407 unsigned long mclk, 408 long *best_diff) 409{ 410 int ret = 0; 411 int divider; 412 int shift; 413 long diff; 414 415 /* try dividers 1 and 3 for CRT and for panel, 416 try divider 5 for panel only.*/ 417 418 for (divider = 1; divider <= max_div; divider += 2) { 419 /* try all 8 shift values.*/ 420 for (shift = 0; shift < 8; shift++) { 421 /* Calculate difference to requested clock */ 422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; 423 if (diff < 0) 424 diff = -diff; 425 426 /* If it is less than the current, use it */ 427 if (diff < *best_diff) { 428 *best_diff = diff; 429 430 clock->mclk = mclk; 431 clock->divider = divider; 432 clock->shift = shift; 433 ret = 1; 434 } 435 } 436 } 437 438 return ret; 439} 440 441/* sm501_calc_pll 442 * 443 * Calculates the nearest discrete clock frequency that can be 444 * achieved using the programmable PLL. 445 * the maximum divisor is 3 or 5 446 */ 447 448static unsigned long sm501_calc_pll(unsigned long freq, 449 struct sm501_clock *clock, 450 int max_div) 451{ 452 unsigned long mclk; 453 unsigned int m, n, k; 454 long best_diff = 999999999; 455 456 /* 457 * The SM502 datasheet doesn't specify the min/max values for M and N. 458 * N = 1 at least doesn't work in practice. 459 */ 460 for (m = 2; m <= 255; m++) { 461 for (n = 2; n <= 127; n++) { 462 for (k = 0; k <= 1; k++) { 463 mclk = (24000000UL * m / n) >> k; 464 465 if (sm501_calc_clock(freq, clock, max_div, 466 mclk, &best_diff)) { 467 clock->m = m; 468 clock->n = n; 469 clock->k = k; 470 } 471 } 472 } 473 } 474 475 /* Return best clock. */ 476 return clock->mclk / (clock->divider << clock->shift); 477} 478 479/* sm501_select_clock 480 * 481 * Calculates the nearest discrete clock frequency that can be 482 * achieved using the 288MHz and 336MHz PLLs. 483 * the maximum divisor is 3 or 5 484 */ 485 486static unsigned long sm501_select_clock(unsigned long freq, 487 struct sm501_clock *clock, 488 int max_div) 489{ 490 unsigned long mclk; 491 long best_diff = 999999999; 492 493 /* Try 288MHz and 336MHz clocks. */ 494 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { 495 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); 496 } 497 498 /* Return best clock. */ 499 return clock->mclk / (clock->divider << clock->shift); 500} 501 502/* sm501_set_clock 503 * 504 * set one of the four clock sources to the closest available frequency to 505 * the one specified 506*/ 507 508unsigned long sm501_set_clock(struct device *dev, 509 int clksrc, 510 unsigned long req_freq) 511{ 512 struct sm501_devdata *sm = dev_get_drvdata(dev); 513 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 514 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 515 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 516 unsigned int pll_reg = 0; 517 unsigned long sm501_freq; /* the actual frequency achieved */ 518 u64 reg; 519 520 struct sm501_clock to; 521 522 /* find achivable discrete frequency and setup register value 523 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK 524 * has an extra bit for the divider */ 525 526 switch (clksrc) { 527 case SM501_CLOCK_P2XCLK: 528 /* This clock is divided in half so to achieve the 529 * requested frequency the value must be multiplied by 530 * 2. This clock also has an additional pre divisor */ 531 532 if (sm->rev >= 0xC0) { 533 /* SM502 -> use the programmable PLL */ 534 sm501_freq = (sm501_calc_pll(2 * req_freq, 535 &to, 5) / 2); 536 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 537 if (to.divider == 3) 538 reg |= 0x08; /* /3 divider required */ 539 else if (to.divider == 5) 540 reg |= 0x10; /* /5 divider required */ 541 reg |= 0x40; /* select the programmable PLL */ 542 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; 543 } else { 544 sm501_freq = (sm501_select_clock(2 * req_freq, 545 &to, 5) / 2); 546 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 547 if (to.divider == 3) 548 reg |= 0x08; /* /3 divider required */ 549 else if (to.divider == 5) 550 reg |= 0x10; /* /5 divider required */ 551 if (to.mclk != 288000000) 552 reg |= 0x20; /* which mclk pll is source */ 553 } 554 break; 555 556 case SM501_CLOCK_V2XCLK: 557 /* This clock is divided in half so to achieve the 558 * requested frequency the value must be multiplied by 2. */ 559 560 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 561 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 562 if (to.divider == 3) 563 reg |= 0x08; /* /3 divider required */ 564 if (to.mclk != 288000000) 565 reg |= 0x10; /* which mclk pll is source */ 566 break; 567 568 case SM501_CLOCK_MCLK: 569 case SM501_CLOCK_M1XCLK: 570 /* These clocks are the same and not further divided */ 571 572 sm501_freq = sm501_select_clock( req_freq, &to, 3); 573 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 574 if (to.divider == 3) 575 reg |= 0x08; /* /3 divider required */ 576 if (to.mclk != 288000000) 577 reg |= 0x10; /* which mclk pll is source */ 578 break; 579 580 default: 581 return 0; /* this is bad */ 582 } 583 584 mutex_lock(&sm->clock_lock); 585 586 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 587 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 588 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 589 590 clock = clock & ~(0xFF << clksrc); 591 clock |= reg<<clksrc; 592 593 mode &= 3; /* find current mode */ 594 595 switch (mode) { 596 case 1: 597 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 598 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 599 mode = 0; 600 break; 601 case 2: 602 case 0: 603 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 604 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 605 mode = 1; 606 break; 607 608 default: 609 mutex_unlock(&sm->clock_lock); 610 return -1; 611 } 612 613 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 614 615 if (pll_reg) 616 smc501_writel(pll_reg, 617 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); 618 619 sm501_sync_regs(sm); 620 621 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 622 gate, clock, mode); 623 624 sm501_mdelay(sm, 16); 625 mutex_unlock(&sm->clock_lock); 626 627 sm501_dump_clk(sm); 628 629 return sm501_freq; 630} 631 632EXPORT_SYMBOL_GPL(sm501_set_clock); 633 634static struct sm501_device *to_sm_device(struct platform_device *pdev) 635{ 636 return container_of(pdev, struct sm501_device, pdev); 637} 638 639/* sm501_device_release 640 * 641 * A release function for the platform devices we create to allow us to 642 * free any items we allocated 643*/ 644 645static void sm501_device_release(struct device *dev) 646{ 647 kfree(to_sm_device(to_platform_device(dev))); 648} 649 650/* sm501_create_subdev 651 * 652 * Create a skeleton platform device with resources for passing to a 653 * sub-driver 654*/ 655 656static struct platform_device * 657sm501_create_subdev(struct sm501_devdata *sm, char *name, 658 unsigned int res_count, unsigned int platform_data_size) 659{ 660 struct sm501_device *smdev; 661 662 smdev = kzalloc(sizeof(struct sm501_device) + 663 (sizeof(struct resource) * res_count) + 664 platform_data_size, GFP_KERNEL); 665 if (!smdev) 666 return NULL; 667 668 smdev->pdev.dev.release = sm501_device_release; 669 670 smdev->pdev.name = name; 671 smdev->pdev.id = sm->pdev_id; 672 smdev->pdev.dev.parent = sm->dev; 673 smdev->pdev.dev.coherent_dma_mask = 0xffffffff; 674 675 if (res_count) { 676 smdev->pdev.resource = (struct resource *)(smdev+1); 677 smdev->pdev.num_resources = res_count; 678 } 679 if (platform_data_size) 680 smdev->pdev.dev.platform_data = (void *)(smdev+1); 681 682 return &smdev->pdev; 683} 684 685/* sm501_register_device 686 * 687 * Register a platform device created with sm501_create_subdev() 688*/ 689 690static int sm501_register_device(struct sm501_devdata *sm, 691 struct platform_device *pdev) 692{ 693 struct sm501_device *smdev = to_sm_device(pdev); 694 int ptr; 695 int ret; 696 697 for (ptr = 0; ptr < pdev->num_resources; ptr++) { 698 printk(KERN_DEBUG "%s[%d] %pR\n", 699 pdev->name, ptr, &pdev->resource[ptr]); 700 } 701 702 ret = platform_device_register(pdev); 703 704 if (ret >= 0) { 705 dev_dbg(sm->dev, "registered %s\n", pdev->name); 706 list_add_tail(&smdev->list, &sm->devices); 707 } else 708 dev_err(sm->dev, "error registering %s (%d)\n", 709 pdev->name, ret); 710 711 return ret; 712} 713 714/* sm501_create_subio 715 * 716 * Fill in an IO resource for a sub device 717*/ 718 719static void sm501_create_subio(struct sm501_devdata *sm, 720 struct resource *res, 721 resource_size_t offs, 722 resource_size_t size) 723{ 724 res->flags = IORESOURCE_MEM; 725 res->parent = sm->io_res; 726 res->start = sm->io_res->start + offs; 727 res->end = res->start + size - 1; 728} 729 730/* sm501_create_mem 731 * 732 * Fill in an MEM resource for a sub device 733*/ 734 735static void sm501_create_mem(struct sm501_devdata *sm, 736 struct resource *res, 737 resource_size_t *offs, 738 resource_size_t size) 739{ 740 *offs -= size; /* adjust memory size */ 741 742 res->flags = IORESOURCE_MEM; 743 res->parent = sm->mem_res; 744 res->start = sm->mem_res->start + *offs; 745 res->end = res->start + size - 1; 746} 747 748/* sm501_create_irq 749 * 750 * Fill in an IRQ resource for a sub device 751*/ 752 753static void sm501_create_irq(struct sm501_devdata *sm, 754 struct resource *res) 755{ 756 res->flags = IORESOURCE_IRQ; 757 res->parent = NULL; 758 res->start = res->end = sm->irq; 759} 760 761static int sm501_register_usbhost(struct sm501_devdata *sm, 762 resource_size_t *mem_avail) 763{ 764 struct platform_device *pdev; 765 766 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0); 767 if (!pdev) 768 return -ENOMEM; 769 770 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000); 771 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024); 772 sm501_create_irq(sm, &pdev->resource[2]); 773 774 return sm501_register_device(sm, pdev); 775} 776 777static void sm501_setup_uart_data(struct sm501_devdata *sm, 778 struct plat_serial8250_port *uart_data, 779 unsigned int offset) 780{ 781 uart_data->membase = sm->regs + offset; 782 uart_data->mapbase = sm->io_res->start + offset; 783 uart_data->iotype = UPIO_MEM; 784 uart_data->irq = sm->irq; 785 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 786 uart_data->regshift = 2; 787 uart_data->uartclk = (9600 * 16); 788} 789 790static int sm501_register_uart(struct sm501_devdata *sm, int devices) 791{ 792 struct platform_device *pdev; 793 struct plat_serial8250_port *uart_data; 794 795 pdev = sm501_create_subdev(sm, "serial8250", 0, 796 sizeof(struct plat_serial8250_port) * 3); 797 if (!pdev) 798 return -ENOMEM; 799 800 uart_data = dev_get_platdata(&pdev->dev); 801 802 if (devices & SM501_USE_UART0) { 803 sm501_setup_uart_data(sm, uart_data++, 0x30000); 804 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1); 805 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0); 806 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0); 807 } 808 if (devices & SM501_USE_UART1) { 809 sm501_setup_uart_data(sm, uart_data++, 0x30020); 810 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1); 811 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0); 812 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0); 813 } 814 815 pdev->id = PLAT8250_DEV_SM501; 816 817 return sm501_register_device(sm, pdev); 818} 819 820static int sm501_register_display(struct sm501_devdata *sm, 821 resource_size_t *mem_avail) 822{ 823 struct platform_device *pdev; 824 825 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0); 826 if (!pdev) 827 return -ENOMEM; 828 829 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000); 830 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000); 831 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail); 832 sm501_create_irq(sm, &pdev->resource[3]); 833 834 return sm501_register_device(sm, pdev); 835} 836 837#ifdef CONFIG_MFD_SM501_GPIO 838 839static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio) 840{ 841 return container_of(gpio, struct sm501_devdata, gpio); 842} 843 844static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) 845 846{ 847 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip); 848 unsigned long result; 849 850 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW); 851 result >>= offset; 852 853 return result & 1UL; 854} 855 856static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, 857 unsigned long bit) 858{ 859 unsigned long ctrl; 860 861 /* check and modify if this pin is not set as gpio. */ 862 863 if (smc501_readl(smchip->control) & bit) { 864 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, 865 "changing mode of gpio, bit %08lx\n", bit); 866 867 ctrl = smc501_readl(smchip->control); 868 ctrl &= ~bit; 869 smc501_writel(ctrl, smchip->control); 870 871 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); 872 } 873} 874 875static int sm501_gpio_set(struct gpio_chip *chip, unsigned int offset, 876 int value) 877 878{ 879 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 880 struct sm501_gpio *smgpio = smchip->ourgpio; 881 unsigned long bit = BIT(offset); 882 void __iomem *regs = smchip->regbase; 883 unsigned long save; 884 unsigned long val; 885 886 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 887 __func__, chip, offset); 888 889 spin_lock_irqsave(&smgpio->lock, save); 890 891 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit; 892 if (value) 893 val |= bit; 894 smc501_writel(val, regs); 895 896 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 897 sm501_gpio_ensure_gpio(smchip, bit); 898 899 spin_unlock_irqrestore(&smgpio->lock, save); 900 901 return 0; 902} 903 904static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) 905{ 906 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 907 struct sm501_gpio *smgpio = smchip->ourgpio; 908 void __iomem *regs = smchip->regbase; 909 unsigned long bit = BIT(offset); 910 unsigned long save; 911 unsigned long ddr; 912 913 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 914 __func__, chip, offset); 915 916 spin_lock_irqsave(&smgpio->lock, save); 917 918 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 919 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); 920 921 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 922 sm501_gpio_ensure_gpio(smchip, bit); 923 924 spin_unlock_irqrestore(&smgpio->lock, save); 925 926 return 0; 927} 928 929static int sm501_gpio_output(struct gpio_chip *chip, 930 unsigned offset, int value) 931{ 932 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 933 struct sm501_gpio *smgpio = smchip->ourgpio; 934 unsigned long bit = BIT(offset); 935 void __iomem *regs = smchip->regbase; 936 unsigned long save; 937 unsigned long val; 938 unsigned long ddr; 939 940 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n", 941 __func__, chip, offset, value); 942 943 spin_lock_irqsave(&smgpio->lock, save); 944 945 val = smc501_readl(regs + SM501_GPIO_DATA_LOW); 946 if (value) 947 val |= bit; 948 else 949 val &= ~bit; 950 smc501_writel(val, regs); 951 952 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 953 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); 954 955 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 956 smc501_writel(val, regs + SM501_GPIO_DATA_LOW); 957 958 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 959 spin_unlock_irqrestore(&smgpio->lock, save); 960 961 return 0; 962} 963 964static const struct gpio_chip gpio_chip_template = { 965 .ngpio = 32, 966 .direction_input = sm501_gpio_input, 967 .direction_output = sm501_gpio_output, 968 .set = sm501_gpio_set, 969 .get = sm501_gpio_get, 970}; 971 972static int sm501_gpio_register_chip(struct sm501_devdata *sm, 973 struct sm501_gpio *gpio, 974 struct sm501_gpio_chip *chip) 975{ 976 struct sm501_platdata *pdata = sm->platdata; 977 struct gpio_chip *gchip = &chip->gpio; 978 int base = pdata->gpio_base; 979 980 chip->gpio = gpio_chip_template; 981 982 if (chip == &gpio->high) { 983 if (base > 0) 984 base += 32; 985 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; 986 chip->control = sm->regs + SM501_GPIO63_32_CONTROL; 987 gchip->label = "SM501-HIGH"; 988 } else { 989 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; 990 chip->control = sm->regs + SM501_GPIO31_0_CONTROL; 991 gchip->label = "SM501-LOW"; 992 } 993 994 gchip->base = base; 995 chip->ourgpio = gpio; 996 997 return gpiochip_add_data(gchip, chip); 998} 999 1000static int sm501_register_gpio(struct sm501_devdata *sm) 1001{ 1002 struct sm501_gpio *gpio = &sm->gpio; 1003 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1004 int ret; 1005 1006 dev_dbg(sm->dev, "registering gpio block %08llx\n", 1007 (unsigned long long)iobase); 1008 1009 spin_lock_init(&gpio->lock); 1010 1011 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio"); 1012 if (!gpio->regs_res) { 1013 dev_err(sm->dev, "gpio: failed to request region\n"); 1014 return -ENXIO; 1015 } 1016 1017 gpio->regs = ioremap(iobase, 0x20); 1018 if (!gpio->regs) { 1019 dev_err(sm->dev, "gpio: failed to remap registers\n"); 1020 ret = -ENXIO; 1021 goto err_claimed; 1022 } 1023 1024 /* Register both our chips. */ 1025 1026 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low); 1027 if (ret) { 1028 dev_err(sm->dev, "failed to add low chip\n"); 1029 goto err_mapped; 1030 } 1031 1032 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high); 1033 if (ret) { 1034 dev_err(sm->dev, "failed to add high chip\n"); 1035 goto err_low_chip; 1036 } 1037 1038 gpio->registered = 1; 1039 1040 return 0; 1041 1042 err_low_chip: 1043 gpiochip_remove(&gpio->low.gpio); 1044 1045 err_mapped: 1046 iounmap(gpio->regs); 1047 1048 err_claimed: 1049 release_mem_region(iobase, 0x20); 1050 1051 return ret; 1052} 1053 1054static void sm501_gpio_remove(struct sm501_devdata *sm) 1055{ 1056 struct sm501_gpio *gpio = &sm->gpio; 1057 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1058 1059 if (!sm->gpio.registered) 1060 return; 1061 1062 gpiochip_remove(&gpio->low.gpio); 1063 gpiochip_remove(&gpio->high.gpio); 1064 1065 iounmap(gpio->regs); 1066 release_mem_region(iobase, 0x20); 1067} 1068 1069static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1070{ 1071 return sm->gpio.registered; 1072} 1073#else 1074static inline int sm501_register_gpio(struct sm501_devdata *sm) 1075{ 1076 return 0; 1077} 1078 1079static inline void sm501_gpio_remove(struct sm501_devdata *sm) 1080{ 1081} 1082 1083static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1084{ 1085 return 0; 1086} 1087#endif 1088 1089static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm, 1090 struct sm501_platdata_gpio_i2c *iic) 1091{ 1092 struct i2c_gpio_platform_data *icd; 1093 struct platform_device *pdev; 1094 struct gpiod_lookup_table *lookup; 1095 1096 pdev = sm501_create_subdev(sm, "i2c-gpio", 0, 1097 sizeof(struct i2c_gpio_platform_data)); 1098 if (!pdev) 1099 return -ENOMEM; 1100 1101 /* Create a gpiod lookup using gpiochip-local offsets */ 1102 lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3), 1103 GFP_KERNEL); 1104 if (!lookup) 1105 return -ENOMEM; 1106 1107 lookup->dev_id = "i2c-gpio"; 1108 lookup->table[0] = (struct gpiod_lookup) 1109 GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH", 1110 iic->pin_sda % 32, NULL, 0, 1111 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN); 1112 lookup->table[1] = (struct gpiod_lookup) 1113 GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH", 1114 iic->pin_scl % 32, NULL, 1, 1115 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN); 1116 gpiod_add_lookup_table(lookup); 1117 1118 icd = dev_get_platdata(&pdev->dev); 1119 icd->timeout = iic->timeout; 1120 icd->udelay = iic->udelay; 1121 1122 /* note, we can't use either of the pin numbers, as the i2c-gpio 1123 * driver uses the platform.id field to generate the bus number 1124 * to register with the i2c core; The i2c core doesn't have enough 1125 * entries to deal with anything we currently use. 1126 */ 1127 1128 pdev->id = iic->bus_num; 1129 1130 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n", 1131 iic->bus_num, 1132 iic->pin_sda, iic->pin_scl); 1133 1134 return sm501_register_device(sm, pdev); 1135} 1136 1137static int sm501_register_gpio_i2c(struct sm501_devdata *sm, 1138 struct sm501_platdata *pdata) 1139{ 1140 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c; 1141 int index; 1142 int ret; 1143 1144 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) { 1145 ret = sm501_register_gpio_i2c_instance(sm, iic); 1146 if (ret < 0) 1147 return ret; 1148 } 1149 1150 return 0; 1151} 1152 1153/* dbg_regs_show 1154 * 1155 * Debug attribute to attach to parent device to show core registers 1156*/ 1157 1158static ssize_t dbg_regs_show(struct device *dev, 1159 struct device_attribute *attr, char *buff) 1160{ 1161 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 1162 unsigned int reg; 1163 char *ptr = buff; 1164 int ret; 1165 1166 for (reg = 0x00; reg < 0x70; reg += 4) { 1167 ret = sprintf(ptr, "%08x = %08x\n", 1168 reg, smc501_readl(sm->regs + reg)); 1169 ptr += ret; 1170 } 1171 1172 return ptr - buff; 1173} 1174 1175 1176static DEVICE_ATTR_RO(dbg_regs); 1177 1178/* sm501_init_reg 1179 * 1180 * Helper function for the init code to setup a register 1181 * 1182 * clear the bits which are set in r->mask, and then set 1183 * the bits set in r->set. 1184*/ 1185 1186static inline void sm501_init_reg(struct sm501_devdata *sm, 1187 unsigned long reg, 1188 struct sm501_reg_init *r) 1189{ 1190 unsigned long tmp; 1191 1192 tmp = smc501_readl(sm->regs + reg); 1193 tmp &= ~r->mask; 1194 tmp |= r->set; 1195 smc501_writel(tmp, sm->regs + reg); 1196} 1197 1198/* sm501_init_regs 1199 * 1200 * Setup core register values 1201*/ 1202 1203static void sm501_init_regs(struct sm501_devdata *sm, 1204 struct sm501_initdata *init) 1205{ 1206 sm501_misc_control(sm->dev, 1207 init->misc_control.set, 1208 init->misc_control.mask); 1209 1210 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing); 1211 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low); 1212 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high); 1213 1214 if (init->m1xclk) { 1215 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk); 1216 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk); 1217 } 1218 1219 if (init->mclk) { 1220 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); 1221 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); 1222 } 1223 1224} 1225 1226/* Check the PLL sources for the M1CLK and M1XCLK 1227 * 1228 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then 1229 * there is a risk (see errata AB-5) that the SM501 will cease proper 1230 * function. If this happens, then it is likely the SM501 will 1231 * hang the system. 1232*/ 1233 1234static int sm501_check_clocks(struct sm501_devdata *sm) 1235{ 1236 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 1237 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); 1238 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); 1239 1240 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0)); 1241} 1242 1243static unsigned int sm501_mem_local[] = { 1244 [0] = 4*1024*1024, 1245 [1] = 8*1024*1024, 1246 [2] = 16*1024*1024, 1247 [3] = 32*1024*1024, 1248 [4] = 64*1024*1024, 1249 [5] = 2*1024*1024, 1250}; 1251 1252/* sm501_init_dev 1253 * 1254 * Common init code for an SM501 1255*/ 1256 1257static int sm501_init_dev(struct sm501_devdata *sm) 1258{ 1259 struct sm501_initdata *idata; 1260 struct sm501_platdata *pdata; 1261 resource_size_t mem_avail; 1262 unsigned long dramctrl; 1263 unsigned long devid; 1264 int ret; 1265 1266 mutex_init(&sm->clock_lock); 1267 spin_lock_init(&sm->reg_lock); 1268 1269 INIT_LIST_HEAD(&sm->devices); 1270 1271 devid = smc501_readl(sm->regs + SM501_DEVICEID); 1272 1273 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { 1274 dev_err(sm->dev, "incorrect device id %08lx\n", devid); 1275 return -EINVAL; 1276 } 1277 1278 /* disable irqs */ 1279 smc501_writel(0, sm->regs + SM501_IRQ_MASK); 1280 1281 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL); 1282 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; 1283 1284 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", 1285 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq); 1286 1287 sm->rev = devid & SM501_DEVICEID_REVMASK; 1288 1289 sm501_dump_gate(sm); 1290 1291 ret = device_create_file(sm->dev, &dev_attr_dbg_regs); 1292 if (ret) 1293 dev_err(sm->dev, "failed to create debug regs file\n"); 1294 1295 sm501_dump_clk(sm); 1296 1297 /* check to see if we have some device initialisation */ 1298 1299 pdata = sm->platdata; 1300 idata = pdata ? pdata->init : NULL; 1301 1302 if (idata) { 1303 sm501_init_regs(sm, idata); 1304 1305 if (idata->devices & SM501_USE_USB_HOST) 1306 sm501_register_usbhost(sm, &mem_avail); 1307 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1)) 1308 sm501_register_uart(sm, idata->devices); 1309 if (idata->devices & SM501_USE_GPIO) 1310 sm501_register_gpio(sm); 1311 } 1312 1313 if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) { 1314 if (!sm501_gpio_isregistered(sm)) 1315 dev_err(sm->dev, "no gpio available for i2c gpio.\n"); 1316 else 1317 sm501_register_gpio_i2c(sm, pdata); 1318 } 1319 1320 ret = sm501_check_clocks(sm); 1321 if (ret) { 1322 dev_err(sm->dev, "M1X and M clocks sourced from different " 1323 "PLLs\n"); 1324 return -EINVAL; 1325 } 1326 1327 /* always create a framebuffer */ 1328 sm501_register_display(sm, &mem_avail); 1329 1330 return 0; 1331} 1332 1333static int sm501_plat_probe(struct platform_device *dev) 1334{ 1335 struct sm501_devdata *sm; 1336 int ret; 1337 1338 sm = kzalloc(sizeof(*sm), GFP_KERNEL); 1339 if (!sm) { 1340 ret = -ENOMEM; 1341 goto err1; 1342 } 1343 1344 sm->dev = &dev->dev; 1345 sm->pdev_id = dev->id; 1346 sm->platdata = dev_get_platdata(&dev->dev); 1347 1348 ret = platform_get_irq(dev, 0); 1349 if (ret < 0) 1350 goto err_res; 1351 sm->irq = ret; 1352 1353 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 1354 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1355 if (!sm->io_res || !sm->mem_res) { 1356 dev_err(&dev->dev, "failed to get IO resource\n"); 1357 ret = -ENOENT; 1358 goto err_res; 1359 } 1360 1361 sm->regs_claim = request_mem_region(sm->io_res->start, 1362 0x100, "sm501"); 1363 if (!sm->regs_claim) { 1364 dev_err(&dev->dev, "cannot claim registers\n"); 1365 ret = -EBUSY; 1366 goto err_res; 1367 } 1368 1369 platform_set_drvdata(dev, sm); 1370 1371 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res)); 1372 if (!sm->regs) { 1373 dev_err(&dev->dev, "cannot remap registers\n"); 1374 ret = -EIO; 1375 goto err_claim; 1376 } 1377 1378 ret = sm501_init_dev(sm); 1379 if (ret) 1380 goto err_unmap; 1381 1382 return 0; 1383 1384 err_unmap: 1385 iounmap(sm->regs); 1386 err_claim: 1387 release_mem_region(sm->io_res->start, 0x100); 1388 err_res: 1389 kfree(sm); 1390 err1: 1391 return ret; 1392 1393} 1394 1395/* power management support */ 1396 1397static void sm501_set_power(struct sm501_devdata *sm, int on) 1398{ 1399 struct sm501_platdata *pd = sm->platdata; 1400 1401 if (!pd) 1402 return; 1403 1404 if (pd->get_power) { 1405 if (pd->get_power(sm->dev) == on) { 1406 dev_dbg(sm->dev, "is already %d\n", on); 1407 return; 1408 } 1409 } 1410 1411 if (pd->set_power) { 1412 dev_dbg(sm->dev, "setting power to %d\n", on); 1413 1414 pd->set_power(sm->dev, on); 1415 sm501_mdelay(sm, 10); 1416 } 1417} 1418 1419static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) 1420{ 1421 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1422 1423 sm->in_suspend = 1; 1424 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 1425 1426 sm501_dump_regs(sm); 1427 1428 if (sm->platdata) { 1429 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF) 1430 sm501_set_power(sm, 0); 1431 } 1432 1433 return 0; 1434} 1435 1436static int sm501_plat_resume(struct platform_device *pdev) 1437{ 1438 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1439 1440 sm501_set_power(sm, 1); 1441 1442 sm501_dump_regs(sm); 1443 sm501_dump_gate(sm); 1444 sm501_dump_clk(sm); 1445 1446 /* check to see if we are in the same state as when suspended */ 1447 1448 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { 1449 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); 1450 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); 1451 1452 /* our suspend causes the controller state to change, 1453 * either by something attempting setup, power loss, 1454 * or an external reset event on power change */ 1455 1456 if (sm->platdata && sm->platdata->init) { 1457 sm501_init_regs(sm, sm->platdata->init); 1458 } 1459 } 1460 1461 /* dump our state from resume */ 1462 1463 sm501_dump_regs(sm); 1464 sm501_dump_clk(sm); 1465 1466 sm->in_suspend = 0; 1467 1468 return 0; 1469} 1470 1471/* Initialisation data for PCI devices */ 1472 1473static struct sm501_initdata sm501_pci_initdata = { 1474 .gpio_high = { 1475 .set = 0x3F000000, /* 24bit panel */ 1476 .mask = 0x0, 1477 }, 1478 .misc_timing = { 1479 .set = 0x010100, /* SDRAM timing */ 1480 .mask = 0x1F1F00, 1481 }, 1482 .misc_control = { 1483 .set = SM501_MISC_PNL_24BIT, 1484 .mask = 0, 1485 }, 1486 1487 .devices = SM501_USE_ALL, 1488 1489 /* Errata AB-3 says that 72MHz is the fastest available 1490 * for 33MHZ PCI with proper bus-mastering operation */ 1491 1492 .mclk = 72 * MHZ, 1493 .m1xclk = 144 * MHZ, 1494}; 1495 1496static struct sm501_platdata_fbsub sm501_pdata_fbsub = { 1497 .flags = (SM501FB_FLAG_USE_INIT_MODE | 1498 SM501FB_FLAG_USE_HWCURSOR | 1499 SM501FB_FLAG_USE_HWACCEL | 1500 SM501FB_FLAG_DISABLE_AT_EXIT), 1501}; 1502 1503static struct sm501_platdata_fb sm501_fb_pdata = { 1504 .fb_route = SM501_FB_OWN, 1505 .fb_crt = &sm501_pdata_fbsub, 1506 .fb_pnl = &sm501_pdata_fbsub, 1507}; 1508 1509static struct sm501_platdata sm501_pci_platdata = { 1510 .init = &sm501_pci_initdata, 1511 .fb = &sm501_fb_pdata, 1512 .gpio_base = -1, 1513}; 1514 1515static int sm501_pci_probe(struct pci_dev *dev, 1516 const struct pci_device_id *id) 1517{ 1518 struct sm501_devdata *sm; 1519 int err; 1520 1521 sm = kzalloc(sizeof(*sm), GFP_KERNEL); 1522 if (!sm) { 1523 err = -ENOMEM; 1524 goto err1; 1525 } 1526 1527 /* set a default set of platform data */ 1528 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata; 1529 1530 /* set a hopefully unique id for our child platform devices */ 1531 sm->pdev_id = 32 + dev->devfn; 1532 1533 pci_set_drvdata(dev, sm); 1534 1535 err = pci_enable_device(dev); 1536 if (err) { 1537 dev_err(&dev->dev, "cannot enable device\n"); 1538 goto err2; 1539 } 1540 1541 sm->dev = &dev->dev; 1542 sm->irq = dev->irq; 1543 1544#ifdef __BIG_ENDIAN 1545 /* if the system is big-endian, we most probably have a 1546 * translation in the IO layer making the PCI bus little endian 1547 * so make the framebuffer swapped pixels */ 1548 1549 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN; 1550#endif 1551 1552 /* check our resources */ 1553 1554 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) { 1555 dev_err(&dev->dev, "region #0 is not memory?\n"); 1556 err = -EINVAL; 1557 goto err3; 1558 } 1559 1560 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) { 1561 dev_err(&dev->dev, "region #1 is not memory?\n"); 1562 err = -EINVAL; 1563 goto err3; 1564 } 1565 1566 /* make our resources ready for sharing */ 1567 1568 sm->io_res = &dev->resource[1]; 1569 sm->mem_res = &dev->resource[0]; 1570 1571 sm->regs_claim = request_mem_region(sm->io_res->start, 1572 0x100, "sm501"); 1573 if (!sm->regs_claim) { 1574 dev_err(&dev->dev, "cannot claim registers\n"); 1575 err= -EBUSY; 1576 goto err3; 1577 } 1578 1579 sm->regs = pci_ioremap_bar(dev, 1); 1580 if (!sm->regs) { 1581 dev_err(&dev->dev, "cannot remap registers\n"); 1582 err = -EIO; 1583 goto err4; 1584 } 1585 1586 sm501_init_dev(sm); 1587 return 0; 1588 1589 err4: 1590 release_mem_region(sm->io_res->start, 0x100); 1591 err3: 1592 pci_disable_device(dev); 1593 err2: 1594 kfree(sm); 1595 err1: 1596 return err; 1597} 1598 1599static void sm501_remove_sub(struct sm501_devdata *sm, 1600 struct sm501_device *smdev) 1601{ 1602 list_del(&smdev->list); 1603 platform_device_unregister(&smdev->pdev); 1604} 1605 1606static void sm501_dev_remove(struct sm501_devdata *sm) 1607{ 1608 struct sm501_device *smdev, *tmp; 1609 1610 list_for_each_entry_safe(smdev, tmp, &sm->devices, list) 1611 sm501_remove_sub(sm, smdev); 1612 1613 device_remove_file(sm->dev, &dev_attr_dbg_regs); 1614 1615 sm501_gpio_remove(sm); 1616} 1617 1618static void sm501_pci_remove(struct pci_dev *dev) 1619{ 1620 struct sm501_devdata *sm = pci_get_drvdata(dev); 1621 1622 sm501_dev_remove(sm); 1623 iounmap(sm->regs); 1624 1625 release_mem_region(sm->io_res->start, 0x100); 1626 1627 pci_disable_device(dev); 1628} 1629 1630static void sm501_plat_remove(struct platform_device *dev) 1631{ 1632 struct sm501_devdata *sm = platform_get_drvdata(dev); 1633 1634 sm501_dev_remove(sm); 1635 iounmap(sm->regs); 1636 1637 release_mem_region(sm->io_res->start, 0x100); 1638} 1639 1640static const struct pci_device_id sm501_pci_tbl[] = { 1641 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1642 { 0, }, 1643}; 1644 1645MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); 1646 1647static struct pci_driver sm501_pci_driver = { 1648 .name = "sm501", 1649 .id_table = sm501_pci_tbl, 1650 .probe = sm501_pci_probe, 1651 .remove = sm501_pci_remove, 1652}; 1653 1654MODULE_ALIAS("platform:sm501"); 1655 1656static const struct of_device_id of_sm501_match_tbl[] = { 1657 { .compatible = "smi,sm501", }, 1658 { /* end */ } 1659}; 1660MODULE_DEVICE_TABLE(of, of_sm501_match_tbl); 1661 1662static struct platform_driver sm501_plat_driver = { 1663 .driver = { 1664 .name = "sm501", 1665 .of_match_table = of_sm501_match_tbl, 1666 }, 1667 .probe = sm501_plat_probe, 1668 .remove = sm501_plat_remove, 1669 .suspend = pm_sleep_ptr(sm501_plat_suspend), 1670 .resume = pm_sleep_ptr(sm501_plat_resume), 1671}; 1672 1673static int __init sm501_base_init(void) 1674{ 1675 int ret; 1676 1677 ret = platform_driver_register(&sm501_plat_driver); 1678 if (ret < 0) 1679 return ret; 1680 1681 return pci_register_driver(&sm501_pci_driver); 1682} 1683 1684static void __exit sm501_base_exit(void) 1685{ 1686 platform_driver_unregister(&sm501_plat_driver); 1687 pci_unregister_driver(&sm501_pci_driver); 1688} 1689 1690module_init(sm501_base_init); 1691module_exit(sm501_base_exit); 1692 1693MODULE_DESCRIPTION("SM501 Core Driver"); 1694MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders"); 1695MODULE_LICENSE("GPL v2");
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