sec-irq.c

  1// SPDX-License-Identifier: GPL-2.0+
  2//
  3// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
  4//              http://www.samsung.com
  5
  6#include <linux/array_size.h>
  7#include <linux/build_bug.h>
  8#include <linux/dev_printk.h>
  9#include <linux/interrupt.h>
 10#include <linux/irq.h>
 11#include <linux/mfd/samsung/core.h>
 12#include <linux/mfd/samsung/irq.h>
 13#include <linux/mfd/samsung/s2mpg10.h>
 14#include <linux/mfd/samsung/s2mps11.h>
 15#include <linux/mfd/samsung/s2mps14.h>
 16#include <linux/mfd/samsung/s2mpu02.h>
 17#include <linux/mfd/samsung/s2mpu05.h>
 18#include <linux/mfd/samsung/s5m8767.h>
 19#include <linux/regmap.h>
 20#include "sec-core.h"
 21
 22static const struct regmap_irq s2mpg10_irqs[] = {
 23	REGMAP_IRQ_REG(S2MPG10_COMMON_IRQ_PMIC, 0, S2MPG10_COMMON_INT_SRC_PMIC),
 24	/* No documentation or other reference for remaining bits */
 25	REGMAP_IRQ_REG(S2MPG10_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)),
 26};
 27
 28static const struct regmap_irq s2mpg10_pmic_irqs[] = {
 29	REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONF, 0, S2MPG10_IRQ_PWRONF_MASK),
 30	REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONR, 0, S2MPG10_IRQ_PWRONR_MASK),
 31	REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBF, 0, S2MPG10_IRQ_JIGONBF_MASK),
 32	REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBR, 0, S2MPG10_IRQ_JIGONBR_MASK),
 33	REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBF, 0, S2MPG10_IRQ_ACOKBF_MASK),
 34	REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBR, 0, S2MPG10_IRQ_ACOKBR_MASK),
 35	REGMAP_IRQ_REG(S2MPG10_IRQ_PWRON1S, 0, S2MPG10_IRQ_PWRON1S_MASK),
 36	REGMAP_IRQ_REG(S2MPG10_IRQ_MRB, 0, S2MPG10_IRQ_MRB_MASK),
 37
 38	REGMAP_IRQ_REG(S2MPG10_IRQ_RTC60S, 1, S2MPG10_IRQ_RTC60S_MASK),
 39	REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA1, 1, S2MPG10_IRQ_RTCA1_MASK),
 40	REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA0, 1, S2MPG10_IRQ_RTCA0_MASK),
 41	REGMAP_IRQ_REG(S2MPG10_IRQ_RTC1S, 1, S2MPG10_IRQ_RTC1S_MASK),
 42	REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_COLDRST, 1, S2MPG10_IRQ_WTSR_COLDRST_MASK),
 43	REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR, 1, S2MPG10_IRQ_WTSR_MASK),
 44	REGMAP_IRQ_REG(S2MPG10_IRQ_WRST, 1, S2MPG10_IRQ_WRST_MASK),
 45	REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL, 1, S2MPG10_IRQ_SMPL_MASK),
 46
 47	REGMAP_IRQ_REG(S2MPG10_IRQ_120C, 2, S2MPG10_IRQ_INT120C_MASK),
 48	REGMAP_IRQ_REG(S2MPG10_IRQ_140C, 2, S2MPG10_IRQ_INT140C_MASK),
 49	REGMAP_IRQ_REG(S2MPG10_IRQ_TSD, 2, S2MPG10_IRQ_TSD_MASK),
 50	REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT1, 2, S2MPG10_IRQ_PIF_TIMEOUT1_MASK),
 51	REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT2, 2, S2MPG10_IRQ_PIF_TIMEOUT2_MASK),
 52	REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_PARITY_ERR, 2, S2MPG10_IRQ_SPD_PARITY_ERR_MASK),
 53	REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_ABNORMAL_STOP, 2, S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK),
 54	REGMAP_IRQ_REG(S2MPG10_IRQ_PMETER_OVERF, 2, S2MPG10_IRQ_PMETER_OVERF_MASK),
 55
 56	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B1M, 3, S2MPG10_IRQ_OCP_B1M_MASK),
 57	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B2M, 3, S2MPG10_IRQ_OCP_B2M_MASK),
 58	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B3M, 3, S2MPG10_IRQ_OCP_B3M_MASK),
 59	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B4M, 3, S2MPG10_IRQ_OCP_B4M_MASK),
 60	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B5M, 3, S2MPG10_IRQ_OCP_B5M_MASK),
 61	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B6M, 3, S2MPG10_IRQ_OCP_B6M_MASK),
 62	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B7M, 3, S2MPG10_IRQ_OCP_B7M_MASK),
 63	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B8M, 3, S2MPG10_IRQ_OCP_B8M_MASK),
 64
 65	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B9M, 4, S2MPG10_IRQ_OCP_B9M_MASK),
 66	REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B10M, 4, S2MPG10_IRQ_OCP_B10M_MASK),
 67	REGMAP_IRQ_REG(S2MPG10_IRQ_WLWP_ACC, 4, S2MPG10_IRQ_WLWP_ACC_MASK),
 68	REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL_TIMEOUT, 4, S2MPG10_IRQ_SMPL_TIMEOUT_MASK),
 69	REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_TIMEOUT, 4, S2MPG10_IRQ_WTSR_TIMEOUT_MASK),
 70	REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_SRP_PKT_RST, 4, S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK),
 71
 72	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH0, 5, S2MPG10_IRQ_PWR_WARN_CH0_MASK),
 73	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH1, 5, S2MPG10_IRQ_PWR_WARN_CH1_MASK),
 74	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH2, 5, S2MPG10_IRQ_PWR_WARN_CH2_MASK),
 75	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH3, 5, S2MPG10_IRQ_PWR_WARN_CH3_MASK),
 76	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH4, 5, S2MPG10_IRQ_PWR_WARN_CH4_MASK),
 77	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH5, 5, S2MPG10_IRQ_PWR_WARN_CH5_MASK),
 78	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH6, 5, S2MPG10_IRQ_PWR_WARN_CH6_MASK),
 79	REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK),
 80};
 81
 82static const struct regmap_irq s2mps11_irqs[] = {
 83	REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
 84	REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
 85	REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
 86	REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
 87	REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
 88	REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
 89	REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
 90	REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
 91
 92	REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
 93	REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
 94	REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
 95	REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
 96	REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
 97	REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
 98
 99	REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
100	REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
101};
102
103static const struct regmap_irq s2mps14_irqs[] = {
104	REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
105	REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
106	REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
107	REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
108	REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
109	REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
110	REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
111	REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
112
113	REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
114	REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
115	REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
116	REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
117	REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
118	REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
119
120	REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
121	REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
122	REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
123};
124
125static const struct regmap_irq s2mpu02_irqs[] = {
126	REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
127	REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
128	REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
129	REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
130	REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
131	REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
132	REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
133	REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
134
135	REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
136	REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
137	REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
138	REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
139	REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
140	REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
141
142	REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
143	REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
144	REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
145};
146
147static const struct regmap_irq s2mpu05_irqs[] = {
148	REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONF, 0, S2MPU05_IRQ_PWRONF_MASK),
149	REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONR, 0, S2MPU05_IRQ_PWRONR_MASK),
150	REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBF, 0, S2MPU05_IRQ_JIGONBF_MASK),
151	REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBR, 0, S2MPU05_IRQ_JIGONBR_MASK),
152	REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKF, 0, S2MPU05_IRQ_ACOKF_MASK),
153	REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKR, 0, S2MPU05_IRQ_ACOKR_MASK),
154	REGMAP_IRQ_REG(S2MPU05_IRQ_PWRON1S, 0, S2MPU05_IRQ_PWRON1S_MASK),
155	REGMAP_IRQ_REG(S2MPU05_IRQ_MRB, 0, S2MPU05_IRQ_MRB_MASK),
156	REGMAP_IRQ_REG(S2MPU05_IRQ_RTC60S, 1, S2MPU05_IRQ_RTC60S_MASK),
157	REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA1, 1, S2MPU05_IRQ_RTCA1_MASK),
158	REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA0, 1, S2MPU05_IRQ_RTCA0_MASK),
159	REGMAP_IRQ_REG(S2MPU05_IRQ_SMPL, 1, S2MPU05_IRQ_SMPL_MASK),
160	REGMAP_IRQ_REG(S2MPU05_IRQ_RTC1S, 1, S2MPU05_IRQ_RTC1S_MASK),
161	REGMAP_IRQ_REG(S2MPU05_IRQ_WTSR, 1, S2MPU05_IRQ_WTSR_MASK),
162	REGMAP_IRQ_REG(S2MPU05_IRQ_INT120C, 2, S2MPU05_IRQ_INT120C_MASK),
163	REGMAP_IRQ_REG(S2MPU05_IRQ_INT140C, 2, S2MPU05_IRQ_INT140C_MASK),
164	REGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK),
165};
166
167static const struct regmap_irq s5m8767_irqs[] = {
168	REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK),
169	REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK),
170	REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK),
171	REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK),
172	REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK),
173	REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK),
174	REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK),
175
176	REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK),
177	REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK),
178	REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK),
179	REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK),
180
181	REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK),
182	REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK),
183	REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK),
184	REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK),
185	REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK),
186	REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),
187};
188
189/* All S2MPG10 interrupt sources are read-only and don't require clearing */
190static const struct regmap_irq_chip s2mpg10_irq_chip = {
191	.name = "s2mpg10",
192	.status_base = S2MPG10_COMMON_INT,
193	.mask_base = S2MPG10_COMMON_INT_MASK,
194	.num_regs = 1,
195	.irqs = s2mpg10_irqs,
196	.num_irqs = ARRAY_SIZE(s2mpg10_irqs),
197};
198
199static const struct regmap_irq_chip s2mpg10_irq_chip_pmic = {
200	.name = "s2mpg10-pmic",
201	.domain_suffix = "pmic",
202	.status_base = S2MPG10_PMIC_INT1,
203	.mask_base = S2MPG10_PMIC_INT1M,
204	.num_regs = 6,
205	.irqs = s2mpg10_pmic_irqs,
206	.num_irqs = ARRAY_SIZE(s2mpg10_pmic_irqs),
207};
208
209static const struct regmap_irq_chip s2mps11_irq_chip = {
210	.name = "s2mps11",
211	.irqs = s2mps11_irqs,
212	.num_irqs = ARRAY_SIZE(s2mps11_irqs),
213	.num_regs = 3,
214	.status_base = S2MPS11_REG_INT1,
215	.mask_base = S2MPS11_REG_INT1M,
216	.ack_base = S2MPS11_REG_INT1,
217};
218
219#define S2MPS1X_IRQ_CHIP_COMMON_DATA		\
220	.irqs = s2mps14_irqs,			\
221	.num_irqs = ARRAY_SIZE(s2mps14_irqs),	\
222	.num_regs = 3,				\
223	.status_base = S2MPS14_REG_INT1,	\
224	.mask_base = S2MPS14_REG_INT1M,		\
225	.ack_base = S2MPS14_REG_INT1		\
226
227static const struct regmap_irq_chip s2mps13_irq_chip = {
228	.name = "s2mps13",
229	S2MPS1X_IRQ_CHIP_COMMON_DATA,
230};
231
232static const struct regmap_irq_chip s2mps14_irq_chip = {
233	.name = "s2mps14",
234	S2MPS1X_IRQ_CHIP_COMMON_DATA,
235};
236
237static const struct regmap_irq_chip s2mps15_irq_chip = {
238	.name = "s2mps15",
239	S2MPS1X_IRQ_CHIP_COMMON_DATA,
240};
241
242static const struct regmap_irq_chip s2mpu02_irq_chip = {
243	.name = "s2mpu02",
244	.irqs = s2mpu02_irqs,
245	.num_irqs = ARRAY_SIZE(s2mpu02_irqs),
246	.num_regs = 3,
247	.status_base = S2MPU02_REG_INT1,
248	.mask_base = S2MPU02_REG_INT1M,
249	.ack_base = S2MPU02_REG_INT1,
250};
251
252static const struct regmap_irq_chip s2mpu05_irq_chip = {
253	.name = "s2mpu05",
254	.irqs = s2mpu05_irqs,
255	.num_irqs = ARRAY_SIZE(s2mpu05_irqs),
256	.num_regs = 3,
257	.status_base = S2MPU05_REG_INT1,
258	.mask_base = S2MPU05_REG_INT1M,
259	.ack_base = S2MPU05_REG_INT1,
260};
261
262static const struct regmap_irq_chip s5m8767_irq_chip = {
263	.name = "s5m8767",
264	.irqs = s5m8767_irqs,
265	.num_irqs = ARRAY_SIZE(s5m8767_irqs),
266	.num_regs = 3,
267	.status_base = S5M8767_REG_INT1,
268	.mask_base = S5M8767_REG_INT1M,
269	.ack_base = S5M8767_REG_INT1,
270};
271
272static int s2mpg1x_add_chained_irq_chip(struct device *dev, struct regmap *regmap, int pirq,
273					struct regmap_irq_chip_data *parent,
274					const struct regmap_irq_chip *chip,
275					struct regmap_irq_chip_data **data)
276{
277	int irq, ret;
278
279	irq = regmap_irq_get_virq(parent, pirq);
280	if (irq < 0)
281		return dev_err_probe(dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n", pirq,
282				     chip->name);
283
284	ret = devm_regmap_add_irq_chip(dev, regmap, irq, IRQF_ONESHOT | IRQF_SHARED, 0, chip, data);
285	if (ret)
286		return dev_err_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name);
287
288	return 0;
289}
290
291static int sec_irq_init_s2mpg1x(struct sec_pmic_dev *sec_pmic)
292{
293	const struct regmap_irq_chip *irq_chip, *chained_irq_chip;
294	struct regmap_irq_chip_data *irq_data;
295	struct regmap *regmap_common;
296	int chained_pirq;
297	int ret;
298
299	switch (sec_pmic->device_type) {
300	case S2MPG10:
301		irq_chip = &s2mpg10_irq_chip;
302		chained_irq_chip = &s2mpg10_irq_chip_pmic;
303		chained_pirq = S2MPG10_COMMON_IRQ_PMIC;
304		break;
305	default:
306		return dev_err_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n",
307				     sec_pmic->device_type);
308	}
309
310	regmap_common = dev_get_regmap(sec_pmic->dev, "common");
311	if (!regmap_common)
312		return dev_err_probe(sec_pmic->dev, -EINVAL, "No 'common' regmap %d\n",
313				     sec_pmic->device_type);
314
315	ret = devm_regmap_add_irq_chip(sec_pmic->dev, regmap_common, sec_pmic->irq, IRQF_ONESHOT, 0,
316				       irq_chip, &irq_data);
317	if (ret)
318		return dev_err_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n",
319				     irq_chip->name);
320
321	return s2mpg1x_add_chained_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic, chained_pirq,
322					    irq_data, chained_irq_chip, &sec_pmic->irq_data);
323}
324
325int sec_irq_init(struct sec_pmic_dev *sec_pmic)
326{
327	const struct regmap_irq_chip *sec_irq_chip;
328	int ret;
329
330	switch (sec_pmic->device_type) {
331	case S5M8767X:
332		sec_irq_chip = &s5m8767_irq_chip;
333		break;
334	case S2DOS05:
335		return 0;
336	case S2MPA01:
337		sec_irq_chip = &s2mps14_irq_chip;
338		break;
339	case S2MPG10:
340		return sec_irq_init_s2mpg1x(sec_pmic);
341	case S2MPS11X:
342		sec_irq_chip = &s2mps11_irq_chip;
343		break;
344	case S2MPS13X:
345		sec_irq_chip = &s2mps13_irq_chip;
346		break;
347	case S2MPS14X:
348		sec_irq_chip = &s2mps14_irq_chip;
349		break;
350	case S2MPS15X:
351		sec_irq_chip = &s2mps15_irq_chip;
352		break;
353	case S2MPU02:
354		sec_irq_chip = &s2mpu02_irq_chip;
355		break;
356	case S2MPU05:
357		sec_irq_chip = &s2mpu05_irq_chip;
358		break;
359	default:
360		return dev_err_probe(sec_pmic->dev, -EINVAL,
361				     "Unsupported device type %d\n",
362				     sec_pmic->device_type);
363	}
364
365	if (!sec_pmic->irq) {
366		dev_warn(sec_pmic->dev,
367			 "No interrupt specified, no interrupts\n");
368		return 0;
369	}
370
371	ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic,
372				       sec_pmic->irq, IRQF_ONESHOT,
373				       0, sec_irq_chip, &sec_pmic->irq_data);
374	if (ret)
375		return dev_err_probe(sec_pmic->dev, ret,
376				     "Failed to add %s IRQ chip\n",
377				     sec_irq_chip->name);
378
379	/*
380	 * The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11
381	 * so the interrupt number must be consistent.
382	 */
383	BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0);
384
385	return 0;
386}