rohm-bd71828.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2//
  3// Copyright (C) 2019 ROHM Semiconductors
  4//
  5// ROHM BD71828/BD71815 PMIC driver
  6
  7#include <linux/gpio_keys.h>
  8#include <linux/i2c.h>
  9#include <linux/input.h>
 10#include <linux/interrupt.h>
 11#include <linux/ioport.h>
 12#include <linux/irq.h>
 13#include <linux/mfd/core.h>
 14#include <linux/mfd/rohm-bd71815.h>
 15#include <linux/mfd/rohm-bd71828.h>
 16#include <linux/mfd/rohm-generic.h>
 17#include <linux/module.h>
 18#include <linux/of.h>
 19#include <linux/regmap.h>
 20#include <linux/types.h>
 21
 22static struct gpio_keys_button button = {
 23	.code = KEY_POWER,
 24	.gpio = -1,
 25	.type = EV_KEY,
 26};
 27
 28static const struct gpio_keys_platform_data bd71828_powerkey_data = {
 29	.buttons = &button,
 30	.nbuttons = 1,
 31	.name = "bd71828-pwrkey",
 32};
 33
 34static const struct resource bd71815_rtc_irqs[] = {
 35	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"),
 36	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"),
 37	DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"),
 38};
 39
 40static const struct resource bd71828_rtc_irqs[] = {
 41	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"),
 42	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"),
 43	DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"),
 44};
 45
 46static const struct resource bd71815_power_irqs[] = {
 47	DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
 48	DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"),
 49	DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"),
 50	DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"),
 51	DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"),
 52	DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"),
 53	DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"),
 54	DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"),
 55	DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"),
 56	DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"),
 57	DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"),
 58	DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"),
 59	DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"),
 60	DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"),
 61	DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"),
 62	DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"),
 63	DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"),
 64	DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"),
 65	DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"),
 66	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"),
 67	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"),
 68	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"),
 69	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"),
 70	DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"),
 71	DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"),
 72	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"),
 73	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"),
 74	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"),
 75	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"),
 76	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"),
 77	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"),
 78	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"),
 79	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"),
 80	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"),
 81	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"),
 82	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"),
 83	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"),
 84	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"),
 85	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"),
 86	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"),
 87	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"),
 88	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"),
 89	DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"),
 90	DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"),
 91	DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"),
 92	DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"),
 93	DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"),
 94};
 95
 96static const struct mfd_cell bd71815_mfd_cells[] = {
 97	{ .name = "bd71815-pmic", },
 98	{ .name = "bd71815-clk", },
 99	{ .name = "bd71815-gpo", },
100	{
101		.name = "bd71815-power",
102		.num_resources = ARRAY_SIZE(bd71815_power_irqs),
103		.resources = &bd71815_power_irqs[0],
104	},
105	{
106		.name = "bd71815-rtc",
107		.num_resources = ARRAY_SIZE(bd71815_rtc_irqs),
108		.resources = &bd71815_rtc_irqs[0],
109	},
110};
111
112static const struct resource bd71828_power_irqs[] = {
113	DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE,
114			     "bd71828-chg-done"),
115	DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"),
116	DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"),
117	DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES,
118			     "bd71828-vbat-normal"),
119	DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"),
120	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"),
121	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"),
122	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"),
123	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES,
124			     "bd71828-btemp-warm"),
125	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET,
126			     "bd71828-temp-hi"),
127	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES,
128			     "bd71828-temp-norm"),
129	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET,
130			     "bd71828-temp-125-over"),
131	DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES,
132			     "bd71828-temp-125-under"),
133};
134
135static struct mfd_cell bd71828_mfd_cells[] = {
136	{ .name = "bd71828-pmic", },
137	{ .name = "bd71828-gpio", },
138	{ .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" },
139	/*
140	 * We use BD71837 driver to drive the clock block. Only differences to
141	 * BD70528 clock gate are the register address and mask.
142	 */
143	{ .name = "bd71828-clk", },
144	{
145		.name = "bd71828-power",
146		.resources = bd71828_power_irqs,
147		.num_resources = ARRAY_SIZE(bd71828_power_irqs),
148	}, {
149		.name = "bd71828-rtc",
150		.resources = bd71828_rtc_irqs,
151		.num_resources = ARRAY_SIZE(bd71828_rtc_irqs),
152	}, {
153		.name = "gpio-keys",
154		.platform_data = &bd71828_powerkey_data,
155		.pdata_size = sizeof(bd71828_powerkey_data),
156	},
157};
158
159static const struct regmap_range bd71815_volatile_ranges[] = {
160	{
161		.range_min = BD71815_REG_SEC,
162		.range_max = BD71815_REG_YEAR,
163	}, {
164		.range_min = BD71815_REG_CONF,
165		.range_max = BD71815_REG_BAT_TEMP,
166	}, {
167		.range_min = BD71815_REG_VM_IBAT_U,
168		.range_max = BD71815_REG_CC_CTRL,
169	}, {
170		.range_min = BD71815_REG_CC_STAT,
171		.range_max = BD71815_REG_CC_CURCD_L,
172	}, {
173		.range_min = BD71815_REG_VM_BTMP_MON,
174		.range_max = BD71815_REG_VM_BTMP_MON,
175	}, {
176		.range_min = BD71815_REG_INT_STAT,
177		.range_max = BD71815_REG_INT_UPDATE,
178	}, {
179		.range_min = BD71815_REG_VM_VSYS_U,
180		.range_max = BD71815_REG_REX_CTRL_1,
181	}, {
182		.range_min = BD71815_REG_FULL_CCNTD_3,
183		.range_max = BD71815_REG_CCNTD_CHG_2,
184	},
185};
186
187static const struct regmap_range bd71828_volatile_ranges[] = {
188	{
189		.range_min = BD71828_REG_PS_CTRL_1,
190		.range_max = BD71828_REG_PS_CTRL_1,
191	}, {
192		.range_min = BD71828_REG_PS_CTRL_3,
193		.range_max = BD71828_REG_PS_CTRL_3,
194	}, {
195		.range_min = BD71828_REG_RTC_SEC,
196		.range_max = BD71828_REG_RTC_YEAR,
197	}, {
198		/*
199		 * For now make all charger registers volatile because many
200		 * needs to be and because the charger block is not that
201		 * performance critical.
202		 */
203		.range_min = BD71828_REG_CHG_STATE,
204		.range_max = BD71828_REG_CHG_FULL,
205	}, {
206		.range_min = BD71828_REG_INT_MAIN,
207		.range_max = BD71828_REG_IO_STAT,
208	},
209};
210
211static const struct regmap_access_table bd71815_volatile_regs = {
212	.yes_ranges = &bd71815_volatile_ranges[0],
213	.n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges),
214};
215
216static const struct regmap_access_table bd71828_volatile_regs = {
217	.yes_ranges = &bd71828_volatile_ranges[0],
218	.n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges),
219};
220
221static const struct regmap_config bd71815_regmap = {
222	.reg_bits = 8,
223	.val_bits = 8,
224	.volatile_table = &bd71815_volatile_regs,
225	.max_register = BD71815_MAX_REGISTER - 1,
226	.cache_type = REGCACHE_MAPLE,
227};
228
229static const struct regmap_config bd71828_regmap = {
230	.reg_bits = 8,
231	.val_bits = 8,
232	.volatile_table = &bd71828_volatile_regs,
233	.max_register = BD71828_MAX_REGISTER,
234	.cache_type = REGCACHE_MAPLE,
235};
236
237/*
238 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
239 * access corect sub-IRQ registers based on bits that are set in main IRQ
240 * register. BD71815 and BD71828 have same sub-register-block offests.
241 */
242
243static unsigned int bit0_offsets[] = {11};		/* RTC IRQ */
244static unsigned int bit1_offsets[] = {10};		/* TEMP IRQ */
245static unsigned int bit2_offsets[] = {6, 7, 8, 9};	/* BAT MON IRQ */
246static unsigned int bit3_offsets[] = {5};		/* BAT IRQ */
247static unsigned int bit4_offsets[] = {4};		/* CHG IRQ */
248static unsigned int bit5_offsets[] = {3};		/* VSYS IRQ */
249static unsigned int bit6_offsets[] = {1, 2};		/* DCIN IRQ */
250static unsigned int bit7_offsets[] = {0};		/* BUCK IRQ */
251
252static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = {
253	REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
254	REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
255	REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
256	REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
257	REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
258	REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
259	REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
260	REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
261};
262
263static const struct regmap_irq bd71815_irqs[] = {
264	REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK),
265	REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK),
266	REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK),
267	REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK),
268	REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK),
269	REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK),
270	REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK),
271	REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK),
272	/* DCIN1 interrupts */
273	REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK),
274	REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK),
275	REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK),
276	REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK),
277	REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK),
278	/* DCIN2 interrupts */
279	REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK),
280	REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK),
281	REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK),
282	/* Vsys */
283	REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK),
284	REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK),
285	REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK),
286	REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK),
287	REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK),
288	REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK),
289	/* Charger */
290	REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK),
291	REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK),
292	REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK),
293	REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK),
294	REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4,
295		       BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
296	REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK),
297	/* Battery */
298	REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK),
299	REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK),
300	REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK),
301	REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK),
302	REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK),
303	REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK),
304	/* Battery Mon 1 */
305	REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK),
306	REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK),
307	REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK),
308	REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK),
309	REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK),
310	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK),
311	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK),
312	/* Battery Mon 2 */
313	REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK),
314	REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK),
315	/* Battery Mon 3 (Coulomb counter) */
316	REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK),
317	REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK),
318	REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK),
319	/* Battery Mon 4 */
320	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK),
321	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK),
322	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK),
323	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK),
324	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK),
325	REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK),
326	/* Temperature */
327	REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK),
328	REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK),
329	REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK),
330	REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK),
331	REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10,
332		       BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK),
333	REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10,
334		       BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK),
335	REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10,
336		       BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK),
337	REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10,
338		       BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK),
339	/* RTC Alarm */
340	REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK),
341	REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK),
342	REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK),
343};
344
345static const struct regmap_irq bd71828_irqs[] = {
346	REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK),
347	REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK),
348	REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK),
349	REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK),
350	REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK),
351	REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK),
352	REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK),
353	REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK),
354	/* DCIN1 interrupts */
355	REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK),
356	REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK),
357	REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK),
358	REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK),
359	/* DCIN2 interrupts */
360	REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK),
361	REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK),
362	REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK),
363	REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK),
364	REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK),
365	REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK),
366	REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK),
367	REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK),
368	/* Vsys */
369	REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK),
370	REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK),
371	REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK),
372	REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK),
373	REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK),
374	REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK),
375	REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK),
376	REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK),
377	/* Charger */
378	REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK),
379	REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK),
380	REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK),
381	REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK),
382	REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK),
383	REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK),
384	REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4,
385		       BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
386	REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK),
387	/* Battery */
388	REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK),
389	REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK),
390	REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK),
391	REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK),
392	REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK),
393	REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK),
394	REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK),
395	/* Battery Mon 1 */
396	REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK),
397	REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK),
398	REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK),
399	REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK),
400	REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK),
401	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK),
402	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK),
403	/* Battery Mon 2 */
404	REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK),
405	REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK),
406	/* Battery Mon 3 (Coulomb counter) */
407	REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK),
408	REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK),
409	REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK),
410	/* Battery Mon 4 */
411	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK),
412	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK),
413	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK),
414	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK),
415	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK),
416	REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK),
417	/* Temperature */
418	REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK),
419	REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK),
420	REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK),
421	REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK),
422	REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10,
423		       BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK),
424	REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10,
425		       BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK),
426	REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10,
427		       BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK),
428	REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10,
429		       BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK),
430	/* RTC Alarm */
431	REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK),
432	REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK),
433	REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK),
434};
435
436static const struct regmap_irq_chip bd71828_irq_chip = {
437	.name = "bd71828_irq",
438	.main_status = BD71828_REG_INT_MAIN,
439	.irqs = &bd71828_irqs[0],
440	.num_irqs = ARRAY_SIZE(bd71828_irqs),
441	.status_base = BD71828_REG_INT_BUCK,
442	.unmask_base = BD71828_REG_INT_MASK_BUCK,
443	.ack_base = BD71828_REG_INT_BUCK,
444	.init_ack_masked = true,
445	.num_regs = 12,
446	.num_main_regs = 1,
447	.sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
448	.num_main_status_bits = 8,
449	.irq_reg_stride = 1,
450};
451
452static const struct regmap_irq_chip bd71815_irq_chip = {
453	.name = "bd71815_irq",
454	.main_status = BD71815_REG_INT_STAT,
455	.irqs = &bd71815_irqs[0],
456	.num_irqs = ARRAY_SIZE(bd71815_irqs),
457	.status_base = BD71815_REG_INT_STAT_01,
458	.unmask_base = BD71815_REG_INT_EN_01,
459	.ack_base = BD71815_REG_INT_STAT_01,
460	.init_ack_masked = true,
461	.num_regs = 12,
462	.num_main_regs = 1,
463	.sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
464	.num_main_status_bits = 8,
465	.irq_reg_stride = 1,
466};
467
468static int set_clk_mode(struct device *dev, struct regmap *regmap,
469			int clkmode_reg)
470{
471	int ret;
472	unsigned int open_drain;
473
474	ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain);
475	if (ret) {
476		if (ret == -EINVAL)
477			return 0;
478		return ret;
479	}
480	if (open_drain > 1) {
481		dev_err(dev, "bad clk32kout mode configuration");
482		return -EINVAL;
483	}
484
485	if (open_drain)
486		return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
487					  OUT32K_MODE_OPEN_DRAIN);
488
489	return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
490				  OUT32K_MODE_CMOS);
491}
492
493static struct i2c_client *bd71828_dev;
494static void bd71828_power_off(void)
495{
496	while (true) {
497		s32 val;
498
499		/* We are not allowed to sleep, so do not use regmap involving mutexes here. */
500		val = i2c_smbus_read_byte_data(bd71828_dev, BD71828_REG_PS_CTRL_1);
501		if (val >= 0)
502			i2c_smbus_write_byte_data(bd71828_dev,
503						  BD71828_REG_PS_CTRL_1,
504						  BD71828_MASK_STATE_HBNT | (u8)val);
505		mdelay(500);
506	}
507}
508
509static void bd71828_remove_poweroff(void *data)
510{
511	pm_power_off = NULL;
512}
513
514static int bd71828_i2c_probe(struct i2c_client *i2c)
515{
516	struct regmap_irq_chip_data *irq_data;
517	int ret;
518	struct regmap *regmap;
519	const struct regmap_config *regmap_config;
520	const struct regmap_irq_chip *irqchip;
521	unsigned int chip_type;
522	const struct mfd_cell *mfd;
523	int cells;
524	int button_irq;
525	int clkmode_reg;
526
527	if (!i2c->irq) {
528		dev_err(&i2c->dev, "No IRQ configured\n");
529		return -EINVAL;
530	}
531
532	chip_type = (unsigned int)(uintptr_t)
533		    of_device_get_match_data(&i2c->dev);
534	switch (chip_type) {
535	case ROHM_CHIP_TYPE_BD71828:
536		mfd = bd71828_mfd_cells;
537		cells = ARRAY_SIZE(bd71828_mfd_cells);
538		regmap_config = &bd71828_regmap;
539		irqchip = &bd71828_irq_chip;
540		clkmode_reg = BD71828_REG_OUT32K;
541		button_irq = BD71828_INT_SHORTPUSH;
542		break;
543	case ROHM_CHIP_TYPE_BD71815:
544		mfd = bd71815_mfd_cells;
545		cells = ARRAY_SIZE(bd71815_mfd_cells);
546		regmap_config = &bd71815_regmap;
547		irqchip = &bd71815_irq_chip;
548		clkmode_reg = BD71815_REG_OUT32K;
549		/*
550		 * If BD71817 support is needed we should be able to handle it
551		 * with proper DT configs + BD71815 drivers + power-button.
552		 * BD71815 data-sheet does not list the power-button IRQ so we
553		 * don't use it.
554		 */
555		button_irq = 0;
556		break;
557	default:
558		dev_err(&i2c->dev, "Unknown device type");
559		return -EINVAL;
560	}
561
562	regmap = devm_regmap_init_i2c(i2c, regmap_config);
563	if (IS_ERR(regmap))
564		return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
565				     "Failed to initialize Regmap\n");
566
567	ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
568				       IRQF_ONESHOT, 0, irqchip, &irq_data);
569	if (ret)
570		return dev_err_probe(&i2c->dev, ret,
571				     "Failed to add IRQ chip\n");
572
573	dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
574		irqchip->num_irqs);
575
576	if (button_irq) {
577		ret = regmap_irq_get_virq(irq_data, button_irq);
578		if (ret < 0)
579			return dev_err_probe(&i2c->dev, ret,
580					     "Failed to get the power-key IRQ\n");
581
582		button.irq = ret;
583	}
584
585	ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg);
586	if (ret)
587		return ret;
588
589	ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells,
590				   NULL, 0, regmap_irq_get_domain(irq_data));
591	if (ret)
592		return	dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
593
594	if (of_device_is_system_power_controller(i2c->dev.of_node) &&
595	    chip_type == ROHM_CHIP_TYPE_BD71828) {
596		if (!pm_power_off) {
597			bd71828_dev = i2c;
598			pm_power_off = bd71828_power_off;
599			ret = devm_add_action_or_reset(&i2c->dev,
600						       bd71828_remove_poweroff,
601						       NULL);
602		} else {
603			dev_warn(&i2c->dev, "Poweroff callback already assigned\n");
604		}
605	}
606
607	return ret;
608}
609
610static const struct of_device_id bd71828_of_match[] = {
611	{
612		.compatible = "rohm,bd71828",
613		.data = (void *)ROHM_CHIP_TYPE_BD71828,
614	}, {
615		.compatible = "rohm,bd71815",
616		.data = (void *)ROHM_CHIP_TYPE_BD71815,
617	 },
618	{ },
619};
620MODULE_DEVICE_TABLE(of, bd71828_of_match);
621
622static struct i2c_driver bd71828_drv = {
623	.driver = {
624		.name = "rohm-bd71828",
625		.of_match_table = bd71828_of_match,
626	},
627	.probe = bd71828_i2c_probe,
628};
629module_i2c_driver(bd71828_drv);
630
631MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
632MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver");
633MODULE_LICENSE("GPL");