rk8xx-core.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * MFD core driver for Rockchip RK8XX
  4 *
  5 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  6 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
  7 *
  8 * Author: Chris Zhong <zyw@rock-chips.com>
  9 * Author: Zhang Qing <zhangqing@rock-chips.com>
 10 * Author: Wadim Egorov <w.egorov@phytec.de>
 11 */
 12
 13#include <linux/bitfield.h>
 14#include <linux/interrupt.h>
 15#include <linux/mfd/rk808.h>
 16#include <linux/mfd/core.h>
 17#include <linux/module.h>
 18#include <linux/property.h>
 19#include <linux/regmap.h>
 20#include <linux/reboot.h>
 21
 22struct rk808_reg_data {
 23	int addr;
 24	int mask;
 25	int value;
 26};
 27
 28static const struct resource rtc_resources[] = {
 29	DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM),
 30};
 31
 32static const struct resource rk816_rtc_resources[] = {
 33	DEFINE_RES_IRQ(RK816_IRQ_RTC_ALARM),
 34};
 35
 36static const struct resource rk817_rtc_resources[] = {
 37	DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM),
 38};
 39
 40static const struct resource rk805_key_resources[] = {
 41	DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE),
 42	DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
 43};
 44
 45static struct resource rk806_pwrkey_resources[] = {
 46	DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL),
 47	DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE),
 48};
 49
 50static const struct resource rk817_pwrkey_resources[] = {
 51	DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
 52	DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
 53};
 54
 55static const struct resource rk817_charger_resources[] = {
 56	DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN),
 57	DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT),
 58};
 59
 60static const struct mfd_cell rk805s[] = {
 61	{ .name = "rk808-clkout", },
 62	{ .name = "rk808-regulator", },
 63	{ .name = "rk805-pinctrl", },
 64	{
 65		.name = "rk808-rtc",
 66		.num_resources = ARRAY_SIZE(rtc_resources),
 67		.resources = &rtc_resources[0],
 68	},
 69	{	.name = "rk805-pwrkey",
 70		.num_resources = ARRAY_SIZE(rk805_key_resources),
 71		.resources = &rk805_key_resources[0],
 72	},
 73};
 74
 75static const struct mfd_cell rk806s[] = {
 76	{ .name = "rk805-pinctrl", },
 77	{ .name = "rk808-regulator", },
 78	{
 79		.name = "rk805-pwrkey",
 80		.resources = rk806_pwrkey_resources,
 81		.num_resources = ARRAY_SIZE(rk806_pwrkey_resources),
 82	},
 83};
 84
 85static const struct mfd_cell rk808s[] = {
 86	{ .name = "rk808-clkout", },
 87	{ .name = "rk808-regulator", },
 88	{
 89		.name = "rk808-rtc",
 90		.num_resources = ARRAY_SIZE(rtc_resources),
 91		.resources = rtc_resources,
 92	},
 93};
 94
 95static const struct mfd_cell rk816s[] = {
 96	{ .name = "rk805-pinctrl", },
 97	{ .name = "rk808-clkout", },
 98	{ .name = "rk808-regulator", },
 99	{
100		.name = "rk805-pwrkey",
101		.num_resources = ARRAY_SIZE(rk805_key_resources),
102		.resources = rk805_key_resources,
103	},
104	{
105		.name = "rk808-rtc",
106		.num_resources = ARRAY_SIZE(rk816_rtc_resources),
107		.resources = rk816_rtc_resources,
108	},
109};
110
111static const struct mfd_cell rk817s[] = {
112	{ .name = "rk808-clkout", },
113	{ .name = "rk808-regulator", },
114	{
115		.name = "rk805-pwrkey",
116		.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
117		.resources = &rk817_pwrkey_resources[0],
118	},
119	{
120		.name = "rk808-rtc",
121		.num_resources = ARRAY_SIZE(rk817_rtc_resources),
122		.resources = &rk817_rtc_resources[0],
123	},
124	{ .name = "rk817-codec", },
125	{
126		.name = "rk817-charger",
127		.num_resources = ARRAY_SIZE(rk817_charger_resources),
128		.resources = &rk817_charger_resources[0],
129	},
130};
131
132static const struct mfd_cell rk818s[] = {
133	{ .name = "rk808-clkout", },
134	{ .name = "rk808-regulator", },
135	{
136		.name = "rk808-rtc",
137		.num_resources = ARRAY_SIZE(rtc_resources),
138		.resources = rtc_resources,
139	},
140};
141
142static const struct rk808_reg_data rk805_pre_init_reg[] = {
143	{RK805_BUCK1_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
144				 RK805_BUCK1_2_ILMAX_4000MA},
145	{RK805_BUCK2_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
146				 RK805_BUCK1_2_ILMAX_4000MA},
147	{RK805_BUCK3_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
148				 RK805_BUCK3_ILMAX_3000MA},
149	{RK805_BUCK4_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
150				 RK805_BUCK4_ILMAX_3500MA},
151	{RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA},
152	{RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
153};
154
155static const struct rk808_reg_data rk806_pre_init_reg[] = {
156	{ RK806_GPIO_INT_CONFIG, RK806_INT_POL_MSK, RK806_INT_POL_L },
157	{ RK806_SYS_CFG3, RK806_SLAVE_RESTART_FUN_MSK, RK806_SLAVE_RESTART_FUN_EN },
158	{ RK806_SYS_OPTION, RK806_SYS_ENB2_2M_MSK, RK806_SYS_ENB2_2M_EN },
159};
160
161static const struct rk808_reg_data rk808_pre_init_reg[] = {
162	{ RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_150MA },
163	{ RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_200MA },
164	{ RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
165	{ RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK,  BUCK_ILMIN_200MA },
166	{ RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK,  BUCK_ILMIN_200MA },
167	{ RK808_DCDC_UV_ACT_REG,  BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE},
168	{ RK808_VB_MON_REG,       MASK_ALL,         VB_LO_ACT |
169						    VB_LO_SEL_3500MV },
170};
171
172static const struct rk808_reg_data rk816_pre_init_reg[] = {
173	{ RK818_BUCK1_CONFIG_REG, RK817_RAMP_RATE_MASK,
174				  RK817_RAMP_RATE_12_5MV_PER_US },
175	{ RK818_BUCK2_CONFIG_REG, RK817_RAMP_RATE_MASK,
176				  RK817_RAMP_RATE_12_5MV_PER_US },
177	{ RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_250MA },
178	{ RK808_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP105C},
179	{ RK808_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
180			    RK808_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
181};
182
183static const struct rk808_reg_data rk817_pre_init_reg[] = {
184	{RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
185	/* Codec specific registers */
186	{ RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 },
187	{ RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 },
188	{ RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 },
189	{ RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 },
190	/* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */
191	{ RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 },
192	{ RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 },
193	{ RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 },
194	/* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */
195	{ RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 },
196	{ RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 },
197	{ RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 },
198	{ RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 },
199	{ RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 },
200	{ RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 },
201	{ RK817_CODEC_DADC_NG, MASK_ALL, 0x00 },
202	{ RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 },
203	{ RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff },
204	{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
205	{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
206	{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
207	{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
208	{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
209	{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
210	{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
211	{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
212	/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
213	{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
214	{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
215	{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
216	{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
217	{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
218	{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
219	{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
220	{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
221	{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
222	{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
223	{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
224	{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
225	{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
226	{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
227	{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
228	{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
229	{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
230	{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
231	/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
232	{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
233	{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
234	{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
235	{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
236	{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
237	{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
238	{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
239	{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
240	{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
241	{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
242	{ RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff },
243	{ RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 },
244	{ RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 },
245	{ RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 },
246	{ RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f },
247	{ RK817_CODEC_AHP_CP, MASK_ALL, 0x09 },
248	{ RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 },
249	{ RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 },
250	{ RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 },
251	{ RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 },
252	{ RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 },
253	{ RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 },
254	{ RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 },
255	{ RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 },
256	{ RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 },
257	{ RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 },
258	{ RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 },
259	{ RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 },
260	{ RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 },
261	{ RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 },
262	{ RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 },
263	{ RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 },
264	{RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
265	{RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
266					   RK817_HOTDIE_105 | RK817_TSD_140},
267};
268
269static const struct rk808_reg_data rk818_pre_init_reg[] = {
270	/* improve efficiency */
271	{ RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK,  BUCK_ILMIN_250MA },
272	{ RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_250MA },
273	{ RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
274	{ RK818_USB_CTRL_REG,	  RK818_USB_ILIM_SEL_MASK,
275						    RK818_USB_ILMIN_2000MA },
276	/* close charger when usb lower then 3.4V */
277	{ RK818_USB_CTRL_REG,	  RK818_USB_CHG_SD_VSEL_MASK,
278						    (0x7 << 4) },
279	/* no action when vref */
280	{ RK818_H5V_EN_REG,	  BIT(1),	    RK818_REF_RDY_CTRL },
281	/* enable HDMI 5V */
282	{ RK818_H5V_EN_REG,	  BIT(0),	    RK818_H5V_EN },
283	{ RK808_VB_MON_REG,	  MASK_ALL,	    VB_LO_ACT |
284						    VB_LO_SEL_3500MV },
285};
286
287static const struct regmap_irq rk805_irqs[] = {
288	[RK805_IRQ_PWRON_RISE] = {
289		.mask = RK805_IRQ_PWRON_RISE_MSK,
290		.reg_offset = 0,
291	},
292	[RK805_IRQ_VB_LOW] = {
293		.mask = RK805_IRQ_VB_LOW_MSK,
294		.reg_offset = 0,
295	},
296	[RK805_IRQ_PWRON] = {
297		.mask = RK805_IRQ_PWRON_MSK,
298		.reg_offset = 0,
299	},
300	[RK805_IRQ_PWRON_LP] = {
301		.mask = RK805_IRQ_PWRON_LP_MSK,
302		.reg_offset = 0,
303	},
304	[RK805_IRQ_HOTDIE] = {
305		.mask = RK805_IRQ_HOTDIE_MSK,
306		.reg_offset = 0,
307	},
308	[RK805_IRQ_RTC_ALARM] = {
309		.mask = RK805_IRQ_RTC_ALARM_MSK,
310		.reg_offset = 0,
311	},
312	[RK805_IRQ_RTC_PERIOD] = {
313		.mask = RK805_IRQ_RTC_PERIOD_MSK,
314		.reg_offset = 0,
315	},
316	[RK805_IRQ_PWRON_FALL] = {
317		.mask = RK805_IRQ_PWRON_FALL_MSK,
318		.reg_offset = 0,
319	},
320};
321
322static const struct regmap_irq rk806_irqs[] = {
323	/* INT_STS0 IRQs */
324	REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL),
325	REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE),
326	REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON),
327	REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP),
328	REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE),
329	REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE),
330	REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL),
331	REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO),
332	/* INT_STS1 IRQs */
333	REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0),
334	REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1),
335	REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2),
336	REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR),
337	REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO),
338	REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO),
339	REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO),
340	REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT),
341};
342
343static const struct regmap_irq rk808_irqs[] = {
344	/* INT_STS */
345	[RK808_IRQ_VOUT_LO] = {
346		.mask = RK808_IRQ_VOUT_LO_MSK,
347		.reg_offset = 0,
348	},
349	[RK808_IRQ_VB_LO] = {
350		.mask = RK808_IRQ_VB_LO_MSK,
351		.reg_offset = 0,
352	},
353	[RK808_IRQ_PWRON] = {
354		.mask = RK808_IRQ_PWRON_MSK,
355		.reg_offset = 0,
356	},
357	[RK808_IRQ_PWRON_LP] = {
358		.mask = RK808_IRQ_PWRON_LP_MSK,
359		.reg_offset = 0,
360	},
361	[RK808_IRQ_HOTDIE] = {
362		.mask = RK808_IRQ_HOTDIE_MSK,
363		.reg_offset = 0,
364	},
365	[RK808_IRQ_RTC_ALARM] = {
366		.mask = RK808_IRQ_RTC_ALARM_MSK,
367		.reg_offset = 0,
368	},
369	[RK808_IRQ_RTC_PERIOD] = {
370		.mask = RK808_IRQ_RTC_PERIOD_MSK,
371		.reg_offset = 0,
372	},
373
374	/* INT_STS2 */
375	[RK808_IRQ_PLUG_IN_INT] = {
376		.mask = RK808_IRQ_PLUG_IN_INT_MSK,
377		.reg_offset = 1,
378	},
379	[RK808_IRQ_PLUG_OUT_INT] = {
380		.mask = RK808_IRQ_PLUG_OUT_INT_MSK,
381		.reg_offset = 1,
382	},
383};
384
385static const unsigned int rk816_irq_status_offsets[] = {
386	RK816_IRQ_STS_OFFSET(RK816_INT_STS_REG1),
387	RK816_IRQ_STS_OFFSET(RK816_INT_STS_REG2),
388	RK816_IRQ_STS_OFFSET(RK816_INT_STS_REG3),
389};
390
391static const unsigned int rk816_irq_mask_offsets[] = {
392	RK816_IRQ_MSK_OFFSET(RK816_INT_STS_MSK_REG1),
393	RK816_IRQ_MSK_OFFSET(RK816_INT_STS_MSK_REG2),
394	RK816_IRQ_MSK_OFFSET(RK816_INT_STS_MSK_REG3),
395};
396
397static unsigned int rk816_get_irq_reg(struct regmap_irq_chip_data *data,
398				      unsigned int base, int index)
399{
400	unsigned int irq_reg = base;
401
402	switch (base) {
403	case RK816_INT_STS_REG1:
404		irq_reg += rk816_irq_status_offsets[index];
405		break;
406	case RK816_INT_STS_MSK_REG1:
407		irq_reg += rk816_irq_mask_offsets[index];
408		break;
409	}
410
411	return irq_reg;
412};
413
414static const struct regmap_irq rk816_irqs[] = {
415	/* INT_STS_REG1 IRQs */
416	REGMAP_IRQ_REG(RK816_IRQ_PWRON_FALL, 0, RK816_INT_STS_PWRON_FALL),
417	REGMAP_IRQ_REG(RK816_IRQ_PWRON_RISE, 0, RK816_INT_STS_PWRON_RISE),
418
419	/* INT_STS_REG2 IRQs  */
420	REGMAP_IRQ_REG(RK816_IRQ_VB_LOW, 1, RK816_INT_STS_VB_LOW),
421	REGMAP_IRQ_REG(RK816_IRQ_PWRON, 1, RK816_INT_STS_PWRON),
422	REGMAP_IRQ_REG(RK816_IRQ_PWRON_LP, 1, RK816_INT_STS_PWRON_LP),
423	REGMAP_IRQ_REG(RK816_IRQ_HOTDIE, 1, RK816_INT_STS_HOTDIE),
424	REGMAP_IRQ_REG(RK816_IRQ_RTC_ALARM, 1, RK816_INT_STS_RTC_ALARM),
425	REGMAP_IRQ_REG(RK816_IRQ_RTC_PERIOD, 1, RK816_INT_STS_RTC_PERIOD),
426	REGMAP_IRQ_REG(RK816_IRQ_USB_OV, 1, RK816_INT_STS_USB_OV),
427
428	/* INT_STS3 IRQs */
429	REGMAP_IRQ_REG(RK816_IRQ_PLUG_IN, 2, RK816_INT_STS_PLUG_IN),
430	REGMAP_IRQ_REG(RK816_IRQ_PLUG_OUT, 2, RK816_INT_STS_PLUG_OUT),
431	REGMAP_IRQ_REG(RK816_IRQ_CHG_OK, 2, RK816_INT_STS_CHG_OK),
432	REGMAP_IRQ_REG(RK816_IRQ_CHG_TE, 2, RK816_INT_STS_CHG_TE),
433	REGMAP_IRQ_REG(RK816_IRQ_CHG_TS, 2, RK816_INT_STS_CHG_TS),
434	REGMAP_IRQ_REG(RK816_IRQ_CHG_CVTLIM, 2, RK816_INT_STS_CHG_CVTLIM),
435	REGMAP_IRQ_REG(RK816_IRQ_DISCHG_ILIM, 2, RK816_INT_STS_DISCHG_ILIM),
436};
437
438static const struct regmap_irq rk818_irqs[] = {
439	/* INT_STS */
440	[RK818_IRQ_VOUT_LO] = {
441		.mask = RK818_IRQ_VOUT_LO_MSK,
442		.reg_offset = 0,
443	},
444	[RK818_IRQ_VB_LO] = {
445		.mask = RK818_IRQ_VB_LO_MSK,
446		.reg_offset = 0,
447	},
448	[RK818_IRQ_PWRON] = {
449		.mask = RK818_IRQ_PWRON_MSK,
450		.reg_offset = 0,
451	},
452	[RK818_IRQ_PWRON_LP] = {
453		.mask = RK818_IRQ_PWRON_LP_MSK,
454		.reg_offset = 0,
455	},
456	[RK818_IRQ_HOTDIE] = {
457		.mask = RK818_IRQ_HOTDIE_MSK,
458		.reg_offset = 0,
459	},
460	[RK818_IRQ_RTC_ALARM] = {
461		.mask = RK818_IRQ_RTC_ALARM_MSK,
462		.reg_offset = 0,
463	},
464	[RK818_IRQ_RTC_PERIOD] = {
465		.mask = RK818_IRQ_RTC_PERIOD_MSK,
466		.reg_offset = 0,
467	},
468	[RK818_IRQ_USB_OV] = {
469		.mask = RK818_IRQ_USB_OV_MSK,
470		.reg_offset = 0,
471	},
472
473	/* INT_STS2 */
474	[RK818_IRQ_PLUG_IN] = {
475		.mask = RK818_IRQ_PLUG_IN_MSK,
476		.reg_offset = 1,
477	},
478	[RK818_IRQ_PLUG_OUT] = {
479		.mask = RK818_IRQ_PLUG_OUT_MSK,
480		.reg_offset = 1,
481	},
482	[RK818_IRQ_CHG_OK] = {
483		.mask = RK818_IRQ_CHG_OK_MSK,
484		.reg_offset = 1,
485	},
486	[RK818_IRQ_CHG_TE] = {
487		.mask = RK818_IRQ_CHG_TE_MSK,
488		.reg_offset = 1,
489	},
490	[RK818_IRQ_CHG_TS1] = {
491		.mask = RK818_IRQ_CHG_TS1_MSK,
492		.reg_offset = 1,
493	},
494	[RK818_IRQ_TS2] = {
495		.mask = RK818_IRQ_TS2_MSK,
496		.reg_offset = 1,
497	},
498	[RK818_IRQ_CHG_CVTLIM] = {
499		.mask = RK818_IRQ_CHG_CVTLIM_MSK,
500		.reg_offset = 1,
501	},
502	[RK818_IRQ_DISCHG_ILIM] = {
503		.mask = RK818_IRQ_DISCHG_ILIM_MSK,
504		.reg_offset = 1,
505	},
506};
507
508static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = {
509	REGMAP_IRQ_REG_LINE(0, 8),
510	REGMAP_IRQ_REG_LINE(1, 8),
511	REGMAP_IRQ_REG_LINE(2, 8),
512	REGMAP_IRQ_REG_LINE(3, 8),
513	REGMAP_IRQ_REG_LINE(4, 8),
514	REGMAP_IRQ_REG_LINE(5, 8),
515	REGMAP_IRQ_REG_LINE(6, 8),
516	REGMAP_IRQ_REG_LINE(7, 8),
517	REGMAP_IRQ_REG_LINE(8, 8),
518	REGMAP_IRQ_REG_LINE(9, 8),
519	REGMAP_IRQ_REG_LINE(10, 8),
520	REGMAP_IRQ_REG_LINE(11, 8),
521	REGMAP_IRQ_REG_LINE(12, 8),
522	REGMAP_IRQ_REG_LINE(13, 8),
523	REGMAP_IRQ_REG_LINE(14, 8),
524	REGMAP_IRQ_REG_LINE(15, 8),
525	REGMAP_IRQ_REG_LINE(16, 8),
526	REGMAP_IRQ_REG_LINE(17, 8),
527	REGMAP_IRQ_REG_LINE(18, 8),
528	REGMAP_IRQ_REG_LINE(19, 8),
529	REGMAP_IRQ_REG_LINE(20, 8),
530	REGMAP_IRQ_REG_LINE(21, 8),
531	REGMAP_IRQ_REG_LINE(22, 8),
532	REGMAP_IRQ_REG_LINE(23, 8)
533};
534
535static const struct regmap_irq_chip rk805_irq_chip = {
536	.name = "rk805",
537	.irqs = rk805_irqs,
538	.num_irqs = ARRAY_SIZE(rk805_irqs),
539	.num_regs = 1,
540	.status_base = RK805_INT_STS_REG,
541	.mask_base = RK805_INT_STS_MSK_REG,
542	.ack_base = RK805_INT_STS_REG,
543	.init_ack_masked = true,
544};
545
546static const struct regmap_irq_chip rk806_irq_chip = {
547	.name = "rk806",
548	.irqs = rk806_irqs,
549	.num_irqs = ARRAY_SIZE(rk806_irqs),
550	.num_regs = 2,
551	.irq_reg_stride = 2,
552	.mask_base = RK806_INT_MSK0,
553	.status_base = RK806_INT_STS0,
554	.ack_base = RK806_INT_STS0,
555	.init_ack_masked = true,
556};
557
558static const struct regmap_irq_chip rk808_irq_chip = {
559	.name = "rk808",
560	.irqs = rk808_irqs,
561	.num_irqs = ARRAY_SIZE(rk808_irqs),
562	.num_regs = 2,
563	.irq_reg_stride = 2,
564	.status_base = RK808_INT_STS_REG1,
565	.mask_base = RK808_INT_STS_MSK_REG1,
566	.ack_base = RK808_INT_STS_REG1,
567	.init_ack_masked = true,
568};
569
570static const struct regmap_irq_chip rk816_irq_chip = {
571	.name = "rk816",
572	.irqs = rk816_irqs,
573	.num_irqs = ARRAY_SIZE(rk816_irqs),
574	.num_regs = 3,
575	.get_irq_reg = rk816_get_irq_reg,
576	.status_base = RK816_INT_STS_REG1,
577	.mask_base = RK816_INT_STS_MSK_REG1,
578	.ack_base = RK816_INT_STS_REG1,
579	.init_ack_masked = true,
580};
581
582static const struct regmap_irq_chip rk817_irq_chip = {
583	.name = "rk817",
584	.irqs = rk817_irqs,
585	.num_irqs = ARRAY_SIZE(rk817_irqs),
586	.num_regs = 3,
587	.irq_reg_stride = 2,
588	.status_base = RK817_INT_STS_REG0,
589	.mask_base = RK817_INT_STS_MSK_REG0,
590	.ack_base = RK817_INT_STS_REG0,
591	.init_ack_masked = true,
592};
593
594static const struct regmap_irq_chip rk818_irq_chip = {
595	.name = "rk818",
596	.irqs = rk818_irqs,
597	.num_irqs = ARRAY_SIZE(rk818_irqs),
598	.num_regs = 2,
599	.irq_reg_stride = 2,
600	.status_base = RK818_INT_STS_REG1,
601	.mask_base = RK818_INT_STS_MSK_REG1,
602	.ack_base = RK818_INT_STS_REG1,
603	.init_ack_masked = true,
604};
605
606static int rk808_power_off(struct sys_off_data *data)
607{
608	struct rk808 *rk808 = data->cb_data;
609	int ret;
610	unsigned int reg, bit;
611
612	switch (rk808->variant) {
613	case RK805_ID:
614		reg = RK805_DEV_CTRL_REG;
615		bit = DEV_OFF;
616		break;
617	case RK806_ID:
618		reg = RK806_SYS_CFG3;
619		bit = DEV_OFF;
620		break;
621	case RK808_ID:
622		reg = RK808_DEVCTRL_REG;
623		bit = DEV_OFF_RST;
624		break;
625	case RK809_ID:
626	case RK817_ID:
627		reg = RK817_SYS_CFG(3);
628		bit = DEV_OFF;
629		break;
630	case RK816_ID:
631	case RK818_ID:
632		reg = RK818_DEVCTRL_REG;
633		bit = DEV_OFF;
634		break;
635	default:
636		return NOTIFY_DONE;
637	}
638	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
639	if (ret)
640		dev_err(rk808->dev, "Failed to shutdown device!\n");
641
642	return NOTIFY_DONE;
643}
644
645static int rk808_restart(struct sys_off_data *data)
646{
647	struct rk808 *rk808 = data->cb_data;
648	unsigned int reg, bit;
649	int ret;
650
651	switch (rk808->variant) {
652	case RK809_ID:
653	case RK817_ID:
654		reg = RK817_SYS_CFG(3);
655		bit = DEV_RST;
656		break;
657
658	default:
659		return NOTIFY_DONE;
660	}
661	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
662	if (ret)
663		dev_err(rk808->dev, "Failed to restart device!\n");
664
665	return NOTIFY_DONE;
666}
667
668void rk8xx_shutdown(struct device *dev)
669{
670	struct rk808 *rk808 = dev_get_drvdata(dev);
671	int ret;
672
673	switch (rk808->variant) {
674	case RK805_ID:
675		ret = regmap_update_bits(rk808->regmap,
676					 RK805_GPIO_IO_POL_REG,
677					 SLP_SD_MSK,
678					 SHUTDOWN_FUN);
679		break;
680	case RK809_ID:
681	case RK817_ID:
682		ret = regmap_update_bits(rk808->regmap,
683					 RK817_SYS_CFG(3),
684					 RK817_SLPPIN_FUNC_MSK,
685					 SLPPIN_DN_FUN);
686		break;
687	default:
688		return;
689	}
690	if (ret)
691		dev_warn(dev,
692			 "Cannot switch to power down function\n");
693}
694EXPORT_SYMBOL_GPL(rk8xx_shutdown);
695
696int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap)
697{
698	struct rk808 *rk808;
699	const struct rk808_reg_data *pre_init_reg;
700	const struct mfd_cell *cells;
701	int dual_support = 0;
702	int nr_pre_init_regs;
703	u32 rst_fun = 0;
704	int nr_cells;
705	int ret;
706	int i;
707
708	rk808 = devm_kzalloc(dev, sizeof(*rk808), GFP_KERNEL);
709	if (!rk808)
710		return -ENOMEM;
711	rk808->dev = dev;
712	rk808->variant = variant;
713	rk808->regmap = regmap;
714	dev_set_drvdata(dev, rk808);
715
716	switch (rk808->variant) {
717	case RK805_ID:
718		rk808->regmap_irq_chip = &rk805_irq_chip;
719		pre_init_reg = rk805_pre_init_reg;
720		nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg);
721		cells = rk805s;
722		nr_cells = ARRAY_SIZE(rk805s);
723		break;
724	case RK806_ID:
725		rk808->regmap_irq_chip = &rk806_irq_chip;
726		pre_init_reg = rk806_pre_init_reg;
727		nr_pre_init_regs = ARRAY_SIZE(rk806_pre_init_reg);
728		cells = rk806s;
729		nr_cells = ARRAY_SIZE(rk806s);
730		dual_support = IRQF_SHARED;
731
732		ret = device_property_read_u32(dev, "rockchip,reset-mode", &rst_fun);
733		if (ret)
734			break;
735
736		ret = regmap_update_bits(rk808->regmap, RK806_SYS_CFG3, RK806_RST_FUN_MSK,
737					 FIELD_PREP(RK806_RST_FUN_MSK, rst_fun));
738		if (ret)
739			return dev_err_probe(dev, ret,
740					     "Failed to configure requested restart/reset behavior\n");
741		break;
742	case RK808_ID:
743		rk808->regmap_irq_chip = &rk808_irq_chip;
744		pre_init_reg = rk808_pre_init_reg;
745		nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg);
746		cells = rk808s;
747		nr_cells = ARRAY_SIZE(rk808s);
748		break;
749	case RK816_ID:
750		rk808->regmap_irq_chip = &rk816_irq_chip;
751		pre_init_reg = rk816_pre_init_reg;
752		nr_pre_init_regs = ARRAY_SIZE(rk816_pre_init_reg);
753		cells = rk816s;
754		nr_cells = ARRAY_SIZE(rk816s);
755		break;
756	case RK818_ID:
757		rk808->regmap_irq_chip = &rk818_irq_chip;
758		pre_init_reg = rk818_pre_init_reg;
759		nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg);
760		cells = rk818s;
761		nr_cells = ARRAY_SIZE(rk818s);
762		break;
763	case RK809_ID:
764	case RK817_ID:
765		rk808->regmap_irq_chip = &rk817_irq_chip;
766		pre_init_reg = rk817_pre_init_reg;
767		nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg);
768		cells = rk817s;
769		nr_cells = ARRAY_SIZE(rk817s);
770		break;
771	default:
772		dev_err(dev, "Unsupported RK8XX ID %lu\n", rk808->variant);
773		return -EINVAL;
774	}
775
776	if (!irq)
777		return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n");
778
779	ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq,
780				       IRQF_ONESHOT | dual_support, -1,
781				       rk808->regmap_irq_chip, &rk808->irq_data);
782	if (ret)
783		return dev_err_probe(dev, ret, "Failed to add irq_chip\n");
784
785	for (i = 0; i < nr_pre_init_regs; i++) {
786		ret = regmap_update_bits(rk808->regmap,
787					pre_init_reg[i].addr,
788					pre_init_reg[i].mask,
789					pre_init_reg[i].value);
790		if (ret)
791			return dev_err_probe(dev, ret, "0x%x write err\n",
792					     pre_init_reg[i].addr);
793	}
794
795	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, nr_cells, NULL, 0,
796			      regmap_irq_get_domain(rk808->irq_data));
797	if (ret)
798		return dev_err_probe(dev, ret, "failed to add MFD devices\n");
799
800	if (device_property_read_bool(dev, "system-power-controller") ||
801	    device_property_read_bool(dev, "rockchip,system-power-controller")) {
802		ret = devm_register_sys_off_handler(dev,
803				    SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
804				    &rk808_power_off, rk808);
805		if (ret)
806			return dev_err_probe(dev, ret,
807					     "failed to register poweroff handler\n");
808
809		switch (rk808->variant) {
810		case RK809_ID:
811		case RK817_ID:
812			ret = devm_register_sys_off_handler(dev,
813							    SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
814							    &rk808_restart, rk808);
815			if (ret)
816				dev_warn(dev, "failed to register rst handler, %d\n", ret);
817			break;
818		default:
819			dev_dbg(dev, "pmic controlled board reset not supported\n");
820			break;
821		}
822	}
823
824	return 0;
825}
826EXPORT_SYMBOL_GPL(rk8xx_probe);
827
828int rk8xx_suspend(struct device *dev)
829{
830	struct rk808 *rk808 = dev_get_drvdata(dev);
831	int ret = 0;
832
833	switch (rk808->variant) {
834	case RK805_ID:
835		ret = regmap_update_bits(rk808->regmap,
836					 RK805_GPIO_IO_POL_REG,
837					 SLP_SD_MSK,
838					 SLEEP_FUN);
839		break;
840	case RK809_ID:
841	case RK817_ID:
842		ret = regmap_update_bits(rk808->regmap,
843					 RK817_SYS_CFG(3),
844					 RK817_SLPPIN_FUNC_MSK,
845					 SLPPIN_SLP_FUN);
846		break;
847	default:
848		break;
849	}
850
851	return ret;
852}
853EXPORT_SYMBOL_GPL(rk8xx_suspend);
854
855int rk8xx_resume(struct device *dev)
856{
857	struct rk808 *rk808 = dev_get_drvdata(dev);
858	int ret = 0;
859
860	switch (rk808->variant) {
861	case RK809_ID:
862	case RK817_ID:
863		ret = regmap_update_bits(rk808->regmap,
864					 RK817_SYS_CFG(3),
865					 RK817_SLPPIN_FUNC_MSK,
866					 SLPPIN_NULL_FUN);
867		break;
868	default:
869		break;
870	}
871
872	return ret;
873}
874EXPORT_SYMBOL_GPL(rk8xx_resume);
875
876MODULE_LICENSE("GPL");
877MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
878MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
879MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
880MODULE_DESCRIPTION("RK8xx PMIC core");