max77620.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Maxim MAX77620 MFD Driver
  4 *
  5 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
  6 *
  7 * Author:
  8 *	Laxman Dewangan <ldewangan@nvidia.com>
  9 *	Chaitanya Bandi <bandik@nvidia.com>
 10 *	Mallikarjun Kasoju <mkasoju@nvidia.com>
 11 */
 12
 13/****************** Teminology used in driver ********************
 14 * Here are some terminology used from datasheet for quick reference:
 15 * Flexible Power Sequence (FPS):
 16 * The Flexible Power Sequencer (FPS) allows each regulator to power up under
 17 * hardware or software control. Additionally, each regulator can power on
 18 * independently or among a group of other regulators with an adjustable
 19 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
 20 * be programmed to be part of a sequence allowing external regulators to be
 21 * sequenced along with internal regulators. 32KHz clock can be programmed to
 22 * be part of a sequence.
 23 * There is 3 FPS confguration registers and all resources are configured to
 24 * any of these FPS or no FPS.
 25 */
 26
 27#include <linux/i2c.h>
 28#include <linux/interrupt.h>
 29#include <linux/mfd/core.h>
 30#include <linux/mfd/max77620.h>
 31#include <linux/init.h>
 32#include <linux/module.h>
 33#include <linux/of.h>
 34#include <linux/regmap.h>
 35#include <linux/slab.h>
 36
 37static struct max77620_chip *max77620_scratch;
 38
 39static const struct resource gpio_resources[] = {
 40	DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
 41};
 42
 43static const struct resource power_resources[] = {
 44	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
 45};
 46
 47static const struct resource rtc_resources[] = {
 48	DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
 49};
 50
 51static const struct resource thermal_resources[] = {
 52	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
 53	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
 54};
 55
 56static const struct regmap_irq max77620_top_irqs[] = {
 57	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
 58	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
 59	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
 60	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
 61	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
 62	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
 63	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
 64	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
 65	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
 66	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
 67};
 68
 69static const struct mfd_cell max77620_children[] = {
 70	{ .name = "max77620-pinctrl", },
 71	{ .name = "max77620-clock", },
 72	{ .name = "max77620-pmic", },
 73	{ .name = "max77620-watchdog", },
 74	{
 75		.name = "max77620-gpio",
 76		.resources = gpio_resources,
 77		.num_resources = ARRAY_SIZE(gpio_resources),
 78	}, {
 79		.name = "max77620-rtc",
 80		.resources = rtc_resources,
 81		.num_resources = ARRAY_SIZE(rtc_resources),
 82	}, {
 83		.name = "max77620-power",
 84		.resources = power_resources,
 85		.num_resources = ARRAY_SIZE(power_resources),
 86	}, {
 87		.name = "max77620-thermal",
 88		.resources = thermal_resources,
 89		.num_resources = ARRAY_SIZE(thermal_resources),
 90	},
 91};
 92
 93static const struct mfd_cell max20024_children[] = {
 94	{ .name = "max20024-pinctrl", },
 95	{ .name = "max77620-clock", },
 96	{ .name = "max20024-pmic", },
 97	{ .name = "max77620-watchdog", },
 98	{
 99		.name = "max77620-gpio",
100		.resources = gpio_resources,
101		.num_resources = ARRAY_SIZE(gpio_resources),
102	}, {
103		.name = "max77620-rtc",
104		.resources = rtc_resources,
105		.num_resources = ARRAY_SIZE(rtc_resources),
106	}, {
107		.name = "max20024-power",
108		.resources = power_resources,
109		.num_resources = ARRAY_SIZE(power_resources),
110	},
111};
112
113static const struct mfd_cell max77663_children[] = {
114	{ .name = "max77620-pinctrl", },
115	{ .name = "max77620-clock", },
116	{ .name = "max77663-pmic", },
117	{ .name = "max77620-watchdog", },
118	{
119		.name = "max77620-gpio",
120		.resources = gpio_resources,
121		.num_resources = ARRAY_SIZE(gpio_resources),
122	}, {
123		.name = "max77620-rtc",
124		.resources = rtc_resources,
125		.num_resources = ARRAY_SIZE(rtc_resources),
126	}, {
127		.name = "max77663-power",
128		.resources = power_resources,
129		.num_resources = ARRAY_SIZE(power_resources),
130	},
131};
132
133static const struct regmap_range max77620_readable_ranges[] = {
134	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
135};
136
137static const struct regmap_access_table max77620_readable_table = {
138	.yes_ranges = max77620_readable_ranges,
139	.n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
140};
141
142static const struct regmap_range max20024_readable_ranges[] = {
143	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
144	regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
145};
146
147static const struct regmap_access_table max20024_readable_table = {
148	.yes_ranges = max20024_readable_ranges,
149	.n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
150};
151
152static const struct regmap_range max77620_writable_ranges[] = {
153	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
154};
155
156static const struct regmap_access_table max77620_writable_table = {
157	.yes_ranges = max77620_writable_ranges,
158	.n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
159};
160
161static const struct regmap_range max77620_cacheable_ranges[] = {
162	regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
163	regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
164};
165
166static const struct regmap_access_table max77620_volatile_table = {
167	.no_ranges = max77620_cacheable_ranges,
168	.n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
169};
170
171static const struct regmap_config max77620_regmap_config = {
172	.name = "power-slave",
173	.reg_bits = 8,
174	.val_bits = 8,
175	.max_register = MAX77620_REG_DVSSD4 + 1,
176	.cache_type = REGCACHE_MAPLE,
177	.rd_table = &max77620_readable_table,
178	.wr_table = &max77620_writable_table,
179	.volatile_table = &max77620_volatile_table,
180	.use_single_write = true,
181};
182
183static const struct regmap_config max20024_regmap_config = {
184	.name = "power-slave",
185	.reg_bits = 8,
186	.val_bits = 8,
187	.max_register = MAX20024_REG_MAX_ADD + 1,
188	.cache_type = REGCACHE_MAPLE,
189	.rd_table = &max20024_readable_table,
190	.wr_table = &max77620_writable_table,
191	.volatile_table = &max77620_volatile_table,
192};
193
194static const struct regmap_range max77663_readable_ranges[] = {
195	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
196};
197
198static const struct regmap_access_table max77663_readable_table = {
199	.yes_ranges = max77663_readable_ranges,
200	.n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),
201};
202
203static const struct regmap_range max77663_writable_ranges[] = {
204	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
205};
206
207static const struct regmap_access_table max77663_writable_table = {
208	.yes_ranges = max77663_writable_ranges,
209	.n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),
210};
211
212static const struct regmap_config max77663_regmap_config = {
213	.name = "power-slave",
214	.reg_bits = 8,
215	.val_bits = 8,
216	.max_register = MAX77620_REG_CID5 + 1,
217	.cache_type = REGCACHE_MAPLE,
218	.rd_table = &max77663_readable_table,
219	.wr_table = &max77663_writable_table,
220	.volatile_table = &max77620_volatile_table,
221};
222
223/*
224 * MAX77620 and MAX20024 has the following steps of the interrupt handling
225 * for TOP interrupts:
226 * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
227 * 2. Read IRQTOP and service the interrupt.
228 * 3. Once all interrupts has been checked and serviced, the interrupt service
229 *    routine un-masks the hardware interrupt line by clearing GLBLM.
230 */
231static int max77620_irq_global_mask(void *irq_drv_data)
232{
233	struct max77620_chip *chip = irq_drv_data;
234	int ret;
235
236	ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
237				 MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
238	if (ret < 0)
239		dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
240
241	return ret;
242}
243
244static int max77620_irq_global_unmask(void *irq_drv_data)
245{
246	struct max77620_chip *chip = irq_drv_data;
247	int ret;
248
249	ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
250				 MAX77620_GLBLM_MASK, 0);
251	if (ret < 0)
252		dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
253
254	return ret;
255}
256
257static const struct regmap_irq_chip max77620_top_irq_chip = {
258	.name = "max77620-top",
259	.irqs = max77620_top_irqs,
260	.num_irqs = ARRAY_SIZE(max77620_top_irqs),
261	.num_regs = 2,
262	.status_base = MAX77620_REG_IRQTOP,
263	.mask_base = MAX77620_REG_IRQTOPM,
264	.handle_pre_irq = max77620_irq_global_mask,
265	.handle_post_irq = max77620_irq_global_unmask,
266};
267
268/* max77620_get_fps_period_reg_value:  Get FPS bit field value from
269 *				       requested periods.
270 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
271 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
272 * 160, 320, 540, 1280 and 2560 microseconds.
273 * The FPS register has 3 bits field to set the FPS period as
274 * bits		max77620		max20024
275 * 000		40			20
276 * 001		80			40
277 * :::
278*/
279static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
280					     int tperiod)
281{
282	int fps_min_period;
283	int i;
284
285	switch (chip->chip_id) {
286	case MAX20024:
287		fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
288		break;
289	case MAX77620:
290		fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
291		break;
292	case MAX77663:
293		fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
294		break;
295	default:
296		return -EINVAL;
297	}
298
299	for (i = 0; i < 7; i++) {
300		if (fps_min_period >= tperiod)
301			return i;
302		fps_min_period *= 2;
303	}
304
305	return i;
306}
307
308/* max77620_config_fps: Configure FPS configuration registers
309 *			based on platform specific information.
310 */
311static int max77620_config_fps(struct max77620_chip *chip,
312			       struct device_node *fps_np)
313{
314	struct device *dev = chip->dev;
315	unsigned int mask = 0, config = 0;
316	u32 fps_max_period;
317	u32 param_val;
318	int tperiod, fps_id;
319	int ret;
320	char fps_name[10];
321
322	switch (chip->chip_id) {
323	case MAX20024:
324		fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
325		break;
326	case MAX77620:
327		fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
328		break;
329	case MAX77663:
330		fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
331		break;
332	default:
333		return -EINVAL;
334	}
335
336	for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
337		sprintf(fps_name, "fps%d", fps_id);
338		if (of_node_name_eq(fps_np, fps_name))
339			break;
340	}
341
342	if (fps_id == MAX77620_FPS_COUNT) {
343		dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);
344		return -EINVAL;
345	}
346
347	ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
348				   &param_val);
349	if (!ret) {
350		mask |= MAX77620_FPS_TIME_PERIOD_MASK;
351		chip->shutdown_fps_period[fps_id] = min(param_val,
352							fps_max_period);
353		tperiod = max77620_get_fps_period_reg_value(chip,
354				chip->shutdown_fps_period[fps_id]);
355		config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
356	}
357
358	ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
359				   &param_val);
360	if (!ret)
361		chip->suspend_fps_period[fps_id] = min(param_val,
362						       fps_max_period);
363
364	ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
365				   &param_val);
366	if (!ret) {
367		if (param_val > 2) {
368			dev_err(dev, "FPS%d event-source invalid\n", fps_id);
369			return -EINVAL;
370		}
371		mask |= MAX77620_FPS_EN_SRC_MASK;
372		config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
373		if (param_val == 2) {
374			mask |= MAX77620_FPS_ENFPS_SW_MASK;
375			config |= MAX77620_FPS_ENFPS_SW;
376		}
377	}
378
379	if (!chip->sleep_enable && !chip->enable_global_lpm) {
380		ret = of_property_read_u32(fps_np,
381				"maxim,device-state-on-disabled-event",
382				&param_val);
383		if (!ret) {
384			if (param_val == 0)
385				chip->sleep_enable = true;
386			else if (param_val == 1)
387				chip->enable_global_lpm = true;
388		}
389	}
390
391	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
392				 mask, config);
393	if (ret < 0) {
394		dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
395		return ret;
396	}
397
398	return 0;
399}
400
401static int max77620_initialise_fps(struct max77620_chip *chip)
402{
403	struct device *dev = chip->dev;
404	struct device_node *fps_np;
405	u8 config;
406	int fps_id;
407	int ret;
408
409	for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
410		chip->shutdown_fps_period[fps_id] = -1;
411		chip->suspend_fps_period[fps_id] = -1;
412	}
413
414	fps_np = of_get_child_by_name(dev->of_node, "fps");
415	if (!fps_np)
416		goto skip_fps;
417
418	for_each_child_of_node_scoped(fps_np, fps_child) {
419		ret = max77620_config_fps(chip, fps_child);
420		if (ret < 0) {
421			of_node_put(fps_np);
422			return ret;
423		}
424	}
425	of_node_put(fps_np);
426
427	config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
428	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
429				 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
430	if (ret < 0) {
431		dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
432		return ret;
433	}
434
435skip_fps:
436	if (chip->chip_id == MAX77663)
437		return 0;
438
439	/* Enable wake on EN0 pin */
440	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
441				 MAX77620_ONOFFCNFG2_WK_EN0,
442				 MAX77620_ONOFFCNFG2_WK_EN0);
443	if (ret < 0) {
444		dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
445		return ret;
446	}
447
448	/* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
449	if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
450		config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
451		ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
452					 config, config);
453		if (ret < 0) {
454			dev_err(dev, "Failed to update SLPEN: %d\n", ret);
455			return ret;
456		}
457	}
458
459	return 0;
460}
461
462static int max77620_read_es_version(struct max77620_chip *chip)
463{
464	unsigned int val;
465	u8 cid_val[6];
466	int i;
467	int ret;
468
469	for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
470		ret = regmap_read(chip->rmap, i, &val);
471		if (ret < 0) {
472			dev_err(chip->dev, "Failed to read CID: %d\n", ret);
473			return ret;
474		}
475		dev_dbg(chip->dev, "CID%d: 0x%02x\n",
476			i - MAX77620_REG_CID0, val);
477		cid_val[i - MAX77620_REG_CID0] = val;
478	}
479
480	/* CID4 is OTP Version  and CID5 is ES version */
481	dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
482		 cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
483
484	return ret;
485}
486
487static void max77620_pm_power_off(void)
488{
489	struct max77620_chip *chip = max77620_scratch;
490
491	regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
492			   MAX77620_ONOFFCNFG1_SFT_RST,
493			   MAX77620_ONOFFCNFG1_SFT_RST);
494}
495
496static int max77620_probe(struct i2c_client *client)
497{
498	const struct i2c_device_id *id = i2c_client_get_device_id(client);
499	const struct regmap_config *rmap_config;
500	struct max77620_chip *chip;
501	struct regmap_irq_chip *chip_desc;
502	const struct mfd_cell *mfd_cells;
503	int n_mfd_cells;
504	bool pm_off;
505	int ret;
506
507	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
508	if (!chip)
509		return -ENOMEM;
510
511	i2c_set_clientdata(client, chip);
512
513	chip_desc = devm_kmemdup(&client->dev, &max77620_top_irq_chip,
514				 sizeof(max77620_top_irq_chip),
515				 GFP_KERNEL);
516	if (!chip_desc)
517		return -ENOMEM;
518	chip_desc->irq_drv_data = chip;
519
520	chip->dev = &client->dev;
521	chip->chip_irq = client->irq;
522	chip->chip_id = (enum max77620_chip_id)id->driver_data;
523
524	switch (chip->chip_id) {
525	case MAX77620:
526		mfd_cells = max77620_children;
527		n_mfd_cells = ARRAY_SIZE(max77620_children);
528		rmap_config = &max77620_regmap_config;
529		break;
530	case MAX20024:
531		mfd_cells = max20024_children;
532		n_mfd_cells = ARRAY_SIZE(max20024_children);
533		rmap_config = &max20024_regmap_config;
534		break;
535	case MAX77663:
536		mfd_cells = max77663_children;
537		n_mfd_cells = ARRAY_SIZE(max77663_children);
538		rmap_config = &max77663_regmap_config;
539		break;
540	default:
541		dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
542		return -EINVAL;
543	}
544
545	chip->rmap = devm_regmap_init_i2c(client, rmap_config);
546	if (IS_ERR(chip->rmap)) {
547		ret = PTR_ERR(chip->rmap);
548		dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
549		return ret;
550	}
551
552	ret = max77620_read_es_version(chip);
553	if (ret < 0)
554		return ret;
555
556	ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
557				       IRQF_ONESHOT | IRQF_SHARED, 0,
558				       chip_desc, &chip->top_irq_data);
559	if (ret < 0) {
560		dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
561		return ret;
562	}
563
564	ret = max77620_initialise_fps(chip);
565	if (ret < 0)
566		return ret;
567
568	ret =  devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
569				    mfd_cells, n_mfd_cells, NULL, 0,
570				    regmap_irq_get_domain(chip->top_irq_data));
571	if (ret < 0) {
572		dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
573		return ret;
574	}
575
576	pm_off = of_device_is_system_power_controller(client->dev.of_node);
577	if (pm_off && !pm_power_off) {
578		max77620_scratch = chip;
579		pm_power_off = max77620_pm_power_off;
580	}
581
582	return 0;
583}
584
585static int max77620_set_fps_period(struct max77620_chip *chip,
586				   int fps_id, int time_period)
587{
588	int period = max77620_get_fps_period_reg_value(chip, time_period);
589	int ret;
590
591	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
592				 MAX77620_FPS_TIME_PERIOD_MASK,
593				 period << MAX77620_FPS_TIME_PERIOD_SHIFT);
594	if (ret < 0) {
595		dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
596		return ret;
597	}
598
599	return 0;
600}
601
602static int max77620_i2c_suspend(struct device *dev)
603{
604	struct max77620_chip *chip = dev_get_drvdata(dev);
605	struct i2c_client *client = to_i2c_client(dev);
606	unsigned int config;
607	int fps;
608	int ret;
609
610	for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
611		if (chip->suspend_fps_period[fps] < 0)
612			continue;
613
614		ret = max77620_set_fps_period(chip, fps,
615					      chip->suspend_fps_period[fps]);
616		if (ret < 0)
617			return ret;
618	}
619
620	/*
621	 * For MAX20024: No need to configure SLPEN on suspend as
622	 * it will be configured on Init.
623	 */
624	if (chip->chip_id == MAX20024)
625		goto out;
626
627	config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
628	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
629				 MAX77620_ONOFFCNFG1_SLPEN,
630				 config);
631	if (ret < 0) {
632		dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
633		return ret;
634	}
635
636	if (chip->chip_id == MAX77663)
637		goto out;
638
639	/* Disable WK_EN0 */
640	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
641				 MAX77620_ONOFFCNFG2_WK_EN0, 0);
642	if (ret < 0) {
643		dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
644		return ret;
645	}
646
647out:
648	disable_irq(client->irq);
649
650	return 0;
651}
652
653static int max77620_i2c_resume(struct device *dev)
654{
655	struct max77620_chip *chip = dev_get_drvdata(dev);
656	struct i2c_client *client = to_i2c_client(dev);
657	int ret;
658	int fps;
659
660	for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
661		if (chip->shutdown_fps_period[fps] < 0)
662			continue;
663
664		ret = max77620_set_fps_period(chip, fps,
665					      chip->shutdown_fps_period[fps]);
666		if (ret < 0)
667			return ret;
668	}
669
670	/*
671	 * For MAX20024: No need to configure WKEN0 on resume as
672	 * it is configured on Init.
673	 */
674	if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
675		goto out;
676
677	/* Enable WK_EN0 */
678	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
679				 MAX77620_ONOFFCNFG2_WK_EN0,
680				 MAX77620_ONOFFCNFG2_WK_EN0);
681	if (ret < 0) {
682		dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
683		return ret;
684	}
685
686out:
687	enable_irq(client->irq);
688
689	return 0;
690}
691
692static const struct i2c_device_id max77620_id[] = {
693	{"max77620", MAX77620},
694	{"max20024", MAX20024},
695	{"max77663", MAX77663},
696	{},
697};
698
699static DEFINE_SIMPLE_DEV_PM_OPS(max77620_pm_ops,
700				max77620_i2c_suspend, max77620_i2c_resume);
701
702static struct i2c_driver max77620_driver = {
703	.driver = {
704		.name = "max77620",
705		.pm = pm_sleep_ptr(&max77620_pm_ops),
706	},
707	.probe = max77620_probe,
708	.id_table = max77620_id,
709};
710builtin_i2c_driver(max77620_driver);
711
712MODULE_DESCRIPTION("Maxim Semiconductor MAX77620 and MAX20024 PMIC Support");
713MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
714MODULE_LICENSE("GPL");