tegra264.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2025, NVIDIA CORPORATION.  All rights reserved.
  4 */
  5
  6#include <dt-bindings/memory/nvidia,tegra264.h>
  7
  8#include <linux/interconnect.h>
  9#include <linux/of_device.h>
 10#include <linux/tegra-icc.h>
 11
 12#include <soc/tegra/bpmp.h>
 13#include <soc/tegra/mc.h>
 14
 15#include "mc.h"
 16#include "tegra264-bwmgr.h"
 17
 18/*
 19 * MC Client entries are sorted in the increasing order of the
 20 * override and security register offsets.
 21 */
 22static const struct tegra_mc_client tegra264_mc_clients[] = {
 23	{
 24		.id = TEGRA264_MEMORY_CLIENT_HDAR,
 25		.name = "hdar",
 26		.bpmp_id = TEGRA264_BWMGR_HDA,
 27		.type = TEGRA_ICC_ISO_AUDIO,
 28	}, {
 29		.id = TEGRA264_MEMORY_CLIENT_HDAW,
 30		.name = "hdaw",
 31		.bpmp_id = TEGRA264_BWMGR_HDA,
 32		.type = TEGRA_ICC_ISO_AUDIO,
 33	}, {
 34		.id = TEGRA264_MEMORY_CLIENT_MGBE0R,
 35		.name = "mgbe0r",
 36		.bpmp_id = TEGRA264_BWMGR_EQOS,
 37		.type = TEGRA_ICC_NISO,
 38	}, {
 39		.id = TEGRA264_MEMORY_CLIENT_MGBE0W,
 40		.name = "mgbe0w",
 41		.bpmp_id = TEGRA264_BWMGR_EQOS,
 42		.type = TEGRA_ICC_NISO,
 43	}, {
 44		.id = TEGRA264_MEMORY_CLIENT_MGBE1R,
 45		.name = "mgbe1r",
 46		.bpmp_id = TEGRA264_BWMGR_EQOS,
 47		.type = TEGRA_ICC_NISO,
 48	}, {
 49		.id = TEGRA264_MEMORY_CLIENT_MGBE1W,
 50		.name = "mgbe1w",
 51		.bpmp_id = TEGRA264_BWMGR_EQOS,
 52		.type = TEGRA_ICC_NISO,
 53	}, {
 54		.id = TEGRA264_MEMORY_CLIENT_SDMMC0R,
 55		.name = "sdmmc0r",
 56		.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
 57		.type = TEGRA_ICC_NISO,
 58	}, {
 59		.id = TEGRA264_MEMORY_CLIENT_SDMMC0W,
 60		.name = "sdmmc0w",
 61		.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
 62		.type = TEGRA_ICC_NISO,
 63	}, {
 64		.id = TEGRA264_MEMORY_CLIENT_VICR,
 65		.name = "vicr",
 66		.bpmp_id = TEGRA264_BWMGR_VIC,
 67		.type = TEGRA_ICC_NISO,
 68	}, {
 69		.id = TEGRA264_MEMORY_CLIENT_VICW,
 70		.name = "vicw",
 71		.bpmp_id = TEGRA264_BWMGR_VIC,
 72		.type = TEGRA_ICC_NISO,
 73	}, {
 74		.id = TEGRA264_MEMORY_CLIENT_APER,
 75		.name = "aper",
 76		.bpmp_id = TEGRA264_BWMGR_APE,
 77		.type = TEGRA_ICC_ISO_AUDIO,
 78	}, {
 79		.id = TEGRA264_MEMORY_CLIENT_APEW,
 80		.name = "apew",
 81		.bpmp_id = TEGRA264_BWMGR_APE,
 82		.type = TEGRA_ICC_ISO_AUDIO,
 83	}, {
 84		.id = TEGRA264_MEMORY_CLIENT_APEDMAR,
 85		.name = "apedmar",
 86		.bpmp_id = TEGRA264_BWMGR_APEDMA,
 87		.type = TEGRA_ICC_ISO_AUDIO,
 88	}, {
 89		.id = TEGRA264_MEMORY_CLIENT_APEDMAW,
 90		.name = "apedmaw",
 91		.bpmp_id = TEGRA264_BWMGR_APEDMA,
 92		.type = TEGRA_ICC_ISO_AUDIO,
 93	}, {
 94		.id = TEGRA264_MEMORY_CLIENT_VIFALCONR,
 95		.name = "vifalconr",
 96		.bpmp_id = TEGRA264_BWMGR_VIFAL,
 97		.type = TEGRA_ICC_ISO_VIFAL,
 98	}, {
 99		.id = TEGRA264_MEMORY_CLIENT_VIFALCONW,
100		.name = "vifalconw",
101		.bpmp_id = TEGRA264_BWMGR_VIFAL,
102		.type = TEGRA_ICC_ISO_VIFAL,
103	}, {
104		.id = TEGRA264_MEMORY_CLIENT_RCER,
105		.name = "rcer",
106		.bpmp_id = TEGRA264_BWMGR_RCE,
107		.type = TEGRA_ICC_NISO,
108	}, {
109		.id = TEGRA264_MEMORY_CLIENT_RCEW,
110		.name = "rcew",
111		.bpmp_id = TEGRA264_BWMGR_RCE,
112		.type = TEGRA_ICC_NISO,
113	}, {
114		.id = TEGRA264_MEMORY_CLIENT_PCIE0W,
115		.name = "pcie0w",
116		.bpmp_id = TEGRA264_BWMGR_PCIE_0,
117		.type = TEGRA_ICC_NISO,
118	}, {
119		.id = TEGRA264_MEMORY_CLIENT_PCIE1R,
120		.name = "pcie1r",
121		.bpmp_id = TEGRA264_BWMGR_PCIE_1,
122		.type = TEGRA_ICC_NISO,
123	}, {
124		.id = TEGRA264_MEMORY_CLIENT_PCIE1W,
125		.name = "pcie1w",
126		.bpmp_id = TEGRA264_BWMGR_PCIE_1,
127		.type = TEGRA_ICC_NISO,
128	}, {
129		.id = TEGRA264_MEMORY_CLIENT_PCIE2AR,
130		.name = "pcie2ar",
131		.bpmp_id = TEGRA264_BWMGR_PCIE_2,
132		.type = TEGRA_ICC_NISO,
133	}, {
134		.id = TEGRA264_MEMORY_CLIENT_PCIE2AW,
135		.name = "pcie2aw",
136		.bpmp_id = TEGRA264_BWMGR_PCIE_2,
137		.type = TEGRA_ICC_NISO,
138	}, {
139		.id = TEGRA264_MEMORY_CLIENT_PCIE3R,
140		.name = "pcie3r",
141		.bpmp_id = TEGRA264_BWMGR_PCIE_3,
142		.type = TEGRA_ICC_NISO,
143	}, {
144		.id = TEGRA264_MEMORY_CLIENT_PCIE3W,
145		.name = "pcie3w",
146		.bpmp_id = TEGRA264_BWMGR_PCIE_3,
147		.type = TEGRA_ICC_NISO,
148	}, {
149		.id = TEGRA264_MEMORY_CLIENT_PCIE4R,
150		.name = "pcie4r",
151		.bpmp_id = TEGRA264_BWMGR_PCIE_4,
152		.type = TEGRA_ICC_NISO,
153	}, {
154		.id = TEGRA264_MEMORY_CLIENT_PCIE4W,
155		.name = "pcie4w",
156		.bpmp_id = TEGRA264_BWMGR_PCIE_4,
157		.type = TEGRA_ICC_NISO,
158	}, {
159		.id = TEGRA264_MEMORY_CLIENT_PCIE5R,
160		.name = "pcie5r",
161		.bpmp_id = TEGRA264_BWMGR_PCIE_5,
162		.type = TEGRA_ICC_NISO,
163	}, {
164		.id = TEGRA264_MEMORY_CLIENT_PCIE5W,
165		.name = "pcie5w",
166		.bpmp_id = TEGRA264_BWMGR_PCIE_5,
167		.type = TEGRA_ICC_NISO,
168	}, {
169		.id = TEGRA264_MEMORY_CLIENT_GPUR02MC,
170		.name = "gpur02mc",
171		.bpmp_id = TEGRA264_BWMGR_GPU,
172		.type = TEGRA_ICC_NISO,
173	}, {
174		.id = TEGRA264_MEMORY_CLIENT_GPUW02MC,
175		.name = "gpuw02mc",
176		.bpmp_id = TEGRA264_BWMGR_GPU,
177		.type = TEGRA_ICC_NISO,
178	}, {
179		.id = TEGRA264_MEMORY_CLIENT_NVDECSRD2MC,
180		.name = "nvdecsrd2mc",
181		.bpmp_id = TEGRA264_BWMGR_NVDEC,
182		.type = TEGRA_ICC_NISO,
183	}, {
184		.id = TEGRA264_MEMORY_CLIENT_NVDECSWR2MC,
185		.name = "nvdecswr2mc",
186		.bpmp_id = TEGRA264_BWMGR_NVDEC,
187		.type = TEGRA_ICC_NISO,
188	},
189};
190
191/*
192 * tegra264_mc_icc_set() - Pass MC client info to the BPMP-FW
193 * @src: ICC node for Memory Controller's (MC) Client
194 * @dst: ICC node for Memory Controller (MC)
195 *
196 * Passing the current request info from the MC to the BPMP-FW where
197 * LA and PTSA registers are accessed and the final EMC freq is set
198 * based on client_id, type, latency and bandwidth.
199 * icc_set_bw() makes set_bw calls for both MC and EMC providers in
200 * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
201 * So, the data passed won't be updated by concurrent set calls from
202 * other clients.
203 */
204static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst)
205{
206	struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
207	struct mrq_bwmgr_int_request bwmgr_req = { 0 };
208	struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
209	const struct tegra_mc_client *pclient = src->data;
210	struct tegra_bpmp_message msg;
211	int ret;
212
213	/*
214	 * Same Src and Dst node will happen during boot from icc_node_add().
215	 * This can be used to pre-initialize and set bandwidth for all clients
216	 * before their drivers are loaded. We are skipping this case as for us,
217	 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
218	 */
219	if (src->id == dst->id)
220		return 0;
221
222	if (!mc->bwmgr_mrq_supported)
223		return 0;
224
225	if (!mc->bpmp) {
226		dev_err(mc->dev, "BPMP reference NULL\n");
227		return -ENOENT;
228	}
229
230	if (pclient->type == TEGRA_ICC_NISO)
231		bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
232	else
233		bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
234
235	bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
236
237	bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
238	bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
239	bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
240
241	memset(&msg, 0, sizeof(msg));
242	msg.mrq = MRQ_BWMGR_INT;
243	msg.tx.data = &bwmgr_req;
244	msg.tx.size = sizeof(bwmgr_req);
245	msg.rx.data = &bwmgr_resp;
246	msg.rx.size = sizeof(bwmgr_resp);
247
248	ret = tegra_bpmp_transfer(mc->bpmp, &msg);
249	if (ret < 0) {
250		dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
251		goto error;
252	}
253	if (msg.rx.ret < 0) {
254		pr_err("failed to set bandwidth for %u: %d\n",
255		       bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
256		ret = -EINVAL;
257	}
258
259error:
260	return ret;
261}
262
263static int tegra264_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
264				     u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
265{
266	struct icc_provider *p = node->provider;
267	struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
268
269	if (!mc->bwmgr_mrq_supported)
270		return 0;
271
272	*agg_avg += avg_bw;
273	*agg_peak = max(*agg_peak, peak_bw);
274
275	return 0;
276}
277
278static int tegra264_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
279{
280	*avg = 0;
281	*peak = 0;
282
283	return 0;
284}
285
286static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = {
287	.xlate = tegra_mc_icc_xlate,
288	.aggregate = tegra264_mc_icc_aggregate,
289	.get_bw = tegra264_mc_icc_get_init_bw,
290	.set = tegra264_mc_icc_set,
291};
292
293const struct tegra_mc_soc tegra264_mc_soc = {
294	.num_clients = ARRAY_SIZE(tegra264_mc_clients),
295	.clients = tegra264_mc_clients,
296	.num_address_bits = 40,
297	.num_channels = 16,
298	.client_id_mask = 0x1ff,
299	.intmask = MC_INT_DECERR_ROUTE_SANITY |
300		   MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
301		   MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
302		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
303	.has_addr_hi_reg = true,
304	.ops = &tegra186_mc_ops,
305	.icc_ops = &tegra264_mc_icc_ops,
306	.ch_intmask = 0x0000ff00,
307	.global_intstatus_channel_shift = 8,
308	/*
309	 * Additionally, there are lite carveouts but those are not currently
310	 * supported.
311	 */
312	.num_carveouts = 32,
313};