tegra124-emc.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   4 *
   5 * Author:
   6 *	Mikko Perttunen <mperttunen@nvidia.com>
   7 */
   8
   9#include <linux/clk-provider.h>
  10#include <linux/clk.h>
  11#include <linux/clkdev.h>
  12#include <linux/clk/tegra.h>
  13#include <linux/debugfs.h>
  14#include <linux/delay.h>
  15#include <linux/interconnect-provider.h>
  16#include <linux/io.h>
  17#include <linux/module.h>
  18#include <linux/mutex.h>
  19#include <linux/of_address.h>
  20#include <linux/of_platform.h>
  21#include <linux/platform_device.h>
  22#include <linux/pm_opp.h>
  23#include <linux/sort.h>
  24#include <linux/string.h>
  25
  26#include <soc/tegra/fuse.h>
  27#include <soc/tegra/mc.h>
  28
  29#include "mc.h"
  30
  31#define EMC_FBIO_CFG5				0x104
  32#define	EMC_FBIO_CFG5_DRAM_TYPE_MASK		0x3
  33#define	EMC_FBIO_CFG5_DRAM_TYPE_SHIFT		0
  34#define EMC_FBIO_CFG5_DRAM_WIDTH_X64		BIT(4)
  35
  36#define EMC_INTSTATUS				0x0
  37#define EMC_INTSTATUS_CLKCHANGE_COMPLETE	BIT(4)
  38
  39#define EMC_CFG					0xc
  40#define EMC_CFG_DRAM_CLKSTOP_PD			BIT(31)
  41#define EMC_CFG_DRAM_CLKSTOP_SR			BIT(30)
  42#define EMC_CFG_DRAM_ACPD			BIT(29)
  43#define EMC_CFG_DYN_SREF			BIT(28)
  44#define EMC_CFG_PWR_MASK			((0xF << 28) | BIT(18))
  45#define EMC_CFG_DSR_VTTGEN_DRV_EN		BIT(18)
  46
  47#define EMC_REFCTRL				0x20
  48#define EMC_REFCTRL_DEV_SEL_SHIFT		0
  49#define EMC_REFCTRL_ENABLE			BIT(31)
  50
  51#define EMC_TIMING_CONTROL			0x28
  52#define EMC_RC					0x2c
  53#define EMC_RFC					0x30
  54#define EMC_RAS					0x34
  55#define EMC_RP					0x38
  56#define EMC_R2W					0x3c
  57#define EMC_W2R					0x40
  58#define EMC_R2P					0x44
  59#define EMC_W2P					0x48
  60#define EMC_RD_RCD				0x4c
  61#define EMC_WR_RCD				0x50
  62#define EMC_RRD					0x54
  63#define EMC_REXT				0x58
  64#define EMC_WDV					0x5c
  65#define EMC_QUSE				0x60
  66#define EMC_QRST				0x64
  67#define EMC_QSAFE				0x68
  68#define EMC_RDV					0x6c
  69#define EMC_REFRESH				0x70
  70#define EMC_BURST_REFRESH_NUM			0x74
  71#define EMC_PDEX2WR				0x78
  72#define EMC_PDEX2RD				0x7c
  73#define EMC_PCHG2PDEN				0x80
  74#define EMC_ACT2PDEN				0x84
  75#define EMC_AR2PDEN				0x88
  76#define EMC_RW2PDEN				0x8c
  77#define EMC_TXSR				0x90
  78#define EMC_TCKE				0x94
  79#define EMC_TFAW				0x98
  80#define EMC_TRPAB				0x9c
  81#define EMC_TCLKSTABLE				0xa0
  82#define EMC_TCLKSTOP				0xa4
  83#define EMC_TREFBW				0xa8
  84#define EMC_ODT_WRITE				0xb0
  85#define EMC_ODT_READ				0xb4
  86#define EMC_WEXT				0xb8
  87#define EMC_CTT					0xbc
  88#define EMC_RFC_SLR				0xc0
  89#define EMC_MRS_WAIT_CNT2			0xc4
  90
  91#define EMC_MRS_WAIT_CNT			0xc8
  92#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT	0
  93#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK	\
  94	(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
  95#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT	16
  96#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK		\
  97	(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
  98
  99#define EMC_MRS					0xcc
 100#define EMC_MODE_SET_DLL_RESET			BIT(8)
 101#define EMC_MODE_SET_LONG_CNT			BIT(26)
 102#define EMC_EMRS				0xd0
 103#define EMC_REF					0xd4
 104#define EMC_PRE					0xd8
 105
 106#define EMC_SELF_REF				0xe0
 107#define EMC_SELF_REF_CMD_ENABLED		BIT(0)
 108#define EMC_SELF_REF_DEV_SEL_SHIFT		30
 109
 110#define EMC_MRW					0xe8
 111
 112#define EMC_MRR					0xec
 113#define EMC_MRR_MA_SHIFT			16
 114#define LPDDR2_MR4_TEMP_SHIFT			0
 115
 116#define EMC_XM2DQSPADCTRL3			0xf8
 117#define EMC_FBIO_SPARE				0x100
 118
 119#define EMC_FBIO_CFG6				0x114
 120#define EMC_EMRS2				0x12c
 121#define EMC_MRW2				0x134
 122#define EMC_MRW4				0x13c
 123#define EMC_EINPUT				0x14c
 124#define EMC_EINPUT_DURATION			0x150
 125#define EMC_PUTERM_EXTRA			0x154
 126#define EMC_TCKESR				0x158
 127#define EMC_TPD					0x15c
 128
 129#define EMC_AUTO_CAL_CONFIG			0x2a4
 130#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START	BIT(31)
 131#define EMC_AUTO_CAL_INTERVAL			0x2a8
 132#define EMC_AUTO_CAL_STATUS			0x2ac
 133#define EMC_AUTO_CAL_STATUS_ACTIVE		BIT(31)
 134#define EMC_STATUS				0x2b4
 135#define EMC_STATUS_TIMING_UPDATE_STALLED	BIT(23)
 136
 137#define EMC_CFG_2				0x2b8
 138#define EMC_CFG_2_MODE_SHIFT			0
 139#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR	BIT(6)
 140
 141#define EMC_CFG_DIG_DLL				0x2bc
 142#define EMC_CFG_DIG_DLL_PERIOD			0x2c0
 143#define EMC_RDV_MASK				0x2cc
 144#define EMC_WDV_MASK				0x2d0
 145#define EMC_CTT_DURATION			0x2d8
 146#define EMC_CTT_TERM_CTRL			0x2dc
 147#define EMC_ZCAL_INTERVAL			0x2e0
 148#define EMC_ZCAL_WAIT_CNT			0x2e4
 149
 150#define EMC_ZQ_CAL				0x2ec
 151#define EMC_ZQ_CAL_CMD				BIT(0)
 152#define EMC_ZQ_CAL_LONG				BIT(4)
 153#define EMC_ZQ_CAL_LONG_CMD_DEV0		\
 154	(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
 155#define EMC_ZQ_CAL_LONG_CMD_DEV1		\
 156	(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
 157
 158#define EMC_XM2CMDPADCTRL			0x2f0
 159#define EMC_XM2DQSPADCTRL			0x2f8
 160#define EMC_XM2DQSPADCTRL2			0x2fc
 161#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE	BIT(0)
 162#define EMC_XM2DQSPADCTRL2_VREF_ENABLE		BIT(5)
 163#define EMC_XM2DQPADCTRL			0x300
 164#define EMC_XM2DQPADCTRL2			0x304
 165#define EMC_XM2CLKPADCTRL			0x308
 166#define EMC_XM2COMPPADCTRL			0x30c
 167#define EMC_XM2VTTGENPADCTRL			0x310
 168#define EMC_XM2VTTGENPADCTRL2			0x314
 169#define EMC_XM2VTTGENPADCTRL3			0x318
 170#define EMC_XM2DQSPADCTRL4			0x320
 171#define EMC_DLL_XFORM_DQS0			0x328
 172#define EMC_DLL_XFORM_DQS1			0x32c
 173#define EMC_DLL_XFORM_DQS2			0x330
 174#define EMC_DLL_XFORM_DQS3			0x334
 175#define EMC_DLL_XFORM_DQS4			0x338
 176#define EMC_DLL_XFORM_DQS5			0x33c
 177#define EMC_DLL_XFORM_DQS6			0x340
 178#define EMC_DLL_XFORM_DQS7			0x344
 179#define EMC_DLL_XFORM_QUSE0			0x348
 180#define EMC_DLL_XFORM_QUSE1			0x34c
 181#define EMC_DLL_XFORM_QUSE2			0x350
 182#define EMC_DLL_XFORM_QUSE3			0x354
 183#define EMC_DLL_XFORM_QUSE4			0x358
 184#define EMC_DLL_XFORM_QUSE5			0x35c
 185#define EMC_DLL_XFORM_QUSE6			0x360
 186#define EMC_DLL_XFORM_QUSE7			0x364
 187#define EMC_DLL_XFORM_DQ0			0x368
 188#define EMC_DLL_XFORM_DQ1			0x36c
 189#define EMC_DLL_XFORM_DQ2			0x370
 190#define EMC_DLL_XFORM_DQ3			0x374
 191#define EMC_DLI_TRIM_TXDQS0			0x3a8
 192#define EMC_DLI_TRIM_TXDQS1			0x3ac
 193#define EMC_DLI_TRIM_TXDQS2			0x3b0
 194#define EMC_DLI_TRIM_TXDQS3			0x3b4
 195#define EMC_DLI_TRIM_TXDQS4			0x3b8
 196#define EMC_DLI_TRIM_TXDQS5			0x3bc
 197#define EMC_DLI_TRIM_TXDQS6			0x3c0
 198#define EMC_DLI_TRIM_TXDQS7			0x3c4
 199#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE	0x3cc
 200#define EMC_SEL_DPD_CTRL			0x3d8
 201#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD		BIT(8)
 202#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD		BIT(5)
 203#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD		BIT(4)
 204#define EMC_SEL_DPD_CTRL_CA_SEL_DPD		BIT(3)
 205#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD		BIT(2)
 206#define EMC_SEL_DPD_CTRL_DDR3_MASK	\
 207	((0xf << 2) | BIT(8))
 208#define EMC_SEL_DPD_CTRL_MASK \
 209	((0x3 << 2) | BIT(5) | BIT(8))
 210#define EMC_PRE_REFRESH_REQ_CNT			0x3dc
 211#define EMC_DYN_SELF_REF_CONTROL		0x3e0
 212#define EMC_TXSRDLL				0x3e4
 213#define EMC_CCFIFO_ADDR				0x3e8
 214#define EMC_CCFIFO_DATA				0x3ec
 215#define EMC_CCFIFO_STATUS			0x3f0
 216#define EMC_CDB_CNTL_1				0x3f4
 217#define EMC_CDB_CNTL_2				0x3f8
 218#define EMC_XM2CLKPADCTRL2			0x3fc
 219#define EMC_AUTO_CAL_CONFIG2			0x458
 220#define EMC_AUTO_CAL_CONFIG3			0x45c
 221#define EMC_IBDLY				0x468
 222#define EMC_DLL_XFORM_ADDR0			0x46c
 223#define EMC_DLL_XFORM_ADDR1			0x470
 224#define EMC_DLL_XFORM_ADDR2			0x474
 225#define EMC_DSR_VTTGEN_DRV			0x47c
 226#define EMC_TXDSRVTTGEN				0x480
 227#define EMC_XM2CMDPADCTRL4			0x484
 228#define EMC_XM2CMDPADCTRL5			0x488
 229#define EMC_DLL_XFORM_DQS8			0x4a0
 230#define EMC_DLL_XFORM_DQS9			0x4a4
 231#define EMC_DLL_XFORM_DQS10			0x4a8
 232#define EMC_DLL_XFORM_DQS11			0x4ac
 233#define EMC_DLL_XFORM_DQS12			0x4b0
 234#define EMC_DLL_XFORM_DQS13			0x4b4
 235#define EMC_DLL_XFORM_DQS14			0x4b8
 236#define EMC_DLL_XFORM_DQS15			0x4bc
 237#define EMC_DLL_XFORM_QUSE8			0x4c0
 238#define EMC_DLL_XFORM_QUSE9			0x4c4
 239#define EMC_DLL_XFORM_QUSE10			0x4c8
 240#define EMC_DLL_XFORM_QUSE11			0x4cc
 241#define EMC_DLL_XFORM_QUSE12			0x4d0
 242#define EMC_DLL_XFORM_QUSE13			0x4d4
 243#define EMC_DLL_XFORM_QUSE14			0x4d8
 244#define EMC_DLL_XFORM_QUSE15			0x4dc
 245#define EMC_DLL_XFORM_DQ4			0x4e0
 246#define EMC_DLL_XFORM_DQ5			0x4e4
 247#define EMC_DLL_XFORM_DQ6			0x4e8
 248#define EMC_DLL_XFORM_DQ7			0x4ec
 249#define EMC_DLI_TRIM_TXDQS8			0x520
 250#define EMC_DLI_TRIM_TXDQS9			0x524
 251#define EMC_DLI_TRIM_TXDQS10			0x528
 252#define EMC_DLI_TRIM_TXDQS11			0x52c
 253#define EMC_DLI_TRIM_TXDQS12			0x530
 254#define EMC_DLI_TRIM_TXDQS13			0x534
 255#define EMC_DLI_TRIM_TXDQS14			0x538
 256#define EMC_DLI_TRIM_TXDQS15			0x53c
 257#define EMC_CDB_CNTL_3				0x540
 258#define EMC_XM2DQSPADCTRL5			0x544
 259#define EMC_XM2DQSPADCTRL6			0x548
 260#define EMC_XM2DQPADCTRL3			0x54c
 261#define EMC_DLL_XFORM_ADDR3			0x550
 262#define EMC_DLL_XFORM_ADDR4			0x554
 263#define EMC_DLL_XFORM_ADDR5			0x558
 264#define EMC_CFG_PIPE				0x560
 265#define EMC_QPOP				0x564
 266#define EMC_QUSE_WIDTH				0x568
 267#define EMC_PUTERM_WIDTH			0x56c
 268#define EMC_BGBIAS_CTL0				0x570
 269#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
 270#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
 271#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD	BIT(1)
 272#define EMC_PUTERM_ADJ				0x574
 273
 274#define DRAM_DEV_SEL_ALL			0
 275#define DRAM_DEV_SEL_0				BIT(31)
 276#define DRAM_DEV_SEL_1				BIT(30)
 277
 278#define EMC_CFG_POWER_FEATURES_MASK		\
 279	(EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
 280	EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
 281#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
 282#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
 283
 284/* Maximum amount of time in us. to wait for changes to become effective */
 285#define EMC_STATUS_UPDATE_TIMEOUT		1000
 286
 287enum emc_dram_type {
 288	DRAM_TYPE_DDR3 = 0,
 289	DRAM_TYPE_DDR1 = 1,
 290	DRAM_TYPE_LPDDR3 = 2,
 291	DRAM_TYPE_DDR2 = 3
 292};
 293
 294enum emc_dll_change {
 295	DLL_CHANGE_NONE,
 296	DLL_CHANGE_ON,
 297	DLL_CHANGE_OFF
 298};
 299
 300static const unsigned long emc_burst_regs[] = {
 301	EMC_RC,
 302	EMC_RFC,
 303	EMC_RFC_SLR,
 304	EMC_RAS,
 305	EMC_RP,
 306	EMC_R2W,
 307	EMC_W2R,
 308	EMC_R2P,
 309	EMC_W2P,
 310	EMC_RD_RCD,
 311	EMC_WR_RCD,
 312	EMC_RRD,
 313	EMC_REXT,
 314	EMC_WEXT,
 315	EMC_WDV,
 316	EMC_WDV_MASK,
 317	EMC_QUSE,
 318	EMC_QUSE_WIDTH,
 319	EMC_IBDLY,
 320	EMC_EINPUT,
 321	EMC_EINPUT_DURATION,
 322	EMC_PUTERM_EXTRA,
 323	EMC_PUTERM_WIDTH,
 324	EMC_PUTERM_ADJ,
 325	EMC_CDB_CNTL_1,
 326	EMC_CDB_CNTL_2,
 327	EMC_CDB_CNTL_3,
 328	EMC_QRST,
 329	EMC_QSAFE,
 330	EMC_RDV,
 331	EMC_RDV_MASK,
 332	EMC_REFRESH,
 333	EMC_BURST_REFRESH_NUM,
 334	EMC_PRE_REFRESH_REQ_CNT,
 335	EMC_PDEX2WR,
 336	EMC_PDEX2RD,
 337	EMC_PCHG2PDEN,
 338	EMC_ACT2PDEN,
 339	EMC_AR2PDEN,
 340	EMC_RW2PDEN,
 341	EMC_TXSR,
 342	EMC_TXSRDLL,
 343	EMC_TCKE,
 344	EMC_TCKESR,
 345	EMC_TPD,
 346	EMC_TFAW,
 347	EMC_TRPAB,
 348	EMC_TCLKSTABLE,
 349	EMC_TCLKSTOP,
 350	EMC_TREFBW,
 351	EMC_FBIO_CFG6,
 352	EMC_ODT_WRITE,
 353	EMC_ODT_READ,
 354	EMC_FBIO_CFG5,
 355	EMC_CFG_DIG_DLL,
 356	EMC_CFG_DIG_DLL_PERIOD,
 357	EMC_DLL_XFORM_DQS0,
 358	EMC_DLL_XFORM_DQS1,
 359	EMC_DLL_XFORM_DQS2,
 360	EMC_DLL_XFORM_DQS3,
 361	EMC_DLL_XFORM_DQS4,
 362	EMC_DLL_XFORM_DQS5,
 363	EMC_DLL_XFORM_DQS6,
 364	EMC_DLL_XFORM_DQS7,
 365	EMC_DLL_XFORM_DQS8,
 366	EMC_DLL_XFORM_DQS9,
 367	EMC_DLL_XFORM_DQS10,
 368	EMC_DLL_XFORM_DQS11,
 369	EMC_DLL_XFORM_DQS12,
 370	EMC_DLL_XFORM_DQS13,
 371	EMC_DLL_XFORM_DQS14,
 372	EMC_DLL_XFORM_DQS15,
 373	EMC_DLL_XFORM_QUSE0,
 374	EMC_DLL_XFORM_QUSE1,
 375	EMC_DLL_XFORM_QUSE2,
 376	EMC_DLL_XFORM_QUSE3,
 377	EMC_DLL_XFORM_QUSE4,
 378	EMC_DLL_XFORM_QUSE5,
 379	EMC_DLL_XFORM_QUSE6,
 380	EMC_DLL_XFORM_QUSE7,
 381	EMC_DLL_XFORM_ADDR0,
 382	EMC_DLL_XFORM_ADDR1,
 383	EMC_DLL_XFORM_ADDR2,
 384	EMC_DLL_XFORM_ADDR3,
 385	EMC_DLL_XFORM_ADDR4,
 386	EMC_DLL_XFORM_ADDR5,
 387	EMC_DLL_XFORM_QUSE8,
 388	EMC_DLL_XFORM_QUSE9,
 389	EMC_DLL_XFORM_QUSE10,
 390	EMC_DLL_XFORM_QUSE11,
 391	EMC_DLL_XFORM_QUSE12,
 392	EMC_DLL_XFORM_QUSE13,
 393	EMC_DLL_XFORM_QUSE14,
 394	EMC_DLL_XFORM_QUSE15,
 395	EMC_DLI_TRIM_TXDQS0,
 396	EMC_DLI_TRIM_TXDQS1,
 397	EMC_DLI_TRIM_TXDQS2,
 398	EMC_DLI_TRIM_TXDQS3,
 399	EMC_DLI_TRIM_TXDQS4,
 400	EMC_DLI_TRIM_TXDQS5,
 401	EMC_DLI_TRIM_TXDQS6,
 402	EMC_DLI_TRIM_TXDQS7,
 403	EMC_DLI_TRIM_TXDQS8,
 404	EMC_DLI_TRIM_TXDQS9,
 405	EMC_DLI_TRIM_TXDQS10,
 406	EMC_DLI_TRIM_TXDQS11,
 407	EMC_DLI_TRIM_TXDQS12,
 408	EMC_DLI_TRIM_TXDQS13,
 409	EMC_DLI_TRIM_TXDQS14,
 410	EMC_DLI_TRIM_TXDQS15,
 411	EMC_DLL_XFORM_DQ0,
 412	EMC_DLL_XFORM_DQ1,
 413	EMC_DLL_XFORM_DQ2,
 414	EMC_DLL_XFORM_DQ3,
 415	EMC_DLL_XFORM_DQ4,
 416	EMC_DLL_XFORM_DQ5,
 417	EMC_DLL_XFORM_DQ6,
 418	EMC_DLL_XFORM_DQ7,
 419	EMC_XM2CMDPADCTRL,
 420	EMC_XM2CMDPADCTRL4,
 421	EMC_XM2CMDPADCTRL5,
 422	EMC_XM2DQPADCTRL2,
 423	EMC_XM2DQPADCTRL3,
 424	EMC_XM2CLKPADCTRL,
 425	EMC_XM2CLKPADCTRL2,
 426	EMC_XM2COMPPADCTRL,
 427	EMC_XM2VTTGENPADCTRL,
 428	EMC_XM2VTTGENPADCTRL2,
 429	EMC_XM2VTTGENPADCTRL3,
 430	EMC_XM2DQSPADCTRL3,
 431	EMC_XM2DQSPADCTRL4,
 432	EMC_XM2DQSPADCTRL5,
 433	EMC_XM2DQSPADCTRL6,
 434	EMC_DSR_VTTGEN_DRV,
 435	EMC_TXDSRVTTGEN,
 436	EMC_FBIO_SPARE,
 437	EMC_ZCAL_WAIT_CNT,
 438	EMC_MRS_WAIT_CNT2,
 439	EMC_CTT,
 440	EMC_CTT_DURATION,
 441	EMC_CFG_PIPE,
 442	EMC_DYN_SELF_REF_CONTROL,
 443	EMC_QPOP
 444};
 445
 446struct emc_timing {
 447	unsigned long rate;
 448
 449	u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
 450
 451	u32 emc_auto_cal_config;
 452	u32 emc_auto_cal_config2;
 453	u32 emc_auto_cal_config3;
 454	u32 emc_auto_cal_interval;
 455	u32 emc_bgbias_ctl0;
 456	u32 emc_cfg;
 457	u32 emc_cfg_2;
 458	u32 emc_ctt_term_ctrl;
 459	u32 emc_mode_1;
 460	u32 emc_mode_2;
 461	u32 emc_mode_4;
 462	u32 emc_mode_reset;
 463	u32 emc_mrs_wait_cnt;
 464	u32 emc_sel_dpd_ctrl;
 465	u32 emc_xm2dqspadctrl2;
 466	u32 emc_zcal_cnt_long;
 467	u32 emc_zcal_interval;
 468};
 469
 470enum emc_rate_request_type {
 471	EMC_RATE_DEBUG,
 472	EMC_RATE_ICC,
 473	EMC_RATE_TYPE_MAX,
 474};
 475
 476struct emc_rate_request {
 477	unsigned long min_rate;
 478	unsigned long max_rate;
 479};
 480
 481struct tegra_emc {
 482	struct device *dev;
 483
 484	struct tegra_mc *mc;
 485
 486	void __iomem *regs;
 487
 488	struct clk *clk;
 489
 490	enum emc_dram_type dram_type;
 491	unsigned int dram_bus_width;
 492	unsigned int dram_num;
 493
 494	struct emc_timing last_timing;
 495	struct emc_timing *timings;
 496	unsigned int num_timings;
 497
 498	struct {
 499		struct dentry *root;
 500		unsigned long min_rate;
 501		unsigned long max_rate;
 502	} debugfs;
 503
 504	struct icc_provider provider;
 505
 506	/*
 507	 * There are multiple sources in the EMC driver which could request
 508	 * a min/max clock rate, these rates are contained in this array.
 509	 */
 510	struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
 511
 512	/* protect shared rate-change code path */
 513	struct mutex rate_lock;
 514};
 515
 516/* Timing change sequence functions */
 517
 518static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
 519			      unsigned long offset)
 520{
 521	writel(value, emc->regs + EMC_CCFIFO_DATA);
 522	writel(offset, emc->regs + EMC_CCFIFO_ADDR);
 523}
 524
 525static void emc_seq_update_timing(struct tegra_emc *emc)
 526{
 527	unsigned int i;
 528	u32 value;
 529
 530	writel(1, emc->regs + EMC_TIMING_CONTROL);
 531
 532	for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
 533		value = readl(emc->regs + EMC_STATUS);
 534		if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
 535			return;
 536		udelay(1);
 537	}
 538
 539	dev_err(emc->dev, "timing update timed out\n");
 540}
 541
 542static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
 543{
 544	unsigned int i;
 545	u32 value;
 546
 547	writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
 548
 549	for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
 550		value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
 551		if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
 552			return;
 553		udelay(1);
 554	}
 555
 556	dev_err(emc->dev, "auto cal disable timed out\n");
 557}
 558
 559static void emc_seq_wait_clkchange(struct tegra_emc *emc)
 560{
 561	unsigned int i;
 562	u32 value;
 563
 564	for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
 565		value = readl(emc->regs + EMC_INTSTATUS);
 566		if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
 567			return;
 568		udelay(1);
 569	}
 570
 571	dev_err(emc->dev, "clock change timed out\n");
 572}
 573
 574static struct emc_timing *tegra124_emc_find_timing(struct tegra_emc *emc,
 575						   unsigned long rate)
 576{
 577	struct emc_timing *timing = NULL;
 578	unsigned int i;
 579
 580	for (i = 0; i < emc->num_timings; i++) {
 581		if (emc->timings[i].rate == rate) {
 582			timing = &emc->timings[i];
 583			break;
 584		}
 585	}
 586
 587	if (!timing) {
 588		dev_err(emc->dev, "no timing for rate %lu\n", rate);
 589		return NULL;
 590	}
 591
 592	return timing;
 593}
 594
 595static int tegra124_emc_prepare_timing_change(struct tegra_emc *emc,
 596					      unsigned long rate)
 597{
 598	struct emc_timing *timing = tegra124_emc_find_timing(emc, rate);
 599	struct emc_timing *last = &emc->last_timing;
 600	enum emc_dll_change dll_change;
 601	unsigned int pre_wait = 0;
 602	u32 val, val2, mask;
 603	bool update = false;
 604	unsigned int i;
 605
 606	if (!timing)
 607		return -ENOENT;
 608
 609	if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
 610		dll_change = DLL_CHANGE_NONE;
 611	else if (timing->emc_mode_1 & 0x1)
 612		dll_change = DLL_CHANGE_ON;
 613	else
 614		dll_change = DLL_CHANGE_OFF;
 615
 616	/* Clear CLKCHANGE_COMPLETE interrupts */
 617	writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
 618
 619	/* Disable dynamic self-refresh */
 620	val = readl(emc->regs + EMC_CFG);
 621	if (val & EMC_CFG_PWR_MASK) {
 622		val &= ~EMC_CFG_POWER_FEATURES_MASK;
 623		writel(val, emc->regs + EMC_CFG);
 624
 625		pre_wait = 5;
 626	}
 627
 628	/* Disable SEL_DPD_CTRL for clock change */
 629	if (emc->dram_type == DRAM_TYPE_DDR3)
 630		mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
 631	else
 632		mask = EMC_SEL_DPD_CTRL_MASK;
 633
 634	val = readl(emc->regs + EMC_SEL_DPD_CTRL);
 635	if (val & mask) {
 636		val &= ~mask;
 637		writel(val, emc->regs + EMC_SEL_DPD_CTRL);
 638	}
 639
 640	/* Prepare DQ/DQS for clock change */
 641	val = readl(emc->regs + EMC_BGBIAS_CTL0);
 642	val2 = last->emc_bgbias_ctl0;
 643	if (!(timing->emc_bgbias_ctl0 &
 644	      EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
 645	    (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
 646		val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
 647		update = true;
 648	}
 649
 650	if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
 651	    (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
 652		update = true;
 653	}
 654
 655	if (update) {
 656		writel(val2, emc->regs + EMC_BGBIAS_CTL0);
 657		if (pre_wait < 5)
 658			pre_wait = 5;
 659	}
 660
 661	update = false;
 662	val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
 663	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
 664	    !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
 665		val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
 666		update = true;
 667	}
 668
 669	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
 670	    !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
 671		val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
 672		update = true;
 673	}
 674
 675	if (update) {
 676		writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
 677		if (pre_wait < 30)
 678			pre_wait = 30;
 679	}
 680
 681	/* Wait to settle */
 682	if (pre_wait) {
 683		emc_seq_update_timing(emc);
 684		udelay(pre_wait);
 685	}
 686
 687	/* Program CTT_TERM control */
 688	if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
 689		emc_seq_disable_auto_cal(emc);
 690		writel(timing->emc_ctt_term_ctrl,
 691		       emc->regs + EMC_CTT_TERM_CTRL);
 692		emc_seq_update_timing(emc);
 693	}
 694
 695	/* Program burst shadow registers */
 696	for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
 697		writel(timing->emc_burst_data[i],
 698		       emc->regs + emc_burst_regs[i]);
 699
 700	writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
 701	writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
 702
 703	tegra_mc_write_emem_configuration(emc->mc, timing->rate);
 704
 705	val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
 706	emc_ccfifo_writel(emc, val, EMC_CFG);
 707
 708	/* Program AUTO_CAL_CONFIG */
 709	if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
 710		emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
 711				  EMC_AUTO_CAL_CONFIG2);
 712
 713	if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
 714		emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
 715				  EMC_AUTO_CAL_CONFIG3);
 716
 717	if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
 718		val = timing->emc_auto_cal_config;
 719		val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
 720		emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
 721	}
 722
 723	/* DDR3: predict MRS long wait count */
 724	if (emc->dram_type == DRAM_TYPE_DDR3 &&
 725	    dll_change == DLL_CHANGE_ON) {
 726		u32 cnt = 512;
 727
 728		if (timing->emc_zcal_interval != 0 &&
 729		    last->emc_zcal_interval == 0)
 730			cnt -= emc->dram_num * 256;
 731
 732		val = (timing->emc_mrs_wait_cnt
 733			& EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
 734			>> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
 735		if (cnt < val)
 736			cnt = val;
 737
 738		val = timing->emc_mrs_wait_cnt
 739			& ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
 740		val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
 741			& EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
 742
 743		writel(val, emc->regs + EMC_MRS_WAIT_CNT);
 744	}
 745
 746	val = timing->emc_cfg_2;
 747	val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
 748	emc_ccfifo_writel(emc, val, EMC_CFG_2);
 749
 750	/* DDR3: Turn off DLL and enter self-refresh */
 751	if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
 752		emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
 753
 754	/* Disable refresh controller */
 755	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
 756			  EMC_REFCTRL);
 757	if (emc->dram_type == DRAM_TYPE_DDR3)
 758		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
 759				       EMC_SELF_REF_CMD_ENABLED,
 760				  EMC_SELF_REF);
 761
 762	/* Flow control marker */
 763	emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
 764
 765	/* DDR3: Exit self-refresh */
 766	if (emc->dram_type == DRAM_TYPE_DDR3)
 767		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
 768				  EMC_SELF_REF);
 769	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
 770			       EMC_REFCTRL_ENABLE,
 771			  EMC_REFCTRL);
 772
 773	/* Set DRAM mode registers */
 774	if (emc->dram_type == DRAM_TYPE_DDR3) {
 775		if (timing->emc_mode_1 != last->emc_mode_1)
 776			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
 777		if (timing->emc_mode_2 != last->emc_mode_2)
 778			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
 779
 780		if ((timing->emc_mode_reset != last->emc_mode_reset) ||
 781		    dll_change == DLL_CHANGE_ON) {
 782			val = timing->emc_mode_reset;
 783			if (dll_change == DLL_CHANGE_ON) {
 784				val |= EMC_MODE_SET_DLL_RESET;
 785				val |= EMC_MODE_SET_LONG_CNT;
 786			} else {
 787				val &= ~EMC_MODE_SET_DLL_RESET;
 788			}
 789			emc_ccfifo_writel(emc, val, EMC_MRS);
 790		}
 791	} else {
 792		if (timing->emc_mode_2 != last->emc_mode_2)
 793			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
 794		if (timing->emc_mode_1 != last->emc_mode_1)
 795			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
 796		if (timing->emc_mode_4 != last->emc_mode_4)
 797			emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
 798	}
 799
 800	/*  Issue ZCAL command if turning ZCAL on */
 801	if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
 802		emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
 803		if (emc->dram_num > 1)
 804			emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
 805					  EMC_ZQ_CAL);
 806	}
 807
 808	/*  Write to RO register to remove stall after change */
 809	emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
 810
 811	if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
 812		emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
 813
 814	/* Disable AUTO_CAL for clock change */
 815	emc_seq_disable_auto_cal(emc);
 816
 817	/* Read register to wait until programming has settled */
 818	readl(emc->regs + EMC_INTSTATUS);
 819
 820	return 0;
 821}
 822
 823static void tegra124_emc_complete_timing_change(struct tegra_emc *emc,
 824						unsigned long rate)
 825{
 826	struct emc_timing *timing = tegra124_emc_find_timing(emc, rate);
 827	struct emc_timing *last = &emc->last_timing;
 828	u32 val;
 829
 830	if (!timing)
 831		return;
 832
 833	/* Wait until the state machine has settled */
 834	emc_seq_wait_clkchange(emc);
 835
 836	/* Restore AUTO_CAL */
 837	if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
 838		writel(timing->emc_auto_cal_interval,
 839		       emc->regs + EMC_AUTO_CAL_INTERVAL);
 840
 841	/* Restore dynamic self-refresh */
 842	if (timing->emc_cfg & EMC_CFG_PWR_MASK)
 843		writel(timing->emc_cfg, emc->regs + EMC_CFG);
 844
 845	/* Set ZCAL wait count */
 846	writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
 847
 848	/* LPDDR3: Turn off BGBIAS if low frequency */
 849	if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
 850	    timing->emc_bgbias_ctl0 &
 851	      EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
 852		val = timing->emc_bgbias_ctl0;
 853		val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
 854		val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
 855		writel(val, emc->regs + EMC_BGBIAS_CTL0);
 856	} else {
 857		if (emc->dram_type == DRAM_TYPE_DDR3 &&
 858		    readl(emc->regs + EMC_BGBIAS_CTL0) !=
 859		      timing->emc_bgbias_ctl0) {
 860			writel(timing->emc_bgbias_ctl0,
 861			       emc->regs + EMC_BGBIAS_CTL0);
 862		}
 863
 864		writel(timing->emc_auto_cal_interval,
 865		       emc->regs + EMC_AUTO_CAL_INTERVAL);
 866	}
 867
 868	/* Wait for timing to settle */
 869	udelay(2);
 870
 871	/* Reprogram SEL_DPD_CTRL */
 872	writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
 873	emc_seq_update_timing(emc);
 874
 875	emc->last_timing = *timing;
 876}
 877
 878/* Initialization and deinitialization */
 879
 880static void emc_read_current_timing(struct tegra_emc *emc,
 881				    struct emc_timing *timing)
 882{
 883	unsigned int i;
 884
 885	for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
 886		timing->emc_burst_data[i] =
 887			readl(emc->regs + emc_burst_regs[i]);
 888
 889	timing->emc_cfg = readl(emc->regs + EMC_CFG);
 890
 891	timing->emc_auto_cal_interval = 0;
 892	timing->emc_zcal_cnt_long = 0;
 893	timing->emc_mode_1 = 0;
 894	timing->emc_mode_2 = 0;
 895	timing->emc_mode_4 = 0;
 896	timing->emc_mode_reset = 0;
 897}
 898
 899static void emc_init(struct tegra_emc *emc)
 900{
 901	emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
 902
 903	if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64)
 904		emc->dram_bus_width = 64;
 905	else
 906		emc->dram_bus_width = 32;
 907
 908	dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
 909
 910	emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
 911	emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
 912
 913	emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
 914
 915	emc_read_current_timing(emc, &emc->last_timing);
 916}
 917
 918static int load_one_timing_from_dt(struct tegra_emc *emc,
 919				   struct emc_timing *timing,
 920				   struct device_node *node)
 921{
 922	u32 value;
 923	int err;
 924
 925	err = of_property_read_u32(node, "clock-frequency", &value);
 926	if (err) {
 927		dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
 928			node, err);
 929		return err;
 930	}
 931
 932	timing->rate = value;
 933
 934	err = of_property_read_u32_array(node, "nvidia,emc-configuration",
 935					 timing->emc_burst_data,
 936					 ARRAY_SIZE(timing->emc_burst_data));
 937	if (err) {
 938		dev_err(emc->dev,
 939			"timing %pOFn: failed to read emc burst data: %d\n",
 940			node, err);
 941		return err;
 942	}
 943
 944#define EMC_READ_PROP(prop, dtprop) { \
 945	err = of_property_read_u32(node, dtprop, &timing->prop); \
 946	if (err) { \
 947		dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
 948			node, err); \
 949		return err; \
 950	} \
 951}
 952
 953	EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
 954	EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
 955	EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
 956	EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
 957	EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
 958	EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
 959	EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
 960	EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
 961	EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
 962	EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
 963	EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
 964	EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
 965	EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
 966	EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
 967	EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
 968	EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
 969	EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
 970
 971#undef EMC_READ_PROP
 972
 973	return 0;
 974}
 975
 976static int cmp_timings(const void *_a, const void *_b)
 977{
 978	const struct emc_timing *a = _a;
 979	const struct emc_timing *b = _b;
 980
 981	if (a->rate < b->rate)
 982		return -1;
 983	else if (a->rate == b->rate)
 984		return 0;
 985	else
 986		return 1;
 987}
 988
 989static int tegra124_emc_load_timings_from_dt(struct tegra_emc *emc,
 990					     struct device_node *node)
 991{
 992	int child_count = of_get_child_count(node);
 993	struct emc_timing *timing;
 994	unsigned int i = 0;
 995	int err;
 996
 997	emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
 998				    GFP_KERNEL);
 999	if (!emc->timings)
1000		return -ENOMEM;
1001
1002	emc->num_timings = child_count;
1003
1004	for_each_child_of_node_scoped(node, child) {
1005		timing = &emc->timings[i++];
1006
1007		err = load_one_timing_from_dt(emc, timing, child);
1008		if (err)
1009			return err;
1010	}
1011
1012	sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
1013	     NULL);
1014
1015	return 0;
1016}
1017
1018static const struct of_device_id tegra124_emc_of_match[] = {
1019	{ .compatible = "nvidia,tegra124-emc" },
1020	{ .compatible = "nvidia,tegra132-emc" },
1021	{}
1022};
1023MODULE_DEVICE_TABLE(of, tegra124_emc_of_match);
1024
1025static struct device_node *
1026tegra124_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
1027{
1028	struct device_node *np;
1029	int err;
1030
1031	for_each_child_of_node(node, np) {
1032		u32 value;
1033
1034		err = of_property_read_u32(np, "nvidia,ram-code", &value);
1035		if (err || (value != ram_code))
1036			continue;
1037
1038		return np;
1039	}
1040
1041	return NULL;
1042}
1043
1044static void tegra124_emc_rate_requests_init(struct tegra_emc *emc)
1045{
1046	unsigned int i;
1047
1048	for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
1049		emc->requested_rate[i].min_rate = 0;
1050		emc->requested_rate[i].max_rate = ULONG_MAX;
1051	}
1052}
1053
1054static int emc_request_rate(struct tegra_emc *emc,
1055			    unsigned long new_min_rate,
1056			    unsigned long new_max_rate,
1057			    enum emc_rate_request_type type)
1058{
1059	struct emc_rate_request *req = emc->requested_rate;
1060	unsigned long min_rate = 0, max_rate = ULONG_MAX;
1061	unsigned int i;
1062	int err;
1063
1064	/* select minimum and maximum rates among the requested rates */
1065	for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
1066		if (i == type) {
1067			min_rate = max(new_min_rate, min_rate);
1068			max_rate = min(new_max_rate, max_rate);
1069		} else {
1070			min_rate = max(req->min_rate, min_rate);
1071			max_rate = min(req->max_rate, max_rate);
1072		}
1073	}
1074
1075	if (min_rate > max_rate) {
1076		dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
1077				    __func__, type, min_rate, max_rate);
1078		return -ERANGE;
1079	}
1080
1081	/*
1082	 * EMC rate-changes should go via OPP API because it manages voltage
1083	 * changes.
1084	 */
1085	err = dev_pm_opp_set_rate(emc->dev, min_rate);
1086	if (err)
1087		return err;
1088
1089	emc->requested_rate[type].min_rate = new_min_rate;
1090	emc->requested_rate[type].max_rate = new_max_rate;
1091
1092	return 0;
1093}
1094
1095static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
1096			    enum emc_rate_request_type type)
1097{
1098	struct emc_rate_request *req = &emc->requested_rate[type];
1099	int ret;
1100
1101	mutex_lock(&emc->rate_lock);
1102	ret = emc_request_rate(emc, rate, req->max_rate, type);
1103	mutex_unlock(&emc->rate_lock);
1104
1105	return ret;
1106}
1107
1108static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
1109			    enum emc_rate_request_type type)
1110{
1111	struct emc_rate_request *req = &emc->requested_rate[type];
1112	int ret;
1113
1114	mutex_lock(&emc->rate_lock);
1115	ret = emc_request_rate(emc, req->min_rate, rate, type);
1116	mutex_unlock(&emc->rate_lock);
1117
1118	return ret;
1119}
1120
1121/*
1122 * debugfs interface
1123 *
1124 * The memory controller driver exposes some files in debugfs that can be used
1125 * to control the EMC frequency. The top-level directory can be found here:
1126 *
1127 *   /sys/kernel/debug/emc
1128 *
1129 * It contains the following files:
1130 *
1131 *   - available_rates: This file contains a list of valid, space-separated
1132 *     EMC frequencies.
1133 *
1134 *   - min_rate: Writing a value to this file sets the given frequency as the
1135 *       floor of the permitted range. If this is higher than the currently
1136 *       configured EMC frequency, this will cause the frequency to be
1137 *       increased so that it stays within the valid range.
1138 *
1139 *   - max_rate: Similarily to the min_rate file, writing a value to this file
1140 *       sets the given frequency as the ceiling of the permitted range. If
1141 *       the value is lower than the currently configured EMC frequency, this
1142 *       will cause the frequency to be decreased so that it stays within the
1143 *       valid range.
1144 */
1145
1146static bool tegra124_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1147{
1148	unsigned int i;
1149
1150	for (i = 0; i < emc->num_timings; i++)
1151		if (rate == emc->timings[i].rate)
1152			return true;
1153
1154	return false;
1155}
1156
1157static int tegra124_emc_debug_available_rates_show(struct seq_file *s,
1158						   void *data)
1159{
1160	struct tegra_emc *emc = s->private;
1161	const char *prefix = "";
1162	unsigned int i;
1163
1164	for (i = 0; i < emc->num_timings; i++) {
1165		seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1166		prefix = " ";
1167	}
1168
1169	seq_puts(s, "\n");
1170
1171	return 0;
1172}
1173
1174DEFINE_SHOW_ATTRIBUTE(tegra124_emc_debug_available_rates);
1175
1176static int tegra124_emc_debug_min_rate_get(void *data, u64 *rate)
1177{
1178	struct tegra_emc *emc = data;
1179
1180	*rate = emc->debugfs.min_rate;
1181
1182	return 0;
1183}
1184
1185static int tegra124_emc_debug_min_rate_set(void *data, u64 rate)
1186{
1187	struct tegra_emc *emc = data;
1188	int err;
1189
1190	if (!tegra124_emc_validate_rate(emc, rate))
1191		return -EINVAL;
1192
1193	err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
1194	if (err < 0)
1195		return err;
1196
1197	emc->debugfs.min_rate = rate;
1198
1199	return 0;
1200}
1201
1202DEFINE_DEBUGFS_ATTRIBUTE(tegra124_emc_debug_min_rate_fops,
1203			 tegra124_emc_debug_min_rate_get,
1204			 tegra124_emc_debug_min_rate_set, "%llu\n");
1205
1206static int tegra124_emc_debug_max_rate_get(void *data, u64 *rate)
1207{
1208	struct tegra_emc *emc = data;
1209
1210	*rate = emc->debugfs.max_rate;
1211
1212	return 0;
1213}
1214
1215static int tegra124_emc_debug_max_rate_set(void *data, u64 rate)
1216{
1217	struct tegra_emc *emc = data;
1218	int err;
1219
1220	if (!tegra124_emc_validate_rate(emc, rate))
1221		return -EINVAL;
1222
1223	err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
1224	if (err < 0)
1225		return err;
1226
1227	emc->debugfs.max_rate = rate;
1228
1229	return 0;
1230}
1231
1232DEFINE_DEBUGFS_ATTRIBUTE(tegra124_emc_debug_max_rate_fops,
1233			 tegra124_emc_debug_max_rate_get,
1234			 tegra124_emc_debug_max_rate_set, "%llu\n");
1235
1236static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
1237{
1238	unsigned int i;
1239	int err;
1240
1241	emc->debugfs.min_rate = ULONG_MAX;
1242	emc->debugfs.max_rate = 0;
1243
1244	for (i = 0; i < emc->num_timings; i++) {
1245		if (emc->timings[i].rate < emc->debugfs.min_rate)
1246			emc->debugfs.min_rate = emc->timings[i].rate;
1247
1248		if (emc->timings[i].rate > emc->debugfs.max_rate)
1249			emc->debugfs.max_rate = emc->timings[i].rate;
1250	}
1251
1252	if (!emc->num_timings) {
1253		emc->debugfs.min_rate = clk_get_rate(emc->clk);
1254		emc->debugfs.max_rate = emc->debugfs.min_rate;
1255	}
1256
1257	err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1258				 emc->debugfs.max_rate);
1259	if (err < 0) {
1260		dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
1261			emc->debugfs.min_rate, emc->debugfs.max_rate,
1262			emc->clk);
1263		return;
1264	}
1265
1266	emc->debugfs.root = debugfs_create_dir("emc", NULL);
1267
1268	debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
1269			    &tegra124_emc_debug_available_rates_fops);
1270	debugfs_create_file("min_rate", 0644, emc->debugfs.root,
1271			    emc, &tegra124_emc_debug_min_rate_fops);
1272	debugfs_create_file("max_rate", 0644, emc->debugfs.root,
1273			    emc, &tegra124_emc_debug_max_rate_fops);
1274}
1275
1276static inline struct tegra_emc *
1277to_tegra_emc_provider(struct icc_provider *provider)
1278{
1279	return container_of(provider, struct tegra_emc, provider);
1280}
1281
1282static struct icc_node_data *
1283emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1284{
1285	struct icc_provider *provider = data;
1286	struct icc_node_data *ndata;
1287	struct icc_node *node;
1288
1289	/* External Memory is the only possible ICC route */
1290	list_for_each_entry(node, &provider->nodes, node_list) {
1291		if (node->id != TEGRA_ICC_EMEM)
1292			continue;
1293
1294		ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
1295		if (!ndata)
1296			return ERR_PTR(-ENOMEM);
1297
1298		/*
1299		 * SRC and DST nodes should have matching TAG in order to have
1300		 * it set by default for a requested path.
1301		 */
1302		ndata->tag = TEGRA_MC_ICC_TAG_ISO;
1303		ndata->node = node;
1304
1305		return ndata;
1306	}
1307
1308	return ERR_PTR(-EPROBE_DEFER);
1309}
1310
1311static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
1312{
1313	struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
1314	unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
1315	unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
1316	unsigned long long rate = max(avg_bw, peak_bw);
1317	unsigned int dram_data_bus_width_bytes;
1318	const unsigned int ddr = 2;
1319	int err;
1320
1321	/*
1322	 * Tegra124 EMC runs on a clock rate of SDRAM bus. This means that
1323	 * EMC clock rate is twice smaller than the peak data rate because
1324	 * data is sampled on both EMC clock edges.
1325	 */
1326	dram_data_bus_width_bytes = emc->dram_bus_width / 8;
1327	do_div(rate, ddr * dram_data_bus_width_bytes);
1328	rate = min_t(u64, rate, U32_MAX);
1329
1330	err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1331	if (err)
1332		return err;
1333
1334	return 0;
1335}
1336
1337static int tegra124_emc_interconnect_init(struct tegra_emc *emc)
1338{
1339	const struct tegra_mc_soc *soc = emc->mc->soc;
1340	struct icc_node *node;
1341	int err;
1342
1343	emc->provider.dev = emc->dev;
1344	emc->provider.set = emc_icc_set;
1345	emc->provider.data = &emc->provider;
1346	emc->provider.aggregate = soc->icc_ops->aggregate;
1347	emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1348
1349	icc_provider_init(&emc->provider);
1350
1351	/* create External Memory Controller node */
1352	node = icc_node_create(TEGRA_ICC_EMC);
1353	if (IS_ERR(node))
1354		return PTR_ERR(node);
1355
1356	node->name = "External Memory Controller";
1357	icc_node_add(node, &emc->provider);
1358
1359	/* link External Memory Controller to External Memory (DRAM) */
1360	err = icc_link_create(node, TEGRA_ICC_EMEM);
1361	if (err)
1362		goto remove_nodes;
1363
1364	/* create External Memory node */
1365	node = icc_node_create(TEGRA_ICC_EMEM);
1366	if (IS_ERR(node)) {
1367		err = PTR_ERR(node);
1368		goto remove_nodes;
1369	}
1370
1371	node->name = "External Memory (DRAM)";
1372	icc_node_add(node, &emc->provider);
1373
1374	err = icc_provider_register(&emc->provider);
1375	if (err)
1376		goto remove_nodes;
1377
1378	return 0;
1379
1380remove_nodes:
1381	icc_nodes_remove(&emc->provider);
1382
1383	return dev_err_probe(emc->dev, err, "failed to initialize ICC\n");
1384}
1385
1386static int tegra124_emc_opp_table_init(struct tegra_emc *emc)
1387{
1388	u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
1389	int opp_token, err;
1390
1391	err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
1392	if (err < 0)
1393		return dev_err_probe(emc->dev, err, "failed to set OPP supported HW\n");
1394
1395	opp_token = err;
1396
1397	err = dev_pm_opp_of_add_table(emc->dev);
1398	if (err) {
1399		if (err == -ENODEV)
1400			dev_err_probe(emc->dev, err,
1401				      "OPP table not found, please update your device tree\n");
1402		else
1403			dev_err_probe(emc->dev, err, "failed to add OPP table\n");
1404
1405		goto put_hw_table;
1406	}
1407
1408	dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
1409		      hw_version, clk_get_rate(emc->clk) / 1000000);
1410
1411	/* first dummy rate-set initializes voltage state */
1412	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
1413	if (err) {
1414		dev_err_probe(emc->dev, err, "failed to initialize OPP clock\n");
1415		goto remove_table;
1416	}
1417
1418	return 0;
1419
1420remove_table:
1421	dev_pm_opp_of_remove_table(emc->dev);
1422put_hw_table:
1423	dev_pm_opp_put_supported_hw(opp_token);
1424
1425	return err;
1426}
1427
1428static void devm_tegra124_emc_unset_callback(void *data)
1429{
1430	tegra124_clk_set_emc_callbacks(NULL, NULL);
1431}
1432
1433static int tegra124_emc_probe(struct platform_device *pdev)
1434{
1435	struct device_node *np;
1436	struct tegra_emc *emc;
1437	u32 ram_code;
1438	int err;
1439
1440	emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1441	if (!emc)
1442		return -ENOMEM;
1443
1444	mutex_init(&emc->rate_lock);
1445	emc->dev = &pdev->dev;
1446
1447	emc->regs = devm_platform_ioremap_resource(pdev, 0);
1448	if (IS_ERR(emc->regs))
1449		return PTR_ERR(emc->regs);
1450
1451	emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
1452	if (IS_ERR(emc->mc))
1453		return PTR_ERR(emc->mc);
1454
1455	ram_code = tegra_read_ram_code();
1456
1457	np = tegra124_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
1458	if (np) {
1459		err = tegra124_emc_load_timings_from_dt(emc, np);
1460		of_node_put(np);
1461		if (err)
1462			return err;
1463	} else {
1464		dev_info_once(&pdev->dev,
1465			      "no memory timings for RAM code %u found in DT\n",
1466			      ram_code);
1467	}
1468
1469	emc_init(emc);
1470
1471	platform_set_drvdata(pdev, emc);
1472
1473	tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change,
1474				       tegra124_emc_complete_timing_change);
1475
1476	err = devm_add_action_or_reset(&pdev->dev, devm_tegra124_emc_unset_callback,
1477				       NULL);
1478	if (err)
1479		return err;
1480
1481	emc->clk = devm_clk_get(&pdev->dev, "emc");
1482	if (IS_ERR(emc->clk))
1483		return dev_err_probe(&pdev->dev, PTR_ERR(emc->clk),
1484				     "failed to get EMC clock\n");
1485
1486	err = tegra124_emc_opp_table_init(emc);
1487	if (err)
1488		return err;
1489
1490	tegra124_emc_rate_requests_init(emc);
1491
1492	if (IS_ENABLED(CONFIG_DEBUG_FS))
1493		emc_debugfs_init(&pdev->dev, emc);
1494
1495	tegra124_emc_interconnect_init(emc);
1496
1497	/*
1498	 * Don't allow the kernel module to be unloaded. Unloading adds some
1499	 * extra complexity which doesn't really worth the effort in a case of
1500	 * this driver.
1501	 */
1502	try_module_get(THIS_MODULE);
1503
1504	return 0;
1505};
1506
1507static struct platform_driver tegra124_emc_driver = {
1508	.probe = tegra124_emc_probe,
1509	.driver = {
1510		.name = "tegra-emc",
1511		.of_match_table = tegra124_emc_of_match,
1512		.suppress_bind_attrs = true,
1513		.sync_state = icc_sync_state,
1514	},
1515};
1516module_platform_driver(tegra124_emc_driver);
1517
1518MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
1519MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver");
1520MODULE_LICENSE("GPL v2");