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mtk-smi.c
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linux-6.19.14/drivers/memory/mtk-smi.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6#include <linux/arm-smccc.h> 7#include <linux/clk.h> 8#include <linux/component.h> 9#include <linux/device.h> 10#include <linux/err.h> 11#include <linux/io.h> 12#include <linux/iopoll.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_platform.h> 16#include <linux/platform_device.h> 17#include <linux/pm_runtime.h> 18#include <linux/soc/mediatek/mtk_sip_svc.h> 19#include <soc/mediatek/smi.h> 20#include <dt-bindings/memory/mt2701-larb-port.h> 21#include <dt-bindings/memory/mtk-memory-port.h> 22 23/* SMI COMMON */ 24#define SMI_L1LEN 0x100 25 26#define SMI_L1_ARB 0x200 27#define SMI_BUS_SEL 0x220 28#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 29/* All are MMU0 defaultly. Only specialize mmu1 here. */ 30#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 31 32#define SMI_READ_FIFO_TH 0x230 33#define SMI_M4U_TH 0x234 34#define SMI_FIFO_TH1 0x238 35#define SMI_FIFO_TH2 0x23c 36#define SMI_DCM 0x300 37#define SMI_DUMMY 0x444 38 39/* SMI LARB */ 40#define SMI_LARB_SLP_CON 0xc 41#define SLP_PROT_EN BIT(0) 42#define SLP_PROT_RDY BIT(16) 43 44#define SMI_LARB_CMD_THRT_CON 0x24 45#define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 46#define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 47 48#define SMI_LARB_SW_FLAG 0x40 49#define SMI_LARB_SW_FLAG_1 0x1 50 51#define SMI_LARB_OSTDL_PORT 0x200 52#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 53 54/* Below are about mmu enable registers, they are different in SoCs */ 55/* gen1: mt2701 */ 56#define REG_SMI_SECUR_CON_BASE 0x5c0 57 58/* every register control 8 port, register offset 0x4 */ 59#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 60#define REG_SMI_SECUR_CON_ADDR(id) \ 61 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 62 63/* 64 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 65 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 66 * or non-security. 67 */ 68#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 69#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 70/* mt2701 domain should be set to 3 */ 71#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 72 73/* gen2: */ 74/* mt8167 */ 75#define MT8167_SMI_LARB_MMU_EN 0xfc0 76 77/* mt8173 */ 78#define MT8173_SMI_LARB_MMU_EN 0xf00 79 80/* general */ 81#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 82#define F_MMU_EN BIT(0) 83#define BANK_SEL(id) ({ \ 84 u32 _id = (id) & 0x3; \ 85 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 86}) 87 88#define SMI_COMMON_INIT_REGS_NR 6 89#define SMI_LARB_PORT_NR_MAX 32 90 91#define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 92#define MTK_SMI_FLAG_SW_FLAG BIT(1) 93#define MTK_SMI_FLAG_SLEEP_CTL BIT(2) 94#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3) 95#define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 96 97struct mtk_smi_reg_pair { 98 unsigned int offset; 99 u32 value; 100}; 101 102enum mtk_smi_type { 103 MTK_SMI_GEN1, 104 MTK_SMI_GEN2, /* gen2 smi common */ 105 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 106}; 107 108/* larbs: Require apb/smi clocks while gals is optional. */ 109static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 110#define MTK_SMI_LARB_REQ_CLK_NR 2 111#define MTK_SMI_LARB_OPT_CLK_NR 1 112 113/* 114 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 115 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 116 */ 117static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 118#define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) 119#define MTK_SMI_COM_REQ_CLK_NR 2 120#define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 121#define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 122 123struct mtk_smi_common_plat { 124 enum mtk_smi_type type; 125 bool has_gals; 126 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 127 128 const struct mtk_smi_reg_pair *init; 129}; 130 131struct mtk_smi_larb_gen { 132 int port_in_larb[MTK_LARB_NR_MAX + 1]; 133 int (*config_port)(struct device *dev); 134 unsigned int larb_direct_to_common_mask; 135 unsigned int flags_general; 136 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 137}; 138 139struct mtk_smi { 140 struct device *dev; 141 unsigned int clk_num; 142 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 143 struct clk *clk_async; /*only needed by mt2701*/ 144 union { 145 void __iomem *smi_ao_base; /* only for gen1 */ 146 void __iomem *base; /* only for gen2 */ 147 }; 148 struct device *smi_common_dev; /* for sub common */ 149 const struct mtk_smi_common_plat *plat; 150}; 151 152struct mtk_smi_larb { /* larb: local arbiter */ 153 struct mtk_smi smi; 154 void __iomem *base; 155 struct device *smi_common_dev; /* common or sub-common dev */ 156 const struct mtk_smi_larb_gen *larb_gen; 157 int larbid; 158 u32 *mmu; 159 unsigned char *bank; 160}; 161 162static int 163mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 164{ 165 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 166 struct mtk_smi_larb_iommu *larb_mmu = data; 167 unsigned int i; 168 169 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 170 if (dev == larb_mmu[i].dev) { 171 larb->larbid = i; 172 larb->mmu = &larb_mmu[i].mmu; 173 larb->bank = larb_mmu[i].bank; 174 return 0; 175 } 176 } 177 return -ENODEV; 178} 179 180static void 181mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 182{ 183 /* Do nothing as the iommu is always enabled. */ 184} 185 186static const struct component_ops mtk_smi_larb_component_ops = { 187 .bind = mtk_smi_larb_bind, 188 .unbind = mtk_smi_larb_unbind, 189}; 190 191static int mtk_smi_larb_config_port_gen1(struct device *dev) 192{ 193 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 194 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 195 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 196 int i, m4u_port_id, larb_port_num; 197 u32 sec_con_val, reg_val; 198 199 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 200 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 201 - larb_gen->port_in_larb[larb->larbid]; 202 203 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 204 if (*larb->mmu & BIT(i)) { 205 /* bit[port + 3] controls the virtual or physical */ 206 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 207 } else { 208 /* do not need to enable m4u for this port */ 209 continue; 210 } 211 reg_val = readl(common->smi_ao_base 212 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 213 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 214 reg_val |= sec_con_val; 215 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 216 writel(reg_val, 217 common->smi_ao_base 218 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 219 } 220 return 0; 221} 222 223static int mtk_smi_larb_config_port_mt8167(struct device *dev) 224{ 225 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 226 227 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 228 return 0; 229} 230 231static int mtk_smi_larb_config_port_mt8173(struct device *dev) 232{ 233 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 234 235 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 236 return 0; 237} 238 239static int mtk_smi_larb_config_port_gen2_general(struct device *dev) 240{ 241 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 242 u32 reg, flags_general = larb->larb_gen->flags_general; 243 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 244 struct arm_smccc_res res; 245 int i; 246 247 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 248 return 0; 249 250 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 252 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 253 reg |= SMI_LARB_THRT_RD_NU_LMT; 254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 255 } 256 257 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 259 260 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 262 263 /* 264 * When mmu_en bits are in security world, the bank_sel still is in the 265 * LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no 266 * effect in this case. 267 */ 268 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) { 269 arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB, 270 larb->larbid, *larb->mmu, 0, 0, 0, 0, &res); 271 if (res.a0 != 0) { 272 dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0); 273 return -EINVAL; 274 } 275 } 276 277 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 278 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 279 reg |= F_MMU_EN; 280 reg |= BANK_SEL(larb->bank[i]); 281 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 282 } 283 return 0; 284} 285 286static const u8 mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = { 287 [0] = {0x2, 0x6, 0x2, 0x2, 0x2, 0x28, 0x18, 0x18, 0x1, 0x1, 0x1, 0x8, 288 0x8, 0x1, 0x3f}, 289 [1] = {0x2, 0x6, 0x2, 0x2, 0x2, 0x28, 0x18, 0x18, 0x1, 0x1, 0x1, 0x8, 290 0x8, 0x1, 0x3f}, 291 [2] = {0x5, 0x5, 0x5, 0x5, 0x1, 0x3f}, 292 [3] = {0x5, 0x5, 0x5, 0x5, 0x1, 0x3f}, 293 [4] = {0x28, 0x19, 0xb, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x1}, 294 [5] = {0x1, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x16}, 295 [6] = {}, 296 [7] = {0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x4, 0x1, 297 0x4, 0x1, 0xa, 0x6, 0x1, 0xa, 0x6, 0x1, 0x1, 0x1, 0x1, 0x5, 298 0x3, 0x3, 0x4}, 299 [8] = {0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x4, 0x1, 300 0x4, 0x1, 0xa, 0x6, 0x1, 0xa, 0x6, 0x1, 0x1, 0x1, 0x1, 0x5, 301 0x3, 0x3, 0x4}, 302 [9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0x6, 0x7, 0x4, 303 0x9, 0x3, 0x4, 0xe, 0x1, 0x7, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2, 304 0xf, 0x8, 0x1, 0x1, 0x1}, 305 [10] = {}, 306 [11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0x6, 0x7, 0x4, 307 0x9, 0x3, 0x4, 0xe, 0x1, 0x7, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 308 0x1, 0x1, 0x1, 0x1, 0x1}, 309 [12] = {}, 310 [13] = {0x2, 0xc, 0xc, 0xe, 0x6, 0x6, 0x6, 0x6, 0x6, 0x12, 0x6, 0x1}, 311 [14] = {0x2, 0xc, 0xc, 0x28, 0x12, 0x6}, 312 [15] = {0x28, 0x1, 0x2, 0x28, 0x1}, 313 [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x2, 0x14, 0x14, 0x4, 0x4, 0x4, 0x2, 314 0x4, 0x2, 0x8, 0x4, 0x4}, 315 [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x2, 0x14, 0x14, 0x4, 0x4, 0x4, 0x2, 316 0x4, 0x2, 0x8, 0x4, 0x4}, 317 [18] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x2, 0x14, 0x14, 0x4, 0x4, 0x4, 0x2, 318 0x4, 0x2, 0x8, 0x4, 0x4}, 319 [19] = {0x2, 0x2, 0x4, 0x2}, 320 [20] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1}, 321}; 322 323static const u8 mtk_smi_larb_mt8186_ostd[][SMI_LARB_PORT_NR_MAX] = { 324 [0] = {0x2, 0x1, 0x8, 0x1,}, 325 [1] = {0x1, 0x3, 0x1, 0x1,}, 326 [2] = {0x6, 0x1, 0x4, 0x1,}, 327 [3] = {}, 328 [4] = {0xf, 0x1, 0x5, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 329 0x1, 0x1, 0x1,}, 330 [5] = {}, 331 [6] = {}, 332 [7] = {0x1, 0x3, 0x1, 0x1, 0x1, 0x3, 0x2, 0xd, 0x7, 0x5, 0x3, 333 0x1, 0x5,}, 334 [8] = {0x1, 0x2, 0x2,}, 335 [9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4, 336 0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 337 0x1, 0x1, 0x1, 0x1, 0x1,}, 338 [10] = {}, 339 [11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4, 340 0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2, 341 0xf, 0x8, 0x1, 0x1, 0x1,}, 342 [12] = {}, 343 [13] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x6, 0x6, 0x6, 0x1, 0x1, 0x1,}, 344 [14] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1,}, 345 [15] = {}, 346 [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4, 347 0x2, 0x4, 0x2, 0x8, 0x4, 0x4,}, 348 [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4, 349 0x2, 0x4, 0x2, 0x8, 0x4, 0x4,}, 350 [18] = {}, 351 [19] = {0x1, 0x1, 0x1, 0x1,}, 352 [20] = {0x2, 0x2, 0x2, 0x2, 0x1, 0x1,}, 353}; 354 355static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = { 356 [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,}, 357 [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,}, 358 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, 359 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 360 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,}, 361 [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,}, 362 [6] = {0x06, 0x01, 0x06, 0x0a,}, 363 [7] = {0x0c, 0x0c, 0x12,}, 364 [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14, 365 0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05, 366 0x03, 0x01, 0x1e, 0x01, 0x05,}, 367 [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10, 368 0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,}, 369 [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, 370 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, 371 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, 372 [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, 373 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, 374 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, 375 [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, 376 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, 377 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, 378 [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 379 0x07, 0x02, 0x04, 0x02, 0x05, 0x05,}, 380 [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02, 381 0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 382 0x02, 0x02, 0x01, 0x01,}, 383 [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c, 384 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, 385 0x0c, 0x01, 0x01,}, 386 [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d, 387 0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,}, 388 [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 389 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 390 [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 391 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 392 [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 393 [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 394 [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 395 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 396 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 397 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 398 0x01,}, 399 [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,}, 400 [24] = {0x12, 0x06, 0x12, 0x06,}, 401 [25] = {0x01}, 402}; 403 404static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] = { 405 [0] = {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,}, 406 [1] = {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,}, 407 [2] = {0x5, 0x5, 0x5, 0x5, 0x1,}, 408 [3] = {}, 409 [4] = {0x28, 0x19, 0xb, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x1,}, 410 [5] = {0x1, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x16,}, 411 [6] = {}, 412 [7] = {0x1, 0x3, 0x2, 0x1, 0x1, 0x5, 0x2, 0x12, 0x13, 0x4, 0x4, 0x1, 413 0x4, 0x2, 0x1,}, 414 [8] = {}, 415 [9] = {0xa, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0x6, 0x7, 0x4, 416 0xa, 0x3, 0x4, 0xe, 0x1, 0x7, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 417 0x1, 0x1, 0x1, 0x1, 0x1,}, 418 [10] = {}, 419 [11] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 420 0x1, 0x1, 0x1, 0xe, 0x1, 0x7, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2, 421 0xf, 0x8, 0x1, 0x1, 0x1,}, 422 [12] = {}, 423 [13] = {0x2, 0xc, 0xc, 0xe, 0x6, 0x6, 0x6, 0x6, 0x6, 0x12, 0x6, 0x28, 424 0x2, 0xc, 0xc, 0x28, 0x12, 0x6,}, 425 [14] = {}, 426 [15] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2, 427 0x4, 0x2, 0x8, 0x4, 0x4,}, 428 [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2, 429 0x4, 0x2, 0x8, 0x4, 0x4,}, 430 [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2, 431 0x4, 0x2, 0x8, 0x4, 0x4,}, 432 [18] = {0x2, 0x2, 0x4, 0x2,}, 433 [19] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1,}, 434}; 435 436static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 437 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 438 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 439 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 440 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 441 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 442 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 443 [6] = {0x06, 0x01, 0x06, 0x0a,}, 444 [7] = {0x0c, 0x0c, 0x12,}, 445 [8] = {0x0c, 0x0c, 0x12,}, 446 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 447 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 448 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 449 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 450 0x0d, 0x06, 0x10, 0x10,}, 451 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 452 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 453 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 454 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 455 0x01, 0x02, 0x02, 0x08, 0x02,}, 456 [15] = {}, 457 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 458 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 459 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 460 [18] = {0x12, 0x06, 0x12, 0x06,}, 461 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 462 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 463 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 464 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 465 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 466 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 467 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 468 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 469 [23] = {0x18, 0x01,}, 470 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 471 0x01, 0x01,}, 472 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 473 0x02, 0x01,}, 474 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 475 0x02, 0x01,}, 476 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 477 0x02, 0x01,}, 478 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 479}; 480 481static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 482 .port_in_larb = { 483 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 484 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 485 }, 486 .config_port = mtk_smi_larb_config_port_gen1, 487}; 488 489static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 490 .config_port = mtk_smi_larb_config_port_gen2_general, 491 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 492}; 493 494static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 495 .config_port = mtk_smi_larb_config_port_gen2_general, 496 .larb_direct_to_common_mask = 497 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 498 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 499}; 500 501static const struct mtk_smi_larb_gen mtk_smi_larb_mt6893 = { 502 .config_port = mtk_smi_larb_config_port_gen2_general, 503 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG, 504 .ostd = mtk_smi_larb_mt6893_ostd, 505}; 506 507static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 508 /* mt8167 do not need the port in larb */ 509 .config_port = mtk_smi_larb_config_port_mt8167, 510}; 511 512static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 513 /* mt8173 do not need the port in larb */ 514 .config_port = mtk_smi_larb_config_port_mt8173, 515}; 516 517static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 518 .config_port = mtk_smi_larb_config_port_gen2_general, 519 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 520 /* IPU0 | IPU1 | CCU */ 521}; 522 523static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { 524 .config_port = mtk_smi_larb_config_port_gen2_general, 525 .flags_general = MTK_SMI_FLAG_SLEEP_CTL, 526 .ostd = mtk_smi_larb_mt8186_ostd, 527}; 528 529static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = { 530 .config_port = mtk_smi_larb_config_port_gen2_general, 531 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 532 MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, 533 .ostd = mtk_smi_larb_mt8188_ostd, 534}; 535 536static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 537 .config_port = mtk_smi_larb_config_port_gen2_general, 538 .ostd = mtk_smi_larb_mt8192_ostd, 539}; 540 541static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 542 .config_port = mtk_smi_larb_config_port_gen2_general, 543 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 544 MTK_SMI_FLAG_SLEEP_CTL, 545 .ostd = mtk_smi_larb_mt8195_ostd, 546}; 547 548static const struct of_device_id mtk_smi_larb_of_ids[] = { 549 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 550 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 551 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 552 {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173}, 553 {.compatible = "mediatek,mt6893-smi-larb", .data = &mtk_smi_larb_mt6893}, 554 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 555 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 556 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 557 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, 558 {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188}, 559 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 560 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 561 {} 562}; 563MODULE_DEVICE_TABLE(of, mtk_smi_larb_of_ids); 564 565static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) 566{ 567 int ret; 568 u32 tmp; 569 570 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); 571 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, 572 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); 573 if (ret) { 574 /* TODO: Reset this larb if it fails here. */ 575 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); 576 } 577 return ret; 578} 579 580static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) 581{ 582 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); 583} 584 585static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 586{ 587 struct platform_device *smi_com_pdev; 588 struct device_node *smi_com_node; 589 struct device *smi_com_dev; 590 struct device_link *link; 591 592 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 593 if (!smi_com_node) 594 return -EINVAL; 595 596 smi_com_pdev = of_find_device_by_node(smi_com_node); 597 of_node_put(smi_com_node); 598 if (smi_com_pdev) { 599 /* smi common is the supplier, Make sure it is ready before */ 600 if (!platform_get_drvdata(smi_com_pdev)) { 601 put_device(&smi_com_pdev->dev); 602 return -EPROBE_DEFER; 603 } 604 smi_com_dev = &smi_com_pdev->dev; 605 link = device_link_add(dev, smi_com_dev, 606 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 607 if (!link) { 608 dev_err(dev, "Unable to link smi-common dev\n"); 609 put_device(&smi_com_pdev->dev); 610 return -ENODEV; 611 } 612 *com_dev = smi_com_dev; 613 } else { 614 dev_err(dev, "Failed to get the smi_common device\n"); 615 return -EINVAL; 616 } 617 return 0; 618} 619 620static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 621 const char * const clks[], 622 unsigned int clk_nr_required, 623 unsigned int clk_nr_optional) 624{ 625 int i, ret; 626 627 for (i = 0; i < clk_nr_required; i++) 628 smi->clks[i].id = clks[i]; 629 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 630 if (ret) 631 return ret; 632 633 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 634 smi->clks[i].id = clks[i]; 635 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 636 smi->clks + clk_nr_required); 637 smi->clk_num = clk_nr_required + clk_nr_optional; 638 return ret; 639} 640 641static int mtk_smi_larb_probe(struct platform_device *pdev) 642{ 643 struct mtk_smi_larb *larb; 644 struct device *dev = &pdev->dev; 645 int ret; 646 647 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 648 if (!larb) 649 return -ENOMEM; 650 651 larb->larb_gen = of_device_get_match_data(dev); 652 larb->base = devm_platform_ioremap_resource(pdev, 0); 653 if (IS_ERR(larb->base)) 654 return PTR_ERR(larb->base); 655 656 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 657 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 658 if (ret) 659 return ret; 660 661 larb->smi.dev = dev; 662 663 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 664 if (ret < 0) 665 return ret; 666 667 pm_runtime_enable(dev); 668 platform_set_drvdata(pdev, larb); 669 ret = component_add(dev, &mtk_smi_larb_component_ops); 670 if (ret) 671 goto err_pm_disable; 672 return 0; 673 674err_pm_disable: 675 pm_runtime_disable(dev); 676 device_link_remove(dev, larb->smi_common_dev); 677 put_device(larb->smi_common_dev); 678 return ret; 679} 680 681static void mtk_smi_larb_remove(struct platform_device *pdev) 682{ 683 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 684 685 device_link_remove(&pdev->dev, larb->smi_common_dev); 686 pm_runtime_disable(&pdev->dev); 687 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 688 put_device(larb->smi_common_dev); 689} 690 691static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 692{ 693 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 694 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 695 int ret; 696 697 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 698 if (ret) 699 return ret; 700 701 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) 702 mtk_smi_larb_sleep_ctrl_disable(larb); 703 704 /* Configure the basic setting for this larb */ 705 return larb_gen->config_port(dev); 706} 707 708static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 709{ 710 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 711 int ret; 712 713 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { 714 ret = mtk_smi_larb_sleep_ctrl_enable(larb); 715 if (ret) 716 return ret; 717 } 718 719 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 720 return 0; 721} 722 723static const struct dev_pm_ops smi_larb_pm_ops = { 724 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 725 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 726 pm_runtime_force_resume) 727}; 728 729static struct platform_driver mtk_smi_larb_driver = { 730 .probe = mtk_smi_larb_probe, 731 .remove = mtk_smi_larb_remove, 732 .driver = { 733 .name = "mtk-smi-larb", 734 .of_match_table = mtk_smi_larb_of_ids, 735 .pm = &smi_larb_pm_ops, 736 } 737}; 738 739static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { 740 {SMI_L1_ARB, 0x1b}, 741 {SMI_M4U_TH, 0xce810c85}, 742 {SMI_FIFO_TH1, 0x43214c8}, 743 {SMI_READ_FIFO_TH, 0x191f}, 744}; 745 746static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 747 {SMI_L1LEN, 0xb}, 748 {SMI_M4U_TH, 0xe100e10}, 749 {SMI_FIFO_TH1, 0x506090a}, 750 {SMI_FIFO_TH2, 0x506090a}, 751 {SMI_DCM, 0x4f1}, 752 {SMI_DUMMY, 0x1}, 753}; 754 755static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 756 .type = MTK_SMI_GEN1, 757}; 758 759static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 760 .type = MTK_SMI_GEN2, 761}; 762 763static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 764 .type = MTK_SMI_GEN2, 765 .has_gals = true, 766 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 767 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 768}; 769 770static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = { 771 .type = MTK_SMI_GEN2, 772 .bus_sel = F_MMU1_LARB(0), 773 .init = mtk_smi_common_mt6795_init, 774}; 775 776static const struct mtk_smi_common_plat mtk_smi_common_mt6893 = { 777 .type = MTK_SMI_GEN2, 778 .has_gals = true, 779 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 780 F_MMU1_LARB(5) | F_MMU1_LARB(7), 781}; 782 783static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 784 .type = MTK_SMI_GEN2, 785 .has_gals = true, 786 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 787 F_MMU1_LARB(7), 788}; 789 790static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { 791 .type = MTK_SMI_GEN2, 792 .has_gals = true, 793 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), 794}; 795 796static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = { 797 .type = MTK_SMI_GEN2, 798 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7), 799 .init = mtk_smi_common_mt8195_init, 800}; 801 802static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = { 803 .type = MTK_SMI_GEN2, 804 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 805 .init = mtk_smi_common_mt8195_init, 806}; 807 808static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 809 .type = MTK_SMI_GEN2, 810 .has_gals = true, 811 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 812 F_MMU1_LARB(6), 813}; 814 815static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 816 .type = MTK_SMI_GEN2, 817 .has_gals = true, 818 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 819 F_MMU1_LARB(7), 820 .init = mtk_smi_common_mt8195_init, 821}; 822 823static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 824 .type = MTK_SMI_GEN2, 825 .has_gals = true, 826 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 827 .init = mtk_smi_common_mt8195_init, 828}; 829 830static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 831 .type = MTK_SMI_GEN2_SUB_COMM, 832 .has_gals = true, 833}; 834 835static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = { 836 .type = MTK_SMI_GEN2, 837 .bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4), 838}; 839 840static const struct of_device_id mtk_smi_common_of_ids[] = { 841 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 842 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 843 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 844 {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795}, 845 {.compatible = "mediatek,mt6893-smi-common", .data = &mtk_smi_common_mt6893}, 846 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 847 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 848 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 849 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, 850 {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo}, 851 {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp}, 852 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 853 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 854 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 855 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 856 {.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365}, 857 {} 858}; 859MODULE_DEVICE_TABLE(of, mtk_smi_common_of_ids); 860 861static int mtk_smi_common_probe(struct platform_device *pdev) 862{ 863 struct device *dev = &pdev->dev; 864 struct mtk_smi *common; 865 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 866 867 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 868 if (!common) 869 return -ENOMEM; 870 common->dev = dev; 871 common->plat = of_device_get_match_data(dev); 872 873 if (common->plat->has_gals) { 874 if (common->plat->type == MTK_SMI_GEN2) 875 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 876 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 877 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 878 } 879 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 880 if (ret) 881 return ret; 882 883 /* 884 * for mtk smi gen 1, we need to get the ao(always on) base to config 885 * m4u port, and we need to enable the aync clock for transform the smi 886 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 887 * base. 888 */ 889 if (common->plat->type == MTK_SMI_GEN1) { 890 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 891 if (IS_ERR(common->smi_ao_base)) 892 return PTR_ERR(common->smi_ao_base); 893 894 common->clk_async = devm_clk_get_enabled(dev, "async"); 895 if (IS_ERR(common->clk_async)) 896 return PTR_ERR(common->clk_async); 897 } else { 898 common->base = devm_platform_ioremap_resource(pdev, 0); 899 if (IS_ERR(common->base)) 900 return PTR_ERR(common->base); 901 } 902 903 /* link its smi-common if this is smi-sub-common */ 904 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 905 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 906 if (ret < 0) 907 return ret; 908 } 909 910 pm_runtime_enable(dev); 911 platform_set_drvdata(pdev, common); 912 return 0; 913} 914 915static void mtk_smi_common_remove(struct platform_device *pdev) 916{ 917 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 918 919 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 920 device_link_remove(&pdev->dev, common->smi_common_dev); 921 pm_runtime_disable(&pdev->dev); 922 put_device(common->smi_common_dev); 923} 924 925static int __maybe_unused mtk_smi_common_resume(struct device *dev) 926{ 927 struct mtk_smi *common = dev_get_drvdata(dev); 928 const struct mtk_smi_reg_pair *init = common->plat->init; 929 u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 930 int ret, i; 931 932 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 933 if (ret) 934 return ret; 935 936 if (common->plat->type != MTK_SMI_GEN2) 937 return 0; 938 939 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 940 writel_relaxed(init[i].value, common->base + init[i].offset); 941 942 writel(bus_sel, common->base + SMI_BUS_SEL); 943 return 0; 944} 945 946static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 947{ 948 struct mtk_smi *common = dev_get_drvdata(dev); 949 950 clk_bulk_disable_unprepare(common->clk_num, common->clks); 951 return 0; 952} 953 954static const struct dev_pm_ops smi_common_pm_ops = { 955 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 956 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 957 pm_runtime_force_resume) 958}; 959 960static struct platform_driver mtk_smi_common_driver = { 961 .probe = mtk_smi_common_probe, 962 .remove = mtk_smi_common_remove, 963 .driver = { 964 .name = "mtk-smi-common", 965 .of_match_table = mtk_smi_common_of_ids, 966 .pm = &smi_common_pm_ops, 967 } 968}; 969 970static struct platform_driver * const smidrivers[] = { 971 &mtk_smi_common_driver, 972 &mtk_smi_larb_driver, 973}; 974 975static int __init mtk_smi_init(void) 976{ 977 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 978} 979module_init(mtk_smi_init); 980 981static void __exit mtk_smi_exit(void) 982{ 983 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 984} 985module_exit(mtk_smi_exit); 986 987MODULE_DESCRIPTION("MediaTek SMI driver"); 988MODULE_LICENSE("GPL v2");
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