mxl111sf-reg.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 *  mxl111sf-reg.h - driver for the MaxLinear MXL111SF
  4 *
  5 *  Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
  6 */
  7
  8#ifndef _DVB_USB_MXL111SF_REG_H_
  9#define _DVB_USB_MXL111SF_REG_H_
 10
 11#define CHIP_ID_REG                  0xFC
 12#define TOP_CHIP_REV_ID_REG          0xFA
 13
 14#define V6_SNR_RB_LSB_REG            0x27
 15#define V6_SNR_RB_MSB_REG            0x28
 16
 17#define V6_N_ACCUMULATE_REG          0x11
 18#define V6_RS_AVG_ERRORS_LSB_REG     0x2C
 19#define V6_RS_AVG_ERRORS_MSB_REG     0x2D
 20
 21#define V6_IRQ_STATUS_REG            0x24
 22#define  IRQ_MASK_FEC_LOCK       0x10
 23
 24#define V6_SYNC_LOCK_REG             0x28
 25#define SYNC_LOCK_MASK           0x10
 26
 27#define V6_RS_LOCK_DET_REG           0x28
 28#define  RS_LOCK_DET_MASK        0x08
 29
 30#define V6_INITACQ_NODETECT_REG    0x20
 31#define V6_FORCE_NFFT_CPSIZE_REG   0x20
 32
 33#define V6_CODE_RATE_TPS_REG       0x29
 34#define V6_CODE_RATE_TPS_MASK      0x07
 35
 36
 37#define V6_CP_LOCK_DET_REG        0x28
 38#define V6_CP_LOCK_DET_MASK       0x04
 39
 40#define V6_TPS_HIERACHY_REG        0x29
 41#define V6_TPS_HIERARCHY_INFO_MASK  0x40
 42
 43#define V6_MODORDER_TPS_REG        0x2A
 44#define V6_PARAM_CONSTELLATION_MASK   0x30
 45
 46#define V6_MODE_TPS_REG            0x2A
 47#define V6_PARAM_FFT_MODE_MASK        0x0C
 48
 49
 50#define V6_CP_TPS_REG             0x29
 51#define V6_PARAM_GI_MASK              0x30
 52
 53#define V6_TPS_LOCK_REG           0x2A
 54#define V6_PARAM_TPS_LOCK_MASK        0x40
 55
 56#define V6_FEC_PER_COUNT_REG      0x2E
 57#define V6_FEC_PER_SCALE_REG      0x2B
 58#define V6_FEC_PER_SCALE_MASK        0x03
 59#define V6_FEC_PER_CLR_REG        0x20
 60#define V6_FEC_PER_CLR_MASK          0x01
 61
 62#define V6_PIN_MUX_MODE_REG       0x1B
 63#define V6_ENABLE_PIN_MUX            0x1E
 64
 65#define V6_I2S_NUM_SAMPLES_REG    0x16
 66
 67#define V6_MPEG_IN_CLK_INV_REG    0x17
 68#define V6_MPEG_IN_CTRL_REG       0x18
 69
 70#define V6_INVERTED_CLK_PHASE       0x20
 71#define V6_MPEG_IN_DATA_PARALLEL    0x01
 72#define V6_MPEG_IN_DATA_SERIAL      0x02
 73
 74#define V6_INVERTED_MPEG_SYNC       0x04
 75#define V6_INVERTED_MPEG_VALID      0x08
 76
 77#define TSIF_INPUT_PARALLEL         0
 78#define TSIF_INPUT_SERIAL           1
 79#define TSIF_NORMAL                 0
 80
 81#define V6_MPEG_INOUT_BIT_ORDER_CTRL_REG  0x19
 82#define V6_MPEG_SER_MSB_FIRST                0x80
 83#define MPEG_SER_MSB_FIRST_ENABLED        0x01
 84
 85#define V6_656_I2S_BUFF_STATUS_REG   0x2F
 86#define V6_656_OVERFLOW_MASK_BIT         0x08
 87#define V6_I2S_OVERFLOW_MASK_BIT         0x01
 88
 89#define V6_I2S_STREAM_START_BIT_REG  0x14
 90#define V6_I2S_STREAM_END_BIT_REG    0x15
 91#define I2S_RIGHT_JUSTIFIED     0
 92#define I2S_LEFT_JUSTIFIED      1
 93#define I2S_DATA_FORMAT         2
 94
 95#define V6_TUNER_LOOP_THRU_CONTROL_REG  0x09
 96#define V6_ENABLE_LOOP_THRU               0x01
 97
 98#define TOTAL_NUM_IF_OUTPUT_FREQ       16
 99
100#define TUNER_NORMAL_IF_SPECTRUM       0x0
101#define TUNER_INVERT_IF_SPECTRUM       0x10
102
103#define V6_TUNER_IF_SEL_REG              0x06
104#define V6_TUNER_IF_FCW_REG              0x3C
105#define V6_TUNER_IF_FCW_BYP_REG          0x3D
106#define V6_RF_LOCK_STATUS_REG            0x23
107
108#define NUM_DIG_TV_CHANNEL     1000
109
110#define V6_DIG_CLK_FREQ_SEL_REG  0x07
111#define V6_REF_SYNTH_INT_REG     0x5C
112#define V6_REF_SYNTH_REMAIN_REG  0x58
113#define V6_DIG_RFREFSELECT_REG   0x32
114#define V6_XTAL_CLK_OUT_GAIN_REG   0x31
115#define V6_TUNER_LOOP_THRU_CTRL_REG      0x09
116#define V6_DIG_XTAL_ENABLE_REG  0x06
117#define V6_DIG_XTAL_BIAS_REG  0x66
118#define V6_XTAL_CAP_REG    0x08
119
120#define V6_GPO_CTRL_REG     0x18
121#define MXL_GPO_0           0x00
122#define MXL_GPO_1           0x01
123#define V6_GPO_0_MASK       0x10
124#define V6_GPO_1_MASK       0x20
125
126#define V6_111SF_GPO_CTRL_REG     0x19
127#define MXL_111SF_GPO_1               0x00
128#define MXL_111SF_GPO_2               0x01
129#define MXL_111SF_GPO_3               0x02
130#define MXL_111SF_GPO_4               0x03
131#define MXL_111SF_GPO_5               0x04
132#define MXL_111SF_GPO_6               0x05
133#define MXL_111SF_GPO_7               0x06
134
135#define MXL_111SF_GPO_0_MASK          0x01
136#define MXL_111SF_GPO_1_MASK          0x02
137#define MXL_111SF_GPO_2_MASK          0x04
138#define MXL_111SF_GPO_3_MASK          0x08
139#define MXL_111SF_GPO_4_MASK          0x10
140#define MXL_111SF_GPO_5_MASK          0x20
141#define MXL_111SF_GPO_6_MASK          0x40
142
143#define V6_ATSC_CONFIG_REG  0x0A
144
145#define MXL_MODE_REG    0x03
146#define START_TUNE_REG  0x1C
147
148#define V6_IDAC_HYSTERESIS_REG    0x0B
149#define V6_IDAC_SETTINGS_REG      0x0C
150#define IDAC_MANUAL_CONTROL             1
151#define IDAC_CURRENT_SINKING_ENABLE     1
152#define IDAC_MANUAL_CONTROL_BIT_MASK      0x80
153#define IDAC_CURRENT_SINKING_BIT_MASK     0x40
154
155#define V8_SPI_MODE_REG  0xE9
156
157#define V6_DIG_RF_PWR_LSB_REG  0x46
158#define V6_DIG_RF_PWR_MSB_REG  0x47
159
160#endif /* _DVB_USB_MXL111SF_REG_H_ */