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cx231xx-avcore.c
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linux-6.19.14/drivers/media/usb/cx231xx/cx231xx-avcore.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 4 USB video capture devices 5 6 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 7 8 This program contains the specific code to control the avdecoder chip and 9 other related usb control functions for cx231xx based chipset. 10 11 */ 12 13#include "cx231xx.h" 14#include <linux/init.h> 15#include <linux/list.h> 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/bitmap.h> 19#include <linux/i2c.h> 20#include <linux/mm.h> 21#include <linux/mutex.h> 22#include <media/tuner.h> 23 24#include <media/v4l2-common.h> 25#include <media/v4l2-ioctl.h> 26 27#include "cx231xx-dif.h" 28 29#define TUNER_MODE_FM_RADIO 0 30/****************************************************************************** 31 -: BLOCK ARRANGEMENT :- 32 I2S block ----------------------| 33 [I2S audio] | 34 | 35 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 36 [video & audio] | [Audio] 37 | 38 |-> Cx25840 --> Video 39 [Video] 40 41*******************************************************************************/ 42/****************************************************************************** 43 * VERVE REGISTER * 44 * * 45 ******************************************************************************/ 46static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 47{ 48 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 49 saddr, 1, data, 1); 50} 51 52static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 53{ 54 int status; 55 u32 temp = 0; 56 57 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 58 saddr, 1, &temp, 1); 59 *data = (u8) temp; 60 return status; 61} 62void initGPIO(struct cx231xx *dev) 63{ 64 u32 _gpio_direction = 0; 65 u32 value = 0; 66 u8 val = 0; 67 68 _gpio_direction = _gpio_direction & 0xFC0003FF; 69 _gpio_direction = _gpio_direction | 0x03FDFC00; 70 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 71 72 verve_read_byte(dev, 0x07, &val); 73 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 74 verve_write_byte(dev, 0x07, 0xF4); 75 verve_read_byte(dev, 0x07, &val); 76 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 77 78 cx231xx_capture_start(dev, 1, Vbi); 79 80 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 81 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 82 83} 84void uninitGPIO(struct cx231xx *dev) 85{ 86 u8 value[4] = { 0, 0, 0, 0 }; 87 88 cx231xx_capture_start(dev, 0, Vbi); 89 verve_write_byte(dev, 0x07, 0x14); 90 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 91 0x68, value, 4); 92} 93 94/****************************************************************************** 95 * A F E - B L O C K C O N T R O L functions * 96 * [ANALOG FRONT END] * 97 ******************************************************************************/ 98static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 99{ 100 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 101 saddr, 2, data, 1); 102} 103 104static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 105{ 106 int status; 107 u32 temp = 0; 108 109 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 110 saddr, 2, &temp, 1); 111 *data = (u8) temp; 112 return status; 113} 114 115int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 116{ 117 int status = 0; 118 u8 temp = 0; 119 u8 afe_power_status = 0; 120 int i = 0; 121 122 /* super block initialize */ 123 temp = (u8) (ref_count & 0xff); 124 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 125 if (status < 0) 126 return status; 127 128 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 129 if (status < 0) 130 return status; 131 132 temp = (u8) ((ref_count & 0x300) >> 8); 133 temp |= 0x40; 134 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 135 if (status < 0) 136 return status; 137 138 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 139 if (status < 0) 140 return status; 141 142 /* enable pll */ 143 while (afe_power_status != 0x18) { 144 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 145 if (status < 0) { 146 dev_dbg(dev->dev, 147 "%s: Init Super Block failed in send cmd\n", 148 __func__); 149 break; 150 } 151 152 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 153 afe_power_status &= 0xff; 154 if (status < 0) { 155 dev_dbg(dev->dev, 156 "%s: Init Super Block failed in receive cmd\n", 157 __func__); 158 break; 159 } 160 i++; 161 if (i == 10) { 162 dev_dbg(dev->dev, 163 "%s: Init Super Block force break in loop !!!!\n", 164 __func__); 165 status = -1; 166 break; 167 } 168 } 169 170 if (status < 0) 171 return status; 172 173 /* start tuning filter */ 174 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 175 if (status < 0) 176 return status; 177 178 msleep(5); 179 180 /* exit tuning */ 181 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 182 183 return status; 184} 185 186int cx231xx_afe_init_channels(struct cx231xx *dev) 187{ 188 int status = 0; 189 190 /* power up all 3 channels, clear pd_buffer */ 191 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 192 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 193 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 194 195 /* Enable quantizer calibration */ 196 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 197 198 /* channel initialize, force modulator (fb) reset */ 199 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 200 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 201 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 202 203 /* start quantilizer calibration */ 204 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 205 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 206 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 207 msleep(5); 208 209 /* exit modulator (fb) reset */ 210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 213 214 /* enable the pre_clamp in each channel for single-ended input */ 215 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 216 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 217 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 218 219 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 220 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 221 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 222 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 223 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 224 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 225 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 226 227 /* dynamic element matching off */ 228 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 229 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 230 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 231 232 return status; 233} 234 235int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 236{ 237 u8 c_value = 0; 238 int status = 0; 239 240 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 241 c_value &= (~(0x50)); 242 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 243 244 return status; 245} 246 247/* 248 The Analog Front End in Cx231xx has 3 channels. These 249 channels are used to share between different inputs 250 like tuner, s-video and composite inputs. 251 252 channel 1 ----- pin 1 to pin4(in reg is 1-4) 253 channel 2 ----- pin 5 to pin8(in reg is 5-8) 254 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 255*/ 256int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 257{ 258 u8 ch1_setting = (u8) input_mux; 259 u8 ch2_setting = (u8) (input_mux >> 8); 260 u8 ch3_setting = (u8) (input_mux >> 16); 261 int status = 0; 262 u8 value = 0; 263 264 if (ch1_setting != 0) { 265 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 266 value &= ~INPUT_SEL_MASK; 267 value |= (ch1_setting - 1) << 4; 268 value &= 0xff; 269 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 270 } 271 272 if (ch2_setting != 0) { 273 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 274 value &= ~INPUT_SEL_MASK; 275 value |= (ch2_setting - 1) << 4; 276 value &= 0xff; 277 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 278 } 279 280 /* For ch3_setting, the value to put in the register is 281 7 less than the input number */ 282 if (ch3_setting != 0) { 283 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 284 value &= ~INPUT_SEL_MASK; 285 value |= (ch3_setting - 1) << 4; 286 value &= 0xff; 287 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 288 } 289 290 return status; 291} 292 293int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 294{ 295 int status = 0; 296 297 /* 298 * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 299 * Currently, only baseband works. 300 */ 301 302 switch (mode) { 303 case AFE_MODE_LOW_IF: 304 cx231xx_Setup_AFE_for_LowIF(dev); 305 break; 306 case AFE_MODE_BASEBAND: 307 status = cx231xx_afe_setup_AFE_for_baseband(dev); 308 break; 309 case AFE_MODE_EU_HI_IF: 310 /* SetupAFEforEuHiIF(); */ 311 break; 312 case AFE_MODE_US_HI_IF: 313 /* SetupAFEforUsHiIF(); */ 314 break; 315 case AFE_MODE_JAPAN_HI_IF: 316 /* SetupAFEforJapanHiIF(); */ 317 break; 318 } 319 320 if ((mode != dev->afe_mode) && 321 (dev->video_input == CX231XX_VMUX_TELEVISION)) 322 status = cx231xx_afe_adjust_ref_count(dev, 323 CX231XX_VMUX_TELEVISION); 324 325 dev->afe_mode = mode; 326 327 return status; 328} 329 330int cx231xx_afe_update_power_control(struct cx231xx *dev, 331 enum AV_MODE avmode) 332{ 333 u8 afe_power_status = 0; 334 int status = 0; 335 336 switch (dev->model) { 337 case CX231XX_BOARD_CNXT_CARRAERA: 338 case CX231XX_BOARD_CNXT_RDE_250: 339 case CX231XX_BOARD_CNXT_SHELBY: 340 case CX231XX_BOARD_CNXT_RDU_250: 341 case CX231XX_BOARD_CNXT_RDE_253S: 342 case CX231XX_BOARD_CNXT_RDU_253S: 343 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 344 case CX231XX_BOARD_HAUPPAUGE_EXETER: 345 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx: 346 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 347 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 348 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 349 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 350 case CX231XX_BOARD_OTG102: 351 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 352 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 353 FLD_PWRDN_ENABLE_PLL)) { 354 status = afe_write_byte(dev, SUP_BLK_PWRDN, 355 FLD_PWRDN_TUNING_BIAS | 356 FLD_PWRDN_ENABLE_PLL); 357 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 358 &afe_power_status); 359 if (status < 0) 360 break; 361 } 362 363 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 364 0x00); 365 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 366 0x00); 367 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 368 0x00); 369 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 370 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 371 0x70); 372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 373 0x70); 374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 375 0x70); 376 377 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 378 &afe_power_status); 379 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 380 FLD_PWRDN_PD_BIAS | 381 FLD_PWRDN_PD_TUNECK; 382 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 383 afe_power_status); 384 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 385 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 386 FLD_PWRDN_ENABLE_PLL)) { 387 status = afe_write_byte(dev, SUP_BLK_PWRDN, 388 FLD_PWRDN_TUNING_BIAS | 389 FLD_PWRDN_ENABLE_PLL); 390 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 391 &afe_power_status); 392 if (status < 0) 393 break; 394 } 395 396 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 397 0x00); 398 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 399 0x00); 400 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 401 0x00); 402 } else { 403 dev_dbg(dev->dev, "Invalid AV mode input\n"); 404 status = -1; 405 } 406 break; 407 default: 408 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 409 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 410 FLD_PWRDN_ENABLE_PLL)) { 411 status = afe_write_byte(dev, SUP_BLK_PWRDN, 412 FLD_PWRDN_TUNING_BIAS | 413 FLD_PWRDN_ENABLE_PLL); 414 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 415 &afe_power_status); 416 if (status < 0) 417 break; 418 } 419 420 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 421 0x40); 422 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 423 0x40); 424 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 425 0x00); 426 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 427 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 428 0x70); 429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 430 0x70); 431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 432 0x70); 433 434 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 435 &afe_power_status); 436 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 437 FLD_PWRDN_PD_BIAS | 438 FLD_PWRDN_PD_TUNECK; 439 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 440 afe_power_status); 441 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 442 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 443 FLD_PWRDN_ENABLE_PLL)) { 444 status = afe_write_byte(dev, SUP_BLK_PWRDN, 445 FLD_PWRDN_TUNING_BIAS | 446 FLD_PWRDN_ENABLE_PLL); 447 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 448 &afe_power_status); 449 if (status < 0) 450 break; 451 } 452 453 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 454 0x00); 455 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 456 0x00); 457 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 458 0x40); 459 } else { 460 dev_dbg(dev->dev, "Invalid AV mode input\n"); 461 status = -1; 462 } 463 } /* switch */ 464 465 return status; 466} 467 468int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 469{ 470 u8 input_mode = 0; 471 u8 ntf_mode = 0; 472 int status = 0; 473 474 dev->video_input = video_input; 475 476 if (video_input == CX231XX_VMUX_TELEVISION) { 477 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 478 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 479 &ntf_mode); 480 } else { 481 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 482 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 483 &ntf_mode); 484 } 485 486 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 487 488 switch (input_mode) { 489 case SINGLE_ENDED: 490 dev->afe_ref_count = 0x23C; 491 break; 492 case LOW_IF: 493 dev->afe_ref_count = 0x24C; 494 break; 495 case EU_IF: 496 dev->afe_ref_count = 0x258; 497 break; 498 case US_IF: 499 dev->afe_ref_count = 0x260; 500 break; 501 default: 502 break; 503 } 504 505 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 506 507 return status; 508} 509 510/****************************************************************************** 511 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 512 ******************************************************************************/ 513static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 514{ 515 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 516 saddr, 2, data, 1); 517} 518 519static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 520{ 521 int status; 522 u32 temp = 0; 523 524 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 525 saddr, 2, &temp, 1); 526 *data = (u8) temp; 527 return status; 528} 529 530static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 531{ 532 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 533 saddr, 2, data, 4); 534} 535 536static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 537{ 538 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 539 saddr, 2, data, 4); 540} 541int cx231xx_check_fw(struct cx231xx *dev) 542{ 543 u8 temp = 0; 544 int status = 0; 545 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 546 if (status < 0) 547 return status; 548 else 549 return temp; 550 551} 552 553int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 554{ 555 int status = 0; 556 557 switch (INPUT(input)->type) { 558 case CX231XX_VMUX_COMPOSITE1: 559 case CX231XX_VMUX_SVIDEO: 560 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 561 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 562 /* External AV */ 563 status = cx231xx_set_power_mode(dev, 564 POLARIS_AVMODE_ENXTERNAL_AV); 565 if (status < 0) { 566 dev_err(dev->dev, 567 "%s: Failed to set Power - errCode [%d]!\n", 568 __func__, status); 569 return status; 570 } 571 } 572 status = cx231xx_set_decoder_video_input(dev, 573 INPUT(input)->type, 574 INPUT(input)->vmux); 575 break; 576 case CX231XX_VMUX_TELEVISION: 577 case CX231XX_VMUX_CABLE: 578 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 579 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 580 /* Tuner */ 581 status = cx231xx_set_power_mode(dev, 582 POLARIS_AVMODE_ANALOGT_TV); 583 if (status < 0) { 584 dev_err(dev->dev, 585 "%s: Failed to set Power - errCode [%d]!\n", 586 __func__, status); 587 return status; 588 } 589 } 590 switch (dev->model) { /* i2c device tuners */ 591 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx: 592 case CX231XX_BOARD_HAUPPAUGE_935C: 593 case CX231XX_BOARD_HAUPPAUGE_955Q: 594 case CX231XX_BOARD_HAUPPAUGE_975: 595 case CX231XX_BOARD_EVROMEDIA_FULL_HYBRID_FULLHD: 596 status = cx231xx_set_decoder_video_input(dev, 597 CX231XX_VMUX_TELEVISION, 598 INPUT(input)->vmux); 599 break; 600 default: 601 if (dev->tuner_type == TUNER_NXP_TDA18271) 602 status = cx231xx_set_decoder_video_input(dev, 603 CX231XX_VMUX_TELEVISION, 604 INPUT(input)->vmux); 605 else 606 status = cx231xx_set_decoder_video_input(dev, 607 CX231XX_VMUX_COMPOSITE1, 608 INPUT(input)->vmux); 609 break; 610 } 611 612 break; 613 default: 614 dev_err(dev->dev, "%s: Unknown Input %d !\n", 615 __func__, INPUT(input)->type); 616 break; 617 } 618 619 /* save the selection */ 620 dev->video_input = input; 621 622 return status; 623} 624 625int cx231xx_set_decoder_video_input(struct cx231xx *dev, 626 u8 pin_type, u32 input) 627{ 628 int status = 0; 629 u32 value = 0; 630 631 if (pin_type != dev->video_input) { 632 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 633 if (status < 0) { 634 dev_err(dev->dev, 635 "%s: adjust_ref_count :Failed to set AFE input mux - errCode [%d]!\n", 636 __func__, status); 637 return status; 638 } 639 } 640 641 /* call afe block to set video inputs */ 642 status = cx231xx_afe_set_input_mux(dev, input); 643 if (status < 0) { 644 dev_err(dev->dev, 645 "%s: set_input_mux :Failed to set AFE input mux - errCode [%d]!\n", 646 __func__, status); 647 return status; 648 } 649 650 switch (pin_type) { 651 case CX231XX_VMUX_COMPOSITE1: 652 status = vid_blk_read_word(dev, AFE_CTRL, &value); 653 value |= (0 << 13) | (1 << 4); 654 value &= ~(1 << 5); 655 656 /* set [24:23] [22:15] to 0 */ 657 value &= (~(0x1ff8000)); 658 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 659 value |= 0x1000000; 660 status = vid_blk_write_word(dev, AFE_CTRL, value); 661 662 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 663 value |= (1 << 7); 664 status = vid_blk_write_word(dev, OUT_CTRL1, value); 665 666 /* Set output mode */ 667 status = cx231xx_read_modify_write_i2c_dword(dev, 668 VID_BLK_I2C_ADDRESS, 669 OUT_CTRL1, 670 FLD_OUT_MODE, 671 dev->board.output_mode); 672 673 /* Tell DIF object to go to baseband mode */ 674 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 675 if (status < 0) { 676 dev_err(dev->dev, 677 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 678 __func__, status); 679 return status; 680 } 681 682 /* Read the DFE_CTRL1 register */ 683 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 684 685 /* enable the VBI_GATE_EN */ 686 value |= FLD_VBI_GATE_EN; 687 688 /* Enable the auto-VGA enable */ 689 value |= FLD_VGA_AUTO_EN; 690 691 /* Write it back */ 692 status = vid_blk_write_word(dev, DFE_CTRL1, value); 693 694 /* Disable auto config of registers */ 695 status = cx231xx_read_modify_write_i2c_dword(dev, 696 VID_BLK_I2C_ADDRESS, 697 MODE_CTRL, FLD_ACFG_DIS, 698 cx231xx_set_field(FLD_ACFG_DIS, 1)); 699 700 /* Set CVBS input mode */ 701 status = cx231xx_read_modify_write_i2c_dword(dev, 702 VID_BLK_I2C_ADDRESS, 703 MODE_CTRL, FLD_INPUT_MODE, 704 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 705 break; 706 case CX231XX_VMUX_SVIDEO: 707 /* Disable the use of DIF */ 708 709 status = vid_blk_read_word(dev, AFE_CTRL, &value); 710 711 /* set [24:23] [22:15] to 0 */ 712 value &= (~(0x1ff8000)); 713 /* set FUNC_MODE[24:23] = 2 714 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 715 value |= 0x1000010; 716 status = vid_blk_write_word(dev, AFE_CTRL, value); 717 718 /* Tell DIF object to go to baseband mode */ 719 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 720 if (status < 0) { 721 dev_err(dev->dev, 722 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 723 __func__, status); 724 return status; 725 } 726 727 /* Read the DFE_CTRL1 register */ 728 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 729 730 /* enable the VBI_GATE_EN */ 731 value |= FLD_VBI_GATE_EN; 732 733 /* Enable the auto-VGA enable */ 734 value |= FLD_VGA_AUTO_EN; 735 736 /* Write it back */ 737 status = vid_blk_write_word(dev, DFE_CTRL1, value); 738 739 /* Disable auto config of registers */ 740 status = cx231xx_read_modify_write_i2c_dword(dev, 741 VID_BLK_I2C_ADDRESS, 742 MODE_CTRL, FLD_ACFG_DIS, 743 cx231xx_set_field(FLD_ACFG_DIS, 1)); 744 745 /* Set YC input mode */ 746 status = cx231xx_read_modify_write_i2c_dword(dev, 747 VID_BLK_I2C_ADDRESS, 748 MODE_CTRL, 749 FLD_INPUT_MODE, 750 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 751 752 /* Chroma to ADC2 */ 753 status = vid_blk_read_word(dev, AFE_CTRL, &value); 754 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 755 756 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 757 This sets them to use video 758 rather than audio. Only one of the two will be in use. */ 759 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 760 761 status = vid_blk_write_word(dev, AFE_CTRL, value); 762 763 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 764 break; 765 case CX231XX_VMUX_TELEVISION: 766 case CX231XX_VMUX_CABLE: 767 default: 768 /* TODO: Test if this is also needed for xc2028/xc3028 */ 769 if (dev->board.tuner_type == TUNER_XC5000) { 770 /* Disable the use of DIF */ 771 772 status = vid_blk_read_word(dev, AFE_CTRL, &value); 773 value |= (0 << 13) | (1 << 4); 774 value &= ~(1 << 5); 775 776 /* set [24:23] [22:15] to 0 */ 777 value &= (~(0x1FF8000)); 778 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 779 value |= 0x1000000; 780 status = vid_blk_write_word(dev, AFE_CTRL, value); 781 782 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 783 value |= (1 << 7); 784 status = vid_blk_write_word(dev, OUT_CTRL1, value); 785 786 /* Set output mode */ 787 status = cx231xx_read_modify_write_i2c_dword(dev, 788 VID_BLK_I2C_ADDRESS, 789 OUT_CTRL1, FLD_OUT_MODE, 790 dev->board.output_mode); 791 792 /* Tell DIF object to go to baseband mode */ 793 status = cx231xx_dif_set_standard(dev, 794 DIF_USE_BASEBAND); 795 if (status < 0) { 796 dev_err(dev->dev, 797 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 798 __func__, status); 799 return status; 800 } 801 802 /* Read the DFE_CTRL1 register */ 803 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 804 805 /* enable the VBI_GATE_EN */ 806 value |= FLD_VBI_GATE_EN; 807 808 /* Enable the auto-VGA enable */ 809 value |= FLD_VGA_AUTO_EN; 810 811 /* Write it back */ 812 status = vid_blk_write_word(dev, DFE_CTRL1, value); 813 814 /* Disable auto config of registers */ 815 status = cx231xx_read_modify_write_i2c_dword(dev, 816 VID_BLK_I2C_ADDRESS, 817 MODE_CTRL, FLD_ACFG_DIS, 818 cx231xx_set_field(FLD_ACFG_DIS, 1)); 819 820 /* Set CVBS input mode */ 821 status = cx231xx_read_modify_write_i2c_dword(dev, 822 VID_BLK_I2C_ADDRESS, 823 MODE_CTRL, FLD_INPUT_MODE, 824 cx231xx_set_field(FLD_INPUT_MODE, 825 INPUT_MODE_CVBS_0)); 826 } else { 827 /* Enable the DIF for the tuner */ 828 829 /* Reinitialize the DIF */ 830 status = cx231xx_dif_set_standard(dev, dev->norm); 831 if (status < 0) { 832 dev_err(dev->dev, 833 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 834 __func__, status); 835 return status; 836 } 837 838 /* Make sure bypass is cleared */ 839 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 840 841 /* Clear the bypass bit */ 842 value &= ~FLD_DIF_DIF_BYPASS; 843 844 /* Enable the use of the DIF block */ 845 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 846 847 /* Read the DFE_CTRL1 register */ 848 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 849 850 /* Disable the VBI_GATE_EN */ 851 value &= ~FLD_VBI_GATE_EN; 852 853 /* Enable the auto-VGA enable, AGC, and 854 set the skip count to 2 */ 855 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 856 857 /* Write it back */ 858 status = vid_blk_write_word(dev, DFE_CTRL1, value); 859 860 /* Wait until AGC locks up */ 861 msleep(1); 862 863 /* Disable the auto-VGA enable AGC */ 864 value &= ~(FLD_VGA_AUTO_EN); 865 866 /* Write it back */ 867 status = vid_blk_write_word(dev, DFE_CTRL1, value); 868 869 /* Enable Polaris B0 AGC output */ 870 status = vid_blk_read_word(dev, PIN_CTRL, &value); 871 value |= (FLD_OEF_AGC_RF) | 872 (FLD_OEF_AGC_IFVGA) | 873 (FLD_OEF_AGC_IF); 874 status = vid_blk_write_word(dev, PIN_CTRL, value); 875 876 /* Set output mode */ 877 status = cx231xx_read_modify_write_i2c_dword(dev, 878 VID_BLK_I2C_ADDRESS, 879 OUT_CTRL1, FLD_OUT_MODE, 880 dev->board.output_mode); 881 882 /* Disable auto config of registers */ 883 status = cx231xx_read_modify_write_i2c_dword(dev, 884 VID_BLK_I2C_ADDRESS, 885 MODE_CTRL, FLD_ACFG_DIS, 886 cx231xx_set_field(FLD_ACFG_DIS, 1)); 887 888 /* Set CVBS input mode */ 889 status = cx231xx_read_modify_write_i2c_dword(dev, 890 VID_BLK_I2C_ADDRESS, 891 MODE_CTRL, FLD_INPUT_MODE, 892 cx231xx_set_field(FLD_INPUT_MODE, 893 INPUT_MODE_CVBS_0)); 894 895 /* Set some bits in AFE_CTRL so that channel 2 or 3 896 * is ready to receive audio */ 897 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 898 /* Clear droop comp (bit 19-20) */ 899 /* Set VGA_SEL (for audio control) (bit 7-8) */ 900 status = vid_blk_read_word(dev, AFE_CTRL, &value); 901 902 /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 903 value &= (~(FLD_FUNC_MODE)); 904 value |= 0x800000; 905 906 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 907 908 status = vid_blk_write_word(dev, AFE_CTRL, value); 909 910 if (dev->tuner_type == TUNER_NXP_TDA18271) { 911 status = vid_blk_read_word(dev, PIN_CTRL, 912 &value); 913 status = vid_blk_write_word(dev, PIN_CTRL, 914 (value & 0xFFFFFFEF)); 915 } 916 917 break; 918 919 } 920 break; 921 } 922 923 /* Set raw VBI mode */ 924 status = cx231xx_read_modify_write_i2c_dword(dev, 925 VID_BLK_I2C_ADDRESS, 926 OUT_CTRL1, FLD_VBIHACTRAW_EN, 927 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 928 929 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 930 if (value & 0x02) { 931 value |= (1 << 19); 932 status = vid_blk_write_word(dev, OUT_CTRL1, value); 933 } 934 935 return status; 936} 937 938void cx231xx_enable656(struct cx231xx *dev) 939{ 940 u8 temp = 0; 941 /*enable TS1 data[0:7] as output to export 656*/ 942 943 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 944 945 /*enable TS1 clock as output to export 656*/ 946 947 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 948 temp = temp|0x04; 949 950 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 951} 952EXPORT_SYMBOL_GPL(cx231xx_enable656); 953 954void cx231xx_disable656(struct cx231xx *dev) 955{ 956 u8 temp = 0; 957 958 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 959 960 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 961 temp = temp&0xFB; 962 963 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 964} 965EXPORT_SYMBOL_GPL(cx231xx_disable656); 966 967/* 968 * Handle any video-mode specific overrides that are different 969 * on a per video standards basis after touching the MODE_CTRL 970 * register which resets many values for autodetect 971 */ 972int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 973{ 974 int status = 0; 975 976 dev_dbg(dev->dev, "%s: 0x%x\n", 977 __func__, (unsigned int)dev->norm); 978 979 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 980 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 981 982 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 983 dev_dbg(dev->dev, "%s: NTSC\n", __func__); 984 985 /* Move the close caption lines out of active video, 986 adjust the active video start point */ 987 status = cx231xx_read_modify_write_i2c_dword(dev, 988 VID_BLK_I2C_ADDRESS, 989 VERT_TIM_CTRL, 990 FLD_VBLANK_CNT, 0x18); 991 status = cx231xx_read_modify_write_i2c_dword(dev, 992 VID_BLK_I2C_ADDRESS, 993 VERT_TIM_CTRL, 994 FLD_VACTIVE_CNT, 995 0x1E7000); 996 status = cx231xx_read_modify_write_i2c_dword(dev, 997 VID_BLK_I2C_ADDRESS, 998 VERT_TIM_CTRL, 999 FLD_V656BLANK_CNT, 1000 0x1C000000); 1001 1002 status = cx231xx_read_modify_write_i2c_dword(dev, 1003 VID_BLK_I2C_ADDRESS, 1004 HORIZ_TIM_CTRL, 1005 FLD_HBLANK_CNT, 1006 cx231xx_set_field 1007 (FLD_HBLANK_CNT, 0x79)); 1008 1009 } else if (dev->norm & V4L2_STD_SECAM) { 1010 dev_dbg(dev->dev, "%s: SECAM\n", __func__); 1011 status = cx231xx_read_modify_write_i2c_dword(dev, 1012 VID_BLK_I2C_ADDRESS, 1013 VERT_TIM_CTRL, 1014 FLD_VBLANK_CNT, 0x20); 1015 status = cx231xx_read_modify_write_i2c_dword(dev, 1016 VID_BLK_I2C_ADDRESS, 1017 VERT_TIM_CTRL, 1018 FLD_VACTIVE_CNT, 1019 cx231xx_set_field 1020 (FLD_VACTIVE_CNT, 1021 0x244)); 1022 status = cx231xx_read_modify_write_i2c_dword(dev, 1023 VID_BLK_I2C_ADDRESS, 1024 VERT_TIM_CTRL, 1025 FLD_V656BLANK_CNT, 1026 cx231xx_set_field 1027 (FLD_V656BLANK_CNT, 1028 0x24)); 1029 /* Adjust the active video horizontal start point */ 1030 status = cx231xx_read_modify_write_i2c_dword(dev, 1031 VID_BLK_I2C_ADDRESS, 1032 HORIZ_TIM_CTRL, 1033 FLD_HBLANK_CNT, 1034 cx231xx_set_field 1035 (FLD_HBLANK_CNT, 0x85)); 1036 } else { 1037 dev_dbg(dev->dev, "%s: PAL\n", __func__); 1038 status = cx231xx_read_modify_write_i2c_dword(dev, 1039 VID_BLK_I2C_ADDRESS, 1040 VERT_TIM_CTRL, 1041 FLD_VBLANK_CNT, 0x20); 1042 status = cx231xx_read_modify_write_i2c_dword(dev, 1043 VID_BLK_I2C_ADDRESS, 1044 VERT_TIM_CTRL, 1045 FLD_VACTIVE_CNT, 1046 cx231xx_set_field 1047 (FLD_VACTIVE_CNT, 1048 0x244)); 1049 status = cx231xx_read_modify_write_i2c_dword(dev, 1050 VID_BLK_I2C_ADDRESS, 1051 VERT_TIM_CTRL, 1052 FLD_V656BLANK_CNT, 1053 cx231xx_set_field 1054 (FLD_V656BLANK_CNT, 1055 0x24)); 1056 /* Adjust the active video horizontal start point */ 1057 status = cx231xx_read_modify_write_i2c_dword(dev, 1058 VID_BLK_I2C_ADDRESS, 1059 HORIZ_TIM_CTRL, 1060 FLD_HBLANK_CNT, 1061 cx231xx_set_field 1062 (FLD_HBLANK_CNT, 0x85)); 1063 1064 } 1065 1066 return status; 1067} 1068 1069int cx231xx_unmute_audio(struct cx231xx *dev) 1070{ 1071 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 1072} 1073EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 1074 1075static int stopAudioFirmware(struct cx231xx *dev) 1076{ 1077 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 1078} 1079 1080static int restartAudioFirmware(struct cx231xx *dev) 1081{ 1082 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 1083} 1084 1085int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1086{ 1087 int status = 0; 1088 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 1089 1090 switch (INPUT(input)->amux) { 1091 case CX231XX_AMUX_VIDEO: 1092 ainput = AUDIO_INPUT_TUNER_TV; 1093 break; 1094 case CX231XX_AMUX_LINE_IN: 1095 status = cx231xx_i2s_blk_set_audio_input(dev, input); 1096 ainput = AUDIO_INPUT_LINE; 1097 break; 1098 default: 1099 break; 1100 } 1101 1102 status = cx231xx_set_audio_decoder_input(dev, ainput); 1103 1104 return status; 1105} 1106 1107int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 1108 enum AUDIO_INPUT audio_input) 1109{ 1110 u32 dwval; 1111 int status; 1112 u8 gen_ctrl; 1113 u32 value = 0; 1114 1115 /* Put it in soft reset */ 1116 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1117 gen_ctrl |= 1; 1118 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1119 1120 switch (audio_input) { 1121 case AUDIO_INPUT_LINE: 1122 /* setup AUD_IO control from Merlin paralle output */ 1123 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 1124 AUD_CHAN_SRC_PARALLEL); 1125 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 1126 1127 /* setup input to Merlin, SRC2 connect to AC97 1128 bypass upsample-by-2, slave mode, sony mode, left justify 1129 adr 091c, dat 01000000 */ 1130 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 1131 1132 status = vid_blk_write_word(dev, AC97_CTL, 1133 (dwval | FLD_AC97_UP2X_BYPASS)); 1134 1135 /* select the parallel1 and SRC3 */ 1136 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1137 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 1138 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 1139 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 1140 1141 /* unmute all, AC97 in, independence mode 1142 adr 08d0, data 0x00063073 */ 1143 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 1144 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1145 1146 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1147 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 1148 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 1149 (dwval | FLD_PATH1_AVC_THRESHOLD)); 1150 1151 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1152 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 1153 status = vid_blk_write_word(dev, PATH1_SC_CTL, 1154 (dwval | FLD_PATH1_SC_THRESHOLD)); 1155 break; 1156 1157 case AUDIO_INPUT_TUNER_TV: 1158 default: 1159 status = stopAudioFirmware(dev); 1160 /* Setup SRC sources and clocks */ 1161 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1162 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1163 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 1164 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 1165 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 1166 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 1167 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 1168 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 1169 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 1170 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 1171 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1172 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1173 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1174 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1175 1176 /* Setup the AUD_IO control */ 1177 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1178 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1179 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1180 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1181 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1182 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1183 1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1185 1186 /* setAudioStandard(_audio_standard); */ 1187 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1188 1189 status = restartAudioFirmware(dev); 1190 1191 switch (dev->board.tuner_type) { 1192 case TUNER_XC5000: 1193 /* SIF passthrough at 28.6363 MHz sample rate */ 1194 status = cx231xx_read_modify_write_i2c_dword(dev, 1195 VID_BLK_I2C_ADDRESS, 1196 CHIP_CTRL, 1197 FLD_SIF_EN, 1198 cx231xx_set_field(FLD_SIF_EN, 1)); 1199 break; 1200 case TUNER_NXP_TDA18271: 1201 /* Normal mode: SIF passthrough at 14.32 MHz */ 1202 status = cx231xx_read_modify_write_i2c_dword(dev, 1203 VID_BLK_I2C_ADDRESS, 1204 CHIP_CTRL, 1205 FLD_SIF_EN, 1206 cx231xx_set_field(FLD_SIF_EN, 0)); 1207 break; 1208 default: 1209 switch (dev->model) { /* i2c device tuners */ 1210 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx: 1211 case CX231XX_BOARD_HAUPPAUGE_935C: 1212 case CX231XX_BOARD_HAUPPAUGE_955Q: 1213 case CX231XX_BOARD_HAUPPAUGE_975: 1214 case CX231XX_BOARD_EVROMEDIA_FULL_HYBRID_FULLHD: 1215 /* TODO: Normal mode: SIF passthrough at 14.32 MHz?? */ 1216 break; 1217 default: 1218 /* This is just a casual suggestion to people adding 1219 new boards in case they use a tuner type we don't 1220 currently know about */ 1221 dev_info(dev->dev, 1222 "Unknown tuner type configuring SIF"); 1223 break; 1224 } 1225 } 1226 break; 1227 1228 case AUDIO_INPUT_TUNER_FM: 1229 /* use SIF for FM radio 1230 setupFM(); 1231 setAudioStandard(_audio_standard); 1232 */ 1233 break; 1234 1235 case AUDIO_INPUT_MUTE: 1236 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1237 break; 1238 } 1239 1240 /* Take it out of soft reset */ 1241 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1242 gen_ctrl &= ~1; 1243 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1244 1245 return status; 1246} 1247 1248/****************************************************************************** 1249 * C H I P Specific C O N T R O L functions * 1250 ******************************************************************************/ 1251int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1252{ 1253 u32 value; 1254 int status = 0; 1255 1256 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1257 value |= (~dev->board.ctl_pin_status_mask); 1258 status = vid_blk_write_word(dev, PIN_CTRL, value); 1259 1260 return status; 1261} 1262 1263int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1264 u8 analog_or_digital) 1265{ 1266 int status; 1267 1268 /* first set the direction to output */ 1269 status = cx231xx_set_gpio_direction(dev, 1270 dev->board. 1271 agc_analog_digital_select_gpio, 1); 1272 1273 /* 0 - demod ; 1 - Analog mode */ 1274 status = cx231xx_set_gpio_value(dev, 1275 dev->board.agc_analog_digital_select_gpio, 1276 analog_or_digital); 1277 1278 if (status < 0) 1279 return status; 1280 1281 return 0; 1282} 1283 1284int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 1285{ 1286 u8 value[4] = { 0, 0, 0, 0 }; 1287 int status = 0; 1288 bool current_is_port_3; 1289 1290 /* 1291 * Should this code check dev->port_3_switch_enabled first 1292 * to skip unnecessary reading of the register? 1293 * If yes, the flag dev->port_3_switch_enabled must be initialized 1294 * correctly. 1295 */ 1296 1297 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1298 PWR_CTL_EN, value, 4); 1299 if (status < 0) 1300 return status; 1301 1302 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 1303 1304 /* Just return, if already using the right port */ 1305 if (current_is_port_3 == is_port_3) 1306 return 0; 1307 1308 if (is_port_3) 1309 value[0] |= I2C_DEMOD_EN; 1310 else 1311 value[0] &= ~I2C_DEMOD_EN; 1312 1313 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1314 PWR_CTL_EN, value, 4); 1315 1316 /* remember status of the switch for usage in is_tuner */ 1317 if (status >= 0) 1318 dev->port_3_switch_enabled = is_port_3; 1319 1320 return status; 1321 1322} 1323EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 1324 1325void update_HH_register_after_set_DIF(struct cx231xx *dev) 1326{ 1327/* 1328 u8 status = 0; 1329 u32 value = 0; 1330 1331 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 1332 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 1333 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 1334 1335 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1336 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1337 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1338*/ 1339} 1340 1341#if 0 1342static void cx231xx_dump_SC_reg(struct cx231xx *dev) 1343{ 1344 u8 value[4] = { 0, 0, 0, 0 }; 1345 dev_dbg(dev->dev, "%s!\n", __func__); 1346 1347 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 1348 value, 4); 1349 dev_dbg(dev->dev, 1350 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 1351 value[1], value[2], value[3]); 1352 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 1353 value, 4); 1354 dev_dbg(dev->dev, 1355 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 1356 value[1], value[2], value[3]); 1357 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 1358 value, 4); 1359 dev_dbg(dev->dev, 1360 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 1361 value[1], value[2], value[3]); 1362 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 1363 value, 4); 1364 dev_dbg(dev->dev, 1365 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 1366 value[1], value[2], value[3]); 1367 1368 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 1369 value, 4); 1370 dev_dbg(dev->dev, 1371 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 1372 value[1], value[2], value[3]); 1373 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 1374 value, 4); 1375 dev_dbg(dev->dev, 1376 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 1377 value[1], value[2], value[3]); 1378 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1379 value, 4); 1380 dev_dbg(dev->dev, 1381 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 1382 value[1], value[2], value[3]); 1383 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 1384 value, 4); 1385 dev_dbg(dev->dev, 1386 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 1387 value[1], value[2], value[3]); 1388 1389 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 1390 value, 4); 1391 dev_dbg(dev->dev, 1392 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 1393 value[1], value[2], value[3]); 1394 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 1395 value, 4); 1396 dev_dbg(dev->dev, 1397 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 1398 value[1], value[2], value[3]); 1399 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 1400 value, 4); 1401 dev_dbg(dev->dev, 1402 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 1403 value[1], value[2], value[3]); 1404 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 1405 value, 4); 1406 dev_dbg(dev->dev, 1407 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 1408 value[1], value[2], value[3]); 1409 1410 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 1411 value, 4); 1412 dev_dbg(dev->dev, 1413 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 1414 value[1], value[2], value[3]); 1415 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 1416 value, 4); 1417 dev_dbg(dev->dev, 1418 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 1419 value[1], value[2], value[3]); 1420 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 1421 value, 4); 1422 dev_dbg(dev->dev, 1423 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 1424 value[1], value[2], value[3]); 1425 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 1426 value, 4); 1427 dev_dbg(dev->dev, 1428 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 1429 value[1], value[2], value[3]); 1430 1431 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 1432 value, 4); 1433 dev_dbg(dev->dev, 1434 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 1435 value[1], value[2], value[3]); 1436 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1437 value, 4); 1438 dev_dbg(dev->dev, 1439 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 1440 value[1], value[2], value[3]); 1441} 1442#endif 1443 1444void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 1445 1446{ 1447 u8 value = 0; 1448 1449 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1450 value = (value & 0xFE)|0x01; 1451 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1452 1453 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1454 value = (value & 0xFE)|0x00; 1455 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1456 1457 1458/* 1459 config colibri to lo-if mode 1460 1461 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1462 the diff IF input by half, 1463 1464 for low-if agc defect 1465*/ 1466 1467 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1468 value = (value & 0xFC)|0x00; 1469 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 1470 1471 afe_read_byte(dev, ADC_INPUT_CH3, &value); 1472 value = (value & 0xF9)|0x02; 1473 afe_write_byte(dev, ADC_INPUT_CH3, value); 1474 1475 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 1476 value = (value & 0xFB)|0x04; 1477 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 1478 1479 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 1480 value = (value & 0xFC)|0x03; 1481 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 1482 1483 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 1484 value = (value & 0xFB)|0x04; 1485 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 1486 1487 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1488 value = (value & 0xF8)|0x06; 1489 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1490 1491 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1492 value = (value & 0x8F)|0x40; 1493 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1494 1495 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 1496 value = (value & 0xDF)|0x20; 1497 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 1498} 1499 1500void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 1501 u8 spectral_invert, u32 mode) 1502{ 1503 u32 colibri_carrier_offset = 0; 1504 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 1505 u32 standard = 0; 1506 u8 value[4] = { 0, 0, 0, 0 }; 1507 1508 dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n"); 1509 value[0] = (u8) 0x6F; 1510 value[1] = (u8) 0x6F; 1511 value[2] = (u8) 0x6F; 1512 value[3] = (u8) 0x6F; 1513 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1514 PWR_CTL_EN, value, 4); 1515 1516 /*Set colibri for low IF*/ 1517 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 1518 1519 /* Set C2HH for low IF operation.*/ 1520 standard = dev->norm; 1521 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1522 func_mode, standard); 1523 1524 /* Get colibri offsets.*/ 1525 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 1526 standard); 1527 1528 dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n", 1529 colibri_carrier_offset, standard); 1530 1531 /* Set the band Pass filter for DIF*/ 1532 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 1533 spectral_invert, mode); 1534} 1535 1536u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1537{ 1538 u32 colibri_carrier_offset = 0; 1539 1540 if (mode == TUNER_MODE_FM_RADIO) { 1541 colibri_carrier_offset = 1100000; 1542 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 1543 colibri_carrier_offset = 4832000; /*4.83MHz */ 1544 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1545 colibri_carrier_offset = 2700000; /*2.70MHz */ 1546 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 1547 | V4L2_STD_SECAM)) { 1548 colibri_carrier_offset = 2100000; /*2.10MHz */ 1549 } 1550 1551 return colibri_carrier_offset; 1552} 1553 1554void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1555 u8 spectral_invert, u32 mode) 1556{ 1557 unsigned long pll_freq_word; 1558 u32 dif_misc_ctrl_value = 0; 1559 u64 pll_freq_u64 = 0; 1560 u32 i = 0; 1561 1562 dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1563 if_freq, spectral_invert, mode); 1564 1565 1566 if (mode == TUNER_MODE_FM_RADIO) { 1567 pll_freq_word = 0x905A1CAC; 1568 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1569 1570 } else /*KSPROPERTY_TUNER_MODE_TV*/{ 1571 /* Calculate the PLL frequency word based on the adjusted if_freq*/ 1572 pll_freq_word = if_freq; 1573 pll_freq_u64 = (u64)pll_freq_word << 28L; 1574 do_div(pll_freq_u64, 50000000); 1575 pll_freq_word = (u32)pll_freq_u64; 1576 /*pll_freq_word = 0x3463497;*/ 1577 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1578 1579 if (spectral_invert) { 1580 if_freq -= 400000; 1581 /* Enable Spectral Invert*/ 1582 vid_blk_read_word(dev, DIF_MISC_CTRL, 1583 &dif_misc_ctrl_value); 1584 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 1585 vid_blk_write_word(dev, DIF_MISC_CTRL, 1586 dif_misc_ctrl_value); 1587 } else { 1588 if_freq += 400000; 1589 /* Disable Spectral Invert*/ 1590 vid_blk_read_word(dev, DIF_MISC_CTRL, 1591 &dif_misc_ctrl_value); 1592 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 1593 vid_blk_write_word(dev, DIF_MISC_CTRL, 1594 dif_misc_ctrl_value); 1595 } 1596 1597 if_freq = (if_freq / 100000) * 100000; 1598 1599 if (if_freq < 3000000) 1600 if_freq = 3000000; 1601 1602 if (if_freq > 16000000) 1603 if_freq = 16000000; 1604 } 1605 1606 dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array)); 1607 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 1608 if (Dif_set_array[i].if_freq == if_freq) { 1609 vid_blk_write_word(dev, 1610 Dif_set_array[i].register_address, Dif_set_array[i].value); 1611 } 1612 } 1613} 1614 1615/****************************************************************************** 1616 * D I F - B L O C K C O N T R O L functions * 1617 ******************************************************************************/ 1618int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1619 u32 function_mode, u32 standard) 1620{ 1621 int status = 0; 1622 1623 1624 if (mode == V4L2_TUNER_RADIO) { 1625 /* C2HH */ 1626 /* lo if big signal */ 1627 status = cx231xx_reg_mask_write(dev, 1628 VID_BLK_I2C_ADDRESS, 32, 1629 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1630 /* FUNC_MODE = DIF */ 1631 status = cx231xx_reg_mask_write(dev, 1632 VID_BLK_I2C_ADDRESS, 32, 1633 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1634 /* IF_MODE */ 1635 status = cx231xx_reg_mask_write(dev, 1636 VID_BLK_I2C_ADDRESS, 32, 1637 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1638 /* no inv */ 1639 status = cx231xx_reg_mask_write(dev, 1640 VID_BLK_I2C_ADDRESS, 32, 1641 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1642 } else if (standard != DIF_USE_BASEBAND) { 1643 if (standard & V4L2_STD_MN) { 1644 /* lo if big signal */ 1645 status = cx231xx_reg_mask_write(dev, 1646 VID_BLK_I2C_ADDRESS, 32, 1647 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1648 /* FUNC_MODE = DIF */ 1649 status = cx231xx_reg_mask_write(dev, 1650 VID_BLK_I2C_ADDRESS, 32, 1651 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1652 function_mode); 1653 /* IF_MODE */ 1654 status = cx231xx_reg_mask_write(dev, 1655 VID_BLK_I2C_ADDRESS, 32, 1656 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1657 /* no inv */ 1658 status = cx231xx_reg_mask_write(dev, 1659 VID_BLK_I2C_ADDRESS, 32, 1660 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1661 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1662 status = cx231xx_reg_mask_write(dev, 1663 VID_BLK_I2C_ADDRESS, 32, 1664 AUD_IO_CTRL, 0, 31, 0x00000003); 1665 } else if ((standard == V4L2_STD_PAL_I) | 1666 (standard & V4L2_STD_PAL_D) | 1667 (standard & V4L2_STD_SECAM)) { 1668 /* C2HH setup */ 1669 /* lo if big signal */ 1670 status = cx231xx_reg_mask_write(dev, 1671 VID_BLK_I2C_ADDRESS, 32, 1672 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1673 /* FUNC_MODE = DIF */ 1674 status = cx231xx_reg_mask_write(dev, 1675 VID_BLK_I2C_ADDRESS, 32, 1676 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1677 function_mode); 1678 /* IF_MODE */ 1679 status = cx231xx_reg_mask_write(dev, 1680 VID_BLK_I2C_ADDRESS, 32, 1681 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1682 /* no inv */ 1683 status = cx231xx_reg_mask_write(dev, 1684 VID_BLK_I2C_ADDRESS, 32, 1685 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1686 } else { 1687 /* default PAL BG */ 1688 /* C2HH setup */ 1689 /* lo if big signal */ 1690 status = cx231xx_reg_mask_write(dev, 1691 VID_BLK_I2C_ADDRESS, 32, 1692 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1693 /* FUNC_MODE = DIF */ 1694 status = cx231xx_reg_mask_write(dev, 1695 VID_BLK_I2C_ADDRESS, 32, 1696 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1697 function_mode); 1698 /* IF_MODE */ 1699 status = cx231xx_reg_mask_write(dev, 1700 VID_BLK_I2C_ADDRESS, 32, 1701 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1702 /* no inv */ 1703 status = cx231xx_reg_mask_write(dev, 1704 VID_BLK_I2C_ADDRESS, 32, 1705 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1706 } 1707 } 1708 1709 return status; 1710} 1711 1712int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1713{ 1714 int status = 0; 1715 u32 dif_misc_ctrl_value = 0; 1716 u32 func_mode = 0; 1717 1718 dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard); 1719 1720 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1721 if (standard != DIF_USE_BASEBAND) 1722 dev->norm = standard; 1723 1724 switch (dev->model) { 1725 case CX231XX_BOARD_CNXT_CARRAERA: 1726 case CX231XX_BOARD_CNXT_RDE_250: 1727 case CX231XX_BOARD_CNXT_SHELBY: 1728 case CX231XX_BOARD_CNXT_RDU_250: 1729 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 1730 case CX231XX_BOARD_HAUPPAUGE_EXETER: 1731 case CX231XX_BOARD_OTG102: 1732 func_mode = 0x03; 1733 break; 1734 case CX231XX_BOARD_CNXT_RDE_253S: 1735 case CX231XX_BOARD_CNXT_RDU_253S: 1736 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 1737 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 1738 func_mode = 0x01; 1739 break; 1740 default: 1741 func_mode = 0x01; 1742 } 1743 1744 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1745 func_mode, standard); 1746 1747 if (standard == DIF_USE_BASEBAND) { /* base band */ 1748 /* There is a different SRC_PHASE_INC value 1749 for baseband vs. DIF */ 1750 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 1751 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1752 &dif_misc_ctrl_value); 1753 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1754 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1755 dif_misc_ctrl_value); 1756 } else if (standard & V4L2_STD_PAL_D) { 1757 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1758 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1759 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1760 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1761 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1762 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1763 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1764 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1765 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1766 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1767 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1768 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1770 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1772 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1773 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1774 DIF_AGC_IF_INT_CURRENT, 0, 31, 1775 0x26001700); 1776 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1777 DIF_AGC_RF_CURRENT, 0, 31, 1778 0x00002660); 1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1780 DIF_VIDEO_AGC_CTRL, 0, 31, 1781 0x72500800); 1782 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1783 DIF_VID_AUD_OVERRIDE, 0, 31, 1784 0x27000100); 1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1786 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1788 DIF_COMP_FLT_CTRL, 0, 31, 1789 0x00000000); 1790 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1791 DIF_SRC_PHASE_INC, 0, 31, 1792 0x1befbf06); 1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1794 DIF_SRC_GAIN_CONTROL, 0, 31, 1795 0x000035e8); 1796 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1797 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1798 /* Save the Spec Inversion value */ 1799 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1800 dif_misc_ctrl_value |= 0x3a023F11; 1801 } else if (standard & V4L2_STD_PAL_I) { 1802 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1803 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1805 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1807 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1808 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1809 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1810 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1811 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1813 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1815 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1817 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1819 DIF_AGC_IF_INT_CURRENT, 0, 31, 1820 0x26001700); 1821 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1822 DIF_AGC_RF_CURRENT, 0, 31, 1823 0x00002660); 1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1825 DIF_VIDEO_AGC_CTRL, 0, 31, 1826 0x72500800); 1827 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1828 DIF_VID_AUD_OVERRIDE, 0, 31, 1829 0x27000100); 1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1831 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1833 DIF_COMP_FLT_CTRL, 0, 31, 1834 0x00000000); 1835 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1836 DIF_SRC_PHASE_INC, 0, 31, 1837 0x1befbf06); 1838 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1839 DIF_SRC_GAIN_CONTROL, 0, 31, 1840 0x000035e8); 1841 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1842 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1843 /* Save the Spec Inversion value */ 1844 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1845 dif_misc_ctrl_value |= 0x3a033F11; 1846 } else if (standard & V4L2_STD_PAL_M) { 1847 /* improved Low Frequency Phase Noise */ 1848 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1849 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1850 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1851 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1852 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1853 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1854 0x26001700); 1855 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1856 0x00002660); 1857 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1858 0x72500800); 1859 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1860 0x27000100); 1861 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 1862 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1863 0x009f50c1); 1864 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1865 0x1befbf06); 1866 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1867 0x000035e8); 1868 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1869 0x00000000); 1870 /* Save the Spec Inversion value */ 1871 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1872 dif_misc_ctrl_value |= 0x3A0A3F10; 1873 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1874 /* improved Low Frequency Phase Noise */ 1875 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1876 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1877 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1878 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1879 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1880 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1881 0x26001700); 1882 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1883 0x00002660); 1884 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1885 0x72500800); 1886 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1887 0x27000100); 1888 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 1889 0x012c405d); 1890 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1891 0x009f50c1); 1892 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1893 0x1befbf06); 1894 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1895 0x000035e8); 1896 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1897 0x00000000); 1898 /* Save the Spec Inversion value */ 1899 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1900 dif_misc_ctrl_value = 0x3A093F10; 1901 } else if (standard & 1902 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1903 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1904 1905 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1906 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1907 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1908 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1909 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1910 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1911 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1912 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1913 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1914 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1915 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1916 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1918 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1920 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1921 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1922 DIF_AGC_IF_INT_CURRENT, 0, 31, 1923 0x26001700); 1924 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1925 DIF_AGC_RF_CURRENT, 0, 31, 1926 0x00002660); 1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1928 DIF_VID_AUD_OVERRIDE, 0, 31, 1929 0x27000100); 1930 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1931 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1932 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1933 DIF_COMP_FLT_CTRL, 0, 31, 1934 0x00000000); 1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1936 DIF_SRC_PHASE_INC, 0, 31, 1937 0x1befbf06); 1938 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1939 DIF_SRC_GAIN_CONTROL, 0, 31, 1940 0x000035e8); 1941 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1942 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1944 DIF_VIDEO_AGC_CTRL, 0, 31, 1945 0xf4000000); 1946 1947 /* Save the Spec Inversion value */ 1948 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1949 dif_misc_ctrl_value |= 0x3a023F11; 1950 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1951 /* Is it SECAM_L1? */ 1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1953 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1955 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1956 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1957 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1958 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1959 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1961 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1963 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1965 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1967 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1968 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1969 DIF_AGC_IF_INT_CURRENT, 0, 31, 1970 0x26001700); 1971 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1972 DIF_AGC_RF_CURRENT, 0, 31, 1973 0x00002660); 1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1975 DIF_VID_AUD_OVERRIDE, 0, 31, 1976 0x27000100); 1977 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1978 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1979 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1980 DIF_COMP_FLT_CTRL, 0, 31, 1981 0x00000000); 1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1983 DIF_SRC_PHASE_INC, 0, 31, 1984 0x1befbf06); 1985 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1986 DIF_SRC_GAIN_CONTROL, 0, 31, 1987 0x000035e8); 1988 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1989 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1991 DIF_VIDEO_AGC_CTRL, 0, 31, 1992 0xf2560000); 1993 1994 /* Save the Spec Inversion value */ 1995 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1996 dif_misc_ctrl_value |= 0x3a023F11; 1997 1998 } else if (standard & V4L2_STD_NTSC_M) { 1999 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 2000 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 2001 2002 /* For NTSC the centre frequency of video coming out of 2003 sidewinder is around 7.1MHz or 3.6MHz depending on the 2004 spectral inversion. so for a non spectrally inverted channel 2005 the pll freq word is 0x03420c49 2006 */ 2007 2008 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 2009 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 2010 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 2011 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 2012 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 2013 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 2014 0x26001700); 2015 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 2016 0x00002660); 2017 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 2018 0x04000800); 2019 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 2020 0x27000100); 2021 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 2022 2023 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 2024 0x009f50c1); 2025 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 2026 0x1befbf06); 2027 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 2028 0x000035e8); 2029 2030 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 2031 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 2032 0xC2262600); 2033 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 2034 2035 /* Save the Spec Inversion value */ 2036 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2037 dif_misc_ctrl_value |= 0x3a003F10; 2038 } else { 2039 /* default PAL BG */ 2040 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2041 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 2042 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2043 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 2044 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2045 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 2046 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2047 DIF_PLL_CTRL3, 0, 31, 0x00008800); 2048 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2049 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 2050 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2051 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2053 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2055 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 2056 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2057 DIF_AGC_IF_INT_CURRENT, 0, 31, 2058 0x26001700); 2059 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2060 DIF_AGC_RF_CURRENT, 0, 31, 2061 0x00002660); 2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2063 DIF_VIDEO_AGC_CTRL, 0, 31, 2064 0x72500800); 2065 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2066 DIF_VID_AUD_OVERRIDE, 0, 31, 2067 0x27000100); 2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2069 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2071 DIF_COMP_FLT_CTRL, 0, 31, 2072 0x00A653A8); 2073 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2074 DIF_SRC_PHASE_INC, 0, 31, 2075 0x1befbf06); 2076 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2077 DIF_SRC_GAIN_CONTROL, 0, 31, 2078 0x000035e8); 2079 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2080 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2081 /* Save the Spec Inversion value */ 2082 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2083 dif_misc_ctrl_value |= 0x3a013F11; 2084 } 2085 2086 /* The AGC values should be the same for all standards, 2087 AUD_SRC_SEL[19] should always be disabled */ 2088 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 2089 2090 /* It is still possible to get Set Standard calls even when we 2091 are in FM mode. 2092 This is done to override the value for FM. */ 2093 if (dev->active_mode == V4L2_TUNER_RADIO) 2094 dif_misc_ctrl_value = 0x7a080000; 2095 2096 /* Write the calculated value for misc ontrol register */ 2097 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 2098 2099 return status; 2100} 2101 2102int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 2103{ 2104 int status = 0; 2105 u32 dwval; 2106 2107 /* Set the RF and IF k_agc values to 3 */ 2108 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2109 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2110 dwval |= 0x33000000; 2111 2112 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2113 2114 return status; 2115} 2116 2117int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 2118{ 2119 int status = 0; 2120 u32 dwval; 2121 dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n", 2122 __func__, dev->tuner_type); 2123 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2124 * SECAM L/B/D standards */ 2125 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2126 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2127 2128 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 2129 V4L2_STD_SECAM_D)) { 2130 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2131 dwval &= ~FLD_DIF_IF_REF; 2132 dwval |= 0x88000300; 2133 } else 2134 dwval |= 0x88000000; 2135 } else { 2136 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2137 dwval &= ~FLD_DIF_IF_REF; 2138 dwval |= 0xCC000300; 2139 } else 2140 dwval |= 0x44000000; 2141 } 2142 2143 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2144 2145 return status == sizeof(dwval) ? 0 : -EIO; 2146} 2147 2148/****************************************************************************** 2149 * I 2 S - B L O C K C O N T R O L functions * 2150 ******************************************************************************/ 2151int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 2152{ 2153 int status = 0; 2154 u32 value; 2155 2156 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2157 CH_PWR_CTRL1, 1, &value, 1); 2158 /* enables clock to delta-sigma and decimation filter */ 2159 value |= 0x80; 2160 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2161 CH_PWR_CTRL1, 1, value, 1); 2162 /* power up all channel */ 2163 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2164 CH_PWR_CTRL2, 1, 0x00, 1); 2165 2166 return status; 2167} 2168 2169int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 2170 enum AV_MODE avmode) 2171{ 2172 int status = 0; 2173 u32 value = 0; 2174 2175 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 2176 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2177 CH_PWR_CTRL2, 1, &value, 1); 2178 value |= 0xfe; 2179 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2180 CH_PWR_CTRL2, 1, value, 1); 2181 } else { 2182 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2183 CH_PWR_CTRL2, 1, 0x00, 1); 2184 } 2185 2186 return status; 2187} 2188 2189/* set i2s_blk for audio input types */ 2190int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 2191{ 2192 int status = 0; 2193 2194 switch (audio_input) { 2195 case CX231XX_AMUX_LINE_IN: 2196 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2197 CH_PWR_CTRL2, 1, 0x00, 1); 2198 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2199 CH_PWR_CTRL1, 1, 0x80, 1); 2200 break; 2201 case CX231XX_AMUX_VIDEO: 2202 default: 2203 break; 2204 } 2205 2206 dev->ctl_ainput = audio_input; 2207 2208 return status; 2209} 2210 2211/****************************************************************************** 2212 * P O W E R C O N T R O L functions * 2213 ******************************************************************************/ 2214int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 2215{ 2216 u8 value[4] = { 0, 0, 0, 0 }; 2217 u32 tmp = 0; 2218 int status = 0; 2219 2220 if (dev->power_mode != mode) 2221 dev->power_mode = mode; 2222 else { 2223 dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n", 2224 __func__, mode); 2225 return 0; 2226 } 2227 2228 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2229 4); 2230 if (status < 0) 2231 return status; 2232 2233 tmp = le32_to_cpu(*((__le32 *) value)); 2234 2235 switch (mode) { 2236 case POLARIS_AVMODE_ENXTERNAL_AV: 2237 2238 tmp &= (~PWR_MODE_MASK); 2239 2240 tmp |= PWR_AV_EN; 2241 value[0] = (u8) tmp; 2242 value[1] = (u8) (tmp >> 8); 2243 value[2] = (u8) (tmp >> 16); 2244 value[3] = (u8) (tmp >> 24); 2245 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2246 PWR_CTL_EN, value, 4); 2247 msleep(PWR_SLEEP_INTERVAL); 2248 2249 tmp |= PWR_ISO_EN; 2250 value[0] = (u8) tmp; 2251 value[1] = (u8) (tmp >> 8); 2252 value[2] = (u8) (tmp >> 16); 2253 value[3] = (u8) (tmp >> 24); 2254 status = 2255 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2256 value, 4); 2257 msleep(PWR_SLEEP_INTERVAL); 2258 2259 tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 2260 value[0] = (u8) tmp; 2261 value[1] = (u8) (tmp >> 8); 2262 value[2] = (u8) (tmp >> 16); 2263 value[3] = (u8) (tmp >> 24); 2264 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2265 PWR_CTL_EN, value, 4); 2266 2267 /* reset state of xceive tuner */ 2268 dev->xc_fw_load_done = 0; 2269 break; 2270 2271 case POLARIS_AVMODE_ANALOGT_TV: 2272 2273 tmp |= PWR_DEMOD_EN; 2274 value[0] = (u8) tmp; 2275 value[1] = (u8) (tmp >> 8); 2276 value[2] = (u8) (tmp >> 16); 2277 value[3] = (u8) (tmp >> 24); 2278 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2279 PWR_CTL_EN, value, 4); 2280 msleep(PWR_SLEEP_INTERVAL); 2281 2282 if (!(tmp & PWR_TUNER_EN)) { 2283 tmp |= (PWR_TUNER_EN); 2284 value[0] = (u8) tmp; 2285 value[1] = (u8) (tmp >> 8); 2286 value[2] = (u8) (tmp >> 16); 2287 value[3] = (u8) (tmp >> 24); 2288 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2289 PWR_CTL_EN, value, 4); 2290 msleep(PWR_SLEEP_INTERVAL); 2291 } 2292 2293 if (!(tmp & PWR_AV_EN)) { 2294 tmp |= PWR_AV_EN; 2295 value[0] = (u8) tmp; 2296 value[1] = (u8) (tmp >> 8); 2297 value[2] = (u8) (tmp >> 16); 2298 value[3] = (u8) (tmp >> 24); 2299 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2300 PWR_CTL_EN, value, 4); 2301 msleep(PWR_SLEEP_INTERVAL); 2302 } 2303 if (!(tmp & PWR_ISO_EN)) { 2304 tmp |= PWR_ISO_EN; 2305 value[0] = (u8) tmp; 2306 value[1] = (u8) (tmp >> 8); 2307 value[2] = (u8) (tmp >> 16); 2308 value[3] = (u8) (tmp >> 24); 2309 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2310 PWR_CTL_EN, value, 4); 2311 msleep(PWR_SLEEP_INTERVAL); 2312 } 2313 2314 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 2315 tmp |= POLARIS_AVMODE_ANALOGT_TV; 2316 value[0] = (u8) tmp; 2317 value[1] = (u8) (tmp >> 8); 2318 value[2] = (u8) (tmp >> 16); 2319 value[3] = (u8) (tmp >> 24); 2320 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2321 PWR_CTL_EN, value, 4); 2322 msleep(PWR_SLEEP_INTERVAL); 2323 } 2324 2325 if (dev->board.tuner_type != TUNER_ABSENT) { 2326 /* reset the Tuner */ 2327 if (dev->board.tuner_gpio) 2328 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2329 2330 if (dev->cx231xx_reset_analog_tuner) 2331 dev->cx231xx_reset_analog_tuner(dev); 2332 } 2333 2334 break; 2335 2336 case POLARIS_AVMODE_DIGITAL: 2337 if (!(tmp & PWR_TUNER_EN)) { 2338 tmp |= (PWR_TUNER_EN); 2339 value[0] = (u8) tmp; 2340 value[1] = (u8) (tmp >> 8); 2341 value[2] = (u8) (tmp >> 16); 2342 value[3] = (u8) (tmp >> 24); 2343 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2344 PWR_CTL_EN, value, 4); 2345 msleep(PWR_SLEEP_INTERVAL); 2346 } 2347 if (!(tmp & PWR_AV_EN)) { 2348 tmp |= PWR_AV_EN; 2349 value[0] = (u8) tmp; 2350 value[1] = (u8) (tmp >> 8); 2351 value[2] = (u8) (tmp >> 16); 2352 value[3] = (u8) (tmp >> 24); 2353 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2354 PWR_CTL_EN, value, 4); 2355 msleep(PWR_SLEEP_INTERVAL); 2356 } 2357 if (!(tmp & PWR_ISO_EN)) { 2358 tmp |= PWR_ISO_EN; 2359 value[0] = (u8) tmp; 2360 value[1] = (u8) (tmp >> 8); 2361 value[2] = (u8) (tmp >> 16); 2362 value[3] = (u8) (tmp >> 24); 2363 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2364 PWR_CTL_EN, value, 4); 2365 msleep(PWR_SLEEP_INTERVAL); 2366 } 2367 2368 tmp &= (~PWR_AV_MODE); 2369 tmp |= POLARIS_AVMODE_DIGITAL; 2370 value[0] = (u8) tmp; 2371 value[1] = (u8) (tmp >> 8); 2372 value[2] = (u8) (tmp >> 16); 2373 value[3] = (u8) (tmp >> 24); 2374 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2375 PWR_CTL_EN, value, 4); 2376 msleep(PWR_SLEEP_INTERVAL); 2377 2378 if (!(tmp & PWR_DEMOD_EN)) { 2379 tmp |= PWR_DEMOD_EN; 2380 value[0] = (u8) tmp; 2381 value[1] = (u8) (tmp >> 8); 2382 value[2] = (u8) (tmp >> 16); 2383 value[3] = (u8) (tmp >> 24); 2384 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2385 PWR_CTL_EN, value, 4); 2386 msleep(PWR_SLEEP_INTERVAL); 2387 } 2388 2389 if (dev->board.tuner_type != TUNER_ABSENT) { 2390 /* reset the Tuner */ 2391 if (dev->board.tuner_gpio) 2392 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2393 2394 if (dev->cx231xx_reset_analog_tuner) 2395 dev->cx231xx_reset_analog_tuner(dev); 2396 } 2397 break; 2398 2399 default: 2400 break; 2401 } 2402 2403 msleep(PWR_SLEEP_INTERVAL); 2404 2405 /* For power saving, only enable Pwr_resetout_n 2406 when digital TV is selected. */ 2407 if (mode == POLARIS_AVMODE_DIGITAL) { 2408 tmp |= PWR_RESETOUT_EN; 2409 value[0] = (u8) tmp; 2410 value[1] = (u8) (tmp >> 8); 2411 value[2] = (u8) (tmp >> 16); 2412 value[3] = (u8) (tmp >> 24); 2413 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2414 PWR_CTL_EN, value, 4); 2415 msleep(PWR_SLEEP_INTERVAL); 2416 } 2417 2418 /* update power control for afe */ 2419 status = cx231xx_afe_update_power_control(dev, mode); 2420 2421 /* update power control for i2s_blk */ 2422 status = cx231xx_i2s_blk_update_power_control(dev, mode); 2423 2424 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2425 4); 2426 2427 return status; 2428} 2429 2430/****************************************************************************** 2431 * S T R E A M C O N T R O L functions * 2432 ******************************************************************************/ 2433int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 2434{ 2435 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2436 u32 tmp = 0; 2437 int status = 0; 2438 2439 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 2440 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 2441 value, 4); 2442 if (status < 0) 2443 return status; 2444 2445 tmp = le32_to_cpu(*((__le32 *) value)); 2446 tmp |= ep_mask; 2447 value[0] = (u8) tmp; 2448 value[1] = (u8) (tmp >> 8); 2449 value[2] = (u8) (tmp >> 16); 2450 value[3] = (u8) (tmp >> 24); 2451 2452 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2453 value, 4); 2454 2455 return status; 2456} 2457 2458int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 2459{ 2460 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2461 u32 tmp = 0; 2462 int status = 0; 2463 2464 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 2465 status = 2466 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 2467 if (status < 0) 2468 return status; 2469 2470 tmp = le32_to_cpu(*((__le32 *) value)); 2471 tmp &= (~ep_mask); 2472 value[0] = (u8) tmp; 2473 value[1] = (u8) (tmp >> 8); 2474 value[2] = (u8) (tmp >> 16); 2475 value[3] = (u8) (tmp >> 24); 2476 2477 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2478 value, 4); 2479 2480 return status; 2481} 2482 2483int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 2484{ 2485 int status = 0; 2486 u32 value = 0; 2487 u8 val[4] = { 0, 0, 0, 0 }; 2488 2489 if (dev->udev->speed == USB_SPEED_HIGH) { 2490 switch (media_type) { 2491 case Audio: 2492 dev_dbg(dev->dev, 2493 "%s: Audio enter HANC\n", __func__); 2494 status = 2495 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2496 break; 2497 2498 case Vbi: 2499 dev_dbg(dev->dev, 2500 "%s: set vanc registers\n", __func__); 2501 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 2502 break; 2503 2504 case Sliced_cc: 2505 dev_dbg(dev->dev, 2506 "%s: set hanc registers\n", __func__); 2507 status = 2508 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 2509 break; 2510 2511 case Raw_Video: 2512 dev_dbg(dev->dev, 2513 "%s: set video registers\n", __func__); 2514 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2515 break; 2516 2517 case TS1_serial_mode: 2518 dev_dbg(dev->dev, 2519 "%s: set ts1 registers", __func__); 2520 2521 if (dev->board.has_417) { 2522 dev_dbg(dev->dev, 2523 "%s: MPEG\n", __func__); 2524 value &= 0xFFFFFFFC; 2525 value |= 0x3; 2526 2527 status = cx231xx_mode_register(dev, 2528 TS_MODE_REG, value); 2529 2530 val[0] = 0x04; 2531 val[1] = 0xA3; 2532 val[2] = 0x3B; 2533 val[3] = 0x00; 2534 status = cx231xx_write_ctrl_reg(dev, 2535 VRT_SET_REGISTER, 2536 TS1_CFG_REG, val, 4); 2537 2538 val[0] = 0x00; 2539 val[1] = 0x08; 2540 val[2] = 0x00; 2541 val[3] = 0x08; 2542 status = cx231xx_write_ctrl_reg(dev, 2543 VRT_SET_REGISTER, 2544 TS1_LENGTH_REG, val, 4); 2545 } else { 2546 dev_dbg(dev->dev, "%s: BDA\n", __func__); 2547 status = cx231xx_mode_register(dev, 2548 TS_MODE_REG, 0x101); 2549 status = cx231xx_mode_register(dev, 2550 TS1_CFG_REG, 0x010); 2551 } 2552 break; 2553 2554 case TS1_parallel_mode: 2555 dev_dbg(dev->dev, 2556 "%s: set ts1 parallel mode registers\n", 2557 __func__); 2558 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2559 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2560 break; 2561 } 2562 } else { 2563 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2564 } 2565 2566 return status; 2567} 2568 2569int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 2570{ 2571 int rc = -1; 2572 u32 ep_mask = -1; 2573 struct pcb_config *pcb_config; 2574 2575 /* get EP for media type */ 2576 pcb_config = (struct pcb_config *)&dev->current_pcb_config; 2577 2578 if (pcb_config->config_num) { 2579 switch (media_type) { 2580 case Raw_Video: 2581 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2582 break; 2583 case Audio: 2584 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2585 break; 2586 case Vbi: 2587 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2588 break; 2589 case Sliced_cc: 2590 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2591 break; 2592 case TS1_serial_mode: 2593 case TS1_parallel_mode: 2594 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2595 break; 2596 case TS2: 2597 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2598 break; 2599 } 2600 } 2601 2602 if (start) { 2603 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2604 2605 if (rc < 0) 2606 return rc; 2607 2608 /* enable video capture */ 2609 if (ep_mask > 0) 2610 rc = cx231xx_start_stream(dev, ep_mask); 2611 } else { 2612 /* disable video capture */ 2613 if (ep_mask > 0) 2614 rc = cx231xx_stop_stream(dev, ep_mask); 2615 } 2616 2617 return rc; 2618} 2619EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2620 2621/***************************************************************************** 2622* G P I O B I T control functions * 2623******************************************************************************/ 2624static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val) 2625{ 2626 int status = 0; 2627 2628 gpio_val = (__force u32)cpu_to_le32(gpio_val); 2629 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0); 2630 2631 return status; 2632} 2633 2634static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val) 2635{ 2636 __le32 tmp; 2637 int status = 0; 2638 2639 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1); 2640 *gpio_val = le32_to_cpu(tmp); 2641 2642 return status; 2643} 2644 2645/* 2646* cx231xx_set_gpio_direction 2647* Sets the direction of the GPIO pin to input or output 2648* 2649* Parameters : 2650* pin_number : The GPIO Pin number to program the direction for 2651* from 0 to 31 2652* pin_value : The Direction of the GPIO Pin under reference. 2653* 0 = Input direction 2654* 1 = Output direction 2655*/ 2656int cx231xx_set_gpio_direction(struct cx231xx *dev, 2657 int pin_number, int pin_value) 2658{ 2659 int status = 0; 2660 u32 value = 0; 2661 2662 /* Check for valid pin_number - if 32 , bail out */ 2663 if (pin_number >= 32) 2664 return -EINVAL; 2665 2666 /* input */ 2667 if (pin_value == 0) 2668 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2669 else 2670 value = dev->gpio_dir | (1 << pin_number); 2671 2672 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val); 2673 2674 /* cache the value for future */ 2675 dev->gpio_dir = value; 2676 2677 return status; 2678} 2679 2680/* 2681* cx231xx_set_gpio_value 2682* Sets the value of the GPIO pin to Logic high or low. The Pin under 2683* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2684* 2685* Parameters : 2686* pin_number : The GPIO Pin number to program the direction for 2687* pin_value : The value of the GPIO Pin under reference. 2688* 0 = set it to 0 2689* 1 = set it to 1 2690*/ 2691int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 2692{ 2693 int status = 0; 2694 u32 value = 0; 2695 2696 /* Check for valid pin_number - if 0xFF , bail out */ 2697 if (pin_number >= 32) 2698 return -EINVAL; 2699 2700 /* first do a sanity check - if the Pin is not output, make it output */ 2701 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 2702 /* It was in input mode */ 2703 value = dev->gpio_dir | (1 << pin_number); 2704 dev->gpio_dir = value; 2705 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2706 dev->gpio_val); 2707 } 2708 2709 if (pin_value == 0) 2710 value = dev->gpio_val & (~(1 << pin_number)); 2711 else 2712 value = dev->gpio_val | (1 << pin_number); 2713 2714 /* store the value */ 2715 dev->gpio_val = value; 2716 2717 /* toggle bit0 of GP_IO */ 2718 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2719 2720 return status; 2721} 2722 2723/***************************************************************************** 2724* G P I O I2C related functions * 2725******************************************************************************/ 2726int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2727{ 2728 int status = 0; 2729 2730 /* set SCL to output 1 ; set SDA to output 1 */ 2731 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2732 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2733 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2734 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2735 2736 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2737 if (status < 0) 2738 return -EINVAL; 2739 2740 /* set SCL to output 1; set SDA to output 0 */ 2741 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2742 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2743 2744 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2745 if (status < 0) 2746 return -EINVAL; 2747 2748 /* set SCL to output 0; set SDA to output 0 */ 2749 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2750 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2751 2752 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2753 if (status < 0) 2754 return -EINVAL; 2755 2756 return status; 2757} 2758 2759int cx231xx_gpio_i2c_end(struct cx231xx *dev) 2760{ 2761 int status = 0; 2762 2763 /* set SCL to output 0; set SDA to output 0 */ 2764 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2765 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2766 2767 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2768 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2769 2770 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2771 if (status < 0) 2772 return -EINVAL; 2773 2774 /* set SCL to output 1; set SDA to output 0 */ 2775 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2776 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2777 2778 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2779 if (status < 0) 2780 return -EINVAL; 2781 2782 /* set SCL to input ,release SCL cable control 2783 set SDA to input ,release SDA cable control */ 2784 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2785 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2786 2787 status = 2788 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2789 if (status < 0) 2790 return -EINVAL; 2791 2792 return status; 2793} 2794 2795int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 2796{ 2797 int status = 0; 2798 u8 i; 2799 2800 /* set SCL to output ; set SDA to output */ 2801 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2802 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2803 2804 for (i = 0; i < 8; i++) { 2805 if (((data << i) & 0x80) == 0) { 2806 /* set SCL to output 0; set SDA to output 0 */ 2807 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2808 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2809 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2810 dev->gpio_val); 2811 2812 /* set SCL to output 1; set SDA to output 0 */ 2813 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2814 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2815 dev->gpio_val); 2816 2817 /* set SCL to output 0; set SDA to output 0 */ 2818 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2819 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2820 dev->gpio_val); 2821 } else { 2822 /* set SCL to output 0; set SDA to output 1 */ 2823 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2824 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2825 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2826 dev->gpio_val); 2827 2828 /* set SCL to output 1; set SDA to output 1 */ 2829 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2830 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2831 dev->gpio_val); 2832 2833 /* set SCL to output 0; set SDA to output 1 */ 2834 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2835 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2836 dev->gpio_val); 2837 } 2838 } 2839 return status; 2840} 2841 2842int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 2843{ 2844 u8 value = 0; 2845 int status = 0; 2846 u32 gpio_logic_value = 0; 2847 u8 i; 2848 2849 /* read byte */ 2850 for (i = 0; i < 8; i++) { /* send write I2c addr */ 2851 2852 /* set SCL to output 0; set SDA to input */ 2853 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2854 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2855 dev->gpio_val); 2856 2857 /* set SCL to output 1; set SDA to input */ 2858 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2859 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2860 dev->gpio_val); 2861 2862 /* get SDA data bit */ 2863 gpio_logic_value = dev->gpio_val; 2864 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2865 &dev->gpio_val); 2866 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 2867 value |= (1 << (8 - i - 1)); 2868 2869 dev->gpio_val = gpio_logic_value; 2870 } 2871 2872 /* set SCL to output 0,finish the read latest SCL signal. 2873 !!!set SDA to input, never to modify SDA direction at 2874 the same times */ 2875 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2876 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2877 2878 /* store the value */ 2879 *buf = value & 0xff; 2880 2881 return status; 2882} 2883 2884int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 2885{ 2886 int status = 0; 2887 u32 gpio_logic_value = 0; 2888 int nCnt = 10; 2889 int nInit = nCnt; 2890 2891 /* clock stretch; set SCL to input; set SDA to input; 2892 get SCL value till SCL = 1 */ 2893 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2894 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2895 2896 gpio_logic_value = dev->gpio_val; 2897 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2898 2899 do { 2900 msleep(2); 2901 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2902 &dev->gpio_val); 2903 nCnt--; 2904 } while (((dev->gpio_val & 2905 (1 << dev->board.tuner_scl_gpio)) == 0) && 2906 (nCnt > 0)); 2907 2908 if (nCnt == 0) 2909 dev_dbg(dev->dev, 2910 "No ACK after %d msec -GPIO I2C failed!", 2911 nInit * 10); 2912 2913 /* 2914 * readAck 2915 * through clock stretch, slave has given a SCL signal, 2916 * so the SDA data can be directly read. 2917 */ 2918 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val); 2919 2920 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2921 dev->gpio_val = gpio_logic_value; 2922 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2923 status = 0; 2924 } else { 2925 dev->gpio_val = gpio_logic_value; 2926 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2927 } 2928 2929 /* read SDA end, set the SCL to output 0, after this operation, 2930 SDA direction can be changed. */ 2931 dev->gpio_val = gpio_logic_value; 2932 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2933 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2934 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2935 2936 return status; 2937} 2938 2939int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 2940{ 2941 int status = 0; 2942 2943 /* set SDA to output */ 2944 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2945 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2946 2947 /* set SCL = 0 (output); set SDA = 0 (output) */ 2948 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2949 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2950 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2951 2952 /* set SCL = 1 (output); set SDA = 0 (output) */ 2953 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2954 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2955 2956 /* set SCL = 0 (output); set SDA = 0 (output) */ 2957 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2958 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2959 2960 /* set SDA to input,and then the slave will read data from SDA. */ 2961 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2962 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2963 2964 return status; 2965} 2966 2967int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 2968{ 2969 int status = 0; 2970 2971 /* set scl to output ; set sda to input */ 2972 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2973 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2974 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2975 2976 /* set scl to output 0; set sda to input */ 2977 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2978 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2979 2980 /* set scl to output 1; set sda to input */ 2981 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2982 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2983 2984 return status; 2985} 2986 2987/***************************************************************************** 2988* G P I O I2C related functions * 2989******************************************************************************/ 2990/* cx231xx_gpio_i2c_read 2991 * Function to read data from gpio based I2C interface 2992 */ 2993int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 2994{ 2995 int status = 0; 2996 int i = 0; 2997 2998 /* get the lock */ 2999 mutex_lock(&dev->gpio_i2c_lock); 3000 3001 /* start */ 3002 status = cx231xx_gpio_i2c_start(dev); 3003 3004 /* write dev_addr */ 3005 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 3006 3007 /* readAck */ 3008 status = cx231xx_gpio_i2c_read_ack(dev); 3009 3010 /* read data */ 3011 for (i = 0; i < len; i++) { 3012 /* read data */ 3013 buf[i] = 0; 3014 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 3015 3016 if ((i + 1) != len) { 3017 /* only do write ack if we more length */ 3018 status = cx231xx_gpio_i2c_write_ack(dev); 3019 } 3020 } 3021 3022 /* write NAK - inform reads are complete */ 3023 status = cx231xx_gpio_i2c_write_nak(dev); 3024 3025 /* write end */ 3026 status = cx231xx_gpio_i2c_end(dev); 3027 3028 /* release the lock */ 3029 mutex_unlock(&dev->gpio_i2c_lock); 3030 3031 return status; 3032} 3033 3034/* cx231xx_gpio_i2c_write 3035 * Function to write data to gpio based I2C interface 3036 */ 3037int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3038{ 3039 int i = 0; 3040 3041 /* get the lock */ 3042 mutex_lock(&dev->gpio_i2c_lock); 3043 3044 /* start */ 3045 cx231xx_gpio_i2c_start(dev); 3046 3047 /* write dev_addr */ 3048 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 3049 3050 /* read Ack */ 3051 cx231xx_gpio_i2c_read_ack(dev); 3052 3053 for (i = 0; i < len; i++) { 3054 /* Write data */ 3055 cx231xx_gpio_i2c_write_byte(dev, buf[i]); 3056 3057 /* read Ack */ 3058 cx231xx_gpio_i2c_read_ack(dev); 3059 } 3060 3061 /* write End */ 3062 cx231xx_gpio_i2c_end(dev); 3063 3064 /* release the lock */ 3065 mutex_unlock(&dev->gpio_i2c_lock); 3066 3067 return 0; 3068}
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