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rockchip_vpu981_hw_av1_dec.c
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linux-6.19.14/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2023, Collabora 4 * 5 * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com> 6 */ 7 8#include <media/v4l2-mem2mem.h> 9#include "hantro.h" 10#include "hantro_v4l2.h" 11#include "rockchip_vpu981_regs.h" 12 13#define AV1_DEC_MODE 17 14#define GM_GLOBAL_MODELS_PER_FRAME 7 15#define GLOBAL_MODEL_TOTAL_SIZE (6 * 4 + 4 * 2) 16#define GLOBAL_MODEL_SIZE ALIGN(GM_GLOBAL_MODELS_PER_FRAME * GLOBAL_MODEL_TOTAL_SIZE, 2048) 17#define AV1_MAX_TILES 128 18#define AV1_TILE_INFO_SIZE (AV1_MAX_TILES * 16) 19#define AV1DEC_MAX_PIC_BUFFERS 24 20#define AV1_REF_SCALE_SHIFT 14 21#define AV1_INVALID_IDX -1 22#define MAX_FRAME_DISTANCE 31 23#define AV1_PRIMARY_REF_NONE 7 24#define AV1_TILE_SIZE ALIGN(32 * 128, 4096) 25/* 26 * These 3 values aren't defined enum v4l2_av1_segment_feature because 27 * they are not part of the specification 28 */ 29#define V4L2_AV1_SEG_LVL_ALT_LF_Y_H 2 30#define V4L2_AV1_SEG_LVL_ALT_LF_U 3 31#define V4L2_AV1_SEG_LVL_ALT_LF_V 4 32 33#define SUPERRES_SCALE_BITS 3 34#define SCALE_NUMERATOR 8 35#define SUPERRES_SCALE_DENOMINATOR_MIN (SCALE_NUMERATOR + 1) 36 37#define RS_SUBPEL_BITS 6 38#define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1) 39#define RS_SCALE_SUBPEL_BITS 14 40#define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1) 41#define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS) 42#define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1)) 43 44#define IS_INTRA(type) ((type == V4L2_AV1_KEY_FRAME) || (type == V4L2_AV1_INTRA_ONLY_FRAME)) 45 46#define LST_BUF_IDX (V4L2_AV1_REF_LAST_FRAME - V4L2_AV1_REF_LAST_FRAME) 47#define LST2_BUF_IDX (V4L2_AV1_REF_LAST2_FRAME - V4L2_AV1_REF_LAST_FRAME) 48#define LST3_BUF_IDX (V4L2_AV1_REF_LAST3_FRAME - V4L2_AV1_REF_LAST_FRAME) 49#define GLD_BUF_IDX (V4L2_AV1_REF_GOLDEN_FRAME - V4L2_AV1_REF_LAST_FRAME) 50#define BWD_BUF_IDX (V4L2_AV1_REF_BWDREF_FRAME - V4L2_AV1_REF_LAST_FRAME) 51#define ALT2_BUF_IDX (V4L2_AV1_REF_ALTREF2_FRAME - V4L2_AV1_REF_LAST_FRAME) 52#define ALT_BUF_IDX (V4L2_AV1_REF_ALTREF_FRAME - V4L2_AV1_REF_LAST_FRAME) 53 54#define DIV_LUT_PREC_BITS 14 55#define DIV_LUT_BITS 8 56#define DIV_LUT_NUM BIT(DIV_LUT_BITS) 57#define WARP_PARAM_REDUCE_BITS 6 58#define WARPEDMODEL_PREC_BITS 16 59 60#define AV1_DIV_ROUND_UP_POW2(value, n) \ 61({ \ 62 typeof(n) _n = n; \ 63 typeof(value) _value = value; \ 64 (_value + (BIT(_n) >> 1)) >> _n; \ 65}) 66 67#define AV1_DIV_ROUND_UP_POW2_SIGNED(value, n) \ 68({ \ 69 typeof(n) _n_ = n; \ 70 typeof(value) _value_ = value; \ 71 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \ 72 : AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \ 73}) 74 75enum rockchip_av1_tx_mode { 76 ROCKCHIP_AV1_TX_MODE_ONLY_4X4 = 0, 77 ROCKCHIP_AV1_TX_MODE_8X8 = 1, 78 ROCKCHIP_AV1_TX_MODE_16x16 = 2, 79 ROCKCHIP_AV1_TX_MODE_32x32 = 3, 80 ROCKCHIP_AV1_TX_MODE_SELECT = 4, 81}; 82 83struct rockchip_av1_film_grain { 84 u8 scaling_lut_y[256]; 85 u8 scaling_lut_cb[256]; 86 u8 scaling_lut_cr[256]; 87 s16 cropped_luma_grain_block[4096]; 88 s16 cropped_chroma_grain_block[1024 * 2]; 89}; 90 91static const short div_lut[DIV_LUT_NUM + 1] = { 92 16384, 16320, 16257, 16194, 16132, 16070, 16009, 15948, 15888, 15828, 15768, 93 15709, 15650, 15592, 15534, 15477, 15420, 15364, 15308, 15252, 15197, 15142, 94 15087, 15033, 14980, 14926, 14873, 14821, 14769, 14717, 14665, 14614, 14564, 95 14513, 14463, 14413, 14364, 14315, 14266, 14218, 14170, 14122, 14075, 14028, 96 13981, 13935, 13888, 13843, 13797, 13752, 13707, 13662, 13618, 13574, 13530, 97 13487, 13443, 13400, 13358, 13315, 13273, 13231, 13190, 13148, 13107, 13066, 98 13026, 12985, 12945, 12906, 12866, 12827, 12788, 12749, 12710, 12672, 12633, 99 12596, 12558, 12520, 12483, 12446, 12409, 12373, 12336, 12300, 12264, 12228, 100 12193, 12157, 12122, 12087, 12053, 12018, 11984, 11950, 11916, 11882, 11848, 101 11815, 11782, 11749, 11716, 11683, 11651, 11619, 11586, 11555, 11523, 11491, 102 11460, 11429, 11398, 11367, 11336, 11305, 11275, 11245, 11215, 11185, 11155, 103 11125, 11096, 11067, 11038, 11009, 10980, 10951, 10923, 10894, 10866, 10838, 104 10810, 10782, 10755, 10727, 10700, 10673, 10645, 10618, 10592, 10565, 10538, 105 10512, 10486, 10460, 10434, 10408, 10382, 10356, 10331, 10305, 10280, 10255, 106 10230, 10205, 10180, 10156, 10131, 10107, 10082, 10058, 10034, 10010, 9986, 107 9963, 9939, 9916, 9892, 9869, 9846, 9823, 9800, 9777, 9754, 9732, 108 9709, 9687, 9664, 9642, 9620, 9598, 9576, 9554, 9533, 9511, 9489, 109 9468, 9447, 9425, 9404, 9383, 9362, 9341, 9321, 9300, 9279, 9259, 110 9239, 9218, 9198, 9178, 9158, 9138, 9118, 9098, 9079, 9059, 9039, 111 9020, 9001, 8981, 8962, 8943, 8924, 8905, 8886, 8867, 8849, 8830, 112 8812, 8793, 8775, 8756, 8738, 8720, 8702, 8684, 8666, 8648, 8630, 113 8613, 8595, 8577, 8560, 8542, 8525, 8508, 8490, 8473, 8456, 8439, 114 8422, 8405, 8389, 8372, 8355, 8339, 8322, 8306, 8289, 8273, 8257, 115 8240, 8224, 8208, 8192, 116}; 117 118static int rockchip_vpu981_get_frame_index(struct hantro_ctx *ctx, int ref) 119{ 120 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 121 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 122 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 123 u64 timestamp; 124 int i, idx = frame->ref_frame_idx[ref]; 125 126 if (idx >= V4L2_AV1_TOTAL_REFS_PER_FRAME || idx < 0) 127 return AV1_INVALID_IDX; 128 129 timestamp = frame->reference_frame_ts[idx]; 130 for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { 131 if (!av1_dec->frame_refs[i].used) 132 continue; 133 if (av1_dec->frame_refs[i].timestamp == timestamp) 134 return i; 135 } 136 137 return AV1_INVALID_IDX; 138} 139 140static int rockchip_vpu981_get_order_hint(struct hantro_ctx *ctx, int ref) 141{ 142 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 143 int idx = rockchip_vpu981_get_frame_index(ctx, ref); 144 145 if (idx != AV1_INVALID_IDX) 146 return av1_dec->frame_refs[idx].order_hint; 147 148 return 0; 149} 150 151static int rockchip_vpu981_av1_dec_frame_ref(struct hantro_ctx *ctx, 152 u64 timestamp) 153{ 154 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 155 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 156 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 157 int i; 158 159 for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { 160 int j; 161 162 if (av1_dec->frame_refs[i].used) 163 continue; 164 165 av1_dec->frame_refs[i].width = frame->frame_width_minus_1 + 1; 166 av1_dec->frame_refs[i].height = frame->frame_height_minus_1 + 1; 167 av1_dec->frame_refs[i].mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); 168 av1_dec->frame_refs[i].mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); 169 av1_dec->frame_refs[i].timestamp = timestamp; 170 av1_dec->frame_refs[i].frame_type = frame->frame_type; 171 av1_dec->frame_refs[i].order_hint = frame->order_hint; 172 av1_dec->frame_refs[i].vb2_ref = hantro_get_dst_buf(ctx); 173 174 for (j = 0; j < V4L2_AV1_TOTAL_REFS_PER_FRAME; j++) 175 av1_dec->frame_refs[i].order_hints[j] = frame->order_hints[j]; 176 av1_dec->frame_refs[i].used = true; 177 av1_dec->current_frame_index = i; 178 179 return i; 180 } 181 182 return AV1_INVALID_IDX; 183} 184 185static void rockchip_vpu981_av1_dec_frame_unref(struct hantro_ctx *ctx, int idx) 186{ 187 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 188 189 if (idx >= 0) 190 av1_dec->frame_refs[idx].used = false; 191} 192 193static void rockchip_vpu981_av1_dec_clean_refs(struct hantro_ctx *ctx) 194{ 195 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 196 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 197 198 int ref, idx; 199 200 for (idx = 0; idx < AV1_MAX_FRAME_BUF_COUNT; idx++) { 201 u64 timestamp = av1_dec->frame_refs[idx].timestamp; 202 bool used = false; 203 204 if (!av1_dec->frame_refs[idx].used) 205 continue; 206 207 for (ref = 0; ref < V4L2_AV1_TOTAL_REFS_PER_FRAME; ref++) { 208 if (ctrls->frame->reference_frame_ts[ref] == timestamp) 209 used = true; 210 } 211 212 if (!used) 213 rockchip_vpu981_av1_dec_frame_unref(ctx, idx); 214 } 215} 216 217static size_t rockchip_vpu981_av1_dec_luma_size(struct hantro_ctx *ctx) 218{ 219 return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8; 220} 221 222static size_t rockchip_vpu981_av1_dec_chroma_size(struct hantro_ctx *ctx) 223{ 224 size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx); 225 226 return ALIGN((cr_offset * 3) / 2, 64); 227} 228 229static void rockchip_vpu981_av1_dec_tiles_free(struct hantro_ctx *ctx) 230{ 231 struct hantro_dev *vpu = ctx->dev; 232 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 233 234 if (av1_dec->db_data_col.cpu) 235 dma_free_coherent(vpu->dev, av1_dec->db_data_col.size, 236 av1_dec->db_data_col.cpu, 237 av1_dec->db_data_col.dma); 238 av1_dec->db_data_col.cpu = NULL; 239 240 if (av1_dec->db_ctrl_col.cpu) 241 dma_free_coherent(vpu->dev, av1_dec->db_ctrl_col.size, 242 av1_dec->db_ctrl_col.cpu, 243 av1_dec->db_ctrl_col.dma); 244 av1_dec->db_ctrl_col.cpu = NULL; 245 246 if (av1_dec->cdef_col.cpu) 247 dma_free_coherent(vpu->dev, av1_dec->cdef_col.size, 248 av1_dec->cdef_col.cpu, av1_dec->cdef_col.dma); 249 av1_dec->cdef_col.cpu = NULL; 250 251 if (av1_dec->sr_col.cpu) 252 dma_free_coherent(vpu->dev, av1_dec->sr_col.size, 253 av1_dec->sr_col.cpu, av1_dec->sr_col.dma); 254 av1_dec->sr_col.cpu = NULL; 255 256 if (av1_dec->lr_col.cpu) 257 dma_free_coherent(vpu->dev, av1_dec->lr_col.size, 258 av1_dec->lr_col.cpu, av1_dec->lr_col.dma); 259 av1_dec->lr_col.cpu = NULL; 260} 261 262static int rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx *ctx) 263{ 264 struct hantro_dev *vpu = ctx->dev; 265 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 266 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 267 const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info; 268 unsigned int num_tile_cols = tile_info->tile_cols; 269 unsigned int height = ALIGN(ctrls->frame->frame_height_minus_1 + 1, 64); 270 unsigned int height_in_sb = height / 64; 271 unsigned int stripe_num = ((height + 8) + 63) / 64; 272 size_t size; 273 274 if (av1_dec->db_data_col.size >= 275 ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols) 276 return 0; 277 278 rockchip_vpu981_av1_dec_tiles_free(ctx); 279 280 size = ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols; 281 av1_dec->db_data_col.cpu = dma_alloc_coherent(vpu->dev, size, 282 &av1_dec->db_data_col.dma, 283 GFP_KERNEL); 284 if (!av1_dec->db_data_col.cpu) 285 goto buffer_allocation_error; 286 av1_dec->db_data_col.size = size; 287 288 size = ALIGN(height * 2 * 16 / 4, 128) * num_tile_cols; 289 av1_dec->db_ctrl_col.cpu = dma_alloc_coherent(vpu->dev, size, 290 &av1_dec->db_ctrl_col.dma, 291 GFP_KERNEL); 292 if (!av1_dec->db_ctrl_col.cpu) 293 goto buffer_allocation_error; 294 av1_dec->db_ctrl_col.size = size; 295 296 size = ALIGN(height_in_sb * 44 * ctx->bit_depth * 16 / 8, 128) * num_tile_cols; 297 av1_dec->cdef_col.cpu = dma_alloc_coherent(vpu->dev, size, 298 &av1_dec->cdef_col.dma, 299 GFP_KERNEL); 300 if (!av1_dec->cdef_col.cpu) 301 goto buffer_allocation_error; 302 av1_dec->cdef_col.size = size; 303 304 size = ALIGN(height_in_sb * (3040 + 1280), 128) * num_tile_cols; 305 av1_dec->sr_col.cpu = dma_alloc_coherent(vpu->dev, size, 306 &av1_dec->sr_col.dma, 307 GFP_KERNEL); 308 if (!av1_dec->sr_col.cpu) 309 goto buffer_allocation_error; 310 av1_dec->sr_col.size = size; 311 312 size = ALIGN(stripe_num * 1536 * ctx->bit_depth / 8, 128) * num_tile_cols; 313 av1_dec->lr_col.cpu = dma_alloc_coherent(vpu->dev, size, 314 &av1_dec->lr_col.dma, 315 GFP_KERNEL); 316 if (!av1_dec->lr_col.cpu) 317 goto buffer_allocation_error; 318 av1_dec->lr_col.size = size; 319 320 av1_dec->num_tile_cols_allocated = num_tile_cols; 321 return 0; 322 323buffer_allocation_error: 324 rockchip_vpu981_av1_dec_tiles_free(ctx); 325 return -ENOMEM; 326} 327 328void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx) 329{ 330 struct hantro_dev *vpu = ctx->dev; 331 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 332 333 if (av1_dec->global_model.cpu) 334 dma_free_coherent(vpu->dev, av1_dec->global_model.size, 335 av1_dec->global_model.cpu, 336 av1_dec->global_model.dma); 337 av1_dec->global_model.cpu = NULL; 338 339 if (av1_dec->tile_info.cpu) 340 dma_free_coherent(vpu->dev, av1_dec->tile_info.size, 341 av1_dec->tile_info.cpu, 342 av1_dec->tile_info.dma); 343 av1_dec->tile_info.cpu = NULL; 344 345 if (av1_dec->film_grain.cpu) 346 dma_free_coherent(vpu->dev, av1_dec->film_grain.size, 347 av1_dec->film_grain.cpu, 348 av1_dec->film_grain.dma); 349 av1_dec->film_grain.cpu = NULL; 350 351 if (av1_dec->prob_tbl.cpu) 352 dma_free_coherent(vpu->dev, av1_dec->prob_tbl.size, 353 av1_dec->prob_tbl.cpu, av1_dec->prob_tbl.dma); 354 av1_dec->prob_tbl.cpu = NULL; 355 356 if (av1_dec->prob_tbl_out.cpu) 357 dma_free_coherent(vpu->dev, av1_dec->prob_tbl_out.size, 358 av1_dec->prob_tbl_out.cpu, 359 av1_dec->prob_tbl_out.dma); 360 av1_dec->prob_tbl_out.cpu = NULL; 361 362 if (av1_dec->tile_buf.cpu) 363 dma_free_coherent(vpu->dev, av1_dec->tile_buf.size, 364 av1_dec->tile_buf.cpu, av1_dec->tile_buf.dma); 365 av1_dec->tile_buf.cpu = NULL; 366 367 rockchip_vpu981_av1_dec_tiles_free(ctx); 368} 369 370int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx) 371{ 372 struct hantro_dev *vpu = ctx->dev; 373 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 374 375 memset(av1_dec, 0, sizeof(*av1_dec)); 376 377 av1_dec->global_model.cpu = dma_alloc_coherent(vpu->dev, GLOBAL_MODEL_SIZE, 378 &av1_dec->global_model.dma, 379 GFP_KERNEL); 380 if (!av1_dec->global_model.cpu) 381 return -ENOMEM; 382 av1_dec->global_model.size = GLOBAL_MODEL_SIZE; 383 384 av1_dec->tile_info.cpu = dma_alloc_coherent(vpu->dev, AV1_TILE_INFO_SIZE, 385 &av1_dec->tile_info.dma, 386 GFP_KERNEL); 387 if (!av1_dec->tile_info.cpu) 388 return -ENOMEM; 389 av1_dec->tile_info.size = AV1_TILE_INFO_SIZE; 390 391 av1_dec->film_grain.cpu = dma_alloc_coherent(vpu->dev, 392 ALIGN(sizeof(struct rockchip_av1_film_grain), 2048), 393 &av1_dec->film_grain.dma, 394 GFP_KERNEL); 395 if (!av1_dec->film_grain.cpu) 396 return -ENOMEM; 397 av1_dec->film_grain.size = ALIGN(sizeof(struct rockchip_av1_film_grain), 2048); 398 399 av1_dec->prob_tbl.cpu = dma_alloc_coherent(vpu->dev, 400 ALIGN(sizeof(struct av1cdfs), 2048), 401 &av1_dec->prob_tbl.dma, 402 GFP_KERNEL); 403 if (!av1_dec->prob_tbl.cpu) 404 return -ENOMEM; 405 av1_dec->prob_tbl.size = ALIGN(sizeof(struct av1cdfs), 2048); 406 407 av1_dec->prob_tbl_out.cpu = dma_alloc_coherent(vpu->dev, 408 ALIGN(sizeof(struct av1cdfs), 2048), 409 &av1_dec->prob_tbl_out.dma, 410 GFP_KERNEL); 411 if (!av1_dec->prob_tbl_out.cpu) 412 return -ENOMEM; 413 av1_dec->prob_tbl_out.size = ALIGN(sizeof(struct av1cdfs), 2048); 414 av1_dec->cdfs = &av1_dec->default_cdfs; 415 av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc; 416 417 rockchip_av1_set_default_cdfs(av1_dec->cdfs, av1_dec->cdfs_ndvc); 418 419 av1_dec->tile_buf.cpu = dma_alloc_coherent(vpu->dev, 420 AV1_TILE_SIZE, 421 &av1_dec->tile_buf.dma, 422 GFP_KERNEL); 423 if (!av1_dec->tile_buf.cpu) 424 return -ENOMEM; 425 av1_dec->tile_buf.size = AV1_TILE_SIZE; 426 427 return 0; 428} 429 430static int rockchip_vpu981_av1_dec_prepare_run(struct hantro_ctx *ctx) 431{ 432 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 433 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 434 435 ctrls->sequence = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_SEQUENCE); 436 if (WARN_ON(!ctrls->sequence)) 437 return -EINVAL; 438 439 ctrls->tile_group_entry = 440 hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY); 441 if (WARN_ON(!ctrls->tile_group_entry)) 442 return -EINVAL; 443 444 ctrls->frame = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FRAME); 445 if (WARN_ON(!ctrls->frame)) 446 return -EINVAL; 447 448 ctrls->film_grain = 449 hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FILM_GRAIN); 450 451 return rockchip_vpu981_av1_dec_tiles_reallocate(ctx); 452} 453 454static inline int rockchip_vpu981_av1_dec_get_msb(u32 n) 455{ 456 if (n == 0) 457 return 0; 458 return 31 ^ __builtin_clz(n); 459} 460 461static short rockchip_vpu981_av1_dec_resolve_divisor_32(u32 d, short *shift) 462{ 463 int f; 464 u64 e; 465 466 *shift = rockchip_vpu981_av1_dec_get_msb(d); 467 /* e is obtained from D after resetting the most significant 1 bit. */ 468 e = d - ((u32)1 << *shift); 469 /* Get the most significant DIV_LUT_BITS (8) bits of e into f */ 470 if (*shift > DIV_LUT_BITS) 471 f = AV1_DIV_ROUND_UP_POW2(e, *shift - DIV_LUT_BITS); 472 else 473 f = e << (DIV_LUT_BITS - *shift); 474 if (f > DIV_LUT_NUM) 475 return -1; 476 *shift += DIV_LUT_PREC_BITS; 477 /* Use f as lookup into the precomputed table of multipliers */ 478 return div_lut[f]; 479} 480 481static void 482rockchip_vpu981_av1_dec_get_shear_params(const u32 *params, s64 *alpha, 483 s64 *beta, s64 *gamma, s64 *delta) 484{ 485 const int *mat = params; 486 short shift; 487 short y; 488 long long gv, dv; 489 490 if (mat[2] <= 0) 491 return; 492 493 *alpha = clamp_val(mat[2] - (1 << WARPEDMODEL_PREC_BITS), S16_MIN, S16_MAX); 494 *beta = clamp_val(mat[3], S16_MIN, S16_MAX); 495 496 y = rockchip_vpu981_av1_dec_resolve_divisor_32(abs(mat[2]), &shift) * (mat[2] < 0 ? -1 : 1); 497 498 gv = ((long long)mat[4] * (1 << WARPEDMODEL_PREC_BITS)) * y; 499 500 *gamma = clamp_val((int)AV1_DIV_ROUND_UP_POW2_SIGNED(gv, shift), S16_MIN, S16_MAX); 501 502 dv = ((long long)mat[3] * mat[4]) * y; 503 *delta = clamp_val(mat[5] - 504 (int)AV1_DIV_ROUND_UP_POW2_SIGNED(dv, shift) - (1 << WARPEDMODEL_PREC_BITS), 505 S16_MIN, S16_MAX); 506 507 *alpha = AV1_DIV_ROUND_UP_POW2_SIGNED(*alpha, WARP_PARAM_REDUCE_BITS) 508 * (1 << WARP_PARAM_REDUCE_BITS); 509 *beta = AV1_DIV_ROUND_UP_POW2_SIGNED(*beta, WARP_PARAM_REDUCE_BITS) 510 * (1 << WARP_PARAM_REDUCE_BITS); 511 *gamma = AV1_DIV_ROUND_UP_POW2_SIGNED(*gamma, WARP_PARAM_REDUCE_BITS) 512 * (1 << WARP_PARAM_REDUCE_BITS); 513 *delta = AV1_DIV_ROUND_UP_POW2_SIGNED(*delta, WARP_PARAM_REDUCE_BITS) 514 * (1 << WARP_PARAM_REDUCE_BITS); 515} 516 517static void rockchip_vpu981_av1_dec_set_global_model(struct hantro_ctx *ctx) 518{ 519 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 520 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 521 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 522 const struct v4l2_av1_global_motion *gm = &frame->global_motion; 523 u8 *dst = av1_dec->global_model.cpu; 524 struct hantro_dev *vpu = ctx->dev; 525 int ref_frame, i; 526 527 memset(dst, 0, GLOBAL_MODEL_SIZE); 528 for (ref_frame = 0; ref_frame < V4L2_AV1_REFS_PER_FRAME; ++ref_frame) { 529 s64 alpha = 0, beta = 0, gamma = 0, delta = 0; 530 531 for (i = 0; i < 6; ++i) { 532 if (i == 2) 533 *(s32 *)dst = 534 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][3]; 535 else if (i == 3) 536 *(s32 *)dst = 537 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][2]; 538 else 539 *(s32 *)dst = 540 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][i]; 541 dst += 4; 542 } 543 544 if (gm->type[V4L2_AV1_REF_LAST_FRAME + ref_frame] <= V4L2_AV1_WARP_MODEL_AFFINE) 545 rockchip_vpu981_av1_dec_get_shear_params(&gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][0], 546 &alpha, &beta, &gamma, &delta); 547 548 *(s16 *)dst = alpha; 549 dst += 2; 550 *(s16 *)dst = beta; 551 dst += 2; 552 *(s16 *)dst = gamma; 553 dst += 2; 554 *(s16 *)dst = delta; 555 dst += 2; 556 } 557 558 hantro_write_addr(vpu, AV1_GLOBAL_MODEL, av1_dec->global_model.dma); 559} 560 561static int rockchip_vpu981_av1_tile_log2(int target) 562{ 563 int k; 564 565 /* 566 * returns the smallest value for k such that 1 << k is greater 567 * than or equal to target 568 */ 569 for (k = 0; (1 << k) < target; k++); 570 571 return k; 572} 573 574static void rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx *ctx) 575{ 576 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 577 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 578 const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info; 579 const struct v4l2_ctrl_av1_tile_group_entry *group_entry = 580 ctrls->tile_group_entry; 581 int context_update_y = 582 tile_info->context_update_tile_id / tile_info->tile_cols; 583 int context_update_x = 584 tile_info->context_update_tile_id % tile_info->tile_cols; 585 int context_update_tile_id = 586 context_update_x * tile_info->tile_rows + context_update_y; 587 u8 *dst = av1_dec->tile_info.cpu; 588 struct hantro_dev *vpu = ctx->dev; 589 int tile0, tile1; 590 591 memset(dst, 0, av1_dec->tile_info.size); 592 593 for (tile0 = 0; tile0 < tile_info->tile_cols; tile0++) { 594 for (tile1 = 0; tile1 < tile_info->tile_rows; tile1++) { 595 int tile_id = tile1 * tile_info->tile_cols + tile0; 596 u32 start, end; 597 u32 y0 = 598 tile_info->height_in_sbs_minus_1[tile1] + 1; 599 u32 x0 = tile_info->width_in_sbs_minus_1[tile0] + 1; 600 601 /* tile size in SB units (width,height) */ 602 *dst++ = x0; 603 *dst++ = 0; 604 *dst++ = 0; 605 *dst++ = 0; 606 *dst++ = y0; 607 *dst++ = 0; 608 *dst++ = 0; 609 *dst++ = 0; 610 611 /* tile start position */ 612 start = group_entry[tile_id].tile_offset - group_entry[0].tile_offset; 613 *dst++ = start & 255; 614 *dst++ = (start >> 8) & 255; 615 *dst++ = (start >> 16) & 255; 616 *dst++ = (start >> 24) & 255; 617 618 /* number of bytes in tile data */ 619 end = start + group_entry[tile_id].tile_size; 620 *dst++ = end & 255; 621 *dst++ = (end >> 8) & 255; 622 *dst++ = (end >> 16) & 255; 623 *dst++ = (end >> 24) & 255; 624 } 625 } 626 627 hantro_reg_write(vpu, &av1_multicore_expect_context_update, !!(context_update_x == 0)); 628 hantro_reg_write(vpu, &av1_tile_enable, 629 !!((tile_info->tile_cols > 1) || (tile_info->tile_rows > 1))); 630 hantro_reg_write(vpu, &av1_num_tile_cols_8k, tile_info->tile_cols); 631 hantro_reg_write(vpu, &av1_num_tile_rows_8k, tile_info->tile_rows); 632 hantro_reg_write(vpu, &av1_context_update_tile_id, context_update_tile_id); 633 hantro_reg_write(vpu, &av1_tile_transpose, 1); 634 if (rockchip_vpu981_av1_tile_log2(tile_info->tile_cols) || 635 rockchip_vpu981_av1_tile_log2(tile_info->tile_rows)) 636 hantro_reg_write(vpu, &av1_dec_tile_size_mag, tile_info->tile_size_bytes - 1); 637 else 638 hantro_reg_write(vpu, &av1_dec_tile_size_mag, 3); 639 640 hantro_write_addr(vpu, AV1_TILE_BASE, av1_dec->tile_info.dma); 641} 642 643static int rockchip_vpu981_av1_dec_get_dist(struct hantro_ctx *ctx, 644 int a, int b) 645{ 646 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 647 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 648 int bits = ctrls->sequence->order_hint_bits - 1; 649 int diff, m; 650 651 if (!ctrls->sequence->order_hint_bits) 652 return 0; 653 654 diff = a - b; 655 m = 1 << bits; 656 diff = (diff & (m - 1)) - (diff & m); 657 658 return diff; 659} 660 661static void rockchip_vpu981_av1_dec_set_frame_sign_bias(struct hantro_ctx *ctx) 662{ 663 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 664 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 665 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 666 const struct v4l2_ctrl_av1_sequence *sequence = ctrls->sequence; 667 int i; 668 669 if (!sequence->order_hint_bits || IS_INTRA(frame->frame_type)) { 670 for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) 671 av1_dec->ref_frame_sign_bias[i] = 0; 672 673 return; 674 } 675 // Identify the nearest forward and backward references. 676 for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; i++) { 677 if (rockchip_vpu981_get_frame_index(ctx, i) >= 0) { 678 int rel_off = 679 rockchip_vpu981_av1_dec_get_dist(ctx, 680 rockchip_vpu981_get_order_hint(ctx, i), 681 frame->order_hint); 682 av1_dec->ref_frame_sign_bias[i + 1] = (rel_off <= 0) ? 0 : 1; 683 } 684 } 685} 686 687static bool 688rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx, 689 int width, int height) 690{ 691 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 692 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 693 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 694 struct hantro_dev *vpu = ctx->dev; 695 struct hantro_decoded_buffer *dst; 696 dma_addr_t luma_addr, chroma_addr, mv_addr = 0; 697 int cur_width = frame->frame_width_minus_1 + 1; 698 int cur_height = frame->frame_height_minus_1 + 1; 699 int scale_width = 700 ((width << AV1_REF_SCALE_SHIFT) + cur_width / 2) / cur_width; 701 int scale_height = 702 ((height << AV1_REF_SCALE_SHIFT) + cur_height / 2) / cur_height; 703 704 switch (ref) { 705 case 0: 706 hantro_reg_write(vpu, &av1_ref0_height, height); 707 hantro_reg_write(vpu, &av1_ref0_width, width); 708 hantro_reg_write(vpu, &av1_ref0_ver_scale, scale_width); 709 hantro_reg_write(vpu, &av1_ref0_hor_scale, scale_height); 710 break; 711 case 1: 712 hantro_reg_write(vpu, &av1_ref1_height, height); 713 hantro_reg_write(vpu, &av1_ref1_width, width); 714 hantro_reg_write(vpu, &av1_ref1_ver_scale, scale_width); 715 hantro_reg_write(vpu, &av1_ref1_hor_scale, scale_height); 716 break; 717 case 2: 718 hantro_reg_write(vpu, &av1_ref2_height, height); 719 hantro_reg_write(vpu, &av1_ref2_width, width); 720 hantro_reg_write(vpu, &av1_ref2_ver_scale, scale_width); 721 hantro_reg_write(vpu, &av1_ref2_hor_scale, scale_height); 722 break; 723 case 3: 724 hantro_reg_write(vpu, &av1_ref3_height, height); 725 hantro_reg_write(vpu, &av1_ref3_width, width); 726 hantro_reg_write(vpu, &av1_ref3_ver_scale, scale_width); 727 hantro_reg_write(vpu, &av1_ref3_hor_scale, scale_height); 728 break; 729 case 4: 730 hantro_reg_write(vpu, &av1_ref4_height, height); 731 hantro_reg_write(vpu, &av1_ref4_width, width); 732 hantro_reg_write(vpu, &av1_ref4_ver_scale, scale_width); 733 hantro_reg_write(vpu, &av1_ref4_hor_scale, scale_height); 734 break; 735 case 5: 736 hantro_reg_write(vpu, &av1_ref5_height, height); 737 hantro_reg_write(vpu, &av1_ref5_width, width); 738 hantro_reg_write(vpu, &av1_ref5_ver_scale, scale_width); 739 hantro_reg_write(vpu, &av1_ref5_hor_scale, scale_height); 740 break; 741 case 6: 742 hantro_reg_write(vpu, &av1_ref6_height, height); 743 hantro_reg_write(vpu, &av1_ref6_width, width); 744 hantro_reg_write(vpu, &av1_ref6_ver_scale, scale_width); 745 hantro_reg_write(vpu, &av1_ref6_hor_scale, scale_height); 746 break; 747 default: 748 pr_warn("AV1 invalid reference frame index\n"); 749 } 750 751 dst = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf); 752 luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); 753 chroma_addr = luma_addr + dst->av1.chroma_offset; 754 mv_addr = luma_addr + dst->av1.mv_offset; 755 756 hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr); 757 hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr); 758 hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), mv_addr); 759 760 return (scale_width != (1 << AV1_REF_SCALE_SHIFT)) || 761 (scale_height != (1 << AV1_REF_SCALE_SHIFT)); 762} 763 764static void rockchip_vpu981_av1_dec_set_sign_bias(struct hantro_ctx *ctx, 765 int ref, int val) 766{ 767 struct hantro_dev *vpu = ctx->dev; 768 769 switch (ref) { 770 case 0: 771 hantro_reg_write(vpu, &av1_ref0_sign_bias, val); 772 break; 773 case 1: 774 hantro_reg_write(vpu, &av1_ref1_sign_bias, val); 775 break; 776 case 2: 777 hantro_reg_write(vpu, &av1_ref2_sign_bias, val); 778 break; 779 case 3: 780 hantro_reg_write(vpu, &av1_ref3_sign_bias, val); 781 break; 782 case 4: 783 hantro_reg_write(vpu, &av1_ref4_sign_bias, val); 784 break; 785 case 5: 786 hantro_reg_write(vpu, &av1_ref5_sign_bias, val); 787 break; 788 case 6: 789 hantro_reg_write(vpu, &av1_ref6_sign_bias, val); 790 break; 791 default: 792 pr_warn("AV1 invalid sign bias index\n"); 793 break; 794 } 795} 796 797static void rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx *ctx) 798{ 799 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 800 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 801 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 802 const struct v4l2_av1_segmentation *seg = &frame->segmentation; 803 u32 segval[V4L2_AV1_MAX_SEGMENTS][V4L2_AV1_SEG_LVL_MAX] = { 0 }; 804 struct hantro_dev *vpu = ctx->dev; 805 u8 segsign = 0, preskip_segid = 0, last_active_seg = 0, i, j; 806 807 if (!!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) && 808 frame->primary_ref_frame < V4L2_AV1_REFS_PER_FRAME) { 809 int idx = rockchip_vpu981_get_frame_index(ctx, frame->primary_ref_frame); 810 811 if (idx >= 0) { 812 dma_addr_t luma_addr, mv_addr = 0; 813 struct hantro_decoded_buffer *seg; 814 size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx); 815 816 seg = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf); 817 luma_addr = hantro_get_dec_buf_addr(ctx, &seg->base.vb.vb2_buf); 818 mv_addr = luma_addr + mv_offset; 819 820 hantro_write_addr(vpu, AV1_SEGMENTATION, mv_addr); 821 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 1); 822 } 823 } 824 825 hantro_reg_write(vpu, &av1_segment_temp_upd_e, 826 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_TEMPORAL_UPDATE)); 827 hantro_reg_write(vpu, &av1_segment_upd_e, 828 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_UPDATE_MAP)); 829 hantro_reg_write(vpu, &av1_segment_e, 830 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED)); 831 832 hantro_reg_write(vpu, &av1_error_resilient, 833 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE)); 834 835 if (IS_INTRA(frame->frame_type) || 836 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE)) { 837 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0); 838 } 839 840 if (seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) { 841 int s; 842 843 for (s = 0; s < V4L2_AV1_MAX_SEGMENTS; s++) { 844 if (seg->feature_enabled[s] & 845 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) { 846 segval[s][V4L2_AV1_SEG_LVL_ALT_Q] = 847 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q]), 848 0, 255); 849 segsign |= 850 (seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q] < 0) << s; 851 } 852 853 if (seg->feature_enabled[s] & 854 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_V)) 855 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V] = 856 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]), 857 -63, 63); 858 859 if (seg->feature_enabled[s] & 860 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_H)) 861 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H] = 862 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]), 863 -63, 63); 864 865 if (seg->feature_enabled[s] & 866 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_U)) 867 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_U] = 868 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_U]), 869 -63, 63); 870 871 if (seg->feature_enabled[s] & 872 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_V)) 873 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_V] = 874 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_V]), 875 -63, 63); 876 877 if (frame->frame_type && seg->feature_enabled[s] & 878 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_FRAME)) 879 segval[s][V4L2_AV1_SEG_LVL_REF_FRAME]++; 880 881 if (seg->feature_enabled[s] & 882 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_SKIP)) 883 segval[s][V4L2_AV1_SEG_LVL_REF_SKIP] = 1; 884 885 if (seg->feature_enabled[s] & 886 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_GLOBALMV)) 887 segval[s][V4L2_AV1_SEG_LVL_REF_GLOBALMV] = 1; 888 } 889 } 890 891 for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { 892 for (j = 0; j < V4L2_AV1_SEG_LVL_MAX; j++) { 893 if (seg->feature_enabled[i] 894 & V4L2_AV1_SEGMENT_FEATURE_ENABLED(j)) { 895 preskip_segid |= (j >= V4L2_AV1_SEG_LVL_REF_FRAME); 896 last_active_seg = max(i, last_active_seg); 897 } 898 } 899 } 900 901 hantro_reg_write(vpu, &av1_last_active_seg, last_active_seg); 902 hantro_reg_write(vpu, &av1_preskip_segid, preskip_segid); 903 904 hantro_reg_write(vpu, &av1_seg_quant_sign, segsign); 905 906 /* Write QP, filter level, ref frame and skip for every segment */ 907 hantro_reg_write(vpu, &av1_quant_seg0, 908 segval[0][V4L2_AV1_SEG_LVL_ALT_Q]); 909 hantro_reg_write(vpu, &av1_filt_level_delta0_seg0, 910 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 911 hantro_reg_write(vpu, &av1_filt_level_delta1_seg0, 912 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 913 hantro_reg_write(vpu, &av1_filt_level_delta2_seg0, 914 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_U]); 915 hantro_reg_write(vpu, &av1_filt_level_delta3_seg0, 916 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_V]); 917 hantro_reg_write(vpu, &av1_refpic_seg0, 918 segval[0][V4L2_AV1_SEG_LVL_REF_FRAME]); 919 hantro_reg_write(vpu, &av1_skip_seg0, 920 segval[0][V4L2_AV1_SEG_LVL_REF_SKIP]); 921 hantro_reg_write(vpu, &av1_global_mv_seg0, 922 segval[0][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 923 924 hantro_reg_write(vpu, &av1_quant_seg1, 925 segval[1][V4L2_AV1_SEG_LVL_ALT_Q]); 926 hantro_reg_write(vpu, &av1_filt_level_delta0_seg1, 927 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 928 hantro_reg_write(vpu, &av1_filt_level_delta1_seg1, 929 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 930 hantro_reg_write(vpu, &av1_filt_level_delta2_seg1, 931 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_U]); 932 hantro_reg_write(vpu, &av1_filt_level_delta3_seg1, 933 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_V]); 934 hantro_reg_write(vpu, &av1_refpic_seg1, 935 segval[1][V4L2_AV1_SEG_LVL_REF_FRAME]); 936 hantro_reg_write(vpu, &av1_skip_seg1, 937 segval[1][V4L2_AV1_SEG_LVL_REF_SKIP]); 938 hantro_reg_write(vpu, &av1_global_mv_seg1, 939 segval[1][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 940 941 hantro_reg_write(vpu, &av1_quant_seg2, 942 segval[2][V4L2_AV1_SEG_LVL_ALT_Q]); 943 hantro_reg_write(vpu, &av1_filt_level_delta0_seg2, 944 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 945 hantro_reg_write(vpu, &av1_filt_level_delta1_seg2, 946 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 947 hantro_reg_write(vpu, &av1_filt_level_delta2_seg2, 948 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_U]); 949 hantro_reg_write(vpu, &av1_filt_level_delta3_seg2, 950 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_V]); 951 hantro_reg_write(vpu, &av1_refpic_seg2, 952 segval[2][V4L2_AV1_SEG_LVL_REF_FRAME]); 953 hantro_reg_write(vpu, &av1_skip_seg2, 954 segval[2][V4L2_AV1_SEG_LVL_REF_SKIP]); 955 hantro_reg_write(vpu, &av1_global_mv_seg2, 956 segval[2][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 957 958 hantro_reg_write(vpu, &av1_quant_seg3, 959 segval[3][V4L2_AV1_SEG_LVL_ALT_Q]); 960 hantro_reg_write(vpu, &av1_filt_level_delta0_seg3, 961 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 962 hantro_reg_write(vpu, &av1_filt_level_delta1_seg3, 963 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 964 hantro_reg_write(vpu, &av1_filt_level_delta2_seg3, 965 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_U]); 966 hantro_reg_write(vpu, &av1_filt_level_delta3_seg3, 967 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_V]); 968 hantro_reg_write(vpu, &av1_refpic_seg3, 969 segval[3][V4L2_AV1_SEG_LVL_REF_FRAME]); 970 hantro_reg_write(vpu, &av1_skip_seg3, 971 segval[3][V4L2_AV1_SEG_LVL_REF_SKIP]); 972 hantro_reg_write(vpu, &av1_global_mv_seg3, 973 segval[3][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 974 975 hantro_reg_write(vpu, &av1_quant_seg4, 976 segval[4][V4L2_AV1_SEG_LVL_ALT_Q]); 977 hantro_reg_write(vpu, &av1_filt_level_delta0_seg4, 978 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 979 hantro_reg_write(vpu, &av1_filt_level_delta1_seg4, 980 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 981 hantro_reg_write(vpu, &av1_filt_level_delta2_seg4, 982 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_U]); 983 hantro_reg_write(vpu, &av1_filt_level_delta3_seg4, 984 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_V]); 985 hantro_reg_write(vpu, &av1_refpic_seg4, 986 segval[4][V4L2_AV1_SEG_LVL_REF_FRAME]); 987 hantro_reg_write(vpu, &av1_skip_seg4, 988 segval[4][V4L2_AV1_SEG_LVL_REF_SKIP]); 989 hantro_reg_write(vpu, &av1_global_mv_seg4, 990 segval[4][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 991 992 hantro_reg_write(vpu, &av1_quant_seg5, 993 segval[5][V4L2_AV1_SEG_LVL_ALT_Q]); 994 hantro_reg_write(vpu, &av1_filt_level_delta0_seg5, 995 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 996 hantro_reg_write(vpu, &av1_filt_level_delta1_seg5, 997 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 998 hantro_reg_write(vpu, &av1_filt_level_delta2_seg5, 999 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1000 hantro_reg_write(vpu, &av1_filt_level_delta3_seg5, 1001 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1002 hantro_reg_write(vpu, &av1_refpic_seg5, 1003 segval[5][V4L2_AV1_SEG_LVL_REF_FRAME]); 1004 hantro_reg_write(vpu, &av1_skip_seg5, 1005 segval[5][V4L2_AV1_SEG_LVL_REF_SKIP]); 1006 hantro_reg_write(vpu, &av1_global_mv_seg5, 1007 segval[5][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1008 1009 hantro_reg_write(vpu, &av1_quant_seg6, 1010 segval[6][V4L2_AV1_SEG_LVL_ALT_Q]); 1011 hantro_reg_write(vpu, &av1_filt_level_delta0_seg6, 1012 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1013 hantro_reg_write(vpu, &av1_filt_level_delta1_seg6, 1014 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1015 hantro_reg_write(vpu, &av1_filt_level_delta2_seg6, 1016 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1017 hantro_reg_write(vpu, &av1_filt_level_delta3_seg6, 1018 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1019 hantro_reg_write(vpu, &av1_refpic_seg6, 1020 segval[6][V4L2_AV1_SEG_LVL_REF_FRAME]); 1021 hantro_reg_write(vpu, &av1_skip_seg6, 1022 segval[6][V4L2_AV1_SEG_LVL_REF_SKIP]); 1023 hantro_reg_write(vpu, &av1_global_mv_seg6, 1024 segval[6][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1025 1026 hantro_reg_write(vpu, &av1_quant_seg7, 1027 segval[7][V4L2_AV1_SEG_LVL_ALT_Q]); 1028 hantro_reg_write(vpu, &av1_filt_level_delta0_seg7, 1029 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1030 hantro_reg_write(vpu, &av1_filt_level_delta1_seg7, 1031 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1032 hantro_reg_write(vpu, &av1_filt_level_delta2_seg7, 1033 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1034 hantro_reg_write(vpu, &av1_filt_level_delta3_seg7, 1035 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1036 hantro_reg_write(vpu, &av1_refpic_seg7, 1037 segval[7][V4L2_AV1_SEG_LVL_REF_FRAME]); 1038 hantro_reg_write(vpu, &av1_skip_seg7, 1039 segval[7][V4L2_AV1_SEG_LVL_REF_SKIP]); 1040 hantro_reg_write(vpu, &av1_global_mv_seg7, 1041 segval[7][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1042} 1043 1044static bool rockchip_vpu981_av1_dec_is_lossless(struct hantro_ctx *ctx) 1045{ 1046 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1047 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1048 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1049 const struct v4l2_av1_segmentation *segmentation = &frame->segmentation; 1050 const struct v4l2_av1_quantization *quantization = &frame->quantization; 1051 int i; 1052 1053 for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { 1054 int qindex = quantization->base_q_idx; 1055 1056 if (segmentation->feature_enabled[i] & 1057 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) { 1058 qindex += segmentation->feature_data[i][V4L2_AV1_SEG_LVL_ALT_Q]; 1059 } 1060 qindex = clamp(qindex, 0, 255); 1061 1062 if (qindex || 1063 quantization->delta_q_y_dc || 1064 quantization->delta_q_u_dc || 1065 quantization->delta_q_u_ac || 1066 quantization->delta_q_v_dc || 1067 quantization->delta_q_v_ac) 1068 return false; 1069 } 1070 return true; 1071} 1072 1073static void rockchip_vpu981_av1_dec_set_loopfilter(struct hantro_ctx *ctx) 1074{ 1075 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1076 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1077 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1078 const struct v4l2_av1_loop_filter *loop_filter = &frame->loop_filter; 1079 bool filtering_dis = (loop_filter->level[0] == 0) && (loop_filter->level[1] == 0); 1080 struct hantro_dev *vpu = ctx->dev; 1081 1082 hantro_reg_write(vpu, &av1_filtering_dis, filtering_dis); 1083 hantro_reg_write(vpu, &av1_filt_level_base_gt32, loop_filter->level[0] > 32); 1084 hantro_reg_write(vpu, &av1_filt_sharpness, loop_filter->sharpness); 1085 1086 hantro_reg_write(vpu, &av1_filt_level0, loop_filter->level[0]); 1087 hantro_reg_write(vpu, &av1_filt_level1, loop_filter->level[1]); 1088 hantro_reg_write(vpu, &av1_filt_level2, loop_filter->level[2]); 1089 hantro_reg_write(vpu, &av1_filt_level3, loop_filter->level[3]); 1090 1091 if (loop_filter->flags & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_ENABLED && 1092 !rockchip_vpu981_av1_dec_is_lossless(ctx) && 1093 !(frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC)) { 1094 hantro_reg_write(vpu, &av1_filt_ref_adj_0, 1095 loop_filter->ref_deltas[0]); 1096 hantro_reg_write(vpu, &av1_filt_ref_adj_1, 1097 loop_filter->ref_deltas[1]); 1098 hantro_reg_write(vpu, &av1_filt_ref_adj_2, 1099 loop_filter->ref_deltas[2]); 1100 hantro_reg_write(vpu, &av1_filt_ref_adj_3, 1101 loop_filter->ref_deltas[3]); 1102 hantro_reg_write(vpu, &av1_filt_ref_adj_4, 1103 loop_filter->ref_deltas[4]); 1104 hantro_reg_write(vpu, &av1_filt_ref_adj_5, 1105 loop_filter->ref_deltas[5]); 1106 hantro_reg_write(vpu, &av1_filt_ref_adj_6, 1107 loop_filter->ref_deltas[6]); 1108 hantro_reg_write(vpu, &av1_filt_ref_adj_7, 1109 loop_filter->ref_deltas[7]); 1110 hantro_reg_write(vpu, &av1_filt_mb_adj_0, 1111 loop_filter->mode_deltas[0]); 1112 hantro_reg_write(vpu, &av1_filt_mb_adj_1, 1113 loop_filter->mode_deltas[1]); 1114 } else { 1115 hantro_reg_write(vpu, &av1_filt_ref_adj_0, 0); 1116 hantro_reg_write(vpu, &av1_filt_ref_adj_1, 0); 1117 hantro_reg_write(vpu, &av1_filt_ref_adj_2, 0); 1118 hantro_reg_write(vpu, &av1_filt_ref_adj_3, 0); 1119 hantro_reg_write(vpu, &av1_filt_ref_adj_4, 0); 1120 hantro_reg_write(vpu, &av1_filt_ref_adj_5, 0); 1121 hantro_reg_write(vpu, &av1_filt_ref_adj_6, 0); 1122 hantro_reg_write(vpu, &av1_filt_ref_adj_7, 0); 1123 hantro_reg_write(vpu, &av1_filt_mb_adj_0, 0); 1124 hantro_reg_write(vpu, &av1_filt_mb_adj_1, 0); 1125 } 1126 1127 hantro_write_addr(vpu, AV1_DB_DATA_COL, av1_dec->db_data_col.dma); 1128 hantro_write_addr(vpu, AV1_DB_CTRL_COL, av1_dec->db_ctrl_col.dma); 1129} 1130 1131static void rockchip_vpu981_av1_dec_update_prob(struct hantro_ctx *ctx) 1132{ 1133 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1134 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1135 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1136 bool frame_is_intra = IS_INTRA(frame->frame_type); 1137 struct av1cdfs *out_cdfs = (struct av1cdfs *)av1_dec->prob_tbl_out.cpu; 1138 int i; 1139 1140 if (frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_FRAME_END_UPDATE_CDF) 1141 return; 1142 1143 for (i = 0; i < NUM_REF_FRAMES; i++) { 1144 if (frame->refresh_frame_flags & BIT(i)) { 1145 struct mvcdfs stored_mv_cdf; 1146 1147 rockchip_av1_get_cdfs(ctx, i); 1148 stored_mv_cdf = av1_dec->cdfs->mv_cdf; 1149 *av1_dec->cdfs = *out_cdfs; 1150 if (frame_is_intra) { 1151 av1_dec->cdfs->mv_cdf = stored_mv_cdf; 1152 *av1_dec->cdfs_ndvc = out_cdfs->mv_cdf; 1153 } 1154 rockchip_av1_store_cdfs(ctx, 1155 frame->refresh_frame_flags); 1156 break; 1157 } 1158 } 1159} 1160 1161void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx) 1162{ 1163 rockchip_vpu981_av1_dec_update_prob(ctx); 1164} 1165 1166static void rockchip_vpu981_av1_dec_set_prob(struct hantro_ctx *ctx) 1167{ 1168 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1169 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1170 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1171 const struct v4l2_av1_quantization *quantization = &frame->quantization; 1172 struct hantro_dev *vpu = ctx->dev; 1173 bool error_resilient_mode = 1174 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE); 1175 bool frame_is_intra = IS_INTRA(frame->frame_type); 1176 1177 if (error_resilient_mode || frame_is_intra || 1178 frame->primary_ref_frame == AV1_PRIMARY_REF_NONE) { 1179 av1_dec->cdfs = &av1_dec->default_cdfs; 1180 av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc; 1181 rockchip_av1_default_coeff_probs(quantization->base_q_idx, 1182 av1_dec->cdfs); 1183 } else { 1184 rockchip_av1_get_cdfs(ctx, frame->ref_frame_idx[frame->primary_ref_frame]); 1185 } 1186 rockchip_av1_store_cdfs(ctx, frame->refresh_frame_flags); 1187 1188 memcpy(av1_dec->prob_tbl.cpu, av1_dec->cdfs, sizeof(struct av1cdfs)); 1189 1190 if (frame_is_intra) { 1191 int mv_offset = offsetof(struct av1cdfs, mv_cdf); 1192 /* Overwrite MV context area with intrabc MV context */ 1193 memcpy(av1_dec->prob_tbl.cpu + mv_offset, av1_dec->cdfs_ndvc, 1194 sizeof(struct mvcdfs)); 1195 } 1196 1197 hantro_write_addr(vpu, AV1_PROP_TABLE_OUT, av1_dec->prob_tbl_out.dma); 1198 hantro_write_addr(vpu, AV1_PROP_TABLE, av1_dec->prob_tbl.dma); 1199} 1200 1201static void 1202rockchip_vpu981_av1_dec_init_scaling_function(const u8 *values, const u8 *scaling, 1203 u8 num_points, u8 *scaling_lut) 1204{ 1205 int i, point; 1206 1207 if (num_points == 0) { 1208 memset(scaling_lut, 0, 256); 1209 return; 1210 } 1211 1212 for (point = 0; point < num_points - 1; point++) { 1213 int x; 1214 s32 delta_y = scaling[point + 1] - scaling[point]; 1215 s32 delta_x = values[point + 1] - values[point]; 1216 s64 delta = 1217 delta_x ? delta_y * ((65536 + (delta_x >> 1)) / 1218 delta_x) : 0; 1219 1220 for (x = 0; x < delta_x; x++) { 1221 scaling_lut[values[point] + x] = 1222 scaling[point] + 1223 (s32)((x * delta + 32768) >> 16); 1224 } 1225 } 1226 1227 for (i = values[num_points - 1]; i < 256; i++) 1228 scaling_lut[i] = scaling[num_points - 1]; 1229} 1230 1231static void rockchip_vpu981_av1_dec_set_fgs(struct hantro_ctx *ctx) 1232{ 1233 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1234 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1235 const struct v4l2_ctrl_av1_film_grain *film_grain = ctrls->film_grain; 1236 struct rockchip_av1_film_grain *fgmem = av1_dec->film_grain.cpu; 1237 struct hantro_dev *vpu = ctx->dev; 1238 bool scaling_from_luma = 1239 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA); 1240 s32 (*ar_coeffs_y)[24]; 1241 s32 (*ar_coeffs_cb)[25]; 1242 s32 (*ar_coeffs_cr)[25]; 1243 s32 (*luma_grain_block)[73][82]; 1244 s32 (*cb_grain_block)[38][44]; 1245 s32 (*cr_grain_block)[38][44]; 1246 s32 ar_coeff_lag, ar_coeff_shift; 1247 s32 grain_scale_shift, bitdepth; 1248 s32 grain_center, grain_min, grain_max; 1249 int i, j; 1250 1251 hantro_reg_write(vpu, &av1_apply_grain, 0); 1252 1253 if (!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_APPLY_GRAIN)) { 1254 hantro_reg_write(vpu, &av1_num_y_points_b, 0); 1255 hantro_reg_write(vpu, &av1_num_cb_points_b, 0); 1256 hantro_reg_write(vpu, &av1_num_cr_points_b, 0); 1257 hantro_reg_write(vpu, &av1_scaling_shift, 0); 1258 hantro_reg_write(vpu, &av1_cb_mult, 0); 1259 hantro_reg_write(vpu, &av1_cb_luma_mult, 0); 1260 hantro_reg_write(vpu, &av1_cb_offset, 0); 1261 hantro_reg_write(vpu, &av1_cr_mult, 0); 1262 hantro_reg_write(vpu, &av1_cr_luma_mult, 0); 1263 hantro_reg_write(vpu, &av1_cr_offset, 0); 1264 hantro_reg_write(vpu, &av1_overlap_flag, 0); 1265 hantro_reg_write(vpu, &av1_clip_to_restricted_range, 0); 1266 hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, 0); 1267 hantro_reg_write(vpu, &av1_random_seed, 0); 1268 hantro_write_addr(vpu, AV1_FILM_GRAIN, 0); 1269 return; 1270 } 1271 1272 ar_coeffs_y = kzalloc(sizeof(int32_t) * 24, GFP_KERNEL); 1273 ar_coeffs_cb = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL); 1274 ar_coeffs_cr = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL); 1275 luma_grain_block = kzalloc(sizeof(int32_t) * 73 * 82, GFP_KERNEL); 1276 cb_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL); 1277 cr_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL); 1278 1279 if (!ar_coeffs_y || !ar_coeffs_cb || !ar_coeffs_cr || 1280 !luma_grain_block || !cb_grain_block || !cr_grain_block) { 1281 pr_warn("Fail allocating memory for film grain parameters\n"); 1282 goto alloc_fail; 1283 } 1284 1285 hantro_reg_write(vpu, &av1_apply_grain, 1); 1286 1287 hantro_reg_write(vpu, &av1_num_y_points_b, 1288 film_grain->num_y_points > 0); 1289 hantro_reg_write(vpu, &av1_num_cb_points_b, 1290 film_grain->num_cb_points > 0); 1291 hantro_reg_write(vpu, &av1_num_cr_points_b, 1292 film_grain->num_cr_points > 0); 1293 hantro_reg_write(vpu, &av1_scaling_shift, 1294 film_grain->grain_scaling_minus_8 + 8); 1295 1296 if (!scaling_from_luma) { 1297 hantro_reg_write(vpu, &av1_cb_mult, film_grain->cb_mult - 128); 1298 hantro_reg_write(vpu, &av1_cb_luma_mult, film_grain->cb_luma_mult - 128); 1299 hantro_reg_write(vpu, &av1_cb_offset, film_grain->cb_offset - 256); 1300 hantro_reg_write(vpu, &av1_cr_mult, film_grain->cr_mult - 128); 1301 hantro_reg_write(vpu, &av1_cr_luma_mult, film_grain->cr_luma_mult - 128); 1302 hantro_reg_write(vpu, &av1_cr_offset, film_grain->cr_offset - 256); 1303 } else { 1304 hantro_reg_write(vpu, &av1_cb_mult, 0); 1305 hantro_reg_write(vpu, &av1_cb_luma_mult, 0); 1306 hantro_reg_write(vpu, &av1_cb_offset, 0); 1307 hantro_reg_write(vpu, &av1_cr_mult, 0); 1308 hantro_reg_write(vpu, &av1_cr_luma_mult, 0); 1309 hantro_reg_write(vpu, &av1_cr_offset, 0); 1310 } 1311 1312 hantro_reg_write(vpu, &av1_overlap_flag, 1313 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_OVERLAP)); 1314 hantro_reg_write(vpu, &av1_clip_to_restricted_range, 1315 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CLIP_TO_RESTRICTED_RANGE)); 1316 hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, scaling_from_luma); 1317 hantro_reg_write(vpu, &av1_random_seed, film_grain->grain_seed); 1318 1319 rockchip_vpu981_av1_dec_init_scaling_function(film_grain->point_y_value, 1320 film_grain->point_y_scaling, 1321 film_grain->num_y_points, 1322 fgmem->scaling_lut_y); 1323 1324 if (film_grain->flags & 1325 V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA) { 1326 memcpy(fgmem->scaling_lut_cb, fgmem->scaling_lut_y, 1327 sizeof(*fgmem->scaling_lut_y) * 256); 1328 memcpy(fgmem->scaling_lut_cr, fgmem->scaling_lut_y, 1329 sizeof(*fgmem->scaling_lut_y) * 256); 1330 } else { 1331 rockchip_vpu981_av1_dec_init_scaling_function 1332 (film_grain->point_cb_value, film_grain->point_cb_scaling, 1333 film_grain->num_cb_points, fgmem->scaling_lut_cb); 1334 rockchip_vpu981_av1_dec_init_scaling_function 1335 (film_grain->point_cr_value, film_grain->point_cr_scaling, 1336 film_grain->num_cr_points, fgmem->scaling_lut_cr); 1337 } 1338 1339 for (i = 0; i < V4L2_AV1_AR_COEFFS_SIZE; i++) { 1340 if (i < 24) 1341 (*ar_coeffs_y)[i] = film_grain->ar_coeffs_y_plus_128[i] - 128; 1342 (*ar_coeffs_cb)[i] = film_grain->ar_coeffs_cb_plus_128[i] - 128; 1343 (*ar_coeffs_cr)[i] = film_grain->ar_coeffs_cr_plus_128[i] - 128; 1344 } 1345 1346 ar_coeff_lag = film_grain->ar_coeff_lag; 1347 ar_coeff_shift = film_grain->ar_coeff_shift_minus_6 + 6; 1348 grain_scale_shift = film_grain->grain_scale_shift; 1349 bitdepth = ctx->bit_depth; 1350 grain_center = 128 << (bitdepth - 8); 1351 grain_min = 0 - grain_center; 1352 grain_max = (256 << (bitdepth - 8)) - 1 - grain_center; 1353 1354 rockchip_av1_generate_luma_grain_block(luma_grain_block, bitdepth, 1355 film_grain->num_y_points, grain_scale_shift, 1356 ar_coeff_lag, ar_coeffs_y, ar_coeff_shift, 1357 grain_min, grain_max, film_grain->grain_seed); 1358 1359 rockchip_av1_generate_chroma_grain_block(luma_grain_block, cb_grain_block, 1360 cr_grain_block, bitdepth, 1361 film_grain->num_y_points, 1362 film_grain->num_cb_points, 1363 film_grain->num_cr_points, 1364 grain_scale_shift, ar_coeff_lag, ar_coeffs_cb, 1365 ar_coeffs_cr, ar_coeff_shift, grain_min, 1366 grain_max, 1367 scaling_from_luma, 1368 film_grain->grain_seed); 1369 1370 for (i = 0; i < 64; i++) { 1371 for (j = 0; j < 64; j++) 1372 fgmem->cropped_luma_grain_block[i * 64 + j] = 1373 (*luma_grain_block)[i + 9][j + 9]; 1374 } 1375 1376 for (i = 0; i < 32; i++) { 1377 for (j = 0; j < 32; j++) { 1378 fgmem->cropped_chroma_grain_block[i * 64 + 2 * j] = 1379 (*cb_grain_block)[i + 6][j + 6]; 1380 fgmem->cropped_chroma_grain_block[i * 64 + 2 * j + 1] = 1381 (*cr_grain_block)[i + 6][j + 6]; 1382 } 1383 } 1384 1385 hantro_write_addr(vpu, AV1_FILM_GRAIN, av1_dec->film_grain.dma); 1386 1387alloc_fail: 1388 kfree(ar_coeffs_y); 1389 kfree(ar_coeffs_cb); 1390 kfree(ar_coeffs_cr); 1391 kfree(luma_grain_block); 1392 kfree(cb_grain_block); 1393 kfree(cr_grain_block); 1394} 1395 1396static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx) 1397{ 1398 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1399 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1400 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1401 const struct v4l2_av1_cdef *cdef = &frame->cdef; 1402 struct hantro_dev *vpu = ctx->dev; 1403 u32 luma_pri_strength = 0; 1404 u16 luma_sec_strength = 0; 1405 u32 chroma_pri_strength = 0; 1406 u16 chroma_sec_strength = 0; 1407 bool enable_cdef; 1408 int i; 1409 1410 enable_cdef = !(cdef->bits == 0 && 1411 cdef->damping_minus_3 == 0 && 1412 cdef->y_pri_strength[0] == 0 && 1413 cdef->y_sec_strength[0] == 0 && 1414 cdef->uv_pri_strength[0] == 0 && 1415 cdef->uv_sec_strength[0] == 0); 1416 hantro_reg_write(vpu, &av1_enable_cdef, enable_cdef); 1417 hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits); 1418 hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3); 1419 1420 for (i = 0; i < BIT(cdef->bits); i++) { 1421 luma_pri_strength |= cdef->y_pri_strength[i] << (i * 4); 1422 if (cdef->y_sec_strength[i] == 4) 1423 luma_sec_strength |= 3 << (i * 2); 1424 else 1425 luma_sec_strength |= cdef->y_sec_strength[i] << (i * 2); 1426 1427 chroma_pri_strength |= cdef->uv_pri_strength[i] << (i * 4); 1428 if (cdef->uv_sec_strength[i] == 4) 1429 chroma_sec_strength |= 3 << (i * 2); 1430 else 1431 chroma_sec_strength |= cdef->uv_sec_strength[i] << (i * 2); 1432 } 1433 1434 hantro_reg_write(vpu, &av1_cdef_luma_primary_strength, 1435 luma_pri_strength); 1436 hantro_reg_write(vpu, &av1_cdef_luma_secondary_strength, 1437 luma_sec_strength); 1438 hantro_reg_write(vpu, &av1_cdef_chroma_primary_strength, 1439 chroma_pri_strength); 1440 hantro_reg_write(vpu, &av1_cdef_chroma_secondary_strength, 1441 chroma_sec_strength); 1442 1443 hantro_write_addr(vpu, AV1_CDEF_COL, av1_dec->cdef_col.dma); 1444} 1445 1446static void rockchip_vpu981_av1_dec_set_lr(struct hantro_ctx *ctx) 1447{ 1448 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1449 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1450 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1451 const struct v4l2_av1_loop_restoration *loop_restoration = 1452 &frame->loop_restoration; 1453 struct hantro_dev *vpu = ctx->dev; 1454 u16 lr_type = 0, lr_unit_size = 0; 1455 u8 restoration_unit_size[V4L2_AV1_NUM_PLANES_MAX] = { 3, 3, 3 }; 1456 int i; 1457 1458 if (loop_restoration->flags & V4L2_AV1_LOOP_RESTORATION_FLAG_USES_LR) { 1459 restoration_unit_size[0] = 1 + loop_restoration->lr_unit_shift; 1460 restoration_unit_size[1] = 1461 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift; 1462 restoration_unit_size[2] = 1463 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift; 1464 } 1465 1466 for (i = 0; i < V4L2_AV1_NUM_PLANES_MAX; i++) { 1467 lr_type |= 1468 loop_restoration->frame_restoration_type[i] << (i * 2); 1469 lr_unit_size |= restoration_unit_size[i] << (i * 2); 1470 } 1471 1472 hantro_reg_write(vpu, &av1_lr_type, lr_type); 1473 hantro_reg_write(vpu, &av1_lr_unit_size, lr_unit_size); 1474 hantro_write_addr(vpu, AV1_LR_COL, av1_dec->lr_col.dma); 1475} 1476 1477static void rockchip_vpu981_av1_dec_set_superres_params(struct hantro_ctx *ctx) 1478{ 1479 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1480 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1481 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1482 struct hantro_dev *vpu = ctx->dev; 1483 u8 superres_scale_denominator = SCALE_NUMERATOR; 1484 int superres_luma_step = RS_SCALE_SUBPEL_BITS; 1485 int superres_chroma_step = RS_SCALE_SUBPEL_BITS; 1486 int superres_luma_step_invra = RS_SCALE_SUBPEL_BITS; 1487 int superres_chroma_step_invra = RS_SCALE_SUBPEL_BITS; 1488 int superres_init_luma_subpel_x = 0; 1489 int superres_init_chroma_subpel_x = 0; 1490 int superres_is_scaled = 0; 1491 int min_w = min_t(uint32_t, 16, frame->upscaled_width); 1492 int upscaled_luma, downscaled_luma; 1493 int downscaled_chroma, upscaled_chroma; 1494 int step_luma, step_chroma; 1495 int err_luma, err_chroma; 1496 int initial_luma, initial_chroma; 1497 int width = 0; 1498 1499 if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES) 1500 superres_scale_denominator = frame->superres_denom; 1501 1502 if (superres_scale_denominator <= SCALE_NUMERATOR) 1503 goto set_regs; 1504 1505 width = (frame->upscaled_width * SCALE_NUMERATOR + 1506 (superres_scale_denominator / 2)) / superres_scale_denominator; 1507 1508 if (width < min_w) 1509 width = min_w; 1510 1511 if (width == frame->upscaled_width) 1512 goto set_regs; 1513 1514 superres_is_scaled = 1; 1515 upscaled_luma = frame->upscaled_width; 1516 downscaled_luma = width; 1517 downscaled_chroma = (downscaled_luma + 1) >> 1; 1518 upscaled_chroma = (upscaled_luma + 1) >> 1; 1519 step_luma = 1520 ((downscaled_luma << RS_SCALE_SUBPEL_BITS) + 1521 (upscaled_luma / 2)) / upscaled_luma; 1522 step_chroma = 1523 ((downscaled_chroma << RS_SCALE_SUBPEL_BITS) + 1524 (upscaled_chroma / 2)) / upscaled_chroma; 1525 err_luma = 1526 (upscaled_luma * step_luma) 1527 - (downscaled_luma << RS_SCALE_SUBPEL_BITS); 1528 err_chroma = 1529 (upscaled_chroma * step_chroma) 1530 - (downscaled_chroma << RS_SCALE_SUBPEL_BITS); 1531 initial_luma = 1532 ((-((upscaled_luma - downscaled_luma) << (RS_SCALE_SUBPEL_BITS - 1)) 1533 + upscaled_luma / 2) 1534 / upscaled_luma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_luma / 2) 1535 & RS_SCALE_SUBPEL_MASK; 1536 initial_chroma = 1537 ((-((upscaled_chroma - downscaled_chroma) << (RS_SCALE_SUBPEL_BITS - 1)) 1538 + upscaled_chroma / 2) 1539 / upscaled_chroma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_chroma / 2) 1540 & RS_SCALE_SUBPEL_MASK; 1541 superres_luma_step = step_luma; 1542 superres_chroma_step = step_chroma; 1543 superres_luma_step_invra = 1544 ((upscaled_luma << RS_SCALE_SUBPEL_BITS) + (downscaled_luma / 2)) 1545 / downscaled_luma; 1546 superres_chroma_step_invra = 1547 ((upscaled_chroma << RS_SCALE_SUBPEL_BITS) + (downscaled_chroma / 2)) 1548 / downscaled_chroma; 1549 superres_init_luma_subpel_x = initial_luma; 1550 superres_init_chroma_subpel_x = initial_chroma; 1551 1552set_regs: 1553 hantro_reg_write(vpu, &av1_superres_pic_width, frame->upscaled_width); 1554 1555 if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES) 1556 hantro_reg_write(vpu, &av1_scale_denom_minus9, 1557 frame->superres_denom - SUPERRES_SCALE_DENOMINATOR_MIN); 1558 else 1559 hantro_reg_write(vpu, &av1_scale_denom_minus9, frame->superres_denom); 1560 1561 hantro_reg_write(vpu, &av1_superres_luma_step, superres_luma_step); 1562 hantro_reg_write(vpu, &av1_superres_chroma_step, superres_chroma_step); 1563 hantro_reg_write(vpu, &av1_superres_luma_step_invra, 1564 superres_luma_step_invra); 1565 hantro_reg_write(vpu, &av1_superres_chroma_step_invra, 1566 superres_chroma_step_invra); 1567 hantro_reg_write(vpu, &av1_superres_init_luma_subpel_x, 1568 superres_init_luma_subpel_x); 1569 hantro_reg_write(vpu, &av1_superres_init_chroma_subpel_x, 1570 superres_init_chroma_subpel_x); 1571 hantro_reg_write(vpu, &av1_superres_is_scaled, superres_is_scaled); 1572 1573 hantro_write_addr(vpu, AV1_SR_COL, av1_dec->sr_col.dma); 1574} 1575 1576static void rockchip_vpu981_av1_dec_set_picture_dimensions(struct hantro_ctx *ctx) 1577{ 1578 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1579 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1580 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1581 struct hantro_dev *vpu = ctx->dev; 1582 int pic_width_in_cbs = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); 1583 int pic_height_in_cbs = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); 1584 int pic_width_pad = ALIGN(frame->frame_width_minus_1 + 1, 8) 1585 - (frame->frame_width_minus_1 + 1); 1586 int pic_height_pad = ALIGN(frame->frame_height_minus_1 + 1, 8) 1587 - (frame->frame_height_minus_1 + 1); 1588 1589 hantro_reg_write(vpu, &av1_pic_width_in_cbs, pic_width_in_cbs); 1590 hantro_reg_write(vpu, &av1_pic_height_in_cbs, pic_height_in_cbs); 1591 hantro_reg_write(vpu, &av1_pic_width_pad, pic_width_pad); 1592 hantro_reg_write(vpu, &av1_pic_height_pad, pic_height_pad); 1593 1594 rockchip_vpu981_av1_dec_set_superres_params(ctx); 1595} 1596 1597static void rockchip_vpu981_av1_dec_set_other_frames(struct hantro_ctx *ctx) 1598{ 1599 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1600 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1601 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1602 struct hantro_dev *vpu = ctx->dev; 1603 bool use_ref_frame_mvs = 1604 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS); 1605 int cur_frame_offset = frame->order_hint; 1606 int alt_frame_offset = 0; 1607 int gld_frame_offset = 0; 1608 int bwd_frame_offset = 0; 1609 int alt2_frame_offset = 0; 1610 int refs_selected[3] = { 0, 0, 0 }; 1611 int cur_mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); 1612 int cur_mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); 1613 int cur_offset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1]; 1614 int cur_roffset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1]; 1615 int mf_types[3] = { 0, 0, 0 }; 1616 int ref_stamp = 2; 1617 int ref_ind = 0; 1618 int rf, idx; 1619 1620 alt_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT_BUF_IDX); 1621 gld_frame_offset = rockchip_vpu981_get_order_hint(ctx, GLD_BUF_IDX); 1622 bwd_frame_offset = rockchip_vpu981_get_order_hint(ctx, BWD_BUF_IDX); 1623 alt2_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT2_BUF_IDX); 1624 1625 idx = rockchip_vpu981_get_frame_index(ctx, LST_BUF_IDX); 1626 if (idx >= 0) { 1627 int alt_frame_offset_in_lst = 1628 av1_dec->frame_refs[idx].order_hints[V4L2_AV1_REF_ALTREF_FRAME]; 1629 bool is_lst_overlay = 1630 (alt_frame_offset_in_lst == gld_frame_offset); 1631 1632 if (!is_lst_overlay) { 1633 int lst_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1634 int lst_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1635 bool lst_intra_only = 1636 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1637 1638 if (lst_mi_cols == cur_mi_cols && 1639 lst_mi_rows == cur_mi_rows && !lst_intra_only) { 1640 mf_types[ref_ind] = V4L2_AV1_REF_LAST_FRAME; 1641 refs_selected[ref_ind++] = LST_BUF_IDX; 1642 } 1643 } 1644 ref_stamp--; 1645 } 1646 1647 idx = rockchip_vpu981_get_frame_index(ctx, BWD_BUF_IDX); 1648 if (rockchip_vpu981_av1_dec_get_dist(ctx, bwd_frame_offset, cur_frame_offset) > 0) { 1649 int bwd_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1650 int bwd_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1651 bool bwd_intra_only = 1652 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1653 1654 if (bwd_mi_cols == cur_mi_cols && bwd_mi_rows == cur_mi_rows && 1655 !bwd_intra_only) { 1656 mf_types[ref_ind] = V4L2_AV1_REF_BWDREF_FRAME; 1657 refs_selected[ref_ind++] = BWD_BUF_IDX; 1658 ref_stamp--; 1659 } 1660 } 1661 1662 idx = rockchip_vpu981_get_frame_index(ctx, ALT2_BUF_IDX); 1663 if (rockchip_vpu981_av1_dec_get_dist(ctx, alt2_frame_offset, cur_frame_offset) > 0) { 1664 int alt2_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1665 int alt2_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1666 bool alt2_intra_only = 1667 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1668 1669 if (alt2_mi_cols == cur_mi_cols && alt2_mi_rows == cur_mi_rows && 1670 !alt2_intra_only) { 1671 mf_types[ref_ind] = V4L2_AV1_REF_ALTREF2_FRAME; 1672 refs_selected[ref_ind++] = ALT2_BUF_IDX; 1673 ref_stamp--; 1674 } 1675 } 1676 1677 idx = rockchip_vpu981_get_frame_index(ctx, ALT_BUF_IDX); 1678 if (rockchip_vpu981_av1_dec_get_dist(ctx, alt_frame_offset, cur_frame_offset) > 0 && 1679 ref_stamp >= 0) { 1680 int alt_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1681 int alt_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1682 bool alt_intra_only = 1683 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1684 1685 if (alt_mi_cols == cur_mi_cols && alt_mi_rows == cur_mi_rows && 1686 !alt_intra_only) { 1687 mf_types[ref_ind] = V4L2_AV1_REF_ALTREF_FRAME; 1688 refs_selected[ref_ind++] = ALT_BUF_IDX; 1689 ref_stamp--; 1690 } 1691 } 1692 1693 idx = rockchip_vpu981_get_frame_index(ctx, LST2_BUF_IDX); 1694 if (idx >= 0 && ref_stamp >= 0) { 1695 int lst2_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1696 int lst2_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1697 bool lst2_intra_only = 1698 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1699 1700 if (lst2_mi_cols == cur_mi_cols && lst2_mi_rows == cur_mi_rows && 1701 !lst2_intra_only) { 1702 mf_types[ref_ind] = V4L2_AV1_REF_LAST2_FRAME; 1703 refs_selected[ref_ind++] = LST2_BUF_IDX; 1704 ref_stamp--; 1705 } 1706 } 1707 1708 for (rf = 0; rf < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; ++rf) { 1709 idx = rockchip_vpu981_get_frame_index(ctx, rf); 1710 if (idx >= 0) { 1711 int rf_order_hint = rockchip_vpu981_get_order_hint(ctx, rf); 1712 1713 cur_offset[rf] = 1714 rockchip_vpu981_av1_dec_get_dist(ctx, cur_frame_offset, rf_order_hint); 1715 cur_roffset[rf] = 1716 rockchip_vpu981_av1_dec_get_dist(ctx, rf_order_hint, cur_frame_offset); 1717 } else { 1718 cur_offset[rf] = 0; 1719 cur_roffset[rf] = 0; 1720 } 1721 } 1722 1723 hantro_reg_write(vpu, &av1_use_temporal0_mvs, 0); 1724 hantro_reg_write(vpu, &av1_use_temporal1_mvs, 0); 1725 hantro_reg_write(vpu, &av1_use_temporal2_mvs, 0); 1726 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0); 1727 1728 hantro_reg_write(vpu, &av1_mf1_last_offset, 0); 1729 hantro_reg_write(vpu, &av1_mf1_last2_offset, 0); 1730 hantro_reg_write(vpu, &av1_mf1_last3_offset, 0); 1731 hantro_reg_write(vpu, &av1_mf1_golden_offset, 0); 1732 hantro_reg_write(vpu, &av1_mf1_bwdref_offset, 0); 1733 hantro_reg_write(vpu, &av1_mf1_altref2_offset, 0); 1734 hantro_reg_write(vpu, &av1_mf1_altref_offset, 0); 1735 1736 if (use_ref_frame_mvs && ref_ind > 0 && 1737 cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && 1738 cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { 1739 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[0]); 1740 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[0]); 1741 u32 *oh = av1_dec->frame_refs[idx].order_hints; 1742 int val; 1743 1744 hantro_reg_write(vpu, &av1_use_temporal0_mvs, 1); 1745 1746 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); 1747 hantro_reg_write(vpu, &av1_mf1_last_offset, val); 1748 1749 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); 1750 hantro_reg_write(vpu, &av1_mf1_last2_offset, val); 1751 1752 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); 1753 hantro_reg_write(vpu, &av1_mf1_last3_offset, val); 1754 1755 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); 1756 hantro_reg_write(vpu, &av1_mf1_golden_offset, val); 1757 1758 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); 1759 hantro_reg_write(vpu, &av1_mf1_bwdref_offset, val); 1760 1761 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); 1762 hantro_reg_write(vpu, &av1_mf1_altref2_offset, val); 1763 1764 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); 1765 hantro_reg_write(vpu, &av1_mf1_altref_offset, val); 1766 } 1767 1768 hantro_reg_write(vpu, &av1_mf2_last_offset, 0); 1769 hantro_reg_write(vpu, &av1_mf2_last2_offset, 0); 1770 hantro_reg_write(vpu, &av1_mf2_last3_offset, 0); 1771 hantro_reg_write(vpu, &av1_mf2_golden_offset, 0); 1772 hantro_reg_write(vpu, &av1_mf2_bwdref_offset, 0); 1773 hantro_reg_write(vpu, &av1_mf2_altref2_offset, 0); 1774 hantro_reg_write(vpu, &av1_mf2_altref_offset, 0); 1775 1776 if (use_ref_frame_mvs && ref_ind > 1 && 1777 cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && 1778 cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { 1779 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[1]); 1780 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[1]); 1781 u32 *oh = av1_dec->frame_refs[idx].order_hints; 1782 int val; 1783 1784 hantro_reg_write(vpu, &av1_use_temporal1_mvs, 1); 1785 1786 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); 1787 hantro_reg_write(vpu, &av1_mf2_last_offset, val); 1788 1789 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); 1790 hantro_reg_write(vpu, &av1_mf2_last2_offset, val); 1791 1792 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); 1793 hantro_reg_write(vpu, &av1_mf2_last3_offset, val); 1794 1795 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); 1796 hantro_reg_write(vpu, &av1_mf2_golden_offset, val); 1797 1798 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); 1799 hantro_reg_write(vpu, &av1_mf2_bwdref_offset, val); 1800 1801 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); 1802 hantro_reg_write(vpu, &av1_mf2_altref2_offset, val); 1803 1804 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); 1805 hantro_reg_write(vpu, &av1_mf2_altref_offset, val); 1806 } 1807 1808 hantro_reg_write(vpu, &av1_mf3_last_offset, 0); 1809 hantro_reg_write(vpu, &av1_mf3_last2_offset, 0); 1810 hantro_reg_write(vpu, &av1_mf3_last3_offset, 0); 1811 hantro_reg_write(vpu, &av1_mf3_golden_offset, 0); 1812 hantro_reg_write(vpu, &av1_mf3_bwdref_offset, 0); 1813 hantro_reg_write(vpu, &av1_mf3_altref2_offset, 0); 1814 hantro_reg_write(vpu, &av1_mf3_altref_offset, 0); 1815 1816 if (use_ref_frame_mvs && ref_ind > 2 && 1817 cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && 1818 cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { 1819 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[2]); 1820 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[2]); 1821 u32 *oh = av1_dec->frame_refs[idx].order_hints; 1822 int val; 1823 1824 hantro_reg_write(vpu, &av1_use_temporal2_mvs, 1); 1825 1826 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); 1827 hantro_reg_write(vpu, &av1_mf3_last_offset, val); 1828 1829 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); 1830 hantro_reg_write(vpu, &av1_mf3_last2_offset, val); 1831 1832 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); 1833 hantro_reg_write(vpu, &av1_mf3_last3_offset, val); 1834 1835 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); 1836 hantro_reg_write(vpu, &av1_mf3_golden_offset, val); 1837 1838 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); 1839 hantro_reg_write(vpu, &av1_mf3_bwdref_offset, val); 1840 1841 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); 1842 hantro_reg_write(vpu, &av1_mf3_altref2_offset, val); 1843 1844 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); 1845 hantro_reg_write(vpu, &av1_mf3_altref_offset, val); 1846 } 1847 1848 hantro_reg_write(vpu, &av1_cur_last_offset, cur_offset[0]); 1849 hantro_reg_write(vpu, &av1_cur_last2_offset, cur_offset[1]); 1850 hantro_reg_write(vpu, &av1_cur_last3_offset, cur_offset[2]); 1851 hantro_reg_write(vpu, &av1_cur_golden_offset, cur_offset[3]); 1852 hantro_reg_write(vpu, &av1_cur_bwdref_offset, cur_offset[4]); 1853 hantro_reg_write(vpu, &av1_cur_altref2_offset, cur_offset[5]); 1854 hantro_reg_write(vpu, &av1_cur_altref_offset, cur_offset[6]); 1855 1856 hantro_reg_write(vpu, &av1_cur_last_roffset, cur_roffset[0]); 1857 hantro_reg_write(vpu, &av1_cur_last2_roffset, cur_roffset[1]); 1858 hantro_reg_write(vpu, &av1_cur_last3_roffset, cur_roffset[2]); 1859 hantro_reg_write(vpu, &av1_cur_golden_roffset, cur_roffset[3]); 1860 hantro_reg_write(vpu, &av1_cur_bwdref_roffset, cur_roffset[4]); 1861 hantro_reg_write(vpu, &av1_cur_altref2_roffset, cur_roffset[5]); 1862 hantro_reg_write(vpu, &av1_cur_altref_roffset, cur_roffset[6]); 1863 1864 hantro_reg_write(vpu, &av1_mf1_type, mf_types[0] - V4L2_AV1_REF_LAST_FRAME); 1865 hantro_reg_write(vpu, &av1_mf2_type, mf_types[1] - V4L2_AV1_REF_LAST_FRAME); 1866 hantro_reg_write(vpu, &av1_mf3_type, mf_types[2] - V4L2_AV1_REF_LAST_FRAME); 1867} 1868 1869static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx) 1870{ 1871 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1872 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1873 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1874 int frame_type = frame->frame_type; 1875 bool allow_intrabc = !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC); 1876 int ref_count[AV1DEC_MAX_PIC_BUFFERS] = { 0 }; 1877 struct hantro_dev *vpu = ctx->dev; 1878 int i, ref_frames = 0; 1879 bool scale_enable = false; 1880 1881 if (IS_INTRA(frame_type) && !allow_intrabc) 1882 return; 1883 1884 if (!allow_intrabc) { 1885 for (i = 0; i < V4L2_AV1_REFS_PER_FRAME; i++) { 1886 int idx = rockchip_vpu981_get_frame_index(ctx, i); 1887 1888 if (idx >= 0) 1889 ref_count[idx]++; 1890 } 1891 1892 for (i = 0; i < AV1DEC_MAX_PIC_BUFFERS; i++) { 1893 if (ref_count[i]) 1894 ref_frames++; 1895 } 1896 } else { 1897 ref_frames = 1; 1898 } 1899 hantro_reg_write(vpu, &av1_ref_frames, ref_frames); 1900 1901 rockchip_vpu981_av1_dec_set_frame_sign_bias(ctx); 1902 1903 for (i = V4L2_AV1_REF_LAST_FRAME; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) { 1904 u32 ref = i - 1; 1905 int idx = 0; 1906 int width, height; 1907 1908 if (allow_intrabc) { 1909 idx = av1_dec->current_frame_index; 1910 width = frame->frame_width_minus_1 + 1; 1911 height = frame->frame_height_minus_1 + 1; 1912 } else { 1913 if (rockchip_vpu981_get_frame_index(ctx, ref) > 0) 1914 idx = rockchip_vpu981_get_frame_index(ctx, ref); 1915 width = av1_dec->frame_refs[idx].width; 1916 height = av1_dec->frame_refs[idx].height; 1917 } 1918 1919 scale_enable |= 1920 rockchip_vpu981_av1_dec_set_ref(ctx, ref, idx, width, 1921 height); 1922 1923 rockchip_vpu981_av1_dec_set_sign_bias(ctx, ref, 1924 av1_dec->ref_frame_sign_bias[i]); 1925 } 1926 hantro_reg_write(vpu, &av1_ref_scaling_enable, scale_enable); 1927 1928 hantro_reg_write(vpu, &av1_ref0_gm_mode, 1929 frame->global_motion.type[V4L2_AV1_REF_LAST_FRAME]); 1930 hantro_reg_write(vpu, &av1_ref1_gm_mode, 1931 frame->global_motion.type[V4L2_AV1_REF_LAST2_FRAME]); 1932 hantro_reg_write(vpu, &av1_ref2_gm_mode, 1933 frame->global_motion.type[V4L2_AV1_REF_LAST3_FRAME]); 1934 hantro_reg_write(vpu, &av1_ref3_gm_mode, 1935 frame->global_motion.type[V4L2_AV1_REF_GOLDEN_FRAME]); 1936 hantro_reg_write(vpu, &av1_ref4_gm_mode, 1937 frame->global_motion.type[V4L2_AV1_REF_BWDREF_FRAME]); 1938 hantro_reg_write(vpu, &av1_ref5_gm_mode, 1939 frame->global_motion.type[V4L2_AV1_REF_ALTREF2_FRAME]); 1940 hantro_reg_write(vpu, &av1_ref6_gm_mode, 1941 frame->global_motion.type[V4L2_AV1_REF_ALTREF_FRAME]); 1942 1943 rockchip_vpu981_av1_dec_set_other_frames(ctx); 1944} 1945 1946static int rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode) 1947{ 1948 switch (tx_mode) { 1949 case V4L2_AV1_TX_MODE_ONLY_4X4: 1950 return ROCKCHIP_AV1_TX_MODE_ONLY_4X4; 1951 case V4L2_AV1_TX_MODE_LARGEST: 1952 return ROCKCHIP_AV1_TX_MODE_32x32; 1953 case V4L2_AV1_TX_MODE_SELECT: 1954 return ROCKCHIP_AV1_TX_MODE_SELECT; 1955 } 1956 1957 return ROCKCHIP_AV1_TX_MODE_32x32; 1958} 1959 1960static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) 1961{ 1962 struct hantro_dev *vpu = ctx->dev; 1963 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1964 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1965 int tx_mode; 1966 1967 hantro_reg_write(vpu, &av1_skip_mode, 1968 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT)); 1969 hantro_reg_write(vpu, &av1_tempor_mvp_e, 1970 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS)); 1971 hantro_reg_write(vpu, &av1_delta_lf_res_log, 1972 ctrls->frame->loop_filter.delta_lf_res); 1973 hantro_reg_write(vpu, &av1_delta_lf_multi, 1974 !!(ctrls->frame->loop_filter.flags 1975 & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_MULTI)); 1976 hantro_reg_write(vpu, &av1_delta_lf_present, 1977 !!(ctrls->frame->loop_filter.flags 1978 & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_PRESENT)); 1979 hantro_reg_write(vpu, &av1_disable_cdf_update, 1980 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_CDF_UPDATE)); 1981 hantro_reg_write(vpu, &av1_allow_warp, 1982 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_WARPED_MOTION)); 1983 hantro_reg_write(vpu, &av1_show_frame, 1984 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SHOW_FRAME)); 1985 hantro_reg_write(vpu, &av1_switchable_motion_mode, 1986 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE)); 1987 hantro_reg_write(vpu, &av1_allow_masked_compound, 1988 !!(ctrls->sequence->flags 1989 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND)); 1990 hantro_reg_write(vpu, &av1_allow_interintra, 1991 !!(ctrls->sequence->flags 1992 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTERINTRA_COMPOUND)); 1993 hantro_reg_write(vpu, &av1_enable_intra_edge_filter, 1994 !!(ctrls->sequence->flags 1995 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTRA_EDGE_FILTER)); 1996 hantro_reg_write(vpu, &av1_allow_filter_intra, 1997 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_FILTER_INTRA)); 1998 hantro_reg_write(vpu, &av1_enable_jnt_comp, 1999 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_JNT_COMP)); 2000 hantro_reg_write(vpu, &av1_enable_dual_filter, 2001 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_DUAL_FILTER)); 2002 hantro_reg_write(vpu, &av1_reduced_tx_set_used, 2003 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REDUCED_TX_SET)); 2004 hantro_reg_write(vpu, &av1_allow_screen_content_tools, 2005 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS)); 2006 hantro_reg_write(vpu, &av1_allow_intrabc, 2007 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC)); 2008 2009 if (!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS)) 2010 hantro_reg_write(vpu, &av1_force_interger_mv, 0); 2011 else 2012 hantro_reg_write(vpu, &av1_force_interger_mv, 2013 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_FORCE_INTEGER_MV)); 2014 2015 hantro_reg_write(vpu, &av1_blackwhite_e, 0); 2016 hantro_reg_write(vpu, &av1_delta_q_res_log, ctrls->frame->quantization.delta_q_res); 2017 hantro_reg_write(vpu, &av1_delta_q_present, 2018 !!(ctrls->frame->quantization.flags 2019 & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT)); 2020 2021 hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type)); 2022 hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx); 2023 hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8); 2024 hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8); 2025 2026 hantro_reg_write(vpu, &av1_mcomp_filt_type, ctrls->frame->interpolation_filter); 2027 hantro_reg_write(vpu, &av1_high_prec_mv_e, 2028 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV)); 2029 hantro_reg_write(vpu, &av1_comp_pred_mode, 2030 (ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0); 2031 2032 tx_mode = rockchip_vpu981_av1_get_hardware_tx_mode(ctrls->frame->tx_mode); 2033 hantro_reg_write(vpu, &av1_transform_mode, tx_mode); 2034 hantro_reg_write(vpu, &av1_max_cb_size, 2035 (ctrls->sequence->flags 2036 & V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6); 2037 hantro_reg_write(vpu, &av1_min_cb_size, 3); 2038 2039 hantro_reg_write(vpu, &av1_comp_pred_fixed_ref, 0); 2040 hantro_reg_write(vpu, &av1_comp_pred_var_ref0_av1, 0); 2041 hantro_reg_write(vpu, &av1_comp_pred_var_ref1_av1, 0); 2042 hantro_reg_write(vpu, &av1_filt_level_seg0, 0); 2043 hantro_reg_write(vpu, &av1_filt_level_seg1, 0); 2044 hantro_reg_write(vpu, &av1_filt_level_seg2, 0); 2045 hantro_reg_write(vpu, &av1_filt_level_seg3, 0); 2046 hantro_reg_write(vpu, &av1_filt_level_seg4, 0); 2047 hantro_reg_write(vpu, &av1_filt_level_seg5, 0); 2048 hantro_reg_write(vpu, &av1_filt_level_seg6, 0); 2049 hantro_reg_write(vpu, &av1_filt_level_seg7, 0); 2050 2051 hantro_reg_write(vpu, &av1_qp_delta_y_dc_av1, ctrls->frame->quantization.delta_q_y_dc); 2052 hantro_reg_write(vpu, &av1_qp_delta_ch_dc_av1, ctrls->frame->quantization.delta_q_u_dc); 2053 hantro_reg_write(vpu, &av1_qp_delta_ch_ac_av1, ctrls->frame->quantization.delta_q_u_ac); 2054 if (ctrls->frame->quantization.flags & V4L2_AV1_QUANTIZATION_FLAG_USING_QMATRIX) { 2055 hantro_reg_write(vpu, &av1_qmlevel_y, ctrls->frame->quantization.qm_y); 2056 hantro_reg_write(vpu, &av1_qmlevel_u, ctrls->frame->quantization.qm_u); 2057 hantro_reg_write(vpu, &av1_qmlevel_v, ctrls->frame->quantization.qm_v); 2058 } else { 2059 hantro_reg_write(vpu, &av1_qmlevel_y, 0xff); 2060 hantro_reg_write(vpu, &av1_qmlevel_u, 0xff); 2061 hantro_reg_write(vpu, &av1_qmlevel_v, 0xff); 2062 } 2063 2064 hantro_reg_write(vpu, &av1_lossless_e, rockchip_vpu981_av1_dec_is_lossless(ctx)); 2065 hantro_reg_write(vpu, &av1_quant_delta_v_dc, ctrls->frame->quantization.delta_q_v_dc); 2066 hantro_reg_write(vpu, &av1_quant_delta_v_ac, ctrls->frame->quantization.delta_q_v_ac); 2067 2068 hantro_reg_write(vpu, &av1_skip_ref0, 2069 (ctrls->frame->skip_mode_frame[0]) ? ctrls->frame->skip_mode_frame[0] : 1); 2070 hantro_reg_write(vpu, &av1_skip_ref1, 2071 (ctrls->frame->skip_mode_frame[1]) ? ctrls->frame->skip_mode_frame[1] : 1); 2072 2073 hantro_write_addr(vpu, AV1_MC_SYNC_CURR, av1_dec->tile_buf.dma); 2074 hantro_write_addr(vpu, AV1_MC_SYNC_LEFT, av1_dec->tile_buf.dma); 2075} 2076 2077static void 2078rockchip_vpu981_av1_dec_set_input_buffer(struct hantro_ctx *ctx, 2079 struct vb2_v4l2_buffer *vb2_src) 2080{ 2081 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 2082 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 2083 const struct v4l2_ctrl_av1_tile_group_entry *group_entry = 2084 ctrls->tile_group_entry; 2085 struct hantro_dev *vpu = ctx->dev; 2086 dma_addr_t src_dma; 2087 u32 src_len, src_buf_len; 2088 int start_bit, offset; 2089 2090 src_dma = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); 2091 src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0); 2092 src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); 2093 2094 start_bit = (group_entry[0].tile_offset & 0xf) * 8; 2095 offset = group_entry[0].tile_offset & ~0xf; 2096 2097 hantro_reg_write(vpu, &av1_strm_buffer_len, src_buf_len); 2098 hantro_reg_write(vpu, &av1_strm_start_bit, start_bit); 2099 hantro_reg_write(vpu, &av1_stream_len, src_len); 2100 hantro_reg_write(vpu, &av1_strm_start_offset, 0); 2101 hantro_write_addr(vpu, AV1_INPUT_STREAM, src_dma + offset); 2102} 2103 2104static void 2105rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx) 2106{ 2107 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 2108 struct hantro_dev *vpu = ctx->dev; 2109 struct hantro_decoded_buffer *dst; 2110 struct vb2_v4l2_buffer *vb2_dst; 2111 dma_addr_t luma_addr, chroma_addr, mv_addr = 0; 2112 size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx); 2113 size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx); 2114 2115 vb2_dst = av1_dec->frame_refs[av1_dec->current_frame_index].vb2_ref; 2116 dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf); 2117 luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); 2118 chroma_addr = luma_addr + cr_offset; 2119 mv_addr = luma_addr + mv_offset; 2120 2121 dst->av1.chroma_offset = cr_offset; 2122 dst->av1.mv_offset = mv_offset; 2123 2124 hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr); 2125 hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr); 2126 hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr); 2127} 2128 2129int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx) 2130{ 2131 struct hantro_dev *vpu = ctx->dev; 2132 struct vb2_v4l2_buffer *vb2_src; 2133 int ret; 2134 2135 hantro_start_prepare_run(ctx); 2136 2137 ret = rockchip_vpu981_av1_dec_prepare_run(ctx); 2138 if (ret) 2139 goto prepare_error; 2140 2141 vb2_src = hantro_get_src_buf(ctx); 2142 if (!vb2_src) { 2143 ret = -EINVAL; 2144 goto prepare_error; 2145 } 2146 2147 rockchip_vpu981_av1_dec_clean_refs(ctx); 2148 rockchip_vpu981_av1_dec_frame_ref(ctx, vb2_src->vb2_buf.timestamp); 2149 2150 rockchip_vpu981_av1_dec_set_parameters(ctx); 2151 rockchip_vpu981_av1_dec_set_global_model(ctx); 2152 rockchip_vpu981_av1_dec_set_tile_info(ctx); 2153 rockchip_vpu981_av1_dec_set_reference_frames(ctx); 2154 rockchip_vpu981_av1_dec_set_segmentation(ctx); 2155 rockchip_vpu981_av1_dec_set_loopfilter(ctx); 2156 rockchip_vpu981_av1_dec_set_picture_dimensions(ctx); 2157 rockchip_vpu981_av1_dec_set_cdef(ctx); 2158 rockchip_vpu981_av1_dec_set_lr(ctx); 2159 rockchip_vpu981_av1_dec_set_fgs(ctx); 2160 rockchip_vpu981_av1_dec_set_prob(ctx); 2161 2162 hantro_reg_write(vpu, &av1_dec_mode, AV1_DEC_MODE); 2163 hantro_reg_write(vpu, &av1_dec_out_ec_byte_word, 0); 2164 hantro_reg_write(vpu, &av1_write_mvs_e, 1); 2165 hantro_reg_write(vpu, &av1_dec_out_ec_bypass, 1); 2166 hantro_reg_write(vpu, &av1_dec_clk_gate_e, 1); 2167 2168 hantro_reg_write(vpu, &av1_dec_abort_e, 0); 2169 hantro_reg_write(vpu, &av1_dec_tile_int_e, 0); 2170 2171 hantro_reg_write(vpu, &av1_dec_alignment, 64); 2172 hantro_reg_write(vpu, &av1_apf_disable, 0); 2173 hantro_reg_write(vpu, &av1_apf_threshold, 8); 2174 hantro_reg_write(vpu, &av1_dec_buswidth, 2); 2175 hantro_reg_write(vpu, &av1_dec_max_burst, 16); 2176 hantro_reg_write(vpu, &av1_error_conceal_e, 0); 2177 hantro_reg_write(vpu, &av1_axi_rd_ostd_threshold, 64); 2178 hantro_reg_write(vpu, &av1_axi_wr_ostd_threshold, 64); 2179 2180 hantro_reg_write(vpu, &av1_ext_timeout_cycles, 0xfffffff); 2181 hantro_reg_write(vpu, &av1_ext_timeout_override_e, 1); 2182 hantro_reg_write(vpu, &av1_timeout_cycles, 0xfffffff); 2183 hantro_reg_write(vpu, &av1_timeout_override_e, 1); 2184 2185 rockchip_vpu981_av1_dec_set_output_buffer(ctx); 2186 rockchip_vpu981_av1_dec_set_input_buffer(ctx, vb2_src); 2187 2188 hantro_end_prepare_run(ctx); 2189 2190 hantro_reg_write(vpu, &av1_dec_e, 1); 2191 2192 return 0; 2193 2194prepare_error: 2195 hantro_end_prepare_run(ctx); 2196 hantro_irq_done(vpu, VB2_BUF_STATE_ERROR); 2197 return ret; 2198} 2199 2200static void rockchip_vpu981_postproc_enable(struct hantro_ctx *ctx) 2201{ 2202 struct hantro_dev *vpu = ctx->dev; 2203 int width = ctx->dst_fmt.width; 2204 int height = ctx->dst_fmt.height; 2205 struct vb2_v4l2_buffer *vb2_dst; 2206 size_t chroma_offset; 2207 dma_addr_t dst_dma; 2208 2209 vb2_dst = hantro_get_dst_buf(ctx); 2210 2211 dst_dma = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); 2212 chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline * 2213 ctx->dst_fmt.height; 2214 2215 /* enable post processor */ 2216 hantro_reg_write(vpu, &av1_pp_out_e, 1); 2217 hantro_reg_write(vpu, &av1_pp_in_format, 0); 2218 hantro_reg_write(vpu, &av1_pp0_dup_hor, 1); 2219 hantro_reg_write(vpu, &av1_pp0_dup_ver, 1); 2220 2221 hantro_reg_write(vpu, &av1_pp_in_height, height / 2); 2222 hantro_reg_write(vpu, &av1_pp_in_width, width / 2); 2223 hantro_reg_write(vpu, &av1_pp_out_height, height); 2224 hantro_reg_write(vpu, &av1_pp_out_width, width); 2225 hantro_reg_write(vpu, &av1_pp_out_y_stride, 2226 ctx->dst_fmt.plane_fmt[0].bytesperline); 2227 hantro_reg_write(vpu, &av1_pp_out_c_stride, 2228 ctx->dst_fmt.plane_fmt[0].bytesperline); 2229 switch (ctx->dst_fmt.pixelformat) { 2230 case V4L2_PIX_FMT_P010: 2231 hantro_reg_write(vpu, &av1_pp_out_format, 1); 2232 break; 2233 case V4L2_PIX_FMT_NV12: 2234 hantro_reg_write(vpu, &av1_pp_out_format, 3); 2235 break; 2236 case V4L2_PIX_FMT_NV15: 2237 /* this mapping is RK specific */ 2238 hantro_reg_write(vpu, &av1_pp_out_format, 10); 2239 break; 2240 default: 2241 hantro_reg_write(vpu, &av1_pp_out_format, 0); 2242 } 2243 2244 hantro_reg_write(vpu, &av1_ppd_blend_exist, 0); 2245 hantro_reg_write(vpu, &av1_ppd_dith_exist, 0); 2246 hantro_reg_write(vpu, &av1_ablend_crop_e, 0); 2247 hantro_reg_write(vpu, &av1_pp_format_customer1_e, 0); 2248 hantro_reg_write(vpu, &av1_pp_crop_exist, 0); 2249 hantro_reg_write(vpu, &av1_pp_up_level, 0); 2250 hantro_reg_write(vpu, &av1_pp_down_level, 0); 2251 hantro_reg_write(vpu, &av1_pp_exist, 0); 2252 2253 hantro_write_addr(vpu, AV1_PP_OUT_LU, dst_dma); 2254 hantro_write_addr(vpu, AV1_PP_OUT_CH, dst_dma + chroma_offset); 2255} 2256 2257static void rockchip_vpu981_postproc_disable(struct hantro_ctx *ctx) 2258{ 2259 struct hantro_dev *vpu = ctx->dev; 2260 2261 /* disable post processor */ 2262 hantro_reg_write(vpu, &av1_pp_out_e, 0); 2263} 2264 2265const struct hantro_postproc_ops rockchip_vpu981_postproc_ops = { 2266 .enable = rockchip_vpu981_postproc_enable, 2267 .disable = rockchip_vpu981_postproc_disable, 2268};
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