hantro.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Hantro VPU codec driver
  4 *
  5 * Copyright 2018 Google LLC.
  6 *	Tomasz Figa <tfiga@chromium.org>
  7 *
  8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
  9 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
 10 */
 11
 12#ifndef HANTRO_H_
 13#define HANTRO_H_
 14
 15#include <linux/platform_device.h>
 16#include <linux/videodev2.h>
 17#include <linux/wait.h>
 18#include <linux/clk.h>
 19#include <linux/reset.h>
 20
 21#include <media/v4l2-ctrls.h>
 22#include <media/v4l2-device.h>
 23#include <media/v4l2-ioctl.h>
 24#include <media/v4l2-mem2mem.h>
 25#include <media/videobuf2-core.h>
 26#include <media/videobuf2-dma-contig.h>
 27
 28#include "hantro_hw.h"
 29
 30struct hantro_ctx;
 31struct hantro_codec_ops;
 32struct hantro_postproc_ops;
 33
 34#define HANTRO_JPEG_ENCODER	BIT(0)
 35#define HANTRO_ENCODERS		0x0000ffff
 36#define HANTRO_MPEG2_DECODER	BIT(16)
 37#define HANTRO_VP8_DECODER	BIT(17)
 38#define HANTRO_H264_DECODER	BIT(18)
 39#define HANTRO_HEVC_DECODER	BIT(19)
 40#define HANTRO_VP9_DECODER	BIT(20)
 41#define HANTRO_AV1_DECODER	BIT(21)
 42#define HANTRO_DECODERS		0xffff0000
 43
 44/**
 45 * struct hantro_irq - irq handler and name
 46 *
 47 * @name:			irq name for device tree lookup
 48 * @handler:			interrupt handler
 49 */
 50struct hantro_irq {
 51	const char *name;
 52	irqreturn_t (*handler)(int irq, void *priv);
 53};
 54
 55/**
 56 * struct hantro_variant - information about VPU hardware variant
 57 *
 58 * @enc_offset:			Offset from VPU base to encoder registers.
 59 * @dec_offset:			Offset from VPU base to decoder registers.
 60 * @enc_fmts:			Encoder formats.
 61 * @num_enc_fmts:		Number of encoder formats.
 62 * @dec_fmts:			Decoder formats.
 63 * @num_dec_fmts:		Number of decoder formats.
 64 * @postproc_fmts:		Post-processor formats.
 65 * @num_postproc_fmts:		Number of post-processor formats.
 66 * @postproc_ops:		Post-processor ops.
 67 * @codec:			Supported codecs
 68 * @codec_ops:			Codec ops.
 69 * @init:			Initialize hardware, optional.
 70 * @runtime_resume:		reenable hardware after power gating, optional.
 71 * @irqs:			array of irq names and interrupt handlers
 72 * @num_irqs:			number of irqs in the array
 73 * @clk_names:			array of clock names
 74 * @num_clocks:			number of clocks in the array
 75 * @reg_names:			array of register range names
 76 * @num_regs:			number of register range names in the array
 77 * @double_buffer:		core needs double buffering
 78 * @legacy_regs:		core uses legacy register set
 79 * @late_postproc:		postproc must be set up at the end of the job
 80 * @shared_devices:		an array of device ids that cannot run concurrently
 81 */
 82struct hantro_variant {
 83	unsigned int enc_offset;
 84	unsigned int dec_offset;
 85	const struct hantro_fmt *enc_fmts;
 86	unsigned int num_enc_fmts;
 87	const struct hantro_fmt *dec_fmts;
 88	unsigned int num_dec_fmts;
 89	const struct hantro_fmt *postproc_fmts;
 90	unsigned int num_postproc_fmts;
 91	const struct hantro_postproc_ops *postproc_ops;
 92	unsigned int codec;
 93	const struct hantro_codec_ops *codec_ops;
 94	int (*init)(struct hantro_dev *vpu);
 95	int (*runtime_resume)(struct hantro_dev *vpu);
 96	const struct hantro_irq *irqs;
 97	int num_irqs;
 98	const char * const *clk_names;
 99	int num_clocks;
100	const char * const *reg_names;
101	int num_regs;
102	unsigned int double_buffer : 1;
103	unsigned int legacy_regs : 1;
104	unsigned int late_postproc : 1;
105	const struct of_device_id *shared_devices;
106};
107
108/**
109 * enum hantro_codec_mode - codec operating mode.
110 * @HANTRO_MODE_NONE:  No operating mode. Used for RAW video formats.
111 * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
112 * @HANTRO_MODE_H264_DEC: H264 decoder.
113 * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
114 * @HANTRO_MODE_VP8_DEC: VP8 decoder.
115 * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
116 * @HANTRO_MODE_VP9_DEC: VP9 decoder.
117 * @HANTRO_MODE_AV1_DEC: AV1 decoder
118 */
119enum hantro_codec_mode {
120	HANTRO_MODE_NONE = -1,
121	HANTRO_MODE_JPEG_ENC,
122	HANTRO_MODE_H264_DEC,
123	HANTRO_MODE_MPEG2_DEC,
124	HANTRO_MODE_VP8_DEC,
125	HANTRO_MODE_HEVC_DEC,
126	HANTRO_MODE_VP9_DEC,
127	HANTRO_MODE_AV1_DEC,
128};
129
130/*
131 * struct hantro_ctrl - helper type to declare supported controls
132 * @codec:	codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
133 * @cfg:	control configuration
134 */
135struct hantro_ctrl {
136	unsigned int codec;
137	struct v4l2_ctrl_config cfg;
138};
139
140/*
141 * struct hantro_func - Hantro VPU functionality
142 *
143 * @id:			processing functionality ID (can be
144 *			%MEDIA_ENT_F_PROC_VIDEO_ENCODER or
145 *			%MEDIA_ENT_F_PROC_VIDEO_DECODER)
146 * @vdev:		&struct video_device that exposes the encoder or
147 *			decoder functionality
148 * @source_pad:		&struct media_pad with the source pad.
149 * @sink:		&struct media_entity pointer with the sink entity
150 * @sink_pad:		&struct media_pad with the sink pad.
151 * @proc:		&struct media_entity pointer with the M2M device itself.
152 * @proc_pads:		&struct media_pad with the @proc pads.
153 * @intf_devnode:	&struct media_intf devnode pointer with the interface
154 *			with controls the M2M device.
155 *
156 * Contains everything needed to attach the video device to the media device.
157 */
158struct hantro_func {
159	unsigned int id;
160	struct video_device vdev;
161	struct media_pad source_pad;
162	struct media_entity sink;
163	struct media_pad sink_pad;
164	struct media_entity proc;
165	struct media_pad proc_pads[2];
166	struct media_intf_devnode *intf_devnode;
167};
168
169static inline struct hantro_func *
170hantro_vdev_to_func(struct video_device *vdev)
171{
172	return container_of(vdev, struct hantro_func, vdev);
173}
174
175/**
176 * struct hantro_dev - driver data
177 * @v4l2_dev:		V4L2 device to register video devices for.
178 * @m2m_dev:		mem2mem device associated to this device.
179 * @mdev:		media device associated to this device.
180 * @encoder:		encoder functionality.
181 * @decoder:		decoder functionality.
182 * @pdev:		Pointer to VPU platform device.
183 * @dev:		Pointer to device for convenient logging using
184 *			dev_ macros.
185 * @clocks:		Array of clock handles.
186 * @resets:		Array of reset handles.
187 * @reg_bases:		Mapped addresses of VPU registers.
188 * @enc_base:		Mapped address of VPU encoder register for convenience.
189 * @dec_base:		Mapped address of VPU decoder register for convenience.
190 * @ctrl_base:		Mapped address of VPU control block.
191 * @vpu_mutex:		Mutex to synchronize V4L2 calls.
192 * @irqlock:		Spinlock to synchronize access to data structures
193 *			shared with interrupt handlers.
194 * @variant:		Hardware variant-specific parameters.
195 * @watchdog_work:	Delayed work for hardware timeout handling.
196 */
197struct hantro_dev {
198	struct v4l2_device v4l2_dev;
199	struct v4l2_m2m_dev *m2m_dev;
200	struct media_device mdev;
201	struct hantro_func *encoder;
202	struct hantro_func *decoder;
203	struct platform_device *pdev;
204	struct device *dev;
205	struct clk_bulk_data *clocks;
206	struct reset_control *resets;
207	void __iomem **reg_bases;
208	void __iomem *enc_base;
209	void __iomem *dec_base;
210	void __iomem *ctrl_base;
211
212	struct mutex vpu_mutex;	/* video_device lock */
213	spinlock_t irqlock;
214	const struct hantro_variant *variant;
215	struct delayed_work watchdog_work;
216};
217
218/**
219 * struct hantro_ctx - Context (instance) private data.
220 *
221 * @dev:		VPU driver data to which the context belongs.
222 * @fh:			V4L2 file handler.
223 * @is_encoder:		Decoder or encoder context?
224 *
225 * @sequence_cap:       Sequence counter for capture queue
226 * @sequence_out:       Sequence counter for output queue
227 *
228 * @vpu_src_fmt:	Descriptor of active source format.
229 * @src_fmt:		V4L2 pixel format of active source format.
230 * @vpu_dst_fmt:	Descriptor of active destination format.
231 * @dst_fmt:		V4L2 pixel format of active destination format.
232 * @ref_fmt:		V4L2 pixel format of the reference frames format.
233 *
234 * @ctrl_handler:	Control handler used to register controls.
235 * @jpeg_quality:	User-specified JPEG compression quality.
236 * @bit_depth:		Bit depth of current frame
237 * @need_postproc:	Set to true if the bitstream features require to
238 *			use the post-processor.
239 *
240 * @codec_ops:		Set of operations related to codec mode.
241 * @postproc:		Post-processing context.
242 * @h264_dec:		H.264-decoding context.
243 * @mpeg2_dec:		MPEG-2-decoding context.
244 * @vp8_dec:		VP8-decoding context.
245 * @hevc_dec:		HEVC-decoding context.
246 * @vp9_dec:		VP9-decoding context.
247 * @av1_dec:		AV1-decoding context.
248 */
249struct hantro_ctx {
250	struct hantro_dev *dev;
251	struct v4l2_fh fh;
252	bool is_encoder;
253
254	u32 sequence_cap;
255	u32 sequence_out;
256
257	const struct hantro_fmt *vpu_src_fmt;
258	struct v4l2_pix_format_mplane src_fmt;
259	const struct hantro_fmt *vpu_dst_fmt;
260	struct v4l2_pix_format_mplane dst_fmt;
261	struct v4l2_pix_format_mplane ref_fmt;
262
263	struct v4l2_ctrl_handler ctrl_handler;
264	int jpeg_quality;
265	int bit_depth;
266
267	const struct hantro_codec_ops *codec_ops;
268	struct hantro_postproc_ctx postproc;
269	bool need_postproc;
270
271	/* Specific for particular codec modes. */
272	union {
273		struct hantro_h264_dec_hw_ctx h264_dec;
274		struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
275		struct hantro_vp8_dec_hw_ctx vp8_dec;
276		struct hantro_hevc_dec_hw_ctx hevc_dec;
277		struct hantro_vp9_dec_hw_ctx vp9_dec;
278		struct hantro_av1_dec_hw_ctx av1_dec;
279	};
280};
281
282/**
283 * struct hantro_fmt - information about supported video formats.
284 * @name:	Human readable name of the format.
285 * @fourcc:	FourCC code of the format. See V4L2_PIX_FMT_*.
286 * @codec_mode:	Codec mode related to this format. See
287 *		enum hantro_codec_mode.
288 * @header_size: Optional header size. Currently used by JPEG encoder.
289 * @max_depth:	Maximum depth, for bitstream formats
290 * @enc_fmt:	Format identifier for encoder registers.
291 * @frmsize:	Supported range of frame sizes (only for bitstream formats).
292 * @postprocessed: Indicates if this format needs the post-processor.
293 * @match_depth: Indicates if format bit depth must match video bit depth
294 */
295struct hantro_fmt {
296	char *name;
297	u32 fourcc;
298	enum hantro_codec_mode codec_mode;
299	int header_size;
300	int max_depth;
301	enum hantro_enc_fmt enc_fmt;
302	struct v4l2_frmsize_stepwise frmsize;
303	bool postprocessed;
304	bool match_depth;
305};
306
307struct hantro_reg {
308	u32 base;
309	u32 shift;
310	u32 mask;
311};
312
313struct hantro_postproc_regs {
314	struct hantro_reg pipeline_en;
315	struct hantro_reg max_burst;
316	struct hantro_reg clk_gate;
317	struct hantro_reg out_swap32;
318	struct hantro_reg out_endian;
319	struct hantro_reg out_luma_base;
320	struct hantro_reg input_width;
321	struct hantro_reg input_height;
322	struct hantro_reg output_width;
323	struct hantro_reg output_height;
324	struct hantro_reg input_fmt;
325	struct hantro_reg output_fmt;
326	struct hantro_reg orig_width;
327	struct hantro_reg display_width;
328	struct hantro_reg input_width_ext;
329	struct hantro_reg input_height_ext;
330};
331
332struct hantro_vp9_decoded_buffer_info {
333	/* Info needed when the decoded frame serves as a reference frame. */
334	unsigned short width;
335	unsigned short height;
336	size_t chroma_offset;
337	size_t mv_offset;
338	u32 bit_depth : 4;
339};
340
341struct hantro_av1_decoded_buffer_info {
342	/* Info needed when the decoded frame serves as a reference frame. */
343	size_t chroma_offset;
344	size_t mv_offset;
345};
346
347struct hantro_decoded_buffer {
348	/* Must be the first field in this struct. */
349	struct v4l2_m2m_buffer base;
350
351	union {
352		struct hantro_vp9_decoded_buffer_info vp9;
353		struct hantro_av1_decoded_buffer_info av1;
354	};
355};
356
357/* Logging helpers */
358
359/**
360 * DOC: hantro_debug: Module parameter to control level of debugging messages.
361 *
362 * Level of debugging messages can be controlled by bits of
363 * module parameter called "debug". Meaning of particular
364 * bits is as follows:
365 *
366 * bit 0 - global information: mode, size, init, release
367 * bit 1 - each run start/result information
368 * bit 2 - contents of small controls from userspace
369 * bit 3 - contents of big controls from userspace
370 * bit 4 - detail fmt, ctrl, buffer q/dq information
371 * bit 5 - detail function enter/leave trace information
372 * bit 6 - register write/read information
373 */
374extern int hantro_debug;
375
376#define vpu_debug(level, fmt, args...)				\
377	do {							\
378		if (hantro_debug & BIT(level))		\
379			pr_info("%s:%d: " fmt,	                \
380				 __func__, __LINE__, ##args);	\
381	} while (0)
382
383#define vpu_err(fmt, args...)					\
384	pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
385
386/* Structure access helpers. */
387static __always_inline struct hantro_ctx *file_to_ctx(struct file *filp)
388{
389	return container_of(file_to_v4l2_fh(filp), struct hantro_ctx, fh);
390}
391
392/* Register accessors. */
393static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu,
394					       u32 val, u32 reg)
395{
396	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
397	writel_relaxed(val, vpu->enc_base + reg);
398}
399
400static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
401{
402	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
403	writel(val, vpu->enc_base + reg);
404}
405
406static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
407{
408	u32 val = readl(vpu->enc_base + reg);
409
410	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
411	return val;
412}
413
414static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu,
415					       u32 val, u32 reg)
416{
417	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
418	writel_relaxed(val, vpu->dec_base + reg);
419}
420
421static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
422{
423	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
424	writel(val, vpu->dec_base + reg);
425}
426
427static __always_inline void hantro_write_addr(struct hantro_dev *vpu,
428					      unsigned long offset,
429					      dma_addr_t addr)
430{
431	vdpu_write(vpu, addr & 0xffffffff, offset);
432}
433
434static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
435{
436	u32 val = readl(vpu->dec_base + reg);
437
438	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
439	return val;
440}
441
442static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu,
443					  const struct hantro_reg *reg,
444					  u32 val)
445{
446	u32 v;
447
448	v = vdpu_read(vpu, reg->base);
449	v &= ~(reg->mask << reg->shift);
450	v |= ((val & reg->mask) << reg->shift);
451	return v;
452}
453
454static __always_inline void hantro_reg_write(struct hantro_dev *vpu,
455					     const struct hantro_reg *reg,
456					     u32 val)
457{
458	vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
459}
460
461static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu,
462						     const struct hantro_reg *reg,
463						     u32 val)
464{
465	vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
466}
467
468void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
469dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
470
471static inline struct vb2_v4l2_buffer *
472hantro_get_src_buf(struct hantro_ctx *ctx)
473{
474	return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
475}
476
477static inline struct vb2_v4l2_buffer *
478hantro_get_dst_buf(struct hantro_ctx *ctx)
479{
480	return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
481}
482
483bool hantro_needs_postproc(const struct hantro_ctx *ctx,
484			   const struct hantro_fmt *fmt);
485
486dma_addr_t
487hantro_postproc_get_dec_buf_addr(struct hantro_ctx *ctx, int index);
488
489static inline dma_addr_t
490hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
491{
492	if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
493		return hantro_postproc_get_dec_buf_addr(ctx, vb->index);
494	return vb2_dma_contig_plane_dma_addr(vb, 0);
495}
496
497static inline struct hantro_decoded_buffer *
498vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)
499{
500	return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);
501}
502
503void hantro_postproc_disable(struct hantro_ctx *ctx);
504void hantro_postproc_enable(struct hantro_ctx *ctx);
505int hantro_postproc_init(struct hantro_ctx *ctx);
506void hantro_postproc_free(struct hantro_ctx *ctx);
507int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
508				   struct v4l2_frmsizeenum *fsize);
509
510#endif /* HANTRO_H_ */