vpe.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
   4 *
   5 * Copyright (c) 2013 Texas Instruments Inc.
   6 * David Griego, <dagriego@biglakesoftware.com>
   7 * Dale Farnsworth, <dale@farnsworth.org>
   8 * Archit Taneja, <archit@ti.com>
   9 *
  10 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  11 * Pawel Osciak, <pawel@osciak.com>
  12 * Marek Szyprowski, <m.szyprowski@samsung.com>
  13 *
  14 * Based on the virtual v4l2-mem2mem example device
  15 */
  16
  17#include <linux/delay.h>
  18#include <linux/dma-mapping.h>
  19#include <linux/err.h>
  20#include <linux/fs.h>
  21#include <linux/interrupt.h>
  22#include <linux/io.h>
  23#include <linux/ioctl.h>
  24#include <linux/module.h>
  25#include <linux/of.h>
  26#include <linux/platform_device.h>
  27#include <linux/pm_runtime.h>
  28#include <linux/sched.h>
  29#include <linux/slab.h>
  30#include <linux/videodev2.h>
  31#include <linux/log2.h>
  32#include <linux/sizes.h>
  33
  34#include <media/v4l2-common.h>
  35#include <media/v4l2-ctrls.h>
  36#include <media/v4l2-device.h>
  37#include <media/v4l2-event.h>
  38#include <media/v4l2-ioctl.h>
  39#include <media/v4l2-mem2mem.h>
  40#include <media/videobuf2-v4l2.h>
  41#include <media/videobuf2-dma-contig.h>
  42
  43#include "vpdma.h"
  44#include "vpdma_priv.h"
  45#include "vpe_regs.h"
  46#include "sc.h"
  47#include "csc.h"
  48
  49#define VPE_MODULE_NAME "vpe"
  50
  51/* minimum and maximum frame sizes */
  52#define MIN_W		32
  53#define MIN_H		32
  54#define MAX_W		2048
  55#define MAX_H		2048
  56
  57/* required alignments */
  58#define S_ALIGN		0	/* multiple of 1 */
  59#define H_ALIGN		1	/* multiple of 2 */
  60
  61/* flags that indicate a format can be used for capture/output */
  62#define VPE_FMT_TYPE_CAPTURE	(1 << 0)
  63#define VPE_FMT_TYPE_OUTPUT	(1 << 1)
  64
  65/* used as plane indices */
  66#define VPE_MAX_PLANES	2
  67#define VPE_LUMA	0
  68#define VPE_CHROMA	1
  69
  70/* per m2m context info */
  71#define VPE_MAX_SRC_BUFS	3	/* need 3 src fields to de-interlace */
  72
  73#define VPE_DEF_BUFS_PER_JOB	1	/* default one buffer per batch job */
  74
  75/*
  76 * each VPE context can need up to 3 config descriptors, 7 input descriptors,
  77 * 3 output descriptors, and 10 control descriptors
  78 */
  79#define VPE_DESC_LIST_SIZE	(10 * VPDMA_DTD_DESC_SIZE +	\
  80					13 * VPDMA_CFD_CTD_DESC_SIZE)
  81
  82#define vpe_dbg(vpedev, fmt, arg...)	\
  83		dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
  84#define vpe_err(vpedev, fmt, arg...)	\
  85		dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
  86
  87struct vpe_us_coeffs {
  88	unsigned short	anchor_fid0_c0;
  89	unsigned short	anchor_fid0_c1;
  90	unsigned short	anchor_fid0_c2;
  91	unsigned short	anchor_fid0_c3;
  92	unsigned short	interp_fid0_c0;
  93	unsigned short	interp_fid0_c1;
  94	unsigned short	interp_fid0_c2;
  95	unsigned short	interp_fid0_c3;
  96	unsigned short	anchor_fid1_c0;
  97	unsigned short	anchor_fid1_c1;
  98	unsigned short	anchor_fid1_c2;
  99	unsigned short	anchor_fid1_c3;
 100	unsigned short	interp_fid1_c0;
 101	unsigned short	interp_fid1_c1;
 102	unsigned short	interp_fid1_c2;
 103	unsigned short	interp_fid1_c3;
 104};
 105
 106/*
 107 * Default upsampler coefficients
 108 */
 109static const struct vpe_us_coeffs us_coeffs[] = {
 110	{
 111		/* Coefficients for progressive input */
 112		0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
 113		0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
 114	},
 115	{
 116		/* Coefficients for Top Field Interlaced input */
 117		0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
 118		/* Coefficients for Bottom Field Interlaced input */
 119		0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
 120	},
 121};
 122
 123/*
 124 * the following registers are for configuring some of the parameters of the
 125 * motion and edge detection blocks inside DEI, these generally remain the same,
 126 * these could be passed later via userspace if some one needs to tweak these.
 127 */
 128struct vpe_dei_regs {
 129	unsigned long mdt_spacial_freq_thr_reg;		/* VPE_DEI_REG2 */
 130	unsigned long edi_config_reg;			/* VPE_DEI_REG3 */
 131	unsigned long edi_lut_reg0;			/* VPE_DEI_REG4 */
 132	unsigned long edi_lut_reg1;			/* VPE_DEI_REG5 */
 133	unsigned long edi_lut_reg2;			/* VPE_DEI_REG6 */
 134	unsigned long edi_lut_reg3;			/* VPE_DEI_REG7 */
 135};
 136
 137/*
 138 * default expert DEI register values, unlikely to be modified.
 139 */
 140static const struct vpe_dei_regs dei_regs = {
 141	.mdt_spacial_freq_thr_reg = 0x020C0804u,
 142	.edi_config_reg = 0x0118100Cu,
 143	.edi_lut_reg0 = 0x08040200u,
 144	.edi_lut_reg1 = 0x1010100Cu,
 145	.edi_lut_reg2 = 0x10101010u,
 146	.edi_lut_reg3 = 0x10101010u,
 147};
 148
 149/*
 150 * The port_data structure contains per-port data.
 151 */
 152struct vpe_port_data {
 153	enum vpdma_channel channel;	/* VPDMA channel */
 154	u8	vb_index;		/* input frame f, f-1, f-2 index */
 155	u8	vb_part;		/* plane index for co-panar formats */
 156};
 157
 158/*
 159 * Define indices into the port_data tables
 160 */
 161#define VPE_PORT_LUMA1_IN	0
 162#define VPE_PORT_CHROMA1_IN	1
 163#define VPE_PORT_LUMA2_IN	2
 164#define VPE_PORT_CHROMA2_IN	3
 165#define VPE_PORT_LUMA3_IN	4
 166#define VPE_PORT_CHROMA3_IN	5
 167#define VPE_PORT_MV_IN		6
 168#define VPE_PORT_MV_OUT		7
 169#define VPE_PORT_LUMA_OUT	8
 170#define VPE_PORT_CHROMA_OUT	9
 171#define VPE_PORT_RGB_OUT	10
 172
 173static const struct vpe_port_data port_data[11] = {
 174	[VPE_PORT_LUMA1_IN] = {
 175		.channel	= VPE_CHAN_LUMA1_IN,
 176		.vb_index	= 0,
 177		.vb_part	= VPE_LUMA,
 178	},
 179	[VPE_PORT_CHROMA1_IN] = {
 180		.channel	= VPE_CHAN_CHROMA1_IN,
 181		.vb_index	= 0,
 182		.vb_part	= VPE_CHROMA,
 183	},
 184	[VPE_PORT_LUMA2_IN] = {
 185		.channel	= VPE_CHAN_LUMA2_IN,
 186		.vb_index	= 1,
 187		.vb_part	= VPE_LUMA,
 188	},
 189	[VPE_PORT_CHROMA2_IN] = {
 190		.channel	= VPE_CHAN_CHROMA2_IN,
 191		.vb_index	= 1,
 192		.vb_part	= VPE_CHROMA,
 193	},
 194	[VPE_PORT_LUMA3_IN] = {
 195		.channel	= VPE_CHAN_LUMA3_IN,
 196		.vb_index	= 2,
 197		.vb_part	= VPE_LUMA,
 198	},
 199	[VPE_PORT_CHROMA3_IN] = {
 200		.channel	= VPE_CHAN_CHROMA3_IN,
 201		.vb_index	= 2,
 202		.vb_part	= VPE_CHROMA,
 203	},
 204	[VPE_PORT_MV_IN] = {
 205		.channel	= VPE_CHAN_MV_IN,
 206	},
 207	[VPE_PORT_MV_OUT] = {
 208		.channel	= VPE_CHAN_MV_OUT,
 209	},
 210	[VPE_PORT_LUMA_OUT] = {
 211		.channel	= VPE_CHAN_LUMA_OUT,
 212		.vb_part	= VPE_LUMA,
 213	},
 214	[VPE_PORT_CHROMA_OUT] = {
 215		.channel	= VPE_CHAN_CHROMA_OUT,
 216		.vb_part	= VPE_CHROMA,
 217	},
 218	[VPE_PORT_RGB_OUT] = {
 219		.channel	= VPE_CHAN_RGB_OUT,
 220		.vb_part	= VPE_LUMA,
 221	},
 222};
 223
 224
 225/* driver info for each of the supported video formats */
 226struct vpe_fmt {
 227	u32	fourcc;			/* standard format identifier */
 228	u8	types;			/* CAPTURE and/or OUTPUT */
 229	u8	coplanar;		/* set for unpacked Luma and Chroma */
 230	/* vpdma format info for each plane */
 231	struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
 232};
 233
 234static struct vpe_fmt vpe_formats[] = {
 235	{
 236		.fourcc		= V4L2_PIX_FMT_NV16,
 237		.types		= VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
 238		.coplanar	= 1,
 239		.vpdma_fmt	= { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
 240				    &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
 241				  },
 242	},
 243	{
 244		.fourcc		= V4L2_PIX_FMT_NV12,
 245		.types		= VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
 246		.coplanar	= 1,
 247		.vpdma_fmt	= { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
 248				    &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
 249				  },
 250	},
 251	{
 252		.fourcc		= V4L2_PIX_FMT_NV21,
 253		.types		= VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
 254		.coplanar	= 1,
 255		.vpdma_fmt	= { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
 256				    &vpdma_yuv_fmts[VPDMA_DATA_FMT_CB420],
 257				  },
 258	},
 259	{
 260		.fourcc		= V4L2_PIX_FMT_YUYV,
 261		.types		= VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
 262		.coplanar	= 0,
 263		.vpdma_fmt	= { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
 264				  },
 265	},
 266	{
 267		.fourcc		= V4L2_PIX_FMT_UYVY,
 268		.types		= VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
 269		.coplanar	= 0,
 270		.vpdma_fmt	= { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
 271				  },
 272	},
 273	{
 274		.fourcc		= V4L2_PIX_FMT_RGB24,
 275		.types		= VPE_FMT_TYPE_CAPTURE,
 276		.coplanar	= 0,
 277		.vpdma_fmt	= { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
 278				  },
 279	},
 280	{
 281		.fourcc		= V4L2_PIX_FMT_RGB32,
 282		.types		= VPE_FMT_TYPE_CAPTURE,
 283		.coplanar	= 0,
 284		.vpdma_fmt	= { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
 285				  },
 286	},
 287	{
 288		.fourcc		= V4L2_PIX_FMT_BGR24,
 289		.types		= VPE_FMT_TYPE_CAPTURE,
 290		.coplanar	= 0,
 291		.vpdma_fmt	= { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
 292				  },
 293	},
 294	{
 295		.fourcc		= V4L2_PIX_FMT_BGR32,
 296		.types		= VPE_FMT_TYPE_CAPTURE,
 297		.coplanar	= 0,
 298		.vpdma_fmt	= { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
 299				  },
 300	},
 301	{
 302		.fourcc		= V4L2_PIX_FMT_RGB565,
 303		.types		= VPE_FMT_TYPE_CAPTURE,
 304		.coplanar	= 0,
 305		.vpdma_fmt	= { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565],
 306				  },
 307	},
 308	{
 309		.fourcc		= V4L2_PIX_FMT_RGB555,
 310		.types		= VPE_FMT_TYPE_CAPTURE,
 311		.coplanar	= 0,
 312		.vpdma_fmt	= { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551],
 313				  },
 314	},
 315};
 316
 317/*
 318 * per-queue, driver-specific private data.
 319 * there is one source queue and one destination queue for each m2m context.
 320 */
 321struct vpe_q_data {
 322	/* current v4l2 format info */
 323	struct v4l2_format	format;
 324	unsigned int		flags;
 325	struct v4l2_rect	c_rect;				/* crop/compose rectangle */
 326	struct vpe_fmt		*fmt;				/* format info */
 327};
 328
 329/* vpe_q_data flag bits */
 330#define	Q_DATA_FRAME_1D			BIT(0)
 331#define	Q_DATA_MODE_TILED		BIT(1)
 332#define	Q_DATA_INTERLACED_ALTERNATE	BIT(2)
 333#define	Q_DATA_INTERLACED_SEQ_TB	BIT(3)
 334#define	Q_DATA_INTERLACED_SEQ_BT	BIT(4)
 335
 336#define Q_IS_SEQ_XX		(Q_DATA_INTERLACED_SEQ_TB | \
 337				Q_DATA_INTERLACED_SEQ_BT)
 338
 339#define Q_IS_INTERLACED		(Q_DATA_INTERLACED_ALTERNATE | \
 340				Q_DATA_INTERLACED_SEQ_TB | \
 341				Q_DATA_INTERLACED_SEQ_BT)
 342
 343enum {
 344	Q_DATA_SRC = 0,
 345	Q_DATA_DST = 1,
 346};
 347
 348/* find our format description corresponding to the passed v4l2_format */
 349static struct vpe_fmt *__find_format(u32 fourcc)
 350{
 351	struct vpe_fmt *fmt;
 352	unsigned int k;
 353
 354	for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
 355		fmt = &vpe_formats[k];
 356		if (fmt->fourcc == fourcc)
 357			return fmt;
 358	}
 359
 360	return NULL;
 361}
 362
 363static struct vpe_fmt *find_format(struct v4l2_format *f)
 364{
 365	return __find_format(f->fmt.pix.pixelformat);
 366}
 367
 368/*
 369 * there is one vpe_dev structure in the driver, it is shared by
 370 * all instances.
 371 */
 372struct vpe_dev {
 373	struct v4l2_device	v4l2_dev;
 374	struct video_device	vfd;
 375	struct v4l2_m2m_dev	*m2m_dev;
 376
 377	atomic_t		num_instances;	/* count of driver instances */
 378	dma_addr_t		loaded_mmrs;	/* shadow mmrs in device */
 379	struct mutex		dev_mutex;
 380	spinlock_t		lock;
 381
 382	int			irq;
 383	void __iomem		*base;
 384	struct resource		*res;
 385
 386	struct vpdma_data	vpdma_data;
 387	struct vpdma_data	*vpdma;		/* vpdma data handle */
 388	struct sc_data		*sc;		/* scaler data handle */
 389	struct csc_data		*csc;		/* csc data handle */
 390};
 391
 392/*
 393 * There is one vpe_ctx structure for each m2m context.
 394 */
 395struct vpe_ctx {
 396	struct v4l2_fh		fh;
 397	struct vpe_dev		*dev;
 398	struct v4l2_ctrl_handler hdl;
 399
 400	unsigned int		field;			/* current field */
 401	unsigned int		sequence;		/* current frame/field seq */
 402	unsigned int		aborting;		/* abort after next irq */
 403
 404	unsigned int		bufs_per_job;		/* input buffers per batch */
 405	unsigned int		bufs_completed;		/* bufs done in this batch */
 406
 407	struct vpe_q_data	q_data[2];		/* src & dst queue data */
 408	struct vb2_v4l2_buffer	*src_vbs[VPE_MAX_SRC_BUFS];
 409	struct vb2_v4l2_buffer	*dst_vb;
 410
 411	dma_addr_t		mv_buf_dma[2];		/* dma addrs of motion vector in/out bufs */
 412	void			*mv_buf[2];		/* virtual addrs of motion vector bufs */
 413	size_t			mv_buf_size;		/* current motion vector buffer size */
 414	struct vpdma_buf	mmr_adb;		/* shadow reg addr/data block */
 415	struct vpdma_buf	sc_coeff_h;		/* h coeff buffer */
 416	struct vpdma_buf	sc_coeff_v;		/* v coeff buffer */
 417	struct vpdma_desc_list	desc_list;		/* DMA descriptor list */
 418
 419	bool			deinterlacing;		/* using de-interlacer */
 420	bool			load_mmrs;		/* have new shadow reg values */
 421
 422	unsigned int		src_mv_buf_selector;
 423};
 424
 425static inline struct vpe_ctx *to_vpe_ctx(struct file *filp)
 426{
 427	return container_of(file_to_v4l2_fh(filp), struct vpe_ctx, fh);
 428}
 429
 430/*
 431 * M2M devices get 2 queues.
 432 * Return the queue given the type.
 433 */
 434static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
 435				     enum v4l2_buf_type type)
 436{
 437	switch (type) {
 438	case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
 439	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
 440		return &ctx->q_data[Q_DATA_SRC];
 441	case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
 442	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
 443		return &ctx->q_data[Q_DATA_DST];
 444	default:
 445		return NULL;
 446	}
 447	return NULL;
 448}
 449
 450static u32 read_reg(struct vpe_dev *dev, int offset)
 451{
 452	return ioread32(dev->base + offset);
 453}
 454
 455static void write_reg(struct vpe_dev *dev, int offset, u32 value)
 456{
 457	iowrite32(value, dev->base + offset);
 458}
 459
 460/* register field read/write helpers */
 461static int get_field(u32 value, u32 mask, int shift)
 462{
 463	return (value & (mask << shift)) >> shift;
 464}
 465
 466static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
 467{
 468	return get_field(read_reg(dev, offset), mask, shift);
 469}
 470
 471static void write_field(u32 *valp, u32 field, u32 mask, int shift)
 472{
 473	u32 val = *valp;
 474
 475	val &= ~(mask << shift);
 476	val |= (field & mask) << shift;
 477	*valp = val;
 478}
 479
 480static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
 481		u32 mask, int shift)
 482{
 483	u32 val = read_reg(dev, offset);
 484
 485	write_field(&val, field, mask, shift);
 486
 487	write_reg(dev, offset, val);
 488}
 489
 490/*
 491 * DMA address/data block for the shadow registers
 492 */
 493struct vpe_mmr_adb {
 494	struct vpdma_adb_hdr	out_fmt_hdr;
 495	u32			out_fmt_reg[1];
 496	u32			out_fmt_pad[3];
 497	struct vpdma_adb_hdr	us1_hdr;
 498	u32			us1_regs[8];
 499	struct vpdma_adb_hdr	us2_hdr;
 500	u32			us2_regs[8];
 501	struct vpdma_adb_hdr	us3_hdr;
 502	u32			us3_regs[8];
 503	struct vpdma_adb_hdr	dei_hdr;
 504	u32			dei_regs[8];
 505	struct vpdma_adb_hdr	sc_hdr0;
 506	u32			sc_regs0[7];
 507	u32			sc_pad0[1];
 508	struct vpdma_adb_hdr	sc_hdr8;
 509	u32			sc_regs8[6];
 510	u32			sc_pad8[2];
 511	struct vpdma_adb_hdr	sc_hdr17;
 512	u32			sc_regs17[9];
 513	u32			sc_pad17[3];
 514	struct vpdma_adb_hdr	csc_hdr;
 515	u32			csc_regs[6];
 516	u32			csc_pad[2];
 517};
 518
 519#define GET_OFFSET_TOP(ctx, obj, reg)	\
 520	((obj)->res->start - ctx->dev->res->start + reg)
 521
 522#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a)	\
 523	VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
 524/*
 525 * Set the headers for all of the address/data block structures.
 526 */
 527static void init_adb_hdrs(struct vpe_ctx *ctx)
 528{
 529	VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
 530	VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
 531	VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
 532	VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
 533	VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
 534	VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
 535		GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
 536	VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
 537		GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
 538	VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
 539		GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
 540	VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
 541		GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
 542};
 543
 544/*
 545 * Allocate or re-allocate the motion vector DMA buffers
 546 * There are two buffers, one for input and one for output.
 547 * However, the roles are reversed after each field is processed.
 548 * In other words, after each field is processed, the previous
 549 * output (dst) MV buffer becomes the new input (src) MV buffer.
 550 */
 551static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
 552{
 553	struct device *dev = ctx->dev->v4l2_dev.dev;
 554
 555	if (ctx->mv_buf_size == size)
 556		return 0;
 557
 558	if (ctx->mv_buf[0])
 559		dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
 560			ctx->mv_buf_dma[0]);
 561
 562	if (ctx->mv_buf[1])
 563		dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
 564			ctx->mv_buf_dma[1]);
 565
 566	if (size == 0)
 567		return 0;
 568
 569	ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
 570				GFP_KERNEL);
 571	if (!ctx->mv_buf[0]) {
 572		vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
 573		return -ENOMEM;
 574	}
 575
 576	ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
 577				GFP_KERNEL);
 578	if (!ctx->mv_buf[1]) {
 579		vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
 580		dma_free_coherent(dev, size, ctx->mv_buf[0],
 581			ctx->mv_buf_dma[0]);
 582
 583		return -ENOMEM;
 584	}
 585
 586	ctx->mv_buf_size = size;
 587	ctx->src_mv_buf_selector = 0;
 588
 589	return 0;
 590}
 591
 592static void free_mv_buffers(struct vpe_ctx *ctx)
 593{
 594	realloc_mv_buffers(ctx, 0);
 595}
 596
 597/*
 598 * While de-interlacing, we keep the two most recent input buffers
 599 * around.  This function frees those two buffers when we have
 600 * finished processing the current stream.
 601 */
 602static void free_vbs(struct vpe_ctx *ctx)
 603{
 604	struct vpe_dev *dev = ctx->dev;
 605	unsigned long flags;
 606
 607	if (ctx->src_vbs[2] == NULL)
 608		return;
 609
 610	spin_lock_irqsave(&dev->lock, flags);
 611	if (ctx->src_vbs[2]) {
 612		v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
 613		if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
 614			v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
 615		ctx->src_vbs[2] = NULL;
 616		ctx->src_vbs[1] = NULL;
 617	}
 618	spin_unlock_irqrestore(&dev->lock, flags);
 619}
 620
 621/*
 622 * Enable or disable the VPE clocks
 623 */
 624static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
 625{
 626	u32 val = 0;
 627
 628	if (on)
 629		val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
 630	write_reg(dev, VPE_CLK_ENABLE, val);
 631}
 632
 633static void vpe_top_reset(struct vpe_dev *dev)
 634{
 635
 636	write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
 637		VPE_DATA_PATH_CLK_RESET_SHIFT);
 638
 639	usleep_range(100, 150);
 640
 641	write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
 642		VPE_DATA_PATH_CLK_RESET_SHIFT);
 643}
 644
 645static void vpe_top_vpdma_reset(struct vpe_dev *dev)
 646{
 647	write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
 648		VPE_VPDMA_CLK_RESET_SHIFT);
 649
 650	usleep_range(100, 150);
 651
 652	write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
 653		VPE_VPDMA_CLK_RESET_SHIFT);
 654}
 655
 656/*
 657 * Load the correct of upsampler coefficients into the shadow MMRs
 658 */
 659static void set_us_coefficients(struct vpe_ctx *ctx)
 660{
 661	struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
 662	struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
 663	u32 *us1_reg = &mmr_adb->us1_regs[0];
 664	u32 *us2_reg = &mmr_adb->us2_regs[0];
 665	u32 *us3_reg = &mmr_adb->us3_regs[0];
 666	const unsigned short *cp, *end_cp;
 667
 668	cp = &us_coeffs[0].anchor_fid0_c0;
 669
 670	if (s_q_data->flags & Q_IS_INTERLACED)		/* interlaced */
 671		cp += sizeof(us_coeffs[0]) / sizeof(*cp);
 672
 673	end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
 674
 675	while (cp < end_cp) {
 676		write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
 677		write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
 678		*us2_reg++ = *us1_reg;
 679		*us3_reg++ = *us1_reg++;
 680	}
 681	ctx->load_mmrs = true;
 682}
 683
 684/*
 685 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
 686 */
 687static void set_cfg_modes(struct vpe_ctx *ctx)
 688{
 689	struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
 690	struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
 691	u32 *us1_reg0 = &mmr_adb->us1_regs[0];
 692	u32 *us2_reg0 = &mmr_adb->us2_regs[0];
 693	u32 *us3_reg0 = &mmr_adb->us3_regs[0];
 694	int cfg_mode = 1;
 695
 696	/*
 697	 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
 698	 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
 699	 */
 700
 701	if (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
 702	    fmt->fourcc == V4L2_PIX_FMT_NV21)
 703		cfg_mode = 0;
 704
 705	write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
 706	write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
 707	write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
 708
 709	ctx->load_mmrs = true;
 710}
 711
 712static void set_line_modes(struct vpe_ctx *ctx)
 713{
 714	struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
 715	int line_mode = 1;
 716
 717	if (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
 718	    fmt->fourcc == V4L2_PIX_FMT_NV21)
 719		line_mode = 0;		/* double lines to line buffer */
 720
 721	/* regs for now */
 722	vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
 723	vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
 724	vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
 725
 726	/* frame start for input luma */
 727	vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
 728		VPE_CHAN_LUMA1_IN);
 729	vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
 730		VPE_CHAN_LUMA2_IN);
 731	vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
 732		VPE_CHAN_LUMA3_IN);
 733
 734	/* frame start for input chroma */
 735	vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
 736		VPE_CHAN_CHROMA1_IN);
 737	vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
 738		VPE_CHAN_CHROMA2_IN);
 739	vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
 740		VPE_CHAN_CHROMA3_IN);
 741
 742	/* frame start for MV in client */
 743	vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
 744		VPE_CHAN_MV_IN);
 745}
 746
 747/*
 748 * Set the shadow registers that are modified when the source
 749 * format changes.
 750 */
 751static void set_src_registers(struct vpe_ctx *ctx)
 752{
 753	set_us_coefficients(ctx);
 754}
 755
 756/*
 757 * Set the shadow registers that are modified when the destination
 758 * format changes.
 759 */
 760static void set_dst_registers(struct vpe_ctx *ctx)
 761{
 762	struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
 763	struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
 764	const struct v4l2_format_info *finfo;
 765	u32 val = 0;
 766
 767	finfo = v4l2_format_info(fmt->fourcc);
 768	if (v4l2_is_format_rgb(finfo)) {
 769		val |= VPE_RGB_OUT_SELECT;
 770		vpdma_set_bg_color(ctx->dev->vpdma,
 771			(struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff);
 772	} else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
 773		val |= VPE_COLOR_SEPARATE_422;
 774
 775	/*
 776	 * the source of CHR_DS and CSC is always the scaler, irrespective of
 777	 * whether it's used or not
 778	 */
 779	val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
 780
 781	if (fmt->fourcc != V4L2_PIX_FMT_NV12 &&
 782	    fmt->fourcc != V4L2_PIX_FMT_NV21)
 783		val |= VPE_DS_BYPASS;
 784
 785	mmr_adb->out_fmt_reg[0] = val;
 786
 787	ctx->load_mmrs = true;
 788}
 789
 790/*
 791 * Set the de-interlacer shadow register values
 792 */
 793static void set_dei_regs(struct vpe_ctx *ctx)
 794{
 795	struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
 796	struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
 797	unsigned int src_h = s_q_data->c_rect.height;
 798	unsigned int src_w = s_q_data->c_rect.width;
 799	u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
 800	bool deinterlace = true;
 801	u32 val = 0;
 802
 803	/*
 804	 * according to TRM, we should set DEI in progressive bypass mode when
 805	 * the input content is progressive, however, DEI is bypassed correctly
 806	 * for both progressive and interlace content in interlace bypass mode.
 807	 * It has been recommended not to use progressive bypass mode.
 808	 */
 809	if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) {
 810		deinterlace = false;
 811		val = VPE_DEI_INTERLACE_BYPASS;
 812	}
 813
 814	src_h = deinterlace ? src_h * 2 : src_h;
 815
 816	val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
 817		(src_w << VPE_DEI_WIDTH_SHIFT) |
 818		VPE_DEI_FIELD_FLUSH;
 819
 820	*dei_mmr0 = val;
 821
 822	ctx->load_mmrs = true;
 823}
 824
 825static void set_dei_shadow_registers(struct vpe_ctx *ctx)
 826{
 827	struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
 828	u32 *dei_mmr = &mmr_adb->dei_regs[0];
 829	const struct vpe_dei_regs *cur = &dei_regs;
 830
 831	dei_mmr[2]  = cur->mdt_spacial_freq_thr_reg;
 832	dei_mmr[3]  = cur->edi_config_reg;
 833	dei_mmr[4]  = cur->edi_lut_reg0;
 834	dei_mmr[5]  = cur->edi_lut_reg1;
 835	dei_mmr[6]  = cur->edi_lut_reg2;
 836	dei_mmr[7]  = cur->edi_lut_reg3;
 837
 838	ctx->load_mmrs = true;
 839}
 840
 841static void config_edi_input_mode(struct vpe_ctx *ctx, int mode)
 842{
 843	struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
 844	u32 *edi_config_reg = &mmr_adb->dei_regs[3];
 845
 846	if (mode & 0x2)
 847		write_field(edi_config_reg, 1, 1, 2);	/* EDI_ENABLE_3D */
 848
 849	if (mode & 0x3)
 850		write_field(edi_config_reg, 1, 1, 3);	/* EDI_CHROMA_3D  */
 851
 852	write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK,
 853		VPE_EDI_INP_MODE_SHIFT);
 854
 855	ctx->load_mmrs = true;
 856}
 857
 858/*
 859 * Set the shadow registers whose values are modified when either the
 860 * source or destination format is changed.
 861 */
 862static int set_srcdst_params(struct vpe_ctx *ctx)
 863{
 864	struct vpe_q_data *s_q_data =  &ctx->q_data[Q_DATA_SRC];
 865	struct vpe_q_data *d_q_data =  &ctx->q_data[Q_DATA_DST];
 866	struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
 867	unsigned int src_w = s_q_data->c_rect.width;
 868	unsigned int src_h = s_q_data->c_rect.height;
 869	unsigned int dst_w = d_q_data->c_rect.width;
 870	unsigned int dst_h = d_q_data->c_rect.height;
 871	struct v4l2_pix_format_mplane *spix;
 872	size_t mv_buf_size;
 873	int ret;
 874
 875	ctx->sequence = 0;
 876	ctx->field = V4L2_FIELD_TOP;
 877	spix = &s_q_data->format.fmt.pix_mp;
 878
 879	if ((s_q_data->flags & Q_IS_INTERLACED) &&
 880			!(d_q_data->flags & Q_IS_INTERLACED)) {
 881		int bytes_per_line;
 882		const struct vpdma_data_format *mv =
 883			&vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
 884
 885		/*
 886		 * we make sure that the source image has a 16 byte aligned
 887		 * stride, we need to do the same for the motion vector buffer
 888		 * by aligning it's stride to the next 16 byte boundary. this
 889		 * extra space will not be used by the de-interlacer, but will
 890		 * ensure that vpdma operates correctly
 891		 */
 892		bytes_per_line = ALIGN((spix->width * mv->depth) >> 3,
 893				       VPDMA_STRIDE_ALIGN);
 894		mv_buf_size = bytes_per_line * spix->height;
 895
 896		ctx->deinterlacing = true;
 897		src_h <<= 1;
 898	} else {
 899		ctx->deinterlacing = false;
 900		mv_buf_size = 0;
 901	}
 902
 903	free_vbs(ctx);
 904	ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL;
 905
 906	ret = realloc_mv_buffers(ctx, mv_buf_size);
 907	if (ret)
 908		return ret;
 909
 910	set_cfg_modes(ctx);
 911	set_dei_regs(ctx);
 912
 913	csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
 914		      &s_q_data->format, &d_q_data->format);
 915
 916	sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
 917	sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
 918
 919	sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
 920		&mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
 921		src_w, src_h, dst_w, dst_h);
 922
 923	return 0;
 924}
 925
 926/*
 927 * mem2mem callbacks
 928 */
 929
 930/*
 931 * job_ready() - check whether an instance is ready to be scheduled to run
 932 */
 933static int job_ready(void *priv)
 934{
 935	struct vpe_ctx *ctx = priv;
 936
 937	/*
 938	 * This check is needed as this might be called directly from driver
 939	 * When called by m2m framework, this will always satisfy, but when
 940	 * called from vpe_irq, this might fail. (src stream with zero buffers)
 941	 */
 942	if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 ||
 943		v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0)
 944		return 0;
 945
 946	return 1;
 947}
 948
 949static void job_abort(void *priv)
 950{
 951	struct vpe_ctx *ctx = priv;
 952
 953	/* Will cancel the transaction in the next interrupt handler */
 954	ctx->aborting = 1;
 955}
 956
 957static void vpe_dump_regs(struct vpe_dev *dev)
 958{
 959#define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
 960
 961	vpe_dbg(dev, "VPE Registers:\n");
 962
 963	DUMPREG(PID);
 964	DUMPREG(SYSCONFIG);
 965	DUMPREG(INT0_STATUS0_RAW);
 966	DUMPREG(INT0_STATUS0);
 967	DUMPREG(INT0_ENABLE0);
 968	DUMPREG(INT0_STATUS1_RAW);
 969	DUMPREG(INT0_STATUS1);
 970	DUMPREG(INT0_ENABLE1);
 971	DUMPREG(CLK_ENABLE);
 972	DUMPREG(CLK_RESET);
 973	DUMPREG(CLK_FORMAT_SELECT);
 974	DUMPREG(CLK_RANGE_MAP);
 975	DUMPREG(US1_R0);
 976	DUMPREG(US1_R1);
 977	DUMPREG(US1_R2);
 978	DUMPREG(US1_R3);
 979	DUMPREG(US1_R4);
 980	DUMPREG(US1_R5);
 981	DUMPREG(US1_R6);
 982	DUMPREG(US1_R7);
 983	DUMPREG(US2_R0);
 984	DUMPREG(US2_R1);
 985	DUMPREG(US2_R2);
 986	DUMPREG(US2_R3);
 987	DUMPREG(US2_R4);
 988	DUMPREG(US2_R5);
 989	DUMPREG(US2_R6);
 990	DUMPREG(US2_R7);
 991	DUMPREG(US3_R0);
 992	DUMPREG(US3_R1);
 993	DUMPREG(US3_R2);
 994	DUMPREG(US3_R3);
 995	DUMPREG(US3_R4);
 996	DUMPREG(US3_R5);
 997	DUMPREG(US3_R6);
 998	DUMPREG(US3_R7);
 999	DUMPREG(DEI_FRAME_SIZE);
1000	DUMPREG(MDT_BYPASS);
1001	DUMPREG(MDT_SF_THRESHOLD);
1002	DUMPREG(EDI_CONFIG);
1003	DUMPREG(DEI_EDI_LUT_R0);
1004	DUMPREG(DEI_EDI_LUT_R1);
1005	DUMPREG(DEI_EDI_LUT_R2);
1006	DUMPREG(DEI_EDI_LUT_R3);
1007	DUMPREG(DEI_FMD_WINDOW_R0);
1008	DUMPREG(DEI_FMD_WINDOW_R1);
1009	DUMPREG(DEI_FMD_CONTROL_R0);
1010	DUMPREG(DEI_FMD_CONTROL_R1);
1011	DUMPREG(DEI_FMD_STATUS_R0);
1012	DUMPREG(DEI_FMD_STATUS_R1);
1013	DUMPREG(DEI_FMD_STATUS_R2);
1014#undef DUMPREG
1015
1016	sc_dump_regs(dev->sc);
1017	csc_dump_regs(dev->csc);
1018}
1019
1020static void add_out_dtd(struct vpe_ctx *ctx, int port)
1021{
1022	struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
1023	const struct vpe_port_data *p_data = &port_data[port];
1024	struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
1025	struct vpe_fmt *fmt = q_data->fmt;
1026	const struct vpdma_data_format *vpdma_fmt;
1027	int mv_buf_selector = !ctx->src_mv_buf_selector;
1028	struct v4l2_pix_format_mplane *pix;
1029	dma_addr_t dma_addr;
1030	u32 flags = 0;
1031	u32 offset = 0;
1032	u32 stride;
1033
1034	if (port == VPE_PORT_MV_OUT) {
1035		vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1036		dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1037		q_data = &ctx->q_data[Q_DATA_SRC];
1038		pix = &q_data->format.fmt.pix_mp;
1039		stride = ALIGN((pix->width * vpdma_fmt->depth) >> 3,
1040			       VPDMA_STRIDE_ALIGN);
1041	} else {
1042		/* to incorporate interleaved formats */
1043		int plane = fmt->coplanar ? p_data->vb_part : 0;
1044
1045		pix = &q_data->format.fmt.pix_mp;
1046		vpdma_fmt = fmt->vpdma_fmt[plane];
1047		/*
1048		 * If we are using a single plane buffer and
1049		 * we need to set a separate vpdma chroma channel.
1050		 */
1051		if (pix->num_planes == 1 && plane) {
1052			dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1053			/* Compute required offset */
1054			offset = pix->plane_fmt[0].bytesperline * pix->height;
1055		} else {
1056			dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1057			/* Use address as is, no offset */
1058			offset = 0;
1059		}
1060		if (!dma_addr) {
1061			vpe_err(ctx->dev,
1062				"acquiring output buffer(%d) dma_addr failed\n",
1063				port);
1064			return;
1065		}
1066		/* Apply the offset */
1067		dma_addr += offset;
1068		stride = pix->plane_fmt[VPE_LUMA].bytesperline;
1069	}
1070
1071	if (q_data->flags & Q_DATA_FRAME_1D)
1072		flags |= VPDMA_DATA_FRAME_1D;
1073	if (q_data->flags & Q_DATA_MODE_TILED)
1074		flags |= VPDMA_DATA_MODE_TILED;
1075
1076	vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1,
1077			   MAX_W, MAX_H);
1078
1079	vpdma_add_out_dtd(&ctx->desc_list, pix->width,
1080			  stride, &q_data->c_rect,
1081			  vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1,
1082			  MAX_OUT_HEIGHT_REG1, p_data->channel, flags);
1083}
1084
1085static void add_in_dtd(struct vpe_ctx *ctx, int port)
1086{
1087	struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1088	const struct vpe_port_data *p_data = &port_data[port];
1089	struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1090	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1091	struct vpe_fmt *fmt = q_data->fmt;
1092	struct v4l2_pix_format_mplane *pix;
1093	const struct vpdma_data_format *vpdma_fmt;
1094	int mv_buf_selector = ctx->src_mv_buf_selector;
1095	int field = vbuf->field == V4L2_FIELD_BOTTOM;
1096	int frame_width, frame_height;
1097	dma_addr_t dma_addr;
1098	u32 flags = 0;
1099	u32 offset = 0;
1100	u32 stride;
1101
1102	pix = &q_data->format.fmt.pix_mp;
1103	if (port == VPE_PORT_MV_IN) {
1104		vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1105		dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1106		stride = ALIGN((pix->width * vpdma_fmt->depth) >> 3,
1107			       VPDMA_STRIDE_ALIGN);
1108	} else {
1109		/* to incorporate interleaved formats */
1110		int plane = fmt->coplanar ? p_data->vb_part : 0;
1111
1112		vpdma_fmt = fmt->vpdma_fmt[plane];
1113		/*
1114		 * If we are using a single plane buffer and
1115		 * we need to set a separate vpdma chroma channel.
1116		 */
1117		if (pix->num_planes == 1 && plane) {
1118			dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1119			/* Compute required offset */
1120			offset = pix->plane_fmt[0].bytesperline * pix->height;
1121		} else {
1122			dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1123			/* Use address as is, no offset */
1124			offset = 0;
1125		}
1126		if (!dma_addr) {
1127			vpe_err(ctx->dev,
1128				"acquiring output buffer(%d) dma_addr failed\n",
1129				port);
1130			return;
1131		}
1132		/* Apply the offset */
1133		dma_addr += offset;
1134		stride = pix->plane_fmt[VPE_LUMA].bytesperline;
1135
1136		/*
1137		 * field used in VPDMA desc  = 0 (top) / 1 (bottom)
1138		 * Use top or bottom field from same vb alternately
1139		 * For each de-interlacing operation, f,f-1,f-2 should be one
1140		 * of TBT or BTB
1141		 */
1142		if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB ||
1143		    q_data->flags & Q_DATA_INTERLACED_SEQ_BT) {
1144			/* Select initial value based on format */
1145			if (q_data->flags & Q_DATA_INTERLACED_SEQ_BT)
1146				field = 1;
1147			else
1148				field = 0;
1149
1150			/* Toggle for each vb_index and each operation */
1151			field = (field + p_data->vb_index + ctx->sequence) % 2;
1152
1153			if (field) {
1154				int height = pix->height / 2;
1155				int bpp;
1156
1157				if (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
1158				    fmt->fourcc == V4L2_PIX_FMT_NV21)
1159					bpp = 1;
1160				else
1161					bpp = vpdma_fmt->depth >> 3;
1162
1163				if (plane)
1164					height /= 2;
1165
1166				dma_addr += pix->width * height * bpp;
1167			}
1168		}
1169	}
1170
1171	if (q_data->flags & Q_DATA_FRAME_1D)
1172		flags |= VPDMA_DATA_FRAME_1D;
1173	if (q_data->flags & Q_DATA_MODE_TILED)
1174		flags |= VPDMA_DATA_MODE_TILED;
1175
1176	frame_width = q_data->c_rect.width;
1177	frame_height = q_data->c_rect.height;
1178
1179	if (p_data->vb_part && (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
1180				fmt->fourcc == V4L2_PIX_FMT_NV21))
1181		frame_height /= 2;
1182
1183	vpdma_add_in_dtd(&ctx->desc_list, pix->width, stride,
1184			 &q_data->c_rect, vpdma_fmt, dma_addr,
1185			 p_data->channel, field, flags, frame_width,
1186			 frame_height, 0, 0);
1187}
1188
1189/*
1190 * Enable the expected IRQ sources
1191 */
1192static void enable_irqs(struct vpe_ctx *ctx)
1193{
1194	write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1195	write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1196				VPE_DS1_UV_ERROR_INT);
1197
1198	vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true);
1199}
1200
1201static void disable_irqs(struct vpe_ctx *ctx)
1202{
1203	write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1204	write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1205
1206	vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false);
1207}
1208
1209/* device_run() - prepares and starts the device
1210 *
1211 * This function is only called when both the source and destination
1212 * buffers are in place.
1213 */
1214static void device_run(void *priv)
1215{
1216	struct vpe_ctx *ctx = priv;
1217	struct sc_data *sc = ctx->dev->sc;
1218	struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1219	struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
1220	const struct v4l2_format_info *d_finfo;
1221
1222	d_finfo = v4l2_format_info(d_q_data->fmt->fourcc);
1223
1224	if (ctx->deinterlacing && s_q_data->flags & Q_IS_SEQ_XX &&
1225	    ctx->sequence % 2 == 0) {
1226		/* When using SEQ_XX type buffers, each buffer has two fields
1227		 * each buffer has two fields (top & bottom)
1228		 * Removing one buffer is actually getting two fields
1229		 * Alternate between two operations:-
1230		 * Even : consume one field but DO NOT REMOVE from queue
1231		 * Odd : consume other field and REMOVE from queue
1232		 */
1233		ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1234		WARN_ON(ctx->src_vbs[0] == NULL);
1235	} else {
1236		ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1237		WARN_ON(ctx->src_vbs[0] == NULL);
1238	}
1239
1240	ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1241	WARN_ON(ctx->dst_vb == NULL);
1242
1243	if (ctx->deinterlacing) {
1244
1245		if (ctx->src_vbs[2] == NULL) {
1246			ctx->src_vbs[2] = ctx->src_vbs[0];
1247			WARN_ON(ctx->src_vbs[2] == NULL);
1248			ctx->src_vbs[1] = ctx->src_vbs[0];
1249			WARN_ON(ctx->src_vbs[1] == NULL);
1250		}
1251
1252		/*
1253		 * we have output the first 2 frames through line average, we
1254		 * now switch to EDI de-interlacer
1255		 */
1256		if (ctx->sequence == 2)
1257			config_edi_input_mode(ctx, 0x3); /* EDI (Y + UV) */
1258	}
1259
1260	/* config descriptors */
1261	if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1262		vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1263		vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1264
1265		set_line_modes(ctx);
1266
1267		ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1268		ctx->load_mmrs = false;
1269	}
1270
1271	if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1272			sc->load_coeff_h) {
1273		vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1274		vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1275			&ctx->sc_coeff_h, 0);
1276
1277		sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1278		sc->load_coeff_h = false;
1279	}
1280
1281	if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1282			sc->load_coeff_v) {
1283		vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1284		vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1285			&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1286
1287		sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1288		sc->load_coeff_v = false;
1289	}
1290
1291	/* output data descriptors */
1292	if (ctx->deinterlacing)
1293		add_out_dtd(ctx, VPE_PORT_MV_OUT);
1294
1295	if (v4l2_is_format_rgb(d_finfo)) {
1296		add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1297	} else {
1298		add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1299		if (d_q_data->fmt->coplanar)
1300			add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1301	}
1302
1303	/* input data descriptors */
1304	if (ctx->deinterlacing) {
1305		add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1306		add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1307
1308		add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1309		add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1310	}
1311
1312	add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1313	add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1314
1315	if (ctx->deinterlacing)
1316		add_in_dtd(ctx, VPE_PORT_MV_IN);
1317
1318	/* sync on channel control descriptors for input ports */
1319	vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1320	vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1321
1322	if (ctx->deinterlacing) {
1323		vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1324			VPE_CHAN_LUMA2_IN);
1325		vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1326			VPE_CHAN_CHROMA2_IN);
1327
1328		vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1329			VPE_CHAN_LUMA3_IN);
1330		vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1331			VPE_CHAN_CHROMA3_IN);
1332
1333		vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1334	}
1335
1336	/* sync on channel control descriptors for output ports */
1337	if (v4l2_is_format_rgb(d_finfo)) {
1338		vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1339			VPE_CHAN_RGB_OUT);
1340	} else {
1341		vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1342			VPE_CHAN_LUMA_OUT);
1343		if (d_q_data->fmt->coplanar)
1344			vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1345				VPE_CHAN_CHROMA_OUT);
1346	}
1347
1348	if (ctx->deinterlacing)
1349		vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1350
1351	enable_irqs(ctx);
1352
1353	vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1354	vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0);
1355}
1356
1357static void dei_error(struct vpe_ctx *ctx)
1358{
1359	dev_warn(ctx->dev->v4l2_dev.dev,
1360		"received DEI error interrupt\n");
1361}
1362
1363static void ds1_uv_error(struct vpe_ctx *ctx)
1364{
1365	dev_warn(ctx->dev->v4l2_dev.dev,
1366		"received downsampler error interrupt\n");
1367}
1368
1369static irqreturn_t vpe_irq(int irq_vpe, void *data)
1370{
1371	struct vpe_dev *dev = (struct vpe_dev *)data;
1372	struct vpe_ctx *ctx;
1373	struct vpe_q_data *d_q_data;
1374	struct vb2_v4l2_buffer *s_vb, *d_vb;
1375	unsigned long flags;
1376	u32 irqst0, irqst1;
1377	bool list_complete = false;
1378
1379	irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1380	if (irqst0) {
1381		write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1382		vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1383	}
1384
1385	irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1386	if (irqst1) {
1387		write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1388		vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1389	}
1390
1391	ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1392	if (!ctx) {
1393		vpe_err(dev, "instance released before end of transaction\n");
1394		goto handled;
1395	}
1396
1397	if (irqst1) {
1398		if (irqst1 & VPE_DEI_ERROR_INT) {
1399			irqst1 &= ~VPE_DEI_ERROR_INT;
1400			dei_error(ctx);
1401		}
1402		if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1403			irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1404			ds1_uv_error(ctx);
1405		}
1406	}
1407
1408	if (irqst0) {
1409		if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1410			vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0);
1411
1412		irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1413		list_complete = true;
1414	}
1415
1416	if (irqst0 | irqst1) {
1417		dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1418			irqst0, irqst1);
1419	}
1420
1421	/*
1422	 * Setup next operation only when list complete IRQ occurs
1423	 * otherwise, skip the following code
1424	 */
1425	if (!list_complete)
1426		goto handled;
1427
1428	disable_irqs(ctx);
1429
1430	vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1431	vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1432	vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1433	vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1434
1435	vpdma_reset_desc_list(&ctx->desc_list);
1436
1437	 /* the previous dst mv buffer becomes the next src mv buffer */
1438	ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1439
1440	s_vb = ctx->src_vbs[0];
1441	d_vb = ctx->dst_vb;
1442
1443	d_vb->flags = s_vb->flags;
1444	d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1445
1446	if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1447		d_vb->timecode = s_vb->timecode;
1448
1449	d_vb->sequence = ctx->sequence;
1450	s_vb->sequence = ctx->sequence;
1451
1452	d_q_data = &ctx->q_data[Q_DATA_DST];
1453	if (d_q_data->flags & Q_IS_INTERLACED) {
1454		d_vb->field = ctx->field;
1455		if (ctx->field == V4L2_FIELD_BOTTOM) {
1456			ctx->sequence++;
1457			ctx->field = V4L2_FIELD_TOP;
1458		} else {
1459			WARN_ON(ctx->field != V4L2_FIELD_TOP);
1460			ctx->field = V4L2_FIELD_BOTTOM;
1461		}
1462	} else {
1463		d_vb->field = V4L2_FIELD_NONE;
1464		ctx->sequence++;
1465	}
1466
1467	if (ctx->deinterlacing) {
1468		/*
1469		 * Allow source buffer to be dequeued only if it won't be used
1470		 * in the next iteration. All vbs are initialized to first
1471		 * buffer and we are shifting buffers every iteration, for the
1472		 * first two iterations, no buffer will be dequeued.
1473		 * This ensures that driver will keep (n-2)th (n-1)th and (n)th
1474		 * field when deinterlacing is enabled
1475		 */
1476		if (ctx->src_vbs[2] != ctx->src_vbs[1])
1477			s_vb = ctx->src_vbs[2];
1478		else
1479			s_vb = NULL;
1480	}
1481
1482	spin_lock_irqsave(&dev->lock, flags);
1483
1484	if (s_vb)
1485		v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1486
1487	v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1488
1489	spin_unlock_irqrestore(&dev->lock, flags);
1490
1491	if (ctx->deinterlacing) {
1492		ctx->src_vbs[2] = ctx->src_vbs[1];
1493		ctx->src_vbs[1] = ctx->src_vbs[0];
1494	}
1495
1496	/*
1497	 * Since the vb2_buf_done has already been called fir therse
1498	 * buffer we can now NULL them out so that we won't try
1499	 * to clean out stray pointer later on.
1500	*/
1501	ctx->src_vbs[0] = NULL;
1502	ctx->dst_vb = NULL;
1503
1504	if (ctx->aborting)
1505		goto finished;
1506
1507	ctx->bufs_completed++;
1508	if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) {
1509		device_run(ctx);
1510		goto handled;
1511	}
1512
1513finished:
1514	vpe_dbg(ctx->dev, "finishing transaction\n");
1515	ctx->bufs_completed = 0;
1516	v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1517handled:
1518	return IRQ_HANDLED;
1519}
1520
1521/*
1522 * video ioctls
1523 */
1524static int vpe_querycap(struct file *file, void *priv,
1525			struct v4l2_capability *cap)
1526{
1527	strscpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver));
1528	strscpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card));
1529	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1530		VPE_MODULE_NAME);
1531	return 0;
1532}
1533
1534static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1535{
1536	int i, index;
1537	struct vpe_fmt *fmt = NULL;
1538
1539	index = 0;
1540	for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1541		if (vpe_formats[i].types & type) {
1542			if (index == f->index) {
1543				fmt = &vpe_formats[i];
1544				break;
1545			}
1546			index++;
1547		}
1548	}
1549
1550	if (!fmt)
1551		return -EINVAL;
1552
1553	f->pixelformat = fmt->fourcc;
1554	return 0;
1555}
1556
1557static int vpe_enum_fmt(struct file *file, void *priv,
1558				struct v4l2_fmtdesc *f)
1559{
1560	if (V4L2_TYPE_IS_OUTPUT(f->type))
1561		return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1562
1563	return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1564}
1565
1566static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1567{
1568	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1569	struct vpe_ctx *ctx = to_vpe_ctx(file);
1570	struct vpe_q_data *q_data;
1571
1572	q_data = get_q_data(ctx, f->type);
1573	if (!q_data)
1574		return -EINVAL;
1575
1576	*f = q_data->format;
1577
1578	if (V4L2_TYPE_IS_CAPTURE(f->type)) {
1579		struct vpe_q_data *s_q_data;
1580		struct v4l2_pix_format_mplane *spix;
1581
1582		/* get colorimetry from the source queue */
1583		s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1584		spix = &s_q_data->format.fmt.pix_mp;
1585
1586		pix->colorspace = spix->colorspace;
1587		pix->xfer_func = spix->xfer_func;
1588		pix->ycbcr_enc = spix->ycbcr_enc;
1589		pix->quantization = spix->quantization;
1590	}
1591
1592	return 0;
1593}
1594
1595static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1596		       struct vpe_fmt *fmt, int type)
1597{
1598	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1599	struct v4l2_plane_pix_format *plane_fmt;
1600	unsigned int w_align;
1601	int i, depth, depth_bytes, height;
1602	unsigned int stride = 0;
1603	const struct v4l2_format_info *finfo;
1604
1605	if (!fmt || !(fmt->types & type)) {
1606		vpe_dbg(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1607			pix->pixelformat);
1608		fmt = __find_format(V4L2_PIX_FMT_YUYV);
1609	}
1610
1611	if (pix->field != V4L2_FIELD_NONE &&
1612	    pix->field != V4L2_FIELD_ALTERNATE &&
1613	    pix->field != V4L2_FIELD_SEQ_TB &&
1614	    pix->field != V4L2_FIELD_SEQ_BT)
1615		pix->field = V4L2_FIELD_NONE;
1616
1617	depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1618
1619	/*
1620	 * the line stride should 16 byte aligned for VPDMA to work, based on
1621	 * the bytes per pixel, figure out how much the width should be aligned
1622	 * to make sure line stride is 16 byte aligned
1623	 */
1624	depth_bytes = depth >> 3;
1625
1626	if (depth_bytes == 3) {
1627		/*
1628		 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1629		 * really help in ensuring line stride is 16 byte aligned
1630		 */
1631		w_align = 4;
1632	} else {
1633		/*
1634		 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1635		 * can ensure a line stride alignment of 16 bytes. For example,
1636		 * if bpp is 2, then the line stride can be 16 byte aligned if
1637		 * the width is 8 byte aligned
1638		 */
1639
1640		/*
1641		 * HACK: using order_base_2() here causes lots of asm output
1642		 * errors with smatch, on i386:
1643		 * ./arch/x86/include/asm/bitops.h:457:22:
1644		 *		 warning: asm output is not an lvalue
1645		 * Perhaps some gcc optimization is doing the wrong thing
1646		 * there.
1647		 * Let's get rid of them by doing the calculus on two steps
1648		 */
1649		w_align = roundup_pow_of_two(VPDMA_DESC_ALIGN / depth_bytes);
1650		w_align = ilog2(w_align);
1651	}
1652
1653	v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1654			      &pix->height, MIN_H, MAX_H, H_ALIGN,
1655			      S_ALIGN);
1656
1657	if (!pix->num_planes || pix->num_planes > 2)
1658		pix->num_planes = fmt->coplanar ? 2 : 1;
1659	else if (pix->num_planes > 1 && !fmt->coplanar)
1660		pix->num_planes = 1;
1661
1662	pix->pixelformat = fmt->fourcc;
1663	finfo = v4l2_format_info(fmt->fourcc);
1664
1665	/*
1666	 * For the actual image parameters, we need to consider the field
1667	 * height of the image for SEQ_XX buffers.
1668	 */
1669	if (pix->field == V4L2_FIELD_SEQ_TB || pix->field == V4L2_FIELD_SEQ_BT)
1670		height = pix->height / 2;
1671	else
1672		height = pix->height;
1673
1674	if (!pix->colorspace) {
1675		if (v4l2_is_format_rgb(finfo)) {
1676			pix->colorspace = V4L2_COLORSPACE_SRGB;
1677		} else {
1678			if (height > 1280)	/* HD */
1679				pix->colorspace = V4L2_COLORSPACE_REC709;
1680			else			/* SD */
1681				pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1682		}
1683	}
1684
1685	for (i = 0; i < pix->num_planes; i++) {
1686		plane_fmt = &pix->plane_fmt[i];
1687		depth = fmt->vpdma_fmt[i]->depth;
1688
1689		stride = (pix->width * fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
1690		if (stride > plane_fmt->bytesperline)
1691			plane_fmt->bytesperline = stride;
1692
1693		plane_fmt->bytesperline = clamp_t(u32, plane_fmt->bytesperline,
1694						  stride,
1695						  VPDMA_MAX_STRIDE);
1696
1697		plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline,
1698						VPDMA_STRIDE_ALIGN);
1699
1700		if (i == VPE_LUMA) {
1701			plane_fmt->sizeimage = pix->height *
1702					       plane_fmt->bytesperline;
1703
1704			if (pix->num_planes == 1 && fmt->coplanar)
1705				plane_fmt->sizeimage += pix->height *
1706					plane_fmt->bytesperline *
1707					fmt->vpdma_fmt[VPE_CHROMA]->depth >> 3;
1708
1709		} else { /* i == VIP_CHROMA */
1710			plane_fmt->sizeimage = (pix->height *
1711					       plane_fmt->bytesperline *
1712					       depth) >> 3;
1713		}
1714	}
1715
1716	return 0;
1717}
1718
1719static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1720{
1721	struct vpe_ctx *ctx = to_vpe_ctx(file);
1722	struct vpe_fmt *fmt = find_format(f);
1723
1724	if (V4L2_TYPE_IS_OUTPUT(f->type))
1725		return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1726	else
1727		return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1728}
1729
1730static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1731{
1732	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1733	struct v4l2_pix_format_mplane *qpix;
1734	struct vpe_q_data *q_data;
1735	struct vb2_queue *vq;
1736
1737	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1738
1739	if (vb2_is_busy(vq)) {
1740		vpe_err(ctx->dev, "queue busy\n");
1741		return -EBUSY;
1742	}
1743
1744	q_data = get_q_data(ctx, f->type);
1745	if (!q_data)
1746		return -EINVAL;
1747
1748	qpix = &q_data->format.fmt.pix_mp;
1749	q_data->fmt		= find_format(f);
1750	q_data->format = *f;
1751
1752	q_data->c_rect.left	= 0;
1753	q_data->c_rect.top	= 0;
1754	q_data->c_rect.width	= pix->width;
1755	q_data->c_rect.height	= pix->height;
1756
1757	if (qpix->field == V4L2_FIELD_ALTERNATE)
1758		q_data->flags |= Q_DATA_INTERLACED_ALTERNATE;
1759	else if (qpix->field == V4L2_FIELD_SEQ_TB)
1760		q_data->flags |= Q_DATA_INTERLACED_SEQ_TB;
1761	else if (qpix->field == V4L2_FIELD_SEQ_BT)
1762		q_data->flags |= Q_DATA_INTERLACED_SEQ_BT;
1763	else
1764		q_data->flags &= ~Q_IS_INTERLACED;
1765
1766	/* the crop height is halved for the case of SEQ_XX buffers */
1767	if (q_data->flags & Q_IS_SEQ_XX)
1768		q_data->c_rect.height /= 2;
1769
1770	vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1771		f->type, pix->width, pix->height, pix->pixelformat,
1772		pix->plane_fmt[0].bytesperline);
1773	if (pix->num_planes == 2)
1774		vpe_dbg(ctx->dev, " bpl_uv %d\n",
1775			pix->plane_fmt[1].bytesperline);
1776
1777	return 0;
1778}
1779
1780static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1781{
1782	int ret;
1783	struct vpe_ctx *ctx = to_vpe_ctx(file);
1784
1785	ret = vpe_try_fmt(file, priv, f);
1786	if (ret)
1787		return ret;
1788
1789	ret = __vpe_s_fmt(ctx, f);
1790	if (ret)
1791		return ret;
1792
1793	if (V4L2_TYPE_IS_OUTPUT(f->type))
1794		set_src_registers(ctx);
1795	else
1796		set_dst_registers(ctx);
1797
1798	return set_srcdst_params(ctx);
1799}
1800
1801static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1802{
1803	struct vpe_q_data *q_data;
1804	struct v4l2_pix_format_mplane *pix;
1805	int height;
1806
1807	if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1808	    (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1809		return -EINVAL;
1810
1811	q_data = get_q_data(ctx, s->type);
1812	if (!q_data)
1813		return -EINVAL;
1814
1815	pix = &q_data->format.fmt.pix_mp;
1816
1817	switch (s->target) {
1818	case V4L2_SEL_TGT_COMPOSE:
1819		/*
1820		 * COMPOSE target is only valid for capture buffer type, return
1821		 * error for output buffer type
1822		 */
1823		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1824			return -EINVAL;
1825		break;
1826	case V4L2_SEL_TGT_CROP:
1827		/*
1828		 * CROP target is only valid for output buffer type, return
1829		 * error for capture buffer type
1830		 */
1831		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1832			return -EINVAL;
1833		break;
1834	/*
1835	 * bound and default crop/compose targets are invalid targets to
1836	 * try/set
1837	 */
1838	default:
1839		return -EINVAL;
1840	}
1841
1842	/*
1843	 * For SEQ_XX buffers, crop height should be less than the height of
1844	 * the field height, not the buffer height
1845	 */
1846	if (q_data->flags & Q_IS_SEQ_XX)
1847		height = pix->height / 2;
1848	else
1849		height = pix->height;
1850
1851	if (s->r.top < 0 || s->r.left < 0) {
1852		vpe_err(ctx->dev, "negative values for top and left\n");
1853		s->r.top = s->r.left = 0;
1854	}
1855
1856	v4l_bound_align_image(&s->r.width, MIN_W, pix->width, 1,
1857		&s->r.height, MIN_H, height, H_ALIGN, S_ALIGN);
1858
1859	/* adjust left/top if cropping rectangle is out of bounds */
1860	if (s->r.left + s->r.width > pix->width)
1861		s->r.left = pix->width - s->r.width;
1862	if (s->r.top + s->r.height > pix->height)
1863		s->r.top = pix->height - s->r.height;
1864
1865	return 0;
1866}
1867
1868static int vpe_g_selection(struct file *file, void *fh,
1869		struct v4l2_selection *s)
1870{
1871	struct vpe_ctx *ctx = to_vpe_ctx(file);
1872	struct vpe_q_data *q_data;
1873	struct v4l2_pix_format_mplane *pix;
1874	bool use_c_rect = false;
1875
1876	if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1877	    (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1878		return -EINVAL;
1879
1880	q_data = get_q_data(ctx, s->type);
1881	if (!q_data)
1882		return -EINVAL;
1883
1884	pix = &q_data->format.fmt.pix_mp;
1885
1886	switch (s->target) {
1887	case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1888	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1889		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1890			return -EINVAL;
1891		break;
1892	case V4L2_SEL_TGT_CROP_BOUNDS:
1893	case V4L2_SEL_TGT_CROP_DEFAULT:
1894		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1895			return -EINVAL;
1896		break;
1897	case V4L2_SEL_TGT_COMPOSE:
1898		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1899			return -EINVAL;
1900		use_c_rect = true;
1901		break;
1902	case V4L2_SEL_TGT_CROP:
1903		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1904			return -EINVAL;
1905		use_c_rect = true;
1906		break;
1907	default:
1908		return -EINVAL;
1909	}
1910
1911	if (use_c_rect) {
1912		/*
1913		 * for CROP/COMPOSE target type, return c_rect params from the
1914		 * respective buffer type
1915		 */
1916		s->r = q_data->c_rect;
1917	} else {
1918		/*
1919		 * for DEFAULT/BOUNDS target type, return width and height from
1920		 * S_FMT of the respective buffer type
1921		 */
1922		s->r.left = 0;
1923		s->r.top = 0;
1924		s->r.width = pix->width;
1925		s->r.height = pix->height;
1926	}
1927
1928	return 0;
1929}
1930
1931
1932static int vpe_s_selection(struct file *file, void *fh,
1933		struct v4l2_selection *s)
1934{
1935	struct vpe_ctx *ctx = to_vpe_ctx(file);
1936	struct vpe_q_data *q_data;
1937	struct v4l2_selection sel = *s;
1938	int ret;
1939
1940	ret = __vpe_try_selection(ctx, &sel);
1941	if (ret)
1942		return ret;
1943
1944	q_data = get_q_data(ctx, sel.type);
1945	if (!q_data)
1946		return -EINVAL;
1947
1948	if ((q_data->c_rect.left == sel.r.left) &&
1949			(q_data->c_rect.top == sel.r.top) &&
1950			(q_data->c_rect.width == sel.r.width) &&
1951			(q_data->c_rect.height == sel.r.height)) {
1952		vpe_dbg(ctx->dev,
1953			"requested crop/compose values are already set\n");
1954		return 0;
1955	}
1956
1957	q_data->c_rect = sel.r;
1958
1959	return set_srcdst_params(ctx);
1960}
1961
1962/*
1963 * defines number of buffers/frames a context can process with VPE before
1964 * switching to a different context. default value is 1 buffer per context
1965 */
1966#define V4L2_CID_VPE_BUFS_PER_JOB		(V4L2_CID_USER_TI_VPE_BASE + 0)
1967
1968static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1969{
1970	struct vpe_ctx *ctx =
1971		container_of(ctrl->handler, struct vpe_ctx, hdl);
1972
1973	switch (ctrl->id) {
1974	case V4L2_CID_VPE_BUFS_PER_JOB:
1975		ctx->bufs_per_job = ctrl->val;
1976		break;
1977
1978	default:
1979		vpe_err(ctx->dev, "Invalid control\n");
1980		return -EINVAL;
1981	}
1982
1983	return 0;
1984}
1985
1986static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1987	.s_ctrl = vpe_s_ctrl,
1988};
1989
1990static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1991	.vidioc_querycap		= vpe_querycap,
1992
1993	.vidioc_enum_fmt_vid_cap	= vpe_enum_fmt,
1994	.vidioc_g_fmt_vid_cap_mplane	= vpe_g_fmt,
1995	.vidioc_try_fmt_vid_cap_mplane	= vpe_try_fmt,
1996	.vidioc_s_fmt_vid_cap_mplane	= vpe_s_fmt,
1997
1998	.vidioc_enum_fmt_vid_out	= vpe_enum_fmt,
1999	.vidioc_g_fmt_vid_out_mplane	= vpe_g_fmt,
2000	.vidioc_try_fmt_vid_out_mplane	= vpe_try_fmt,
2001	.vidioc_s_fmt_vid_out_mplane	= vpe_s_fmt,
2002
2003	.vidioc_g_selection		= vpe_g_selection,
2004	.vidioc_s_selection		= vpe_s_selection,
2005
2006	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
2007	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
2008	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
2009	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
2010	.vidioc_expbuf			= v4l2_m2m_ioctl_expbuf,
2011	.vidioc_streamon		= v4l2_m2m_ioctl_streamon,
2012	.vidioc_streamoff		= v4l2_m2m_ioctl_streamoff,
2013
2014	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,
2015	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
2016};
2017
2018/*
2019 * Queue operations
2020 */
2021static int vpe_queue_setup(struct vb2_queue *vq,
2022			   unsigned int *nbuffers, unsigned int *nplanes,
2023			   unsigned int sizes[], struct device *alloc_devs[])
2024{
2025	int i;
2026	struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
2027	struct vpe_q_data *q_data;
2028	struct v4l2_pix_format_mplane *pix;
2029
2030	q_data = get_q_data(ctx, vq->type);
2031	if (!q_data)
2032		return -EINVAL;
2033
2034	pix = &q_data->format.fmt.pix_mp;
2035	*nplanes = pix->num_planes;
2036
2037	for (i = 0; i < *nplanes; i++)
2038		sizes[i] = pix->plane_fmt[i].sizeimage;
2039
2040	vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
2041		sizes[VPE_LUMA]);
2042	if (*nplanes == 2)
2043		vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
2044
2045	return 0;
2046}
2047
2048static int vpe_buf_prepare(struct vb2_buffer *vb)
2049{
2050	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2051	struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2052	struct vpe_q_data *q_data;
2053	struct v4l2_pix_format_mplane *pix;
2054	int i;
2055
2056	vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
2057
2058	q_data = get_q_data(ctx, vb->vb2_queue->type);
2059	if (!q_data)
2060		return -EINVAL;
2061
2062	pix = &q_data->format.fmt.pix_mp;
2063
2064	if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
2065		if (!(q_data->flags & Q_IS_INTERLACED)) {
2066			vbuf->field = V4L2_FIELD_NONE;
2067		} else {
2068			if (vbuf->field != V4L2_FIELD_TOP &&
2069			    vbuf->field != V4L2_FIELD_BOTTOM &&
2070			    vbuf->field != V4L2_FIELD_SEQ_TB &&
2071			    vbuf->field != V4L2_FIELD_SEQ_BT)
2072				return -EINVAL;
2073		}
2074	}
2075
2076	for (i = 0; i < pix->num_planes; i++) {
2077		if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
2078			vpe_err(ctx->dev,
2079				"data will not fit into plane (%lu < %lu)\n",
2080				vb2_plane_size(vb, i),
2081				(long)pix->plane_fmt[i].sizeimage);
2082			return -EINVAL;
2083		}
2084	}
2085
2086	for (i = 0; i < pix->num_planes; i++)
2087		vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
2088
2089	return 0;
2090}
2091
2092static void vpe_buf_queue(struct vb2_buffer *vb)
2093{
2094	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2095	struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2096
2097	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
2098}
2099
2100static int check_srcdst_sizes(struct vpe_ctx *ctx)
2101{
2102	struct vpe_q_data *s_q_data =  &ctx->q_data[Q_DATA_SRC];
2103	struct vpe_q_data *d_q_data =  &ctx->q_data[Q_DATA_DST];
2104	unsigned int src_w = s_q_data->c_rect.width;
2105	unsigned int src_h = s_q_data->c_rect.height;
2106	unsigned int dst_w = d_q_data->c_rect.width;
2107	unsigned int dst_h = d_q_data->c_rect.height;
2108
2109	if (src_w == dst_w && src_h == dst_h)
2110		return 0;
2111
2112	if (src_h <= SC_MAX_PIXEL_HEIGHT &&
2113	    src_w <= SC_MAX_PIXEL_WIDTH &&
2114	    dst_h <= SC_MAX_PIXEL_HEIGHT &&
2115	    dst_w <= SC_MAX_PIXEL_WIDTH)
2116		return 0;
2117
2118	return -1;
2119}
2120
2121static void vpe_return_all_buffers(struct vpe_ctx *ctx,  struct vb2_queue *q,
2122				   enum vb2_buffer_state state)
2123{
2124	struct vb2_v4l2_buffer *vb;
2125	unsigned long flags;
2126
2127	for (;;) {
2128		if (V4L2_TYPE_IS_OUTPUT(q->type))
2129			vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
2130		else
2131			vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2132		if (!vb)
2133			break;
2134		spin_lock_irqsave(&ctx->dev->lock, flags);
2135		v4l2_m2m_buf_done(vb, state);
2136		spin_unlock_irqrestore(&ctx->dev->lock, flags);
2137	}
2138
2139	/*
2140	 * Cleanup the in-transit vb2 buffers that have been
2141	 * removed from their respective queue already but for
2142	 * which procecessing has not been completed yet.
2143	 */
2144	if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2145		spin_lock_irqsave(&ctx->dev->lock, flags);
2146
2147		if (ctx->src_vbs[2])
2148			v4l2_m2m_buf_done(ctx->src_vbs[2], state);
2149
2150		if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
2151			v4l2_m2m_buf_done(ctx->src_vbs[1], state);
2152
2153		if (ctx->src_vbs[0] &&
2154		    (ctx->src_vbs[0] != ctx->src_vbs[1]) &&
2155		    (ctx->src_vbs[0] != ctx->src_vbs[2]))
2156			v4l2_m2m_buf_done(ctx->src_vbs[0], state);
2157
2158		ctx->src_vbs[2] = NULL;
2159		ctx->src_vbs[1] = NULL;
2160		ctx->src_vbs[0] = NULL;
2161
2162		spin_unlock_irqrestore(&ctx->dev->lock, flags);
2163	} else {
2164		if (ctx->dst_vb) {
2165			spin_lock_irqsave(&ctx->dev->lock, flags);
2166
2167			v4l2_m2m_buf_done(ctx->dst_vb, state);
2168			ctx->dst_vb = NULL;
2169			spin_unlock_irqrestore(&ctx->dev->lock, flags);
2170		}
2171	}
2172}
2173
2174static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
2175{
2176	struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2177
2178	/* Check any of the size exceed maximum scaling sizes */
2179	if (check_srcdst_sizes(ctx)) {
2180		vpe_err(ctx->dev,
2181			"Conversion setup failed, check source and destination parameters\n"
2182			);
2183		vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_QUEUED);
2184		return -EINVAL;
2185	}
2186
2187	if (ctx->deinterlacing)
2188		config_edi_input_mode(ctx, 0x0);
2189
2190	if (ctx->sequence != 0)
2191		set_srcdst_params(ctx);
2192
2193	return 0;
2194}
2195
2196static void vpe_stop_streaming(struct vb2_queue *q)
2197{
2198	struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2199
2200	vpe_dump_regs(ctx->dev);
2201	vpdma_dump_regs(ctx->dev->vpdma);
2202
2203	vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_ERROR);
2204}
2205
2206static const struct vb2_ops vpe_qops = {
2207	.queue_setup	 = vpe_queue_setup,
2208	.buf_prepare	 = vpe_buf_prepare,
2209	.buf_queue	 = vpe_buf_queue,
2210	.start_streaming = vpe_start_streaming,
2211	.stop_streaming  = vpe_stop_streaming,
2212};
2213
2214static int queue_init(void *priv, struct vb2_queue *src_vq,
2215		      struct vb2_queue *dst_vq)
2216{
2217	struct vpe_ctx *ctx = priv;
2218	struct vpe_dev *dev = ctx->dev;
2219	int ret;
2220
2221	memset(src_vq, 0, sizeof(*src_vq));
2222	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2223	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2224	src_vq->drv_priv = ctx;
2225	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2226	src_vq->ops = &vpe_qops;
2227	src_vq->mem_ops = &vb2_dma_contig_memops;
2228	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2229	src_vq->lock = &dev->dev_mutex;
2230	src_vq->dev = dev->v4l2_dev.dev;
2231
2232	ret = vb2_queue_init(src_vq);
2233	if (ret)
2234		return ret;
2235
2236	memset(dst_vq, 0, sizeof(*dst_vq));
2237	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2238	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2239	dst_vq->drv_priv = ctx;
2240	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2241	dst_vq->ops = &vpe_qops;
2242	dst_vq->mem_ops = &vb2_dma_contig_memops;
2243	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2244	dst_vq->lock = &dev->dev_mutex;
2245	dst_vq->dev = dev->v4l2_dev.dev;
2246
2247	return vb2_queue_init(dst_vq);
2248}
2249
2250static const struct v4l2_ctrl_config vpe_bufs_per_job = {
2251	.ops = &vpe_ctrl_ops,
2252	.id = V4L2_CID_VPE_BUFS_PER_JOB,
2253	.name = "Buffers Per Transaction",
2254	.type = V4L2_CTRL_TYPE_INTEGER,
2255	.def = VPE_DEF_BUFS_PER_JOB,
2256	.min = 1,
2257	.max = VIDEO_MAX_FRAME,
2258	.step = 1,
2259};
2260
2261/*
2262 * File operations
2263 */
2264static int vpe_open(struct file *file)
2265{
2266	struct vpe_dev *dev = video_drvdata(file);
2267	struct vpe_q_data *s_q_data;
2268	struct v4l2_ctrl_handler *hdl;
2269	struct vpe_ctx *ctx;
2270	struct v4l2_pix_format_mplane *pix;
2271	int ret;
2272
2273	vpe_dbg(dev, "vpe_open\n");
2274
2275	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2276	if (!ctx)
2277		return -ENOMEM;
2278
2279	ctx->dev = dev;
2280
2281	if (mutex_lock_interruptible(&dev->dev_mutex)) {
2282		ret = -ERESTARTSYS;
2283		goto free_ctx;
2284	}
2285
2286	ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2287			VPDMA_LIST_TYPE_NORMAL);
2288	if (ret != 0)
2289		goto unlock;
2290
2291	ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2292	if (ret != 0)
2293		goto free_desc_list;
2294
2295	ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2296	if (ret != 0)
2297		goto free_mmr_adb;
2298
2299	ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2300	if (ret != 0)
2301		goto free_sc_h;
2302
2303	init_adb_hdrs(ctx);
2304
2305	v4l2_fh_init(&ctx->fh, video_devdata(file));
2306
2307	hdl = &ctx->hdl;
2308	v4l2_ctrl_handler_init(hdl, 1);
2309	v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2310	if (hdl->error) {
2311		ret = hdl->error;
2312		goto exit_fh;
2313	}
2314	ctx->fh.ctrl_handler = hdl;
2315	v4l2_ctrl_handler_setup(hdl);
2316
2317	s_q_data = &ctx->q_data[Q_DATA_SRC];
2318	pix = &s_q_data->format.fmt.pix_mp;
2319	s_q_data->fmt = __find_format(V4L2_PIX_FMT_YUYV);
2320	pix->pixelformat = s_q_data->fmt->fourcc;
2321	s_q_data->format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2322	pix->width = 1920;
2323	pix->height = 1080;
2324	pix->num_planes = 1;
2325	pix->plane_fmt[VPE_LUMA].bytesperline = (pix->width *
2326			s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2327	pix->plane_fmt[VPE_LUMA].sizeimage =
2328			pix->plane_fmt[VPE_LUMA].bytesperline *
2329			pix->height;
2330	pix->colorspace = V4L2_COLORSPACE_REC709;
2331	pix->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2332	pix->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2333	pix->quantization = V4L2_QUANTIZATION_DEFAULT;
2334	pix->field = V4L2_FIELD_NONE;
2335	s_q_data->c_rect.left = 0;
2336	s_q_data->c_rect.top = 0;
2337	s_q_data->c_rect.width = pix->width;
2338	s_q_data->c_rect.height = pix->height;
2339	s_q_data->flags = 0;
2340
2341	ctx->q_data[Q_DATA_DST] = *s_q_data;
2342	ctx->q_data[Q_DATA_DST].format.type =
2343			V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2344
2345	set_dei_shadow_registers(ctx);
2346	set_src_registers(ctx);
2347	set_dst_registers(ctx);
2348	ret = set_srcdst_params(ctx);
2349	if (ret)
2350		goto exit_fh;
2351
2352	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2353
2354	if (IS_ERR(ctx->fh.m2m_ctx)) {
2355		ret = PTR_ERR(ctx->fh.m2m_ctx);
2356		goto exit_fh;
2357	}
2358
2359	v4l2_fh_add(&ctx->fh, file);
2360
2361	/*
2362	 * for now, just report the creation of the first instance, we can later
2363	 * optimize the driver to enable or disable clocks when the first
2364	 * instance is created or the last instance released
2365	 */
2366	if (atomic_inc_return(&dev->num_instances) == 1)
2367		vpe_dbg(dev, "first instance created\n");
2368
2369	ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2370
2371	ctx->load_mmrs = true;
2372
2373	vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2374		ctx, ctx->fh.m2m_ctx);
2375
2376	mutex_unlock(&dev->dev_mutex);
2377
2378	return 0;
2379exit_fh:
2380	v4l2_ctrl_handler_free(hdl);
2381	v4l2_fh_exit(&ctx->fh);
2382	vpdma_free_desc_buf(&ctx->sc_coeff_v);
2383free_sc_h:
2384	vpdma_free_desc_buf(&ctx->sc_coeff_h);
2385free_mmr_adb:
2386	vpdma_free_desc_buf(&ctx->mmr_adb);
2387free_desc_list:
2388	vpdma_free_desc_list(&ctx->desc_list);
2389unlock:
2390	mutex_unlock(&dev->dev_mutex);
2391free_ctx:
2392	kfree(ctx);
2393	return ret;
2394}
2395
2396static int vpe_release(struct file *file)
2397{
2398	struct vpe_dev *dev = video_drvdata(file);
2399	struct vpe_ctx *ctx = to_vpe_ctx(file);
2400
2401	vpe_dbg(dev, "releasing instance %p\n", ctx);
2402
2403	mutex_lock(&dev->dev_mutex);
2404	free_mv_buffers(ctx);
2405
2406	vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
2407	vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
2408	vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
2409	vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
2410
2411	vpdma_free_desc_list(&ctx->desc_list);
2412	vpdma_free_desc_buf(&ctx->mmr_adb);
2413
2414	vpdma_free_desc_buf(&ctx->sc_coeff_v);
2415	vpdma_free_desc_buf(&ctx->sc_coeff_h);
2416
2417	v4l2_fh_del(&ctx->fh, file);
2418	v4l2_fh_exit(&ctx->fh);
2419	v4l2_ctrl_handler_free(&ctx->hdl);
2420	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2421
2422	kfree(ctx);
2423
2424	/*
2425	 * for now, just report the release of the last instance, we can later
2426	 * optimize the driver to enable or disable clocks when the first
2427	 * instance is created or the last instance released
2428	 */
2429	if (atomic_dec_return(&dev->num_instances) == 0)
2430		vpe_dbg(dev, "last instance released\n");
2431
2432	mutex_unlock(&dev->dev_mutex);
2433
2434	return 0;
2435}
2436
2437static const struct v4l2_file_operations vpe_fops = {
2438	.owner		= THIS_MODULE,
2439	.open		= vpe_open,
2440	.release	= vpe_release,
2441	.poll		= v4l2_m2m_fop_poll,
2442	.unlocked_ioctl	= video_ioctl2,
2443	.mmap		= v4l2_m2m_fop_mmap,
2444};
2445
2446static const struct video_device vpe_videodev = {
2447	.name		= VPE_MODULE_NAME,
2448	.fops		= &vpe_fops,
2449	.ioctl_ops	= &vpe_ioctl_ops,
2450	.minor		= -1,
2451	.release	= video_device_release_empty,
2452	.vfl_dir	= VFL_DIR_M2M,
2453	.device_caps	= V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
2454};
2455
2456static const struct v4l2_m2m_ops m2m_ops = {
2457	.device_run	= device_run,
2458	.job_ready	= job_ready,
2459	.job_abort	= job_abort,
2460};
2461
2462static int vpe_runtime_get(struct platform_device *pdev)
2463{
2464	int r;
2465
2466	dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2467
2468	r = pm_runtime_resume_and_get(&pdev->dev);
2469	WARN_ON(r < 0);
2470	return r;
2471}
2472
2473static void vpe_runtime_put(struct platform_device *pdev)
2474{
2475
2476	int r;
2477
2478	dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2479
2480	r = pm_runtime_put_sync(&pdev->dev);
2481	WARN_ON(r < 0 && r != -ENOSYS);
2482}
2483
2484static void vpe_fw_cb(struct platform_device *pdev)
2485{
2486	struct vpe_dev *dev = platform_get_drvdata(pdev);
2487	struct video_device *vfd;
2488	int ret;
2489
2490	vfd = &dev->vfd;
2491	*vfd = vpe_videodev;
2492	vfd->lock = &dev->dev_mutex;
2493	vfd->v4l2_dev = &dev->v4l2_dev;
2494
2495	ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
2496	if (ret) {
2497		vpe_err(dev, "Failed to register video device\n");
2498
2499		vpe_set_clock_enable(dev, 0);
2500		vpe_runtime_put(pdev);
2501		pm_runtime_disable(&pdev->dev);
2502		v4l2_m2m_release(dev->m2m_dev);
2503		v4l2_device_unregister(&dev->v4l2_dev);
2504
2505		return;
2506	}
2507
2508	video_set_drvdata(vfd, dev);
2509	dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2510		vfd->num);
2511}
2512
2513static int vpe_probe(struct platform_device *pdev)
2514{
2515	struct vpe_dev *dev;
2516	int ret, irq, func;
2517
2518	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2519	if (ret) {
2520		dev_err(&pdev->dev,
2521			"32-bit consistent DMA enable failed\n");
2522		return ret;
2523	}
2524
2525	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2526	if (!dev)
2527		return -ENOMEM;
2528
2529	spin_lock_init(&dev->lock);
2530
2531	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2532	if (ret)
2533		return ret;
2534
2535	atomic_set(&dev->num_instances, 0);
2536	mutex_init(&dev->dev_mutex);
2537
2538	dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2539						"vpe_top");
2540	if (!dev->res) {
2541		dev_err(&pdev->dev, "missing 'vpe_top' resources data\n");
2542		return -ENODEV;
2543	}
2544
2545	/*
2546	 * HACK: we get resource info from device tree in the form of a list of
2547	 * VPE sub blocks, the driver currently uses only the base of vpe_top
2548	 * for register access, the driver should be changed later to access
2549	 * registers based on the sub block base addresses
2550	 */
2551	dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2552	if (!dev->base) {
2553		ret = -ENOMEM;
2554		goto v4l2_dev_unreg;
2555	}
2556
2557	irq = platform_get_irq(pdev, 0);
2558	ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2559			dev);
2560	if (ret)
2561		goto v4l2_dev_unreg;
2562
2563	platform_set_drvdata(pdev, dev);
2564
2565	dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2566	if (IS_ERR(dev->m2m_dev)) {
2567		vpe_err(dev, "Failed to init mem2mem device\n");
2568		ret = PTR_ERR(dev->m2m_dev);
2569		goto v4l2_dev_unreg;
2570	}
2571
2572	pm_runtime_enable(&pdev->dev);
2573
2574	ret = vpe_runtime_get(pdev);
2575	if (ret < 0)
2576		goto rel_m2m;
2577
2578	/* Perform clk enable followed by reset */
2579	vpe_set_clock_enable(dev, 1);
2580
2581	vpe_top_reset(dev);
2582
2583	func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2584		VPE_PID_FUNC_SHIFT);
2585	vpe_dbg(dev, "VPE PID function %x\n", func);
2586
2587	vpe_top_vpdma_reset(dev);
2588
2589	dev->sc = sc_create(pdev, "sc");
2590	if (IS_ERR(dev->sc)) {
2591		ret = PTR_ERR(dev->sc);
2592		goto runtime_put;
2593	}
2594
2595	dev->csc = csc_create(pdev, "csc");
2596	if (IS_ERR(dev->csc)) {
2597		ret = PTR_ERR(dev->csc);
2598		goto runtime_put;
2599	}
2600
2601	dev->vpdma = &dev->vpdma_data;
2602	ret = vpdma_create(pdev, dev->vpdma, vpe_fw_cb);
2603	if (ret)
2604		goto runtime_put;
2605
2606	return 0;
2607
2608runtime_put:
2609	vpe_runtime_put(pdev);
2610rel_m2m:
2611	pm_runtime_disable(&pdev->dev);
2612	v4l2_m2m_release(dev->m2m_dev);
2613v4l2_dev_unreg:
2614	v4l2_device_unregister(&dev->v4l2_dev);
2615
2616	return ret;
2617}
2618
2619static void vpe_remove(struct platform_device *pdev)
2620{
2621	struct vpe_dev *dev = platform_get_drvdata(pdev);
2622
2623	v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2624
2625	v4l2_m2m_release(dev->m2m_dev);
2626	video_unregister_device(&dev->vfd);
2627	v4l2_device_unregister(&dev->v4l2_dev);
2628
2629	vpe_set_clock_enable(dev, 0);
2630	vpe_runtime_put(pdev);
2631	pm_runtime_disable(&pdev->dev);
2632}
2633
2634#if defined(CONFIG_OF)
2635static const struct of_device_id vpe_of_match[] = {
2636	{
2637		.compatible = "ti,dra7-vpe",
2638	},
2639	{},
2640};
2641MODULE_DEVICE_TABLE(of, vpe_of_match);
2642#endif
2643
2644static struct platform_driver vpe_pdrv = {
2645	.probe		= vpe_probe,
2646	.remove		= vpe_remove,
2647	.driver		= {
2648		.name	= VPE_MODULE_NAME,
2649		.of_match_table = of_match_ptr(vpe_of_match),
2650	},
2651};
2652
2653module_platform_driver(vpe_pdrv);
2654
2655MODULE_DESCRIPTION("TI VPE driver");
2656MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2657MODULE_LICENSE("GPL");