vpdma.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * VPDMA helper library
   4 *
   5 * Copyright (c) 2013 Texas Instruments Inc.
   6 *
   7 * David Griego, <dagriego@biglakesoftware.com>
   8 * Dale Farnsworth, <dale@farnsworth.org>
   9 * Archit Taneja, <archit@ti.com>
  10 */
  11
  12#include <linux/delay.h>
  13#include <linux/dma-mapping.h>
  14#include <linux/err.h>
  15#include <linux/firmware.h>
  16#include <linux/io.h>
  17#include <linux/module.h>
  18#include <linux/platform_device.h>
  19#include <linux/sched.h>
  20#include <linux/slab.h>
  21#include <linux/videodev2.h>
  22
  23#include "vpdma.h"
  24#include "vpdma_priv.h"
  25
  26#define VPDMA_FIRMWARE	"vpdma-1b8.bin"
  27
  28const struct vpdma_data_format vpdma_yuv_fmts[] = {
  29	[VPDMA_DATA_FMT_Y444] = {
  30		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  31		.data_type	= DATA_TYPE_Y444,
  32		.depth		= 8,
  33	},
  34	[VPDMA_DATA_FMT_Y422] = {
  35		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  36		.data_type	= DATA_TYPE_Y422,
  37		.depth		= 8,
  38	},
  39	[VPDMA_DATA_FMT_Y420] = {
  40		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  41		.data_type	= DATA_TYPE_Y420,
  42		.depth		= 8,
  43	},
  44	[VPDMA_DATA_FMT_C444] = {
  45		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  46		.data_type	= DATA_TYPE_C444,
  47		.depth		= 8,
  48	},
  49	[VPDMA_DATA_FMT_C422] = {
  50		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  51		.data_type	= DATA_TYPE_C422,
  52		.depth		= 8,
  53	},
  54	[VPDMA_DATA_FMT_C420] = {
  55		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  56		.data_type	= DATA_TYPE_C420,
  57		.depth		= 4,
  58	},
  59	[VPDMA_DATA_FMT_CB420] = {
  60		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  61		.data_type	= DATA_TYPE_CB420,
  62		.depth		= 4,
  63	},
  64	[VPDMA_DATA_FMT_YCR422] = {
  65		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  66		.data_type	= DATA_TYPE_YCR422,
  67		.depth		= 16,
  68	},
  69	[VPDMA_DATA_FMT_YC444] = {
  70		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  71		.data_type	= DATA_TYPE_YC444,
  72		.depth		= 24,
  73	},
  74	[VPDMA_DATA_FMT_CRY422] = {
  75		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  76		.data_type	= DATA_TYPE_CRY422,
  77		.depth		= 16,
  78	},
  79	[VPDMA_DATA_FMT_CBY422] = {
  80		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  81		.data_type	= DATA_TYPE_CBY422,
  82		.depth		= 16,
  83	},
  84	[VPDMA_DATA_FMT_YCB422] = {
  85		.type		= VPDMA_DATA_FMT_TYPE_YUV,
  86		.data_type	= DATA_TYPE_YCB422,
  87		.depth		= 16,
  88	},
  89};
  90EXPORT_SYMBOL(vpdma_yuv_fmts);
  91
  92const struct vpdma_data_format vpdma_rgb_fmts[] = {
  93	[VPDMA_DATA_FMT_RGB565] = {
  94		.type		= VPDMA_DATA_FMT_TYPE_RGB,
  95		.data_type	= DATA_TYPE_RGB16_565,
  96		.depth		= 16,
  97	},
  98	[VPDMA_DATA_FMT_ARGB16_1555] = {
  99		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 100		.data_type	= DATA_TYPE_ARGB_1555,
 101		.depth		= 16,
 102	},
 103	[VPDMA_DATA_FMT_ARGB16] = {
 104		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 105		.data_type	= DATA_TYPE_ARGB_4444,
 106		.depth		= 16,
 107	},
 108	[VPDMA_DATA_FMT_RGBA16_5551] = {
 109		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 110		.data_type	= DATA_TYPE_RGBA_5551,
 111		.depth		= 16,
 112	},
 113	[VPDMA_DATA_FMT_RGBA16] = {
 114		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 115		.data_type	= DATA_TYPE_RGBA_4444,
 116		.depth		= 16,
 117	},
 118	[VPDMA_DATA_FMT_ARGB24] = {
 119		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 120		.data_type	= DATA_TYPE_ARGB24_6666,
 121		.depth		= 24,
 122	},
 123	[VPDMA_DATA_FMT_RGB24] = {
 124		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 125		.data_type	= DATA_TYPE_RGB24_888,
 126		.depth		= 24,
 127	},
 128	[VPDMA_DATA_FMT_ARGB32] = {
 129		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 130		.data_type	= DATA_TYPE_ARGB32_8888,
 131		.depth		= 32,
 132	},
 133	[VPDMA_DATA_FMT_RGBA24] = {
 134		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 135		.data_type	= DATA_TYPE_RGBA24_6666,
 136		.depth		= 24,
 137	},
 138	[VPDMA_DATA_FMT_RGBA32] = {
 139		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 140		.data_type	= DATA_TYPE_RGBA32_8888,
 141		.depth		= 32,
 142	},
 143	[VPDMA_DATA_FMT_BGR565] = {
 144		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 145		.data_type	= DATA_TYPE_BGR16_565,
 146		.depth		= 16,
 147	},
 148	[VPDMA_DATA_FMT_ABGR16_1555] = {
 149		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 150		.data_type	= DATA_TYPE_ABGR_1555,
 151		.depth		= 16,
 152	},
 153	[VPDMA_DATA_FMT_ABGR16] = {
 154		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 155		.data_type	= DATA_TYPE_ABGR_4444,
 156		.depth		= 16,
 157	},
 158	[VPDMA_DATA_FMT_BGRA16_5551] = {
 159		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 160		.data_type	= DATA_TYPE_BGRA_5551,
 161		.depth		= 16,
 162	},
 163	[VPDMA_DATA_FMT_BGRA16] = {
 164		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 165		.data_type	= DATA_TYPE_BGRA_4444,
 166		.depth		= 16,
 167	},
 168	[VPDMA_DATA_FMT_ABGR24] = {
 169		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 170		.data_type	= DATA_TYPE_ABGR24_6666,
 171		.depth		= 24,
 172	},
 173	[VPDMA_DATA_FMT_BGR24] = {
 174		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 175		.data_type	= DATA_TYPE_BGR24_888,
 176		.depth		= 24,
 177	},
 178	[VPDMA_DATA_FMT_ABGR32] = {
 179		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 180		.data_type	= DATA_TYPE_ABGR32_8888,
 181		.depth		= 32,
 182	},
 183	[VPDMA_DATA_FMT_BGRA24] = {
 184		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 185		.data_type	= DATA_TYPE_BGRA24_6666,
 186		.depth		= 24,
 187	},
 188	[VPDMA_DATA_FMT_BGRA32] = {
 189		.type		= VPDMA_DATA_FMT_TYPE_RGB,
 190		.data_type	= DATA_TYPE_BGRA32_8888,
 191		.depth		= 32,
 192	},
 193};
 194EXPORT_SYMBOL(vpdma_rgb_fmts);
 195
 196/*
 197 * To handle RAW format we are re-using the CBY422
 198 * vpdma data type so that we use the vpdma to re-order
 199 * the incoming bytes, as the parser assumes that the
 200 * first byte presented on the bus is the MSB of a 2
 201 * bytes value.
 202 * RAW8 handles from 1 to 8 bits
 203 * RAW16 handles from 9 to 16 bits
 204 */
 205const struct vpdma_data_format vpdma_raw_fmts[] = {
 206	[VPDMA_DATA_FMT_RAW8] = {
 207		.type		= VPDMA_DATA_FMT_TYPE_YUV,
 208		.data_type	= DATA_TYPE_CBY422,
 209		.depth		= 8,
 210	},
 211	[VPDMA_DATA_FMT_RAW16] = {
 212		.type		= VPDMA_DATA_FMT_TYPE_YUV,
 213		.data_type	= DATA_TYPE_CBY422,
 214		.depth		= 16,
 215	},
 216};
 217EXPORT_SYMBOL(vpdma_raw_fmts);
 218
 219const struct vpdma_data_format vpdma_misc_fmts[] = {
 220	[VPDMA_DATA_FMT_MV] = {
 221		.type		= VPDMA_DATA_FMT_TYPE_MISC,
 222		.data_type	= DATA_TYPE_MV,
 223		.depth		= 4,
 224	},
 225};
 226EXPORT_SYMBOL(vpdma_misc_fmts);
 227
 228struct vpdma_channel_info {
 229	int num;		/* VPDMA channel number */
 230	int cstat_offset;	/* client CSTAT register offset */
 231};
 232
 233static const struct vpdma_channel_info chan_info[] = {
 234	[VPE_CHAN_LUMA1_IN] = {
 235		.num		= VPE_CHAN_NUM_LUMA1_IN,
 236		.cstat_offset	= VPDMA_DEI_LUMA1_CSTAT,
 237	},
 238	[VPE_CHAN_CHROMA1_IN] = {
 239		.num		= VPE_CHAN_NUM_CHROMA1_IN,
 240		.cstat_offset	= VPDMA_DEI_CHROMA1_CSTAT,
 241	},
 242	[VPE_CHAN_LUMA2_IN] = {
 243		.num		= VPE_CHAN_NUM_LUMA2_IN,
 244		.cstat_offset	= VPDMA_DEI_LUMA2_CSTAT,
 245	},
 246	[VPE_CHAN_CHROMA2_IN] = {
 247		.num		= VPE_CHAN_NUM_CHROMA2_IN,
 248		.cstat_offset	= VPDMA_DEI_CHROMA2_CSTAT,
 249	},
 250	[VPE_CHAN_LUMA3_IN] = {
 251		.num		= VPE_CHAN_NUM_LUMA3_IN,
 252		.cstat_offset	= VPDMA_DEI_LUMA3_CSTAT,
 253	},
 254	[VPE_CHAN_CHROMA3_IN] = {
 255		.num		= VPE_CHAN_NUM_CHROMA3_IN,
 256		.cstat_offset	= VPDMA_DEI_CHROMA3_CSTAT,
 257	},
 258	[VPE_CHAN_MV_IN] = {
 259		.num		= VPE_CHAN_NUM_MV_IN,
 260		.cstat_offset	= VPDMA_DEI_MV_IN_CSTAT,
 261	},
 262	[VPE_CHAN_MV_OUT] = {
 263		.num		= VPE_CHAN_NUM_MV_OUT,
 264		.cstat_offset	= VPDMA_DEI_MV_OUT_CSTAT,
 265	},
 266	[VPE_CHAN_LUMA_OUT] = {
 267		.num		= VPE_CHAN_NUM_LUMA_OUT,
 268		.cstat_offset	= VPDMA_VIP_UP_Y_CSTAT,
 269	},
 270	[VPE_CHAN_CHROMA_OUT] = {
 271		.num		= VPE_CHAN_NUM_CHROMA_OUT,
 272		.cstat_offset	= VPDMA_VIP_UP_UV_CSTAT,
 273	},
 274	[VPE_CHAN_RGB_OUT] = {
 275		.num		= VPE_CHAN_NUM_RGB_OUT,
 276		.cstat_offset	= VPDMA_VIP_UP_Y_CSTAT,
 277	},
 278};
 279
 280static u32 read_reg(struct vpdma_data *vpdma, int offset)
 281{
 282	return ioread32(vpdma->base + offset);
 283}
 284
 285static void write_reg(struct vpdma_data *vpdma, int offset, u32 value)
 286{
 287	iowrite32(value, vpdma->base + offset);
 288}
 289
 290static int read_field_reg(struct vpdma_data *vpdma, int offset,
 291		u32 mask, int shift)
 292{
 293	return (read_reg(vpdma, offset) & (mask << shift)) >> shift;
 294}
 295
 296static void write_field_reg(struct vpdma_data *vpdma, int offset, u32 field,
 297		u32 mask, int shift)
 298{
 299	u32 val = read_reg(vpdma, offset);
 300
 301	val &= ~(mask << shift);
 302	val |= (field & mask) << shift;
 303
 304	write_reg(vpdma, offset, val);
 305}
 306
 307void vpdma_dump_regs(struct vpdma_data *vpdma)
 308{
 309	struct device *dev = &vpdma->pdev->dev;
 310
 311#define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(vpdma, VPDMA_##r))
 312
 313	dev_dbg(dev, "VPDMA Registers:\n");
 314
 315	DUMPREG(PID);
 316	DUMPREG(LIST_ADDR);
 317	DUMPREG(LIST_ATTR);
 318	DUMPREG(LIST_STAT_SYNC);
 319	DUMPREG(BG_RGB);
 320	DUMPREG(BG_YUV);
 321	DUMPREG(SETUP);
 322	DUMPREG(MAX_SIZE1);
 323	DUMPREG(MAX_SIZE2);
 324	DUMPREG(MAX_SIZE3);
 325
 326	/*
 327	 * dumping registers of only group0 and group3, because VPE channels
 328	 * lie within group0 and group3 registers
 329	 */
 330	DUMPREG(INT_CHAN_STAT(0));
 331	DUMPREG(INT_CHAN_MASK(0));
 332	DUMPREG(INT_CHAN_STAT(3));
 333	DUMPREG(INT_CHAN_MASK(3));
 334	DUMPREG(INT_CLIENT0_STAT);
 335	DUMPREG(INT_CLIENT0_MASK);
 336	DUMPREG(INT_CLIENT1_STAT);
 337	DUMPREG(INT_CLIENT1_MASK);
 338	DUMPREG(INT_LIST0_STAT);
 339	DUMPREG(INT_LIST0_MASK);
 340
 341	/*
 342	 * these are registers specific to VPE clients, we can make this
 343	 * function dump client registers specific to VPE or VIP based on
 344	 * who is using it
 345	 */
 346	DUMPREG(DEI_CHROMA1_CSTAT);
 347	DUMPREG(DEI_LUMA1_CSTAT);
 348	DUMPREG(DEI_CHROMA2_CSTAT);
 349	DUMPREG(DEI_LUMA2_CSTAT);
 350	DUMPREG(DEI_CHROMA3_CSTAT);
 351	DUMPREG(DEI_LUMA3_CSTAT);
 352	DUMPREG(DEI_MV_IN_CSTAT);
 353	DUMPREG(DEI_MV_OUT_CSTAT);
 354	DUMPREG(VIP_UP_Y_CSTAT);
 355	DUMPREG(VIP_UP_UV_CSTAT);
 356	DUMPREG(VPI_CTL_CSTAT);
 357}
 358EXPORT_SYMBOL(vpdma_dump_regs);
 359
 360/*
 361 * Allocate a DMA buffer
 362 */
 363int vpdma_alloc_desc_buf(struct vpdma_buf *buf, size_t size)
 364{
 365	buf->size = size;
 366	buf->mapped = false;
 367	buf->addr = kzalloc(size, GFP_KERNEL);
 368	if (!buf->addr)
 369		return -ENOMEM;
 370
 371	WARN_ON(((unsigned long)buf->addr & VPDMA_DESC_ALIGN) != 0);
 372
 373	return 0;
 374}
 375EXPORT_SYMBOL(vpdma_alloc_desc_buf);
 376
 377void vpdma_free_desc_buf(struct vpdma_buf *buf)
 378{
 379	WARN_ON(buf->mapped);
 380	kfree(buf->addr);
 381	buf->addr = NULL;
 382	buf->size = 0;
 383}
 384EXPORT_SYMBOL(vpdma_free_desc_buf);
 385
 386/*
 387 * map descriptor/payload DMA buffer, enabling DMA access
 388 */
 389int vpdma_map_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
 390{
 391	struct device *dev = &vpdma->pdev->dev;
 392
 393	WARN_ON(buf->mapped);
 394	buf->dma_addr = dma_map_single(dev, buf->addr, buf->size,
 395				DMA_BIDIRECTIONAL);
 396	if (dma_mapping_error(dev, buf->dma_addr)) {
 397		dev_err(dev, "failed to map buffer\n");
 398		return -EINVAL;
 399	}
 400
 401	buf->mapped = true;
 402
 403	return 0;
 404}
 405EXPORT_SYMBOL(vpdma_map_desc_buf);
 406
 407/*
 408 * unmap descriptor/payload DMA buffer, disabling DMA access and
 409 * allowing the main processor to access the data
 410 */
 411void vpdma_unmap_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
 412{
 413	struct device *dev = &vpdma->pdev->dev;
 414
 415	if (buf->mapped)
 416		dma_unmap_single(dev, buf->dma_addr, buf->size,
 417				DMA_BIDIRECTIONAL);
 418
 419	buf->mapped = false;
 420}
 421EXPORT_SYMBOL(vpdma_unmap_desc_buf);
 422
 423/*
 424 * Cleanup all pending descriptors of a list
 425 * First, stop the current list being processed.
 426 * If the VPDMA was busy, this step makes vpdma to accept post lists.
 427 * To cleanup the internal FSM, post abort list descriptor for all the
 428 * channels from @channels array of size @size.
 429 */
 430int vpdma_list_cleanup(struct vpdma_data *vpdma, int list_num,
 431		int *channels, int size)
 432{
 433	struct vpdma_desc_list abort_list;
 434	int i, ret, timeout = 500;
 435
 436	write_reg(vpdma, VPDMA_LIST_ATTR,
 437			(list_num << VPDMA_LIST_NUM_SHFT) |
 438			(1 << VPDMA_LIST_STOP_SHFT));
 439
 440	if (size <= 0 || !channels)
 441		return 0;
 442
 443	ret = vpdma_create_desc_list(&abort_list,
 444		size * sizeof(struct vpdma_dtd), VPDMA_LIST_TYPE_NORMAL);
 445	if (ret)
 446		return ret;
 447
 448	for (i = 0; i < size; i++)
 449		vpdma_add_abort_channel_ctd(&abort_list, channels[i]);
 450
 451	ret = vpdma_map_desc_buf(vpdma, &abort_list.buf);
 452	if (ret)
 453		goto free_desc;
 454	ret = vpdma_submit_descs(vpdma, &abort_list, list_num);
 455	if (ret)
 456		goto unmap_desc;
 457
 458	while (vpdma_list_busy(vpdma, list_num) && --timeout)
 459		;
 460
 461	if (timeout == 0) {
 462		dev_err(&vpdma->pdev->dev, "Timed out cleaning up VPDMA list\n");
 463		ret = -EBUSY;
 464	}
 465
 466unmap_desc:
 467	vpdma_unmap_desc_buf(vpdma, &abort_list.buf);
 468free_desc:
 469	vpdma_free_desc_buf(&abort_list.buf);
 470
 471	return ret;
 472}
 473EXPORT_SYMBOL(vpdma_list_cleanup);
 474
 475/*
 476 * create a descriptor list, the user of this list will append configuration,
 477 * control and data descriptors to this list, this list will be submitted to
 478 * VPDMA. VPDMA's list parser will go through each descriptor and perform the
 479 * required DMA operations
 480 */
 481int vpdma_create_desc_list(struct vpdma_desc_list *list, size_t size, int type)
 482{
 483	int r;
 484
 485	r = vpdma_alloc_desc_buf(&list->buf, size);
 486	if (r)
 487		return r;
 488
 489	list->next = list->buf.addr;
 490
 491	list->type = type;
 492
 493	return 0;
 494}
 495EXPORT_SYMBOL(vpdma_create_desc_list);
 496
 497/*
 498 * once a descriptor list is parsed by VPDMA, we reset the list by emptying it,
 499 * to allow new descriptors to be added to the list.
 500 */
 501void vpdma_reset_desc_list(struct vpdma_desc_list *list)
 502{
 503	list->next = list->buf.addr;
 504}
 505EXPORT_SYMBOL(vpdma_reset_desc_list);
 506
 507/*
 508 * free the buffer allocated for the VPDMA descriptor list, this should be
 509 * called when the user doesn't want to use VPDMA any more.
 510 */
 511void vpdma_free_desc_list(struct vpdma_desc_list *list)
 512{
 513	vpdma_free_desc_buf(&list->buf);
 514
 515	list->next = NULL;
 516}
 517EXPORT_SYMBOL(vpdma_free_desc_list);
 518
 519bool vpdma_list_busy(struct vpdma_data *vpdma, int list_num)
 520{
 521	return read_reg(vpdma, VPDMA_LIST_STAT_SYNC) & BIT(list_num + 16);
 522}
 523EXPORT_SYMBOL(vpdma_list_busy);
 524
 525/*
 526 * submit a list of DMA descriptors to the VPE VPDMA, do not wait for completion
 527 */
 528int vpdma_submit_descs(struct vpdma_data *vpdma,
 529			struct vpdma_desc_list *list, int list_num)
 530{
 531	int list_size;
 532	unsigned long flags;
 533
 534	if (vpdma_list_busy(vpdma, list_num))
 535		return -EBUSY;
 536
 537	/* 16-byte granularity */
 538	list_size = (list->next - list->buf.addr) >> 4;
 539
 540	spin_lock_irqsave(&vpdma->lock, flags);
 541	write_reg(vpdma, VPDMA_LIST_ADDR, (u32) list->buf.dma_addr);
 542
 543	write_reg(vpdma, VPDMA_LIST_ATTR,
 544			(list_num << VPDMA_LIST_NUM_SHFT) |
 545			(list->type << VPDMA_LIST_TYPE_SHFT) |
 546			list_size);
 547	spin_unlock_irqrestore(&vpdma->lock, flags);
 548
 549	return 0;
 550}
 551EXPORT_SYMBOL(vpdma_submit_descs);
 552
 553static void dump_dtd(struct vpdma_dtd *dtd);
 554
 555void vpdma_set_max_size(struct vpdma_data *vpdma, int reg_addr,
 556			u32 width, u32 height)
 557{
 558	if (reg_addr != VPDMA_MAX_SIZE1 && reg_addr != VPDMA_MAX_SIZE2 &&
 559	    reg_addr != VPDMA_MAX_SIZE3)
 560		reg_addr = VPDMA_MAX_SIZE1;
 561
 562	write_field_reg(vpdma, reg_addr, width - 1,
 563			VPDMA_MAX_SIZE_WIDTH_MASK, VPDMA_MAX_SIZE_WIDTH_SHFT);
 564
 565	write_field_reg(vpdma, reg_addr, height - 1,
 566			VPDMA_MAX_SIZE_HEIGHT_MASK, VPDMA_MAX_SIZE_HEIGHT_SHFT);
 567
 568}
 569EXPORT_SYMBOL(vpdma_set_max_size);
 570
 571static void dump_cfd(struct vpdma_cfd *cfd)
 572{
 573	int class;
 574
 575	class = cfd_get_class(cfd);
 576
 577	pr_debug("config descriptor of payload class: %s\n",
 578		class == CFD_CLS_BLOCK ? "simple block" :
 579		"address data block");
 580
 581	if (class == CFD_CLS_BLOCK)
 582		pr_debug("word0: dst_addr_offset = 0x%08x\n",
 583			cfd->dest_addr_offset);
 584
 585	if (class == CFD_CLS_BLOCK)
 586		pr_debug("word1: num_data_wrds = %d\n", cfd->block_len);
 587
 588	pr_debug("word2: payload_addr = 0x%08x\n", cfd->payload_addr);
 589
 590	pr_debug("word3: pkt_type = %d, direct = %d, class = %d, dest = %d, payload_len = %d\n",
 591		 cfd_get_pkt_type(cfd),
 592		 cfd_get_direct(cfd), class, cfd_get_dest(cfd),
 593		 cfd_get_payload_len(cfd));
 594}
 595
 596/*
 597 * append a configuration descriptor to the given descriptor list, where the
 598 * payload is in the form of a simple data block specified in the descriptor
 599 * header, this is used to upload scaler coefficients to the scaler module
 600 */
 601void vpdma_add_cfd_block(struct vpdma_desc_list *list, int client,
 602		struct vpdma_buf *blk, u32 dest_offset)
 603{
 604	struct vpdma_cfd *cfd;
 605	int len = blk->size;
 606
 607	WARN_ON(blk->dma_addr & VPDMA_DESC_ALIGN);
 608
 609	cfd = list->next;
 610	WARN_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
 611
 612	cfd->dest_addr_offset = dest_offset;
 613	cfd->block_len = len;
 614	cfd->payload_addr = (u32) blk->dma_addr;
 615	cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_BLOCK,
 616				client, len >> 4);
 617
 618	list->next = cfd + 1;
 619
 620	dump_cfd(cfd);
 621}
 622EXPORT_SYMBOL(vpdma_add_cfd_block);
 623
 624/*
 625 * append a configuration descriptor to the given descriptor list, where the
 626 * payload is in the address data block format, this is used to a configure a
 627 * discontiguous set of MMRs
 628 */
 629void vpdma_add_cfd_adb(struct vpdma_desc_list *list, int client,
 630		struct vpdma_buf *adb)
 631{
 632	struct vpdma_cfd *cfd;
 633	unsigned int len = adb->size;
 634
 635	WARN_ON(len & VPDMA_ADB_SIZE_ALIGN);
 636	WARN_ON(adb->dma_addr & VPDMA_DESC_ALIGN);
 637
 638	cfd = list->next;
 639	BUG_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
 640
 641	cfd->w0 = 0;
 642	cfd->w1 = 0;
 643	cfd->payload_addr = (u32) adb->dma_addr;
 644	cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_ADB,
 645				client, len >> 4);
 646
 647	list->next = cfd + 1;
 648
 649	dump_cfd(cfd);
 650};
 651EXPORT_SYMBOL(vpdma_add_cfd_adb);
 652
 653/*
 654 * control descriptor format change based on what type of control descriptor it
 655 * is, we only use 'sync on channel' control descriptors for now, so assume it's
 656 * that
 657 */
 658static void dump_ctd(struct vpdma_ctd *ctd)
 659{
 660	pr_debug("control descriptor\n");
 661
 662	pr_debug("word3: pkt_type = %d, source = %d, ctl_type = %d\n",
 663		ctd_get_pkt_type(ctd), ctd_get_source(ctd), ctd_get_ctl(ctd));
 664}
 665
 666/*
 667 * append a 'sync on channel' type control descriptor to the given descriptor
 668 * list, this descriptor stalls the VPDMA list till the time DMA is completed
 669 * on the specified channel
 670 */
 671void vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list *list,
 672		enum vpdma_channel chan)
 673{
 674	struct vpdma_ctd *ctd;
 675
 676	ctd = list->next;
 677	WARN_ON((void *)(ctd + 1) > (list->buf.addr + list->buf.size));
 678
 679	ctd->w0 = 0;
 680	ctd->w1 = 0;
 681	ctd->w2 = 0;
 682	ctd->type_source_ctl = ctd_type_source_ctl(chan_info[chan].num,
 683				CTD_TYPE_SYNC_ON_CHANNEL);
 684
 685	list->next = ctd + 1;
 686
 687	dump_ctd(ctd);
 688}
 689EXPORT_SYMBOL(vpdma_add_sync_on_channel_ctd);
 690
 691/*
 692 * append an 'abort_channel' type control descriptor to the given descriptor
 693 * list, this descriptor aborts any DMA transaction happening using the
 694 * specified channel
 695 */
 696void vpdma_add_abort_channel_ctd(struct vpdma_desc_list *list,
 697		int chan_num)
 698{
 699	struct vpdma_ctd *ctd;
 700
 701	ctd = list->next;
 702	WARN_ON((void *)(ctd + 1) > (list->buf.addr + list->buf.size));
 703
 704	ctd->w0 = 0;
 705	ctd->w1 = 0;
 706	ctd->w2 = 0;
 707	ctd->type_source_ctl = ctd_type_source_ctl(chan_num,
 708				CTD_TYPE_ABORT_CHANNEL);
 709
 710	list->next = ctd + 1;
 711
 712	dump_ctd(ctd);
 713}
 714EXPORT_SYMBOL(vpdma_add_abort_channel_ctd);
 715
 716static void dump_dtd(struct vpdma_dtd *dtd)
 717{
 718	int dir, chan;
 719
 720	dir = dtd_get_dir(dtd);
 721	chan = dtd_get_chan(dtd);
 722
 723	pr_debug("%s data transfer descriptor for channel %d\n",
 724		dir == DTD_DIR_OUT ? "outbound" : "inbound", chan);
 725
 726	pr_debug("word0: data_type = %d, notify = %d, field = %d, 1D = %d, even_ln_skp = %d, odd_ln_skp = %d, line_stride = %d\n",
 727		dtd_get_data_type(dtd), dtd_get_notify(dtd), dtd_get_field(dtd),
 728		dtd_get_1d(dtd), dtd_get_even_line_skip(dtd),
 729		dtd_get_odd_line_skip(dtd), dtd_get_line_stride(dtd));
 730
 731	if (dir == DTD_DIR_IN)
 732		pr_debug("word1: line_length = %d, xfer_height = %d\n",
 733			dtd_get_line_length(dtd), dtd_get_xfer_height(dtd));
 734
 735	pr_debug("word2: start_addr = %x\n", dtd->start_addr);
 736
 737	pr_debug("word3: pkt_type = %d, mode = %d, dir = %d, chan = %d, pri = %d, next_chan = %d\n",
 738		 dtd_get_pkt_type(dtd),
 739		 dtd_get_mode(dtd), dir, chan, dtd_get_priority(dtd),
 740		 dtd_get_next_chan(dtd));
 741
 742	if (dir == DTD_DIR_IN)
 743		pr_debug("word4: frame_width = %d, frame_height = %d\n",
 744			dtd_get_frame_width(dtd), dtd_get_frame_height(dtd));
 745	else
 746		pr_debug("word4: desc_write_addr = 0x%08x, write_desc = %d, drp_data = %d, use_desc_reg = %d\n",
 747			dtd_get_desc_write_addr(dtd), dtd_get_write_desc(dtd),
 748			dtd_get_drop_data(dtd), dtd_get_use_desc(dtd));
 749
 750	if (dir == DTD_DIR_IN)
 751		pr_debug("word5: hor_start = %d, ver_start = %d\n",
 752			dtd_get_h_start(dtd), dtd_get_v_start(dtd));
 753	else
 754		pr_debug("word5: max_width %d, max_height %d\n",
 755			dtd_get_max_width(dtd), dtd_get_max_height(dtd));
 756
 757	pr_debug("word6: client specific attr0 = 0x%08x\n", dtd->client_attr0);
 758	pr_debug("word7: client specific attr1 = 0x%08x\n", dtd->client_attr1);
 759}
 760
 761/*
 762 * append an outbound data transfer descriptor to the given descriptor list,
 763 * this sets up a 'client to memory' VPDMA transfer for the given VPDMA channel
 764 *
 765 * @list: vpdma desc list to which we add this descriptor
 766 * @width: width of the image in pixels in memory
 767 * @c_rect: compose params of output image
 768 * @fmt: vpdma data format of the buffer
 769 * dma_addr: dma address as seen by VPDMA
 770 * max_width: enum for maximum width of data transfer
 771 * max_height: enum for maximum height of data transfer
 772 * chan: VPDMA channel
 773 * flags: VPDMA flags to configure some descriptor fields
 774 */
 775void vpdma_add_out_dtd(struct vpdma_desc_list *list, int width,
 776		int stride, const struct v4l2_rect *c_rect,
 777		const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
 778		int max_w, int max_h, enum vpdma_channel chan, u32 flags)
 779{
 780	vpdma_rawchan_add_out_dtd(list, width, stride, c_rect, fmt, dma_addr,
 781				  max_w, max_h, chan_info[chan].num, flags);
 782}
 783EXPORT_SYMBOL(vpdma_add_out_dtd);
 784
 785void vpdma_rawchan_add_out_dtd(struct vpdma_desc_list *list, int width,
 786		int stride, const struct v4l2_rect *c_rect,
 787		const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
 788		int max_w, int max_h, int raw_vpdma_chan, u32 flags)
 789{
 790	int priority = 0;
 791	int field = 0;
 792	int notify = 1;
 793	int channel, next_chan;
 794	struct v4l2_rect rect = *c_rect;
 795	int depth = fmt->depth;
 796	struct vpdma_dtd *dtd;
 797
 798	channel = next_chan = raw_vpdma_chan;
 799
 800	if (fmt->type == VPDMA_DATA_FMT_TYPE_YUV &&
 801	    (fmt->data_type == DATA_TYPE_C420 ||
 802	     fmt->data_type == DATA_TYPE_CB420)) {
 803		rect.height >>= 1;
 804		rect.top >>= 1;
 805		depth = 8;
 806	}
 807
 808	dma_addr += rect.top * stride + (rect.left * depth >> 3);
 809
 810	dtd = list->next;
 811	WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
 812
 813	dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
 814					notify,
 815					field,
 816					!!(flags & VPDMA_DATA_FRAME_1D),
 817					!!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
 818					!!(flags & VPDMA_DATA_ODD_LINE_SKIP),
 819					stride);
 820	dtd->w1 = 0;
 821	dtd->start_addr = (u32) dma_addr;
 822	dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
 823				DTD_DIR_OUT, channel, priority, next_chan);
 824	dtd->desc_write_addr = dtd_desc_write_addr(0, 0, 0, 0);
 825	dtd->max_width_height = dtd_max_width_height(max_w, max_h);
 826	dtd->client_attr0 = 0;
 827	dtd->client_attr1 = 0;
 828
 829	list->next = dtd + 1;
 830
 831	dump_dtd(dtd);
 832}
 833EXPORT_SYMBOL(vpdma_rawchan_add_out_dtd);
 834
 835/*
 836 * append an inbound data transfer descriptor to the given descriptor list,
 837 * this sets up a 'memory to client' VPDMA transfer for the given VPDMA channel
 838 *
 839 * @list: vpdma desc list to which we add this descriptor
 840 * @width: width of the image in pixels in memory(not the cropped width)
 841 * @c_rect: crop params of input image
 842 * @fmt: vpdma data format of the buffer
 843 * dma_addr: dma address as seen by VPDMA
 844 * chan: VPDMA channel
 845 * field: top or bottom field info of the input image
 846 * flags: VPDMA flags to configure some descriptor fields
 847 * frame_width/height: the complete width/height of the image presented to the
 848 *			client (this makes sense when multiple channels are
 849 *			connected to the same client, forming a larger frame)
 850 * start_h, start_v: position where the given channel starts providing pixel
 851 *			data to the client (makes sense when multiple channels
 852 *			contribute to the client)
 853 */
 854void vpdma_add_in_dtd(struct vpdma_desc_list *list, int width,
 855		int stride, const struct v4l2_rect *c_rect,
 856		const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
 857		enum vpdma_channel chan, int field, u32 flags, int frame_width,
 858		int frame_height, int start_h, int start_v)
 859{
 860	int priority = 0;
 861	int notify = 1;
 862	int depth = fmt->depth;
 863	int channel, next_chan;
 864	struct v4l2_rect rect = *c_rect;
 865	struct vpdma_dtd *dtd;
 866
 867	channel = next_chan = chan_info[chan].num;
 868
 869	if (fmt->type == VPDMA_DATA_FMT_TYPE_YUV &&
 870	    (fmt->data_type == DATA_TYPE_C420 ||
 871	     fmt->data_type == DATA_TYPE_CB420)) {
 872		rect.height >>= 1;
 873		rect.top >>= 1;
 874		depth = 8;
 875	}
 876
 877	dma_addr += rect.top * stride + (rect.left * depth >> 3);
 878
 879	dtd = list->next;
 880	WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
 881
 882	dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
 883					notify,
 884					field,
 885					!!(flags & VPDMA_DATA_FRAME_1D),
 886					!!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
 887					!!(flags & VPDMA_DATA_ODD_LINE_SKIP),
 888					stride);
 889
 890	dtd->xfer_length_height = dtd_xfer_length_height(rect.width,
 891					rect.height);
 892	dtd->start_addr = (u32) dma_addr;
 893	dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
 894				DTD_DIR_IN, channel, priority, next_chan);
 895	dtd->frame_width_height = dtd_frame_width_height(frame_width,
 896					frame_height);
 897	dtd->start_h_v = dtd_start_h_v(start_h, start_v);
 898	dtd->client_attr0 = 0;
 899	dtd->client_attr1 = 0;
 900
 901	list->next = dtd + 1;
 902
 903	dump_dtd(dtd);
 904}
 905EXPORT_SYMBOL(vpdma_add_in_dtd);
 906
 907int vpdma_hwlist_alloc(struct vpdma_data *vpdma, void *priv)
 908{
 909	int i, list_num = -1;
 910	unsigned long flags;
 911
 912	spin_lock_irqsave(&vpdma->lock, flags);
 913	for (i = 0; i < VPDMA_MAX_NUM_LIST && vpdma->hwlist_used[i]; i++)
 914		;
 915
 916	if (i < VPDMA_MAX_NUM_LIST) {
 917		list_num = i;
 918		vpdma->hwlist_used[i] = true;
 919		vpdma->hwlist_priv[i] = priv;
 920	}
 921	spin_unlock_irqrestore(&vpdma->lock, flags);
 922
 923	return list_num;
 924}
 925EXPORT_SYMBOL(vpdma_hwlist_alloc);
 926
 927void *vpdma_hwlist_get_priv(struct vpdma_data *vpdma, int list_num)
 928{
 929	if (!vpdma || list_num >= VPDMA_MAX_NUM_LIST)
 930		return NULL;
 931
 932	return vpdma->hwlist_priv[list_num];
 933}
 934EXPORT_SYMBOL(vpdma_hwlist_get_priv);
 935
 936void *vpdma_hwlist_release(struct vpdma_data *vpdma, int list_num)
 937{
 938	void *priv;
 939	unsigned long flags;
 940
 941	spin_lock_irqsave(&vpdma->lock, flags);
 942	vpdma->hwlist_used[list_num] = false;
 943	priv = vpdma->hwlist_priv;
 944	spin_unlock_irqrestore(&vpdma->lock, flags);
 945
 946	return priv;
 947}
 948EXPORT_SYMBOL(vpdma_hwlist_release);
 949
 950/* set or clear the mask for list complete interrupt */
 951void vpdma_enable_list_complete_irq(struct vpdma_data *vpdma, int irq_num,
 952		int list_num, bool enable)
 953{
 954	u32 reg_addr = VPDMA_INT_LIST0_MASK + VPDMA_INTX_OFFSET * irq_num;
 955	u32 val;
 956
 957	val = read_reg(vpdma, reg_addr);
 958	if (enable)
 959		val |= (1 << (list_num * 2));
 960	else
 961		val &= ~(1 << (list_num * 2));
 962	write_reg(vpdma, reg_addr, val);
 963}
 964EXPORT_SYMBOL(vpdma_enable_list_complete_irq);
 965
 966/* get the LIST_STAT register */
 967unsigned int vpdma_get_list_stat(struct vpdma_data *vpdma, int irq_num)
 968{
 969	u32 reg_addr = VPDMA_INT_LIST0_STAT + VPDMA_INTX_OFFSET * irq_num;
 970
 971	return read_reg(vpdma, reg_addr);
 972}
 973EXPORT_SYMBOL(vpdma_get_list_stat);
 974
 975/* get the LIST_MASK register */
 976unsigned int vpdma_get_list_mask(struct vpdma_data *vpdma, int irq_num)
 977{
 978	u32 reg_addr = VPDMA_INT_LIST0_MASK + VPDMA_INTX_OFFSET * irq_num;
 979
 980	return read_reg(vpdma, reg_addr);
 981}
 982EXPORT_SYMBOL(vpdma_get_list_mask);
 983
 984/* clear previously occurred list interrupts in the LIST_STAT register */
 985void vpdma_clear_list_stat(struct vpdma_data *vpdma, int irq_num,
 986			   int list_num)
 987{
 988	u32 reg_addr = VPDMA_INT_LIST0_STAT + VPDMA_INTX_OFFSET * irq_num;
 989
 990	write_reg(vpdma, reg_addr, 3 << (list_num * 2));
 991}
 992EXPORT_SYMBOL(vpdma_clear_list_stat);
 993
 994void vpdma_set_bg_color(struct vpdma_data *vpdma,
 995		struct vpdma_data_format *fmt, u32 color)
 996{
 997	if (fmt->type == VPDMA_DATA_FMT_TYPE_RGB)
 998		write_reg(vpdma, VPDMA_BG_RGB, color);
 999	else if (fmt->type == VPDMA_DATA_FMT_TYPE_YUV)
1000		write_reg(vpdma, VPDMA_BG_YUV, color);
1001}
1002EXPORT_SYMBOL(vpdma_set_bg_color);
1003
1004/*
1005 * configures the output mode of the line buffer for the given client, the
1006 * line buffer content can either be mirrored(each line repeated twice) or
1007 * passed to the client as is
1008 */
1009void vpdma_set_line_mode(struct vpdma_data *vpdma, int line_mode,
1010		enum vpdma_channel chan)
1011{
1012	int client_cstat = chan_info[chan].cstat_offset;
1013
1014	write_field_reg(vpdma, client_cstat, line_mode,
1015		VPDMA_CSTAT_LINE_MODE_MASK, VPDMA_CSTAT_LINE_MODE_SHIFT);
1016}
1017EXPORT_SYMBOL(vpdma_set_line_mode);
1018
1019/*
1020 * configures the event which should trigger VPDMA transfer for the given
1021 * client
1022 */
1023void vpdma_set_frame_start_event(struct vpdma_data *vpdma,
1024		enum vpdma_frame_start_event fs_event,
1025		enum vpdma_channel chan)
1026{
1027	int client_cstat = chan_info[chan].cstat_offset;
1028
1029	write_field_reg(vpdma, client_cstat, fs_event,
1030		VPDMA_CSTAT_FRAME_START_MASK, VPDMA_CSTAT_FRAME_START_SHIFT);
1031}
1032EXPORT_SYMBOL(vpdma_set_frame_start_event);
1033
1034static void vpdma_firmware_cb(const struct firmware *f, void *context)
1035{
1036	struct vpdma_data *vpdma = context;
1037	struct vpdma_buf fw_dma_buf;
1038	int i, r;
1039
1040	dev_dbg(&vpdma->pdev->dev, "firmware callback\n");
1041
1042	if (!f || !f->data) {
1043		dev_err(&vpdma->pdev->dev, "couldn't get firmware\n");
1044		return;
1045	}
1046
1047	/* already initialized */
1048	if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
1049			VPDMA_LIST_RDY_SHFT)) {
1050		vpdma->cb(vpdma->pdev);
1051		return;
1052	}
1053
1054	r = vpdma_alloc_desc_buf(&fw_dma_buf, f->size);
1055	if (r) {
1056		dev_err(&vpdma->pdev->dev,
1057			"failed to allocate dma buffer for firmware\n");
1058		goto rel_fw;
1059	}
1060
1061	memcpy(fw_dma_buf.addr, f->data, f->size);
1062
1063	vpdma_map_desc_buf(vpdma, &fw_dma_buf);
1064
1065	write_reg(vpdma, VPDMA_LIST_ADDR, (u32) fw_dma_buf.dma_addr);
1066
1067	for (i = 0; i < 100; i++) {		/* max 1 second */
1068		msleep_interruptible(10);
1069
1070		if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
1071				VPDMA_LIST_RDY_SHFT))
1072			break;
1073	}
1074
1075	if (i == 100) {
1076		dev_err(&vpdma->pdev->dev, "firmware upload failed\n");
1077		goto free_buf;
1078	}
1079
1080	vpdma->cb(vpdma->pdev);
1081
1082free_buf:
1083	vpdma_unmap_desc_buf(vpdma, &fw_dma_buf);
1084
1085	vpdma_free_desc_buf(&fw_dma_buf);
1086rel_fw:
1087	release_firmware(f);
1088}
1089
1090static int vpdma_load_firmware(struct vpdma_data *vpdma)
1091{
1092	int r;
1093	struct device *dev = &vpdma->pdev->dev;
1094
1095	r = request_firmware_nowait(THIS_MODULE, 1,
1096		(const char *) VPDMA_FIRMWARE, dev, GFP_KERNEL, vpdma,
1097		vpdma_firmware_cb);
1098	if (r) {
1099		dev_err(dev, "firmware not available %s\n", VPDMA_FIRMWARE);
1100		return r;
1101	} else {
1102		dev_info(dev, "loading firmware %s\n", VPDMA_FIRMWARE);
1103	}
1104
1105	return 0;
1106}
1107
1108int vpdma_create(struct platform_device *pdev, struct vpdma_data *vpdma,
1109		void (*cb)(struct platform_device *pdev))
1110{
1111	struct resource *res;
1112	int r;
1113
1114	dev_dbg(&pdev->dev, "vpdma_create\n");
1115
1116	vpdma->pdev = pdev;
1117	vpdma->cb = cb;
1118	spin_lock_init(&vpdma->lock);
1119
1120	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpdma");
1121	if (res == NULL) {
1122		dev_err(&pdev->dev, "missing platform resources data\n");
1123		return -ENODEV;
1124	}
1125
1126	vpdma->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1127	if (!vpdma->base) {
1128		dev_err(&pdev->dev, "failed to ioremap\n");
1129		return -ENOMEM;
1130	}
1131
1132	r = vpdma_load_firmware(vpdma);
1133	if (r) {
1134		pr_err("failed to load firmware %s\n", VPDMA_FIRMWARE);
1135		return r;
1136	}
1137
1138	return 0;
1139}
1140EXPORT_SYMBOL(vpdma_create);
1141
1142MODULE_AUTHOR("Texas Instruments Inc.");
1143MODULE_FIRMWARE(VPDMA_FIRMWARE);
1144MODULE_DESCRIPTION("TI VPDMA helper library");
1145MODULE_LICENSE("GPL v2");