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cal.c
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linux-6.19.14/drivers/media/platform/ti/cal/cal.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * TI Camera Access Layer (CAL) - Driver 4 * 5 * Copyright (c) 2015-2020 Texas Instruments Inc. 6 * 7 * Authors: 8 * Benoit Parrot <bparrot@ti.com> 9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12#include <linux/clk.h> 13#include <linux/interrupt.h> 14#include <linux/mfd/syscon.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/pm_runtime.h> 19#include <linux/regmap.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22 23#include <media/media-device.h> 24#include <media/v4l2-async.h> 25#include <media/v4l2-common.h> 26#include <media/v4l2-device.h> 27#include <media/videobuf2-core.h> 28#include <media/videobuf2-dma-contig.h> 29 30#include "cal.h" 31#include "cal_regs.h" 32 33MODULE_DESCRIPTION("TI CAL driver"); 34MODULE_AUTHOR("Benoit Parrot, <bparrot@ti.com>"); 35MODULE_LICENSE("GPL v2"); 36MODULE_VERSION("0.1.0"); 37 38int cal_video_nr = -1; 39module_param_named(video_nr, cal_video_nr, uint, 0644); 40MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect"); 41 42unsigned int cal_debug; 43module_param_named(debug, cal_debug, uint, 0644); 44MODULE_PARM_DESC(debug, "activates debug info"); 45 46#ifdef CONFIG_VIDEO_TI_CAL_MC 47#define CAL_MC_API_DEFAULT 1 48#else 49#define CAL_MC_API_DEFAULT 0 50#endif 51 52bool cal_mc_api = CAL_MC_API_DEFAULT; 53module_param_named(mc_api, cal_mc_api, bool, 0444); 54MODULE_PARM_DESC(mc_api, "activates the MC API"); 55 56/* ------------------------------------------------------------------ 57 * Format Handling 58 * ------------------------------------------------------------------ 59 */ 60 61const struct cal_format_info cal_formats[] = { 62 { 63 .fourcc = V4L2_PIX_FMT_YUYV, 64 .code = MEDIA_BUS_FMT_YUYV8_1X16, 65 .bpp = 16, 66 }, { 67 .fourcc = V4L2_PIX_FMT_UYVY, 68 .code = MEDIA_BUS_FMT_UYVY8_1X16, 69 .bpp = 16, 70 }, { 71 .fourcc = V4L2_PIX_FMT_YVYU, 72 .code = MEDIA_BUS_FMT_YVYU8_1X16, 73 .bpp = 16, 74 }, { 75 .fourcc = V4L2_PIX_FMT_VYUY, 76 .code = MEDIA_BUS_FMT_VYUY8_1X16, 77 .bpp = 16, 78 }, { 79 .fourcc = V4L2_PIX_FMT_RGB565, 80 .code = MEDIA_BUS_FMT_RGB565_1X16, 81 .bpp = 16, 82 }, { 83 .fourcc = V4L2_PIX_FMT_SBGGR8, 84 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 85 .bpp = 8, 86 }, { 87 .fourcc = V4L2_PIX_FMT_SGBRG8, 88 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 89 .bpp = 8, 90 }, { 91 .fourcc = V4L2_PIX_FMT_SGRBG8, 92 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 93 .bpp = 8, 94 }, { 95 .fourcc = V4L2_PIX_FMT_SRGGB8, 96 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 97 .bpp = 8, 98 }, { 99 .fourcc = V4L2_PIX_FMT_SBGGR10, 100 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 101 .bpp = 10, 102 }, { 103 .fourcc = V4L2_PIX_FMT_SGBRG10, 104 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 105 .bpp = 10, 106 }, { 107 .fourcc = V4L2_PIX_FMT_SGRBG10, 108 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 109 .bpp = 10, 110 }, { 111 .fourcc = V4L2_PIX_FMT_SRGGB10, 112 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 113 .bpp = 10, 114 }, { 115 .fourcc = V4L2_PIX_FMT_SBGGR12, 116 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 117 .bpp = 12, 118 }, { 119 .fourcc = V4L2_PIX_FMT_SGBRG12, 120 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 121 .bpp = 12, 122 }, { 123 .fourcc = V4L2_PIX_FMT_SGRBG12, 124 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 125 .bpp = 12, 126 }, { 127 .fourcc = V4L2_PIX_FMT_SRGGB12, 128 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 129 .bpp = 12, 130 }, 131}; 132 133const unsigned int cal_num_formats = ARRAY_SIZE(cal_formats); 134 135const struct cal_format_info *cal_format_by_fourcc(u32 fourcc) 136{ 137 unsigned int i; 138 139 for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) { 140 if (cal_formats[i].fourcc == fourcc) 141 return &cal_formats[i]; 142 } 143 144 return NULL; 145} 146 147const struct cal_format_info *cal_format_by_code(u32 code) 148{ 149 unsigned int i; 150 151 for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) { 152 if (cal_formats[i].code == code) 153 return &cal_formats[i]; 154 } 155 156 return NULL; 157} 158 159/* ------------------------------------------------------------------ 160 * Platform Data 161 * ------------------------------------------------------------------ 162 */ 163 164static const struct cal_camerarx_data dra72x_cal_camerarx[] = { 165 { 166 .fields = { 167 [F_CTRLCLKEN] = { 10, 10 }, 168 [F_CAMMODE] = { 11, 12 }, 169 [F_LANEENABLE] = { 13, 16 }, 170 [F_CSI_MODE] = { 17, 17 }, 171 }, 172 .num_lanes = 4, 173 }, 174 { 175 .fields = { 176 [F_CTRLCLKEN] = { 0, 0 }, 177 [F_CAMMODE] = { 1, 2 }, 178 [F_LANEENABLE] = { 3, 4 }, 179 [F_CSI_MODE] = { 5, 5 }, 180 }, 181 .num_lanes = 2, 182 }, 183}; 184 185static const struct cal_data dra72x_cal_data = { 186 .camerarx = dra72x_cal_camerarx, 187 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx), 188}; 189 190static const struct cal_data dra72x_es1_cal_data = { 191 .camerarx = dra72x_cal_camerarx, 192 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx), 193 .flags = DRA72_CAL_PRE_ES2_LDO_DISABLE, 194}; 195 196static const struct cal_camerarx_data dra76x_cal_csi_phy[] = { 197 { 198 .fields = { 199 [F_CTRLCLKEN] = { 8, 8 }, 200 [F_CAMMODE] = { 9, 10 }, 201 [F_CSI_MODE] = { 11, 11 }, 202 [F_LANEENABLE] = { 27, 31 }, 203 }, 204 .num_lanes = 5, 205 }, 206 { 207 .fields = { 208 [F_CTRLCLKEN] = { 0, 0 }, 209 [F_CAMMODE] = { 1, 2 }, 210 [F_CSI_MODE] = { 3, 3 }, 211 [F_LANEENABLE] = { 24, 26 }, 212 }, 213 .num_lanes = 3, 214 }, 215}; 216 217static const struct cal_data dra76x_cal_data = { 218 .camerarx = dra76x_cal_csi_phy, 219 .num_csi2_phy = ARRAY_SIZE(dra76x_cal_csi_phy), 220}; 221 222static const struct cal_camerarx_data am654_cal_csi_phy[] = { 223 { 224 .fields = { 225 [F_CTRLCLKEN] = { 15, 15 }, 226 [F_CAMMODE] = { 24, 25 }, 227 [F_LANEENABLE] = { 0, 4 }, 228 }, 229 .num_lanes = 5, 230 }, 231}; 232 233static const struct cal_data am654_cal_data = { 234 .camerarx = am654_cal_csi_phy, 235 .num_csi2_phy = ARRAY_SIZE(am654_cal_csi_phy), 236}; 237 238/* ------------------------------------------------------------------ 239 * I/O Register Accessors 240 * ------------------------------------------------------------------ 241 */ 242 243void cal_quickdump_regs(struct cal_dev *cal) 244{ 245 unsigned int i; 246 247 cal_info(cal, "CAL Registers @ 0x%pa:\n", &cal->res->start); 248 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4, 249 (__force const void *)cal->base, 250 resource_size(cal->res), false); 251 252 for (i = 0; i < cal->data->num_csi2_phy; ++i) { 253 struct cal_camerarx *phy = cal->phy[i]; 254 255 cal_info(cal, "CSI2 Core %u Registers @ %pa:\n", i, 256 &phy->res->start); 257 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4, 258 (__force const void *)phy->base, 259 resource_size(phy->res), 260 false); 261 } 262} 263 264/* ------------------------------------------------------------------ 265 * Context Management 266 * ------------------------------------------------------------------ 267 */ 268 269#define CAL_MAX_PIX_PROC 4 270 271static int cal_reserve_pix_proc(struct cal_dev *cal) 272{ 273 unsigned long ret; 274 275 spin_lock(&cal->v4l2_dev.lock); 276 277 ret = find_first_zero_bit(&cal->reserved_pix_proc_mask, CAL_MAX_PIX_PROC); 278 279 if (ret == CAL_MAX_PIX_PROC) { 280 spin_unlock(&cal->v4l2_dev.lock); 281 return -ENOSPC; 282 } 283 284 cal->reserved_pix_proc_mask |= BIT(ret); 285 286 spin_unlock(&cal->v4l2_dev.lock); 287 288 return ret; 289} 290 291static void cal_release_pix_proc(struct cal_dev *cal, unsigned int pix_proc_num) 292{ 293 spin_lock(&cal->v4l2_dev.lock); 294 295 cal->reserved_pix_proc_mask &= ~BIT(pix_proc_num); 296 297 spin_unlock(&cal->v4l2_dev.lock); 298} 299 300static void cal_ctx_csi2_config(struct cal_ctx *ctx) 301{ 302 u32 val; 303 304 val = cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx)); 305 cal_set_field(&val, ctx->cport, CAL_CSI2_CTX_CPORT_MASK); 306 /* 307 * DT type: MIPI CSI-2 Specs 308 * 0x1: All - DT filter is disabled 309 * 0x24: RGB888 1 pixel = 3 bytes 310 * 0x2B: RAW10 4 pixels = 5 bytes 311 * 0x2A: RAW8 1 pixel = 1 byte 312 * 0x1E: YUV422 2 pixels = 4 bytes 313 */ 314 cal_set_field(&val, ctx->datatype, CAL_CSI2_CTX_DT_MASK); 315 cal_set_field(&val, ctx->vc, CAL_CSI2_CTX_VC_MASK); 316 cal_set_field(&val, ctx->v_fmt.fmt.pix.height, CAL_CSI2_CTX_LINES_MASK); 317 cal_set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK); 318 cal_set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE, 319 CAL_CSI2_CTX_PACK_MODE_MASK); 320 cal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), val); 321 ctx_dbg(3, ctx, "CAL_CSI2_CTX(%u, %u) = 0x%08x\n", 322 ctx->phy->instance, ctx->csi2_ctx, 323 cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx))); 324} 325 326static void cal_ctx_pix_proc_config(struct cal_ctx *ctx) 327{ 328 u32 val, extract, pack; 329 330 switch (ctx->fmtinfo->bpp) { 331 case 8: 332 extract = CAL_PIX_PROC_EXTRACT_B8; 333 pack = CAL_PIX_PROC_PACK_B8; 334 break; 335 case 10: 336 extract = CAL_PIX_PROC_EXTRACT_B10_MIPI; 337 pack = CAL_PIX_PROC_PACK_B16; 338 break; 339 case 12: 340 extract = CAL_PIX_PROC_EXTRACT_B12_MIPI; 341 pack = CAL_PIX_PROC_PACK_B16; 342 break; 343 case 16: 344 extract = CAL_PIX_PROC_EXTRACT_B16_LE; 345 pack = CAL_PIX_PROC_PACK_B16; 346 break; 347 default: 348 /* 349 * If you see this warning then it means that you added 350 * some new entry in the cal_formats[] array with a different 351 * bit per pixel values then the one supported below. 352 * Either add support for the new bpp value below or adjust 353 * the new entry to use one of the value below. 354 * 355 * Instead of failing here just use 8 bpp as a default. 356 */ 357 dev_warn_once(ctx->cal->dev, 358 "%s:%d:%s: bpp:%d unsupported! Overwritten with 8.\n", 359 __FILE__, __LINE__, __func__, ctx->fmtinfo->bpp); 360 extract = CAL_PIX_PROC_EXTRACT_B8; 361 pack = CAL_PIX_PROC_PACK_B8; 362 break; 363 } 364 365 val = cal_read(ctx->cal, CAL_PIX_PROC(ctx->pix_proc)); 366 cal_set_field(&val, extract, CAL_PIX_PROC_EXTRACT_MASK); 367 cal_set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK); 368 cal_set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK); 369 cal_set_field(&val, pack, CAL_PIX_PROC_PACK_MASK); 370 cal_set_field(&val, ctx->cport, CAL_PIX_PROC_CPORT_MASK); 371 cal_set_field(&val, 1, CAL_PIX_PROC_EN_MASK); 372 cal_write(ctx->cal, CAL_PIX_PROC(ctx->pix_proc), val); 373 ctx_dbg(3, ctx, "CAL_PIX_PROC(%u) = 0x%08x\n", ctx->pix_proc, 374 cal_read(ctx->cal, CAL_PIX_PROC(ctx->pix_proc))); 375} 376 377static void cal_ctx_wr_dma_config(struct cal_ctx *ctx) 378{ 379 unsigned int stride = ctx->v_fmt.fmt.pix.bytesperline; 380 u32 val; 381 382 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx)); 383 cal_set_field(&val, ctx->cport, CAL_WR_DMA_CTRL_CPORT_MASK); 384 cal_set_field(&val, ctx->v_fmt.fmt.pix.height, 385 CAL_WR_DMA_CTRL_YSIZE_MASK); 386 cal_set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT, 387 CAL_WR_DMA_CTRL_DTAG_MASK); 388 cal_set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR, 389 CAL_WR_DMA_CTRL_PATTERN_MASK); 390 cal_set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK); 391 cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val); 392 ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->dma_ctx, 393 cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx))); 394 395 cal_write_field(ctx->cal, CAL_WR_DMA_OFST(ctx->dma_ctx), 396 stride / 16, CAL_WR_DMA_OFST_MASK); 397 ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->dma_ctx, 398 cal_read(ctx->cal, CAL_WR_DMA_OFST(ctx->dma_ctx))); 399 400 val = cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx)); 401 /* 64 bit word means no skipping */ 402 cal_set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK); 403 /* 404 * The XSIZE field is expressed in 64-bit units and prevents overflows 405 * in case of synchronization issues by limiting the number of bytes 406 * written per line. 407 */ 408 cal_set_field(&val, stride / 8, CAL_WR_DMA_XSIZE_MASK); 409 cal_write(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx), val); 410 ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->dma_ctx, 411 cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx))); 412} 413 414void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr) 415{ 416 cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->dma_ctx), addr); 417} 418 419static void cal_ctx_wr_dma_enable(struct cal_ctx *ctx) 420{ 421 u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx)); 422 423 cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST, 424 CAL_WR_DMA_CTRL_MODE_MASK); 425 cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val); 426} 427 428static void cal_ctx_wr_dma_disable(struct cal_ctx *ctx) 429{ 430 u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx)); 431 432 cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_DIS, 433 CAL_WR_DMA_CTRL_MODE_MASK); 434 cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val); 435} 436 437static bool cal_ctx_wr_dma_stopped(struct cal_ctx *ctx) 438{ 439 bool stopped; 440 441 spin_lock_irq(&ctx->dma.lock); 442 stopped = ctx->dma.state == CAL_DMA_STOPPED; 443 spin_unlock_irq(&ctx->dma.lock); 444 445 return stopped; 446} 447 448static int 449cal_get_remote_frame_desc_entry(struct cal_ctx *ctx, 450 struct v4l2_mbus_frame_desc_entry *entry) 451{ 452 struct v4l2_mbus_frame_desc fd; 453 struct media_pad *phy_source_pad; 454 int ret; 455 456 phy_source_pad = media_pad_remote_pad_first(&ctx->pad); 457 if (!phy_source_pad) 458 return -ENODEV; 459 460 ret = v4l2_subdev_call(&ctx->phy->subdev, pad, get_frame_desc, 461 phy_source_pad->index, &fd); 462 if (ret) 463 return ret; 464 465 if (fd.num_entries != 1) 466 return -EINVAL; 467 468 *entry = fd.entry[0]; 469 470 return 0; 471} 472 473int cal_ctx_prepare(struct cal_ctx *ctx) 474{ 475 struct v4l2_mbus_frame_desc_entry entry; 476 int ret; 477 478 ret = cal_get_remote_frame_desc_entry(ctx, &entry); 479 480 if (ret == -ENOIOCTLCMD) { 481 ctx->vc = 0; 482 ctx->datatype = CAL_CSI2_CTX_DT_ANY; 483 } else if (!ret) { 484 ctx_dbg(2, ctx, "Framedesc: stream %u, len %u, vc %u, dt %#x\n", 485 entry.stream, entry.length, entry.bus.csi2.vc, 486 entry.bus.csi2.dt); 487 488 ctx->vc = entry.bus.csi2.vc; 489 ctx->datatype = entry.bus.csi2.dt; 490 } else { 491 return ret; 492 } 493 494 ctx->use_pix_proc = ctx->vb_vidq.type == V4L2_BUF_TYPE_VIDEO_CAPTURE; 495 496 if (ctx->use_pix_proc) { 497 ret = cal_reserve_pix_proc(ctx->cal); 498 if (ret < 0) { 499 ctx_err(ctx, "Failed to reserve pix proc: %d\n", ret); 500 return ret; 501 } 502 503 ctx->pix_proc = ret; 504 } 505 506 return 0; 507} 508 509void cal_ctx_unprepare(struct cal_ctx *ctx) 510{ 511 if (ctx->use_pix_proc) 512 cal_release_pix_proc(ctx->cal, ctx->pix_proc); 513} 514 515void cal_ctx_start(struct cal_ctx *ctx) 516{ 517 struct cal_camerarx *phy = ctx->phy; 518 519 /* 520 * Reset the frame number & sequence number, but only if the 521 * virtual channel is not already in use. 522 */ 523 524 spin_lock(&phy->vc_lock); 525 526 if (phy->vc_enable_count[ctx->vc]++ == 0) { 527 phy->vc_frame_number[ctx->vc] = 0; 528 phy->vc_sequence[ctx->vc] = 0; 529 } 530 531 spin_unlock(&phy->vc_lock); 532 533 ctx->dma.state = CAL_DMA_RUNNING; 534 535 /* Configure the CSI-2, pixel processing and write DMA contexts. */ 536 cal_ctx_csi2_config(ctx); 537 if (ctx->use_pix_proc) 538 cal_ctx_pix_proc_config(ctx); 539 cal_ctx_wr_dma_config(ctx); 540 541 /* Enable IRQ_WDMA_END and IRQ_WDMA_START. */ 542 cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(1), 543 CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx)); 544 cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2), 545 CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx)); 546 547 cal_ctx_wr_dma_enable(ctx); 548} 549 550void cal_ctx_stop(struct cal_ctx *ctx) 551{ 552 struct cal_camerarx *phy = ctx->phy; 553 long time_left; 554 555 WARN_ON(phy->vc_enable_count[ctx->vc] == 0); 556 557 spin_lock(&phy->vc_lock); 558 phy->vc_enable_count[ctx->vc]--; 559 spin_unlock(&phy->vc_lock); 560 561 /* 562 * Request DMA stop and wait until it completes. If completion times 563 * out, forcefully disable the DMA. 564 */ 565 spin_lock_irq(&ctx->dma.lock); 566 ctx->dma.state = CAL_DMA_STOP_REQUESTED; 567 spin_unlock_irq(&ctx->dma.lock); 568 569 time_left = wait_event_timeout(ctx->dma.wait, cal_ctx_wr_dma_stopped(ctx), 570 msecs_to_jiffies(500)); 571 if (!time_left) { 572 ctx_err(ctx, "failed to disable dma cleanly\n"); 573 cal_ctx_wr_dma_disable(ctx); 574 } 575 576 /* Disable IRQ_WDMA_END and IRQ_WDMA_START. */ 577 cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(1), 578 CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx)); 579 cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(2), 580 CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx)); 581 582 ctx->dma.state = CAL_DMA_STOPPED; 583 584 /* Disable CSI2 context */ 585 cal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), 0); 586 587 /* Disable pix proc */ 588 if (ctx->use_pix_proc) 589 cal_write(ctx->cal, CAL_PIX_PROC(ctx->pix_proc), 0); 590} 591 592/* ------------------------------------------------------------------ 593 * IRQ Handling 594 * ------------------------------------------------------------------ 595 */ 596 597/* 598 * Track a sequence number for each virtual channel, which is shared by 599 * all contexts using the same virtual channel. This is done using the 600 * CSI-2 frame number as a base. 601 */ 602static void cal_update_seq_number(struct cal_ctx *ctx) 603{ 604 struct cal_dev *cal = ctx->cal; 605 struct cal_camerarx *phy = ctx->phy; 606 u16 prev_frame_num, frame_num; 607 u8 vc = ctx->vc; 608 609 frame_num = 610 cal_read(cal, CAL_CSI2_STATUS(phy->instance, ctx->csi2_ctx)) & 611 0xffff; 612 613 if (phy->vc_frame_number[vc] != frame_num) { 614 prev_frame_num = phy->vc_frame_number[vc]; 615 616 if (prev_frame_num >= frame_num) 617 phy->vc_sequence[vc] += 1; 618 else 619 phy->vc_sequence[vc] += frame_num - prev_frame_num; 620 621 phy->vc_frame_number[vc] = frame_num; 622 } 623} 624 625static inline void cal_irq_wdma_start(struct cal_ctx *ctx) 626{ 627 spin_lock(&ctx->dma.lock); 628 629 if (ctx->dma.state == CAL_DMA_STOP_REQUESTED) { 630 /* 631 * If a stop is requested, disable the write DMA context 632 * immediately. The CAL_WR_DMA_CTRL_j.MODE field is shadowed, 633 * the current frame will complete and the DMA will then stop. 634 */ 635 cal_ctx_wr_dma_disable(ctx); 636 ctx->dma.state = CAL_DMA_STOP_PENDING; 637 } else if (!list_empty(&ctx->dma.queue) && !ctx->dma.pending) { 638 /* 639 * Otherwise, if a new buffer is available, queue it to the 640 * hardware. 641 */ 642 struct cal_buffer *buf; 643 dma_addr_t addr; 644 645 buf = list_first_entry(&ctx->dma.queue, struct cal_buffer, 646 list); 647 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); 648 cal_ctx_set_dma_addr(ctx, addr); 649 650 ctx->dma.pending = buf; 651 list_del(&buf->list); 652 } 653 654 spin_unlock(&ctx->dma.lock); 655 656 cal_update_seq_number(ctx); 657} 658 659static inline void cal_irq_wdma_end(struct cal_ctx *ctx) 660{ 661 struct cal_buffer *buf = NULL; 662 663 spin_lock(&ctx->dma.lock); 664 665 /* If the DMA context was stopping, it is now stopped. */ 666 if (ctx->dma.state == CAL_DMA_STOP_PENDING) { 667 ctx->dma.state = CAL_DMA_STOPPED; 668 wake_up(&ctx->dma.wait); 669 } 670 671 /* If a new buffer was queued, complete the current buffer. */ 672 if (ctx->dma.pending) { 673 buf = ctx->dma.active; 674 ctx->dma.active = ctx->dma.pending; 675 ctx->dma.pending = NULL; 676 } 677 678 spin_unlock(&ctx->dma.lock); 679 680 if (buf) { 681 buf->vb.vb2_buf.timestamp = ktime_get_ns(); 682 buf->vb.field = ctx->v_fmt.fmt.pix.field; 683 buf->vb.sequence = ctx->phy->vc_sequence[ctx->vc]; 684 685 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 686 } 687} 688 689static void cal_irq_handle_wdma(struct cal_ctx *ctx, bool start, bool end) 690{ 691 /* 692 * CAL HW interrupts are inherently racy. If we get both start and end 693 * interrupts, we don't know what has happened: did the DMA for a single 694 * frame start and end, or did one frame end and a new frame start? 695 * 696 * Usually for normal pixel frames we get the interrupts separately. If 697 * we do get both, we have to guess. The assumption in the code below is 698 * that the active vertical area is larger than the blanking vertical 699 * area, and thus it is more likely that we get the end of the old frame 700 * and the start of a new frame. 701 * 702 * However, for embedded data, which is only a few lines high, we always 703 * get both interrupts. Here the assumption is that we get both for the 704 * same frame. 705 */ 706 if (ctx->v_fmt.fmt.pix.height < 10) { 707 if (start) 708 cal_irq_wdma_start(ctx); 709 710 if (end) 711 cal_irq_wdma_end(ctx); 712 } else { 713 if (end) 714 cal_irq_wdma_end(ctx); 715 716 if (start) 717 cal_irq_wdma_start(ctx); 718 } 719} 720 721static irqreturn_t cal_irq(int irq_cal, void *data) 722{ 723 struct cal_dev *cal = data; 724 u32 status[3]; 725 unsigned int i; 726 727 for (i = 0; i < 3; ++i) { 728 status[i] = cal_read(cal, CAL_HL_IRQSTATUS(i)); 729 if (status[i]) 730 cal_write(cal, CAL_HL_IRQSTATUS(i), status[i]); 731 } 732 733 if (status[0]) { 734 if (status[0] & CAL_HL_IRQ_OCPO_ERR_MASK) 735 dev_err_ratelimited(cal->dev, "OCPO ERROR\n"); 736 737 for (i = 0; i < cal->data->num_csi2_phy; ++i) { 738 if (status[0] & CAL_HL_IRQ_CIO_MASK(i)) { 739 u32 cio_stat = cal_read(cal, 740 CAL_CSI2_COMPLEXIO_IRQSTATUS(i)); 741 742 dev_err_ratelimited(cal->dev, 743 "CIO%u error: %#08x\n", i, cio_stat); 744 745 cal_write(cal, CAL_CSI2_COMPLEXIO_IRQSTATUS(i), 746 cio_stat); 747 } 748 749 if (status[0] & CAL_HL_IRQ_VC_MASK(i)) { 750 u32 vc_stat = cal_read(cal, CAL_CSI2_VC_IRQSTATUS(i)); 751 752 dev_err_ratelimited(cal->dev, 753 "CIO%u VC error: %#08x\n", 754 i, vc_stat); 755 756 cal_write(cal, CAL_CSI2_VC_IRQSTATUS(i), vc_stat); 757 } 758 } 759 } 760 761 for (i = 0; i < cal->num_contexts; ++i) { 762 bool end = !!(status[1] & CAL_HL_IRQ_WDMA_END_MASK(i)); 763 bool start = !!(status[2] & CAL_HL_IRQ_WDMA_START_MASK(i)); 764 765 if (start || end) 766 cal_irq_handle_wdma(cal->ctx[i], start, end); 767 } 768 769 return IRQ_HANDLED; 770} 771 772/* ------------------------------------------------------------------ 773 * Asynchronous V4L2 subdev binding 774 * ------------------------------------------------------------------ 775 */ 776 777struct cal_v4l2_async_subdev { 778 struct v4l2_async_connection asd; /* Must be first */ 779 struct cal_camerarx *phy; 780}; 781 782static inline struct cal_v4l2_async_subdev * 783to_cal_asd(struct v4l2_async_connection *asd) 784{ 785 return container_of(asd, struct cal_v4l2_async_subdev, asd); 786} 787 788static int cal_async_notifier_bound(struct v4l2_async_notifier *notifier, 789 struct v4l2_subdev *subdev, 790 struct v4l2_async_connection *asd) 791{ 792 struct cal_camerarx *phy = to_cal_asd(asd)->phy; 793 int pad; 794 int ret; 795 796 if (phy->source) { 797 phy_info(phy, "Rejecting subdev %s (Already set!!)", 798 subdev->name); 799 return 0; 800 } 801 802 phy_dbg(1, phy, "Using source %s for capture\n", subdev->name); 803 804 pad = media_entity_get_fwnode_pad(&subdev->entity, 805 of_fwnode_handle(phy->source_ep_node), 806 MEDIA_PAD_FL_SOURCE); 807 if (pad < 0) { 808 phy_err(phy, "Source %s has no connected source pad\n", 809 subdev->name); 810 return pad; 811 } 812 813 ret = media_create_pad_link(&subdev->entity, pad, 814 &phy->subdev.entity, CAL_CAMERARX_PAD_SINK, 815 MEDIA_LNK_FL_IMMUTABLE | 816 MEDIA_LNK_FL_ENABLED); 817 if (ret) { 818 phy_err(phy, "Failed to create media link for source %s\n", 819 subdev->name); 820 return ret; 821 } 822 823 phy->source = subdev; 824 phy->source_pad = pad; 825 826 return 0; 827} 828 829static int cal_async_notifier_complete(struct v4l2_async_notifier *notifier) 830{ 831 struct cal_dev *cal = container_of(notifier, struct cal_dev, notifier); 832 unsigned int i; 833 int ret; 834 835 for (i = 0; i < cal->num_contexts; ++i) { 836 ret = cal_ctx_v4l2_register(cal->ctx[i]); 837 if (ret) 838 goto err_ctx_unreg; 839 } 840 841 if (!cal_mc_api) 842 return 0; 843 844 ret = v4l2_device_register_subdev_nodes(&cal->v4l2_dev); 845 if (ret) 846 goto err_ctx_unreg; 847 848 return 0; 849 850err_ctx_unreg: 851 for (; i > 0; --i) { 852 if (!cal->ctx[i - 1]) 853 continue; 854 855 cal_ctx_v4l2_unregister(cal->ctx[i - 1]); 856 } 857 858 return ret; 859} 860 861static const struct v4l2_async_notifier_operations cal_async_notifier_ops = { 862 .bound = cal_async_notifier_bound, 863 .complete = cal_async_notifier_complete, 864}; 865 866static int cal_async_notifier_register(struct cal_dev *cal) 867{ 868 unsigned int i; 869 int ret; 870 871 v4l2_async_nf_init(&cal->notifier, &cal->v4l2_dev); 872 cal->notifier.ops = &cal_async_notifier_ops; 873 874 for (i = 0; i < cal->data->num_csi2_phy; ++i) { 875 struct cal_camerarx *phy = cal->phy[i]; 876 struct cal_v4l2_async_subdev *casd; 877 struct fwnode_handle *fwnode; 878 879 if (!phy->source_node) 880 continue; 881 882 fwnode = of_fwnode_handle(phy->source_node); 883 casd = v4l2_async_nf_add_fwnode(&cal->notifier, 884 fwnode, 885 struct cal_v4l2_async_subdev); 886 if (IS_ERR(casd)) { 887 phy_err(phy, "Failed to add subdev to notifier\n"); 888 ret = PTR_ERR(casd); 889 goto error; 890 } 891 892 casd->phy = phy; 893 } 894 895 ret = v4l2_async_nf_register(&cal->notifier); 896 if (ret) { 897 cal_err(cal, "Error registering async notifier\n"); 898 goto error; 899 } 900 901 return 0; 902 903error: 904 v4l2_async_nf_cleanup(&cal->notifier); 905 return ret; 906} 907 908static void cal_async_notifier_unregister(struct cal_dev *cal) 909{ 910 v4l2_async_nf_unregister(&cal->notifier); 911 v4l2_async_nf_cleanup(&cal->notifier); 912} 913 914/* ------------------------------------------------------------------ 915 * Media and V4L2 device handling 916 * ------------------------------------------------------------------ 917 */ 918 919/* 920 * Register user-facing devices. To be called at the end of the probe function 921 * when all resources are initialized and ready. 922 */ 923static int cal_media_register(struct cal_dev *cal) 924{ 925 int ret; 926 927 ret = media_device_register(&cal->mdev); 928 if (ret) { 929 cal_err(cal, "Failed to register media device\n"); 930 return ret; 931 } 932 933 /* 934 * Register the async notifier. This may trigger registration of the 935 * V4L2 video devices if all subdevs are ready. 936 */ 937 ret = cal_async_notifier_register(cal); 938 if (ret) { 939 media_device_unregister(&cal->mdev); 940 return ret; 941 } 942 943 return 0; 944} 945 946/* 947 * Unregister the user-facing devices, but don't free memory yet. To be called 948 * at the beginning of the remove function, to disallow access from userspace. 949 */ 950static void cal_media_unregister(struct cal_dev *cal) 951{ 952 unsigned int i; 953 954 /* Unregister all the V4L2 video devices. */ 955 for (i = 0; i < cal->num_contexts; i++) 956 cal_ctx_v4l2_unregister(cal->ctx[i]); 957 958 cal_async_notifier_unregister(cal); 959 media_device_unregister(&cal->mdev); 960} 961 962/* 963 * Initialize the in-kernel objects. To be called at the beginning of the probe 964 * function, before the V4L2 device is used by the driver. 965 */ 966static int cal_media_init(struct cal_dev *cal) 967{ 968 struct media_device *mdev = &cal->mdev; 969 int ret; 970 971 mdev->dev = cal->dev; 972 mdev->hw_revision = cal->revision; 973 strscpy(mdev->model, "CAL", sizeof(mdev->model)); 974 media_device_init(mdev); 975 976 /* 977 * Initialize the V4L2 device (despite the function name, this performs 978 * initialization, not registration). 979 */ 980 cal->v4l2_dev.mdev = mdev; 981 ret = v4l2_device_register(cal->dev, &cal->v4l2_dev); 982 if (ret) { 983 cal_err(cal, "Failed to register V4L2 device\n"); 984 return ret; 985 } 986 987 vb2_dma_contig_set_max_seg_size(cal->dev, DMA_BIT_MASK(32)); 988 989 return 0; 990} 991 992/* 993 * Cleanup the in-kernel objects, freeing memory. To be called at the very end 994 * of the remove sequence, when nothing (including userspace) can access the 995 * objects anymore. 996 */ 997static void cal_media_cleanup(struct cal_dev *cal) 998{ 999 v4l2_device_unregister(&cal->v4l2_dev); 1000 media_device_cleanup(&cal->mdev); 1001 1002 vb2_dma_contig_clear_max_seg_size(cal->dev); 1003} 1004 1005/* ------------------------------------------------------------------ 1006 * Initialization and module stuff 1007 * ------------------------------------------------------------------ 1008 */ 1009 1010static struct cal_ctx *cal_ctx_create(struct cal_dev *cal, int inst) 1011{ 1012 struct cal_ctx *ctx; 1013 int ret; 1014 1015 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1016 if (!ctx) 1017 return NULL; 1018 1019 ctx->cal = cal; 1020 ctx->dma_ctx = inst; 1021 ctx->csi2_ctx = inst; 1022 ctx->cport = inst; 1023 1024 ret = cal_ctx_v4l2_init(ctx); 1025 if (ret) { 1026 kfree(ctx); 1027 return NULL; 1028 } 1029 1030 return ctx; 1031} 1032 1033static void cal_ctx_destroy(struct cal_ctx *ctx) 1034{ 1035 cal_ctx_v4l2_cleanup(ctx); 1036 1037 kfree(ctx); 1038} 1039 1040static const struct of_device_id cal_of_match[] = { 1041 { 1042 .compatible = "ti,dra72-cal", 1043 .data = (void *)&dra72x_cal_data, 1044 }, 1045 { 1046 .compatible = "ti,dra72-pre-es2-cal", 1047 .data = (void *)&dra72x_es1_cal_data, 1048 }, 1049 { 1050 .compatible = "ti,dra76-cal", 1051 .data = (void *)&dra76x_cal_data, 1052 }, 1053 { 1054 .compatible = "ti,am654-cal", 1055 .data = (void *)&am654_cal_data, 1056 }, 1057 {}, 1058}; 1059MODULE_DEVICE_TABLE(of, cal_of_match); 1060 1061/* Get hardware revision and info. */ 1062 1063#define CAL_HL_HWINFO_VALUE 0xa3c90469 1064 1065static void cal_get_hwinfo(struct cal_dev *cal) 1066{ 1067 u32 hwinfo; 1068 1069 cal->revision = cal_read(cal, CAL_HL_REVISION); 1070 switch (FIELD_GET(CAL_HL_REVISION_SCHEME_MASK, cal->revision)) { 1071 case CAL_HL_REVISION_SCHEME_H08: 1072 cal_dbg(3, cal, "CAL HW revision %lu.%lu.%lu (0x%08x)\n", 1073 FIELD_GET(CAL_HL_REVISION_MAJOR_MASK, cal->revision), 1074 FIELD_GET(CAL_HL_REVISION_MINOR_MASK, cal->revision), 1075 FIELD_GET(CAL_HL_REVISION_RTL_MASK, cal->revision), 1076 cal->revision); 1077 break; 1078 1079 case CAL_HL_REVISION_SCHEME_LEGACY: 1080 default: 1081 cal_info(cal, "Unexpected CAL HW revision 0x%08x\n", 1082 cal->revision); 1083 break; 1084 } 1085 1086 hwinfo = cal_read(cal, CAL_HL_HWINFO); 1087 if (hwinfo != CAL_HL_HWINFO_VALUE) 1088 cal_info(cal, "CAL_HL_HWINFO = 0x%08x, expected 0x%08x\n", 1089 hwinfo, CAL_HL_HWINFO_VALUE); 1090} 1091 1092static int cal_init_camerarx_regmap(struct cal_dev *cal) 1093{ 1094 struct platform_device *pdev = to_platform_device(cal->dev); 1095 struct device_node *np = cal->dev->of_node; 1096 struct regmap_config config = { }; 1097 struct regmap *syscon; 1098 struct resource *res; 1099 unsigned int offset; 1100 void __iomem *base; 1101 1102 syscon = syscon_regmap_lookup_by_phandle_args(np, "ti,camerrx-control", 1103 1, &offset); 1104 if (!IS_ERR(syscon)) { 1105 cal->syscon_camerrx = syscon; 1106 cal->syscon_camerrx_offset = offset; 1107 return 0; 1108 } 1109 1110 dev_warn(cal->dev, "failed to get ti,camerrx-control: %pe\n", syscon); 1111 1112 /* 1113 * Backward DTS compatibility. If syscon entry is not present then 1114 * check if the camerrx_control resource is present. 1115 */ 1116 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1117 "camerrx_control"); 1118 base = devm_ioremap_resource(cal->dev, res); 1119 if (IS_ERR(base)) { 1120 cal_err(cal, "failed to ioremap camerrx_control\n"); 1121 return PTR_ERR(base); 1122 } 1123 1124 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n", 1125 res->name, &res->start, &res->end); 1126 1127 config.reg_bits = 32; 1128 config.reg_stride = 4; 1129 config.val_bits = 32; 1130 config.max_register = resource_size(res) - 4; 1131 1132 syscon = regmap_init_mmio(NULL, base, &config); 1133 if (IS_ERR(syscon)) { 1134 pr_err("regmap init failed\n"); 1135 return PTR_ERR(syscon); 1136 } 1137 1138 /* 1139 * In this case the base already point to the direct CM register so no 1140 * need for an offset. 1141 */ 1142 cal->syscon_camerrx = syscon; 1143 cal->syscon_camerrx_offset = 0; 1144 1145 return 0; 1146} 1147 1148static int cal_probe(struct platform_device *pdev) 1149{ 1150 struct cal_dev *cal; 1151 bool connected = false; 1152 unsigned int i; 1153 int ret; 1154 int irq; 1155 1156 cal = devm_kzalloc(&pdev->dev, sizeof(*cal), GFP_KERNEL); 1157 if (!cal) 1158 return -ENOMEM; 1159 1160 cal->data = of_device_get_match_data(&pdev->dev); 1161 if (!cal->data) { 1162 dev_err(&pdev->dev, "Could not get feature data based on compatible version\n"); 1163 return -ENODEV; 1164 } 1165 1166 cal->dev = &pdev->dev; 1167 platform_set_drvdata(pdev, cal); 1168 1169 /* Acquire resources: clocks, CAMERARX regmap, I/O memory and IRQ. */ 1170 cal->fclk = devm_clk_get(&pdev->dev, "fck"); 1171 if (IS_ERR(cal->fclk)) { 1172 dev_err(&pdev->dev, "cannot get CAL fclk\n"); 1173 return PTR_ERR(cal->fclk); 1174 } 1175 1176 ret = cal_init_camerarx_regmap(cal); 1177 if (ret < 0) 1178 return ret; 1179 1180 cal->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1181 "cal_top"); 1182 cal->base = devm_ioremap_resource(&pdev->dev, cal->res); 1183 if (IS_ERR(cal->base)) 1184 return PTR_ERR(cal->base); 1185 1186 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n", 1187 cal->res->name, &cal->res->start, &cal->res->end); 1188 1189 irq = platform_get_irq(pdev, 0); 1190 cal_dbg(1, cal, "got irq# %d\n", irq); 1191 ret = devm_request_irq(&pdev->dev, irq, cal_irq, 0, CAL_MODULE_NAME, 1192 cal); 1193 if (ret) 1194 return ret; 1195 1196 /* Read the revision and hardware info to verify hardware access. */ 1197 pm_runtime_enable(&pdev->dev); 1198 ret = pm_runtime_resume_and_get(&pdev->dev); 1199 if (ret) 1200 goto error_pm_runtime; 1201 1202 cal_get_hwinfo(cal); 1203 pm_runtime_put_sync(&pdev->dev); 1204 1205 /* Initialize the media device. */ 1206 ret = cal_media_init(cal); 1207 if (ret < 0) 1208 goto error_pm_runtime; 1209 1210 /* Create CAMERARX PHYs. */ 1211 for (i = 0; i < cal->data->num_csi2_phy; ++i) { 1212 cal->phy[i] = cal_camerarx_create(cal, i); 1213 if (IS_ERR(cal->phy[i])) { 1214 ret = PTR_ERR(cal->phy[i]); 1215 cal->phy[i] = NULL; 1216 goto error_camerarx; 1217 } 1218 1219 if (cal->phy[i]->source_node) 1220 connected = true; 1221 } 1222 1223 if (!connected) { 1224 cal_err(cal, "Neither port is configured, no point in staying up\n"); 1225 ret = -ENODEV; 1226 goto error_camerarx; 1227 } 1228 1229 /* Create contexts. */ 1230 if (!cal_mc_api) { 1231 for (i = 0; i < cal->data->num_csi2_phy; ++i) { 1232 struct cal_ctx *ctx; 1233 1234 if (!cal->phy[i]->source_node) 1235 continue; 1236 1237 ctx = cal_ctx_create(cal, i); 1238 if (!ctx) { 1239 cal_err(cal, "Failed to create context %u\n", cal->num_contexts); 1240 ret = -ENODEV; 1241 goto error_context; 1242 } 1243 1244 ctx->phy = cal->phy[i]; 1245 1246 cal->ctx[cal->num_contexts++] = ctx; 1247 } 1248 } else { 1249 for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) { 1250 struct cal_ctx *ctx; 1251 1252 ctx = cal_ctx_create(cal, i); 1253 if (!ctx) { 1254 cal_err(cal, "Failed to create context %u\n", i); 1255 ret = -ENODEV; 1256 goto error_context; 1257 } 1258 1259 cal->ctx[cal->num_contexts++] = ctx; 1260 } 1261 } 1262 1263 /* Register the media device. */ 1264 ret = cal_media_register(cal); 1265 if (ret) 1266 goto error_context; 1267 1268 return 0; 1269 1270error_context: 1271 for (i = 0; i < cal->num_contexts; i++) 1272 cal_ctx_destroy(cal->ctx[i]); 1273 1274error_camerarx: 1275 for (i = 0; i < cal->data->num_csi2_phy; i++) 1276 cal_camerarx_destroy(cal->phy[i]); 1277 1278 cal_media_cleanup(cal); 1279 1280error_pm_runtime: 1281 pm_runtime_disable(&pdev->dev); 1282 1283 return ret; 1284} 1285 1286static void cal_remove(struct platform_device *pdev) 1287{ 1288 struct cal_dev *cal = platform_get_drvdata(pdev); 1289 unsigned int i; 1290 int ret; 1291 1292 cal_dbg(1, cal, "Removing %s\n", CAL_MODULE_NAME); 1293 1294 ret = pm_runtime_resume_and_get(&pdev->dev); 1295 1296 cal_media_unregister(cal); 1297 1298 for (i = 0; i < cal->data->num_csi2_phy; i++) 1299 cal_camerarx_disable(cal->phy[i]); 1300 1301 for (i = 0; i < cal->num_contexts; i++) 1302 cal_ctx_destroy(cal->ctx[i]); 1303 1304 for (i = 0; i < cal->data->num_csi2_phy; i++) 1305 cal_camerarx_destroy(cal->phy[i]); 1306 1307 cal_media_cleanup(cal); 1308 1309 if (ret >= 0) 1310 pm_runtime_put_sync(&pdev->dev); 1311 pm_runtime_disable(&pdev->dev); 1312} 1313 1314static int cal_runtime_resume(struct device *dev) 1315{ 1316 struct cal_dev *cal = dev_get_drvdata(dev); 1317 unsigned int i; 1318 u32 val; 1319 1320 if (cal->data->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) { 1321 /* 1322 * Apply errata on both port everytime we (re-)enable 1323 * the clock 1324 */ 1325 for (i = 0; i < cal->data->num_csi2_phy; i++) 1326 cal_camerarx_i913_errata(cal->phy[i]); 1327 } 1328 1329 /* 1330 * Enable global interrupts that are not related to a particular 1331 * CAMERARAX or context. 1332 */ 1333 cal_write(cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK); 1334 1335 val = cal_read(cal, CAL_CTRL); 1336 cal_set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, 1337 CAL_CTRL_BURSTSIZE_MASK); 1338 cal_set_field(&val, 0xf, CAL_CTRL_TAGCNT_MASK); 1339 cal_set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED, 1340 CAL_CTRL_POSTED_WRITES_MASK); 1341 cal_set_field(&val, 0xff, CAL_CTRL_MFLAGL_MASK); 1342 cal_set_field(&val, 0xff, CAL_CTRL_MFLAGH_MASK); 1343 cal_write(cal, CAL_CTRL, val); 1344 cal_dbg(3, cal, "CAL_CTRL = 0x%08x\n", cal_read(cal, CAL_CTRL)); 1345 1346 return 0; 1347} 1348 1349static const struct dev_pm_ops cal_pm_ops = { 1350 .runtime_resume = cal_runtime_resume, 1351}; 1352 1353static struct platform_driver cal_pdrv = { 1354 .probe = cal_probe, 1355 .remove = cal_remove, 1356 .driver = { 1357 .name = CAL_MODULE_NAME, 1358 .pm = &cal_pm_ops, 1359 .of_match_table = cal_of_match, 1360 }, 1361}; 1362 1363module_platform_driver(cal_pdrv);
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