snps_hdmirx.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
  4 *
  5 * Author: Dingxian Wen <shawn.wen@rock-chips.com>
  6 */
  7
  8#ifndef DW_HDMIRX_H
  9#define DW_HDMIRX_H
 10
 11#include <linux/bitfield.h>
 12#include <linux/bitops.h>
 13#include <linux/hw_bitfield.h>
 14
 15#define UPDATE(x, h, l)		FIELD_PREP(GENMASK((h), (l)), (x))
 16#define HIWORD_UPDATE(v, h, l)	FIELD_PREP_WM16(GENMASK((h), (l)), (v))
 17
 18/* SYS_GRF */
 19#define SYS_GRF_SOC_CON1			0x0304
 20#define HDMIRXPHY_SRAM_EXT_LD_DONE		BIT(1)
 21#define HDMIRXPHY_SRAM_BYPASS			BIT(0)
 22#define SYS_GRF_SOC_STATUS1			0x0384
 23#define HDMIRXPHY_SRAM_INIT_DONE		BIT(10)
 24#define SYS_GRF_CHIP_ID				0x0600
 25
 26/* VO1_GRF */
 27#define VO1_GRF_VO1_CON2			0x0008
 28#define HDMIRX_SDAIN_MSK			BIT(2)
 29#define HDMIRX_SCLIN_MSK			BIT(1)
 30
 31/* HDMIRX PHY */
 32#define SUP_DIG_ANA_CREGS_SUP_ANA_NC			0x004f
 33
 34#define	LANE0_DIG_ASIC_RX_OVRD_OUT_0			0x100f
 35#define	LANE1_DIG_ASIC_RX_OVRD_OUT_0			0x110f
 36#define	LANE2_DIG_ASIC_RX_OVRD_OUT_0			0x120f
 37#define	LANE3_DIG_ASIC_RX_OVRD_OUT_0			0x130f
 38#define ASIC_ACK_OVRD_EN				BIT(1)
 39#define ASIC_ACK					BIT(0)
 40
 41#define	LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x104a
 42#define	LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x114a
 43#define	LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x124a
 44#define	LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2		0x134a
 45#define FREQ_TUNE_START_VAL_MASK			GENMASK(9, 0)
 46#define FREQ_TUNE_START_VAL(x)				UPDATE(x, 9, 0)
 47
 48#define	HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG	0x20c4
 49#define	HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM	0x20c7
 50#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG	0x20e9
 51#define CDR_SETTING_BOUNDARY_3_DEFAULT			0x52da
 52#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG	0x20ea
 53#define CDR_SETTING_BOUNDARY_4_DEFAULT			0x43cd
 54#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG	0x20eb
 55#define CDR_SETTING_BOUNDARY_5_DEFAULT			0x35b3
 56#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG	0x20fb
 57#define	CDR_SETTING_BOUNDARY_6_DEFAULT			0x2799
 58#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG	0x20fc
 59#define CDR_SETTING_BOUNDARY_7_DEFAULT			0x1b65
 60
 61#define	RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT			0x300e
 62#define	RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT			0x310e
 63#define	RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT			0x320e
 64#define	RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT			0x330e
 65#define PCS_ACK_WRITE_SELECT				BIT(14)
 66#define PCS_EN_CTL					BIT(1)
 67#define PCS_ACK						BIT(0)
 68
 69#define	RAWLANE0_DIG_AON_FAST_FLAGS			0x305c
 70#define	RAWLANE1_DIG_AON_FAST_FLAGS			0x315c
 71#define	RAWLANE2_DIG_AON_FAST_FLAGS			0x325c
 72#define	RAWLANE3_DIG_AON_FAST_FLAGS			0x335c
 73
 74/* HDMIRX Ctrler */
 75#define GLOBAL_SWRESET_REQUEST			0x0020
 76#define DATAPATH_SWRESETREQ			BIT(12)
 77#define GLOBAL_SWENABLE				0x0024
 78#define PHYCTRL_ENABLE				BIT(21)
 79#define CEC_ENABLE				BIT(16)
 80#define TMDS_ENABLE				BIT(13)
 81#define DATAPATH_ENABLE				BIT(12)
 82#define PKTFIFO_ENABLE				BIT(11)
 83#define AVPUNIT_ENABLE				BIT(8)
 84#define MAIN_ENABLE				BIT(0)
 85#define GLOBAL_TIMER_REF_BASE			0x0028
 86#define CORE_CONFIG				0x0050
 87#define CMU_CONFIG0				0x0060
 88#define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK	GENMASK(30, 16)
 89#define TMDSQPCLK_STABLE_FREQ_MARGIN(x)		UPDATE(x, 30, 16)
 90#define AUDCLK_STABLE_FREQ_MARGIN_MASK		GENMASK(11, 9)
 91#define AUDCLK_STABLE_FREQ_MARGIN(x)		UPDATE(x, 11, 9)
 92#define CMU_STATUS				0x007c
 93#define TMDSQPCLK_LOCKED_ST			BIT(4)
 94#define CMU_TMDSQPCLK_FREQ			0x0084
 95#define PHY_CONFIG				0x00c0
 96#define LDO_AFE_PROG_MASK			GENMASK(24, 23)
 97#define LDO_AFE_PROG(x)				UPDATE(x, 24, 23)
 98#define LDO_PWRDN				BIT(21)
 99#define TMDS_CLOCK_RATIO			BIT(16)
100#define RXDATA_WIDTH				BIT(15)
101#define REFFREQ_SEL_MASK			GENMASK(11, 9)
102#define REFFREQ_SEL(x)				UPDATE(x, 11, 9)
103#define HDMI_DISABLE				BIT(8)
104#define PHY_PDDQ				BIT(1)
105#define PHY_RESET				BIT(0)
106#define PHY_STATUS				0x00c8
107#define HDMI_DISABLE_ACK			BIT(1)
108#define PDDQ_ACK				BIT(0)
109#define PHYCREG_CONFIG0				0x00e0
110#define PHYCREG_CR_PARA_SELECTION_MODE_MASK	GENMASK(1, 0)
111#define PHYCREG_CR_PARA_SELECTION_MODE(x)	UPDATE(x, 1, 0)
112#define PHYCREG_CONFIG1				0x00e4
113#define PHYCREG_CONFIG2				0x00e8
114#define PHYCREG_CONFIG3				0x00ec
115#define PHYCREG_CONTROL				0x00f0
116#define PHYCREG_CR_PARA_WRITE_P			BIT(1)
117#define PHYCREG_CR_PARA_READ_P			BIT(0)
118#define PHYCREG_STATUS				0x00f4
119
120#define MAINUNIT_STATUS				0x0150
121#define TMDSVALID_STABLE_ST			BIT(1)
122#define DESCRAND_EN_CONTROL			0x0210
123#define SCRAMB_EN_SEL_QST_MASK			GENMASK(1, 0)
124#define SCRAMB_EN_SEL_QST(x)			UPDATE(x, 1, 0)
125#define DESCRAND_SYNC_CONTROL			0x0214
126#define RECOVER_UNSYNC_STREAM_QST		BIT(0)
127#define DESCRAND_SYNC_SEQ_CONFIG		0x022c
128#define DESCRAND_SYNC_SEQ_ERR_CNT_EN		BIT(0)
129#define DESCRAND_SYNC_SEQ_STATUS		0x0234
130#define DEFRAMER_CONFIG0			0x0270
131#define VS_CNT_THR_QST_MASK			GENMASK(27, 20)
132#define VS_CNT_THR_QST(x)			UPDATE(x, 27, 20)
133#define HS_POL_QST_MASK				GENMASK(19, 18)
134#define HS_POL_QST(x)				UPDATE(x, 19, 18)
135#define VS_POL_QST_MASK				GENMASK(17, 16)
136#define VS_POL_QST(x)				UPDATE(x, 17, 16)
137#define VS_REMAPFILTER_EN_QST			BIT(8)
138#define VS_FILTER_ORDER_QST_MASK		GENMASK(1, 0)
139#define VS_FILTER_ORDER_QST(x)			UPDATE(x, 1, 0)
140#define DEFRAMER_VSYNC_CNT_CLEAR		0x0278
141#define VSYNC_CNT_CLR_P				BIT(0)
142#define DEFRAMER_STATUS				0x027c
143#define OPMODE_STS_MASK				GENMASK(6, 4)
144#define I2C_SLAVE_CONFIG1			0x0164
145#define I2C_SDA_OUT_HOLD_VALUE_QST_MASK		GENMASK(15, 8)
146#define I2C_SDA_OUT_HOLD_VALUE_QST(x)		UPDATE(x, 15, 8)
147#define I2C_SDA_IN_HOLD_VALUE_QST_MASK		GENMASK(7, 0)
148#define I2C_SDA_IN_HOLD_VALUE_QST(x)		UPDATE(x, 7, 0)
149#define OPMODE_STS_MASK				GENMASK(6, 4)
150#define REPEATER_QST				BIT(28)
151#define FASTREAUTH_QST				BIT(27)
152#define FEATURES_1DOT1_QST			BIT(26)
153#define FASTI2C_QST				BIT(25)
154#define EESS_CTL_THR_QST_MASK			GENMASK(19, 16)
155#define EESS_CTL_THR_QST(x)			UPDATE(x, 19, 16)
156#define OESS_CTL3_THR_QST_MASK			GENMASK(11, 8)
157#define OESS_CTL3_THR_QST(x)			UPDATE(x, 11, 8)
158#define EESS_OESS_SEL_QST_MASK			GENMASK(5, 4)
159#define EESS_OESS_SEL_QST(x)			UPDATE(x, 5, 4)
160#define KEY_DECRYPT_EN_QST			BIT(0)
161#define KEY_DECRYPT_SEED_QST_MASK		GENMASK(15, 0)
162#define KEY_DECRYPT_SEED_QST(x)			UPDATE(x, 15, 0)
163#define HDCP_INT_CLEAR				0x50d8
164#define HDCP_1_INT_CLEAR			0x50e8
165#define HDCP2_CONFIG				0x02f0
166#define HDCP2_SWITCH_OVR_VALUE			BIT(2)
167#define HDCP2_SWITCH_OVR_EN			BIT(1)
168
169#define VIDEO_CONFIG2				0x042c
170#define VPROC_VSYNC_POL_OVR_VALUE		BIT(19)
171#define VPROC_VSYNC_POL_OVR_EN			BIT(18)
172#define VPROC_HSYNC_POL_OVR_VALUE		BIT(17)
173#define VPROC_HSYNC_POL_OVR_EN			BIT(16)
174#define VPROC_FMT_OVR_VALUE_MASK		GENMASK(6, 4)
175#define VPROC_FMT_OVR_VALUE(x)			UPDATE(x, 6, 4)
176#define VPROC_FMT_OVR_EN			BIT(0)
177
178#define AFIFO_FILL_RESTART			BIT(0)
179#define AFIFO_INIT_P				BIT(0)
180#define AFIFO_THR_LOW_QST_MASK			GENMASK(25, 16)
181#define AFIFO_THR_LOW_QST(x)			UPDATE(x, 25, 16)
182#define AFIFO_THR_HIGH_QST_MASK			GENMASK(9, 0)
183#define AFIFO_THR_HIGH_QST(x)			UPDATE(x, 9, 0)
184#define AFIFO_THR_MUTE_LOW_QST_MASK		GENMASK(25, 16)
185#define AFIFO_THR_MUTE_LOW_QST(x)		UPDATE(x, 25, 16)
186#define AFIFO_THR_MUTE_HIGH_QST_MASK		GENMASK(9, 0)
187#define AFIFO_THR_MUTE_HIGH_QST(x)		UPDATE(x, 9, 0)
188
189#define AFIFO_UNDERFLOW_ST			BIT(25)
190#define AFIFO_OVERFLOW_ST			BIT(24)
191
192#define SPEAKER_ALLOC_OVR_EN			BIT(16)
193#define I2S_BPCUV_EN				BIT(4)
194#define SPDIF_EN				BIT(2)
195#define I2S_EN					BIT(1)
196#define AFIFO_THR_PASS_DEMUTEMASK_N		BIT(24)
197#define AVMUTE_DEMUTEMASK_N			BIT(16)
198#define AFIFO_THR_MUTE_LOW_MUTEMASK_N		BIT(9)
199#define AFIFO_THR_MUTE_HIGH_MUTEMASK_N		BIT(8)
200#define AVMUTE_MUTEMASK_N			BIT(0)
201#define SCDC_CONFIG				0x0580
202#define HPDLOW					BIT(1)
203#define POWERPROVIDED				BIT(0)
204#define SCDC_REGBANK_STATUS1			0x058c
205#define SCDC_TMDSBITCLKRATIO			BIT(1)
206#define SCDC_REGBANK_STATUS3			0x0594
207#define SCDC_REGBANK_CONFIG0			0x05c0
208#define SCDC_SINKVERSION_QST_MASK		GENMASK(7, 0)
209#define SCDC_SINKVERSION_QST(x)			UPDATE(x, 7, 0)
210#define AGEN_LAYOUT				BIT(4)
211#define AGEN_SPEAKER_ALLOC			GENMASK(15, 8)
212
213#define CED_CONFIG				0x0760
214#define CED_VIDDATACHECKEN_QST			BIT(27)
215#define CED_DATAISCHECKEN_QST			BIT(26)
216#define CED_GBCHECKEN_QST			BIT(25)
217#define CED_CTRLCHECKEN_QST			BIT(24)
218#define CED_CHLOCKMAXER_QST_MASK		GENMASK(14, 0)
219#define CED_CHLOCKMAXER_QST(x)			UPDATE(x, 14, 0)
220#define CED_DYN_CONFIG				0x0768
221#define CED_DYN_CONTROL				0x076c
222#define PKTEX_BCH_ERRFILT_CONFIG		0x07c4
223#define PKTEX_CHKSUM_ERRFILT_CONFIG		0x07c8
224
225#define PKTDEC_ACR_PH2_1			0x1100
226#define PKTDEC_ACR_PB3_0			0x1104
227#define PKTDEC_ACR_PB7_4			0x1108
228#define PKTDEC_AVIIF_PH2_1			0x1200
229#define PKTDEC_AVIIF_PB3_0			0x1204
230#define PKTDEC_AVIIF_PB7_4			0x1208
231#define VIC_VAL_MASK				GENMASK(6, 0)
232#define PKTDEC_AVIIF_PB11_8			0x120c
233#define PKTDEC_AVIIF_PB15_12			0x1210
234#define PKTDEC_AVIIF_PB19_16			0x1214
235#define PKTDEC_AVIIF_PB23_20			0x1218
236#define PKTDEC_AVIIF_PB27_24			0x121c
237
238#define PKTFIFO_CONFIG				0x1500
239#define PKTFIFO_STORE_FILT_CONFIG		0x1504
240#define PKTFIFO_THR_CONFIG0			0x1508
241#define PKTFIFO_THR_CONFIG1			0x150c
242#define PKTFIFO_CONTROL				0x1510
243
244#define VMON_STATUS1				0x1580
245#define VMON_STATUS2				0x1584
246#define VMON_STATUS3				0x1588
247#define VMON_STATUS4				0x158c
248#define VMON_STATUS5				0x1590
249#define VMON_STATUS6				0x1594
250#define VMON_STATUS7				0x1598
251#define VMON_ILACE_DETECT			BIT(4)
252
253#define CEC_TX_CONTROL				0x2000
254#define CEC_STATUS				0x2004
255#define CEC_CONFIG				0x2008
256#define RX_AUTO_DRIVE_ACKNOWLEDGE		BIT(9)
257#define CEC_ADDR				0x200c
258#define CEC_TX_COUNT				0x2020
259#define CEC_TX_DATA3_0				0x2024
260#define CEC_RX_COUNT_STATUS			0x2040
261#define CEC_RX_DATA3_0				0x2044
262#define CEC_LOCK_CONTROL			0x2054
263#define CEC_RXQUAL_BITTIME_CONFIG		0x2060
264#define CEC_RX_BITTIME_CONFIG			0x2064
265#define CEC_TX_BITTIME_CONFIG			0x2068
266
267#define DMA_CONFIG1				0x4400
268#define UV_WID_MASK				GENMASK(31, 28)
269#define UV_WID(x)				UPDATE(x, 31, 28)
270#define Y_WID_MASK				GENMASK(27, 24)
271#define Y_WID(x)				UPDATE(x, 27, 24)
272#define DDR_STORE_FORMAT_MASK			GENMASK(15, 12)
273#define DDR_STORE_FORMAT(x)			UPDATE(x, 15, 12)
274#define ABANDON_EN				BIT(0)
275#define DMA_CONFIG2				0x4404
276#define DMA_CONFIG3				0x4408
277#define DMA_CONFIG4				0x440c // dma irq en
278#define DMA_CONFIG5				0x4410 // dma irq clear status
279#define LINE_FLAG_INT_EN			BIT(8)
280#define HDMIRX_DMA_IDLE_INT			BIT(7)
281#define HDMIRX_LOCK_DISABLE_INT			BIT(6)
282#define LAST_FRAME_AXI_UNFINISH_INT_EN		BIT(5)
283#define FIFO_OVERFLOW_INT_EN			BIT(2)
284#define FIFO_UNDERFLOW_INT_EN			BIT(1)
285#define HDMIRX_AXI_ERROR_INT_EN			BIT(0)
286#define DMA_CONFIG6				0x4414
287#define RB_SWAP_EN				BIT(9)
288#define HSYNC_TOGGLE_EN				BIT(5)
289#define VSYNC_TOGGLE_EN				BIT(4)
290#define HDMIRX_DMA_EN				BIT(1)
291#define DMA_CONFIG7				0x4418
292#define LINE_FLAG_NUM_MASK			GENMASK(31, 16)
293#define LINE_FLAG_NUM(x)			UPDATE(x, 31, 16)
294#define LOCK_FRAME_NUM_MASK			GENMASK(11, 0)
295#define LOCK_FRAME_NUM(x)			UPDATE(x, 11, 0)
296#define DMA_CONFIG8				0x441c
297#define REG_MIRROR_EN				BIT(0)
298#define DMA_CONFIG9				0x4420
299#define DMA_CONFIG10				0x4424
300#define DMA_CONFIG11				0x4428
301#define EDID_READ_EN_MASK			BIT(8)
302#define EDID_READ_EN(x)				UPDATE(x, 8, 8)
303#define EDID_WRITE_EN_MASK			BIT(7)
304#define EDID_WRITE_EN(x)			UPDATE(x, 7, 7)
305#define EDID_SLAVE_ADDR_MASK			GENMASK(6, 0)
306#define EDID_SLAVE_ADDR(x)			UPDATE(x, 6, 0)
307#define DMA_STATUS1				0x4430 // dma irq status
308#define DMA_STATUS2				0x4434
309#define DMA_STATUS3				0x4438
310#define DMA_STATUS4				0x443c
311#define DMA_STATUS5				0x4440
312#define DMA_STATUS6				0x4444
313#define DMA_STATUS7				0x4448
314#define DMA_STATUS8				0x444c
315#define DMA_STATUS9				0x4450
316#define DMA_STATUS10				0x4454
317#define HDMIRX_LOCK				BIT(3)
318#define DMA_STATUS11				0x4458
319#define HDMIRX_TYPE_MASK			GENMASK(8, 7)
320#define HDMIRX_COLOR_DEPTH_MASK			GENMASK(6, 3)
321#define HDMIRX_FORMAT_MASK			GENMASK(2, 0)
322#define DMA_STATUS12				0x445c
323#define DMA_STATUS13				0x4460
324#define DMA_STATUS14				0x4464
325
326#define MAINUNIT_INTVEC_INDEX			0x5000
327#define MAINUNIT_0_INT_STATUS			0x5010
328#define CECRX_NOTIFY_ERR			BIT(12)
329#define CECRX_EOM				BIT(11)
330#define CECTX_DRIVE_ERR				BIT(10)
331#define CECRX_BUSY				BIT(9)
332#define CECTX_BUSY				BIT(8)
333#define CECTX_FRAME_DISCARDED			BIT(5)
334#define CECTX_NRETRANSMIT_FAIL			BIT(4)
335#define CECTX_LINE_ERR				BIT(3)
336#define CECTX_ARBLOST				BIT(2)
337#define CECTX_NACK				BIT(1)
338#define CECTX_DONE				BIT(0)
339#define MAINUNIT_0_INT_MASK_N			0x5014
340#define MAINUNIT_0_INT_CLEAR			0x5018
341#define MAINUNIT_0_INT_FORCE			0x501c
342#define TIMER_BASE_LOCKED_IRQ			BIT(26)
343#define TMDSQPCLK_OFF_CHG			BIT(5)
344#define TMDSQPCLK_LOCKED_CHG			BIT(4)
345#define MAINUNIT_1_INT_STATUS			0x5020
346#define MAINUNIT_1_INT_MASK_N			0x5024
347#define MAINUNIT_1_INT_CLEAR			0x5028
348#define MAINUNIT_1_INT_FORCE			0x502c
349#define MAINUNIT_2_INT_STATUS			0x5030
350#define MAINUNIT_2_INT_MASK_N			0x5034
351#define MAINUNIT_2_INT_CLEAR			0x5038
352#define MAINUNIT_2_INT_FORCE			0x503c
353#define PHYCREG_CR_READ_DONE			BIT(11)
354#define PHYCREG_CR_WRITE_DONE			BIT(10)
355#define TMDSVALID_STABLE_CHG			BIT(1)
356
357#define AVPUNIT_0_INT_STATUS			0x5040
358#define AVPUNIT_0_INT_MASK_N			0x5044
359#define AVPUNIT_0_INT_CLEAR			0x5048
360#define AVPUNIT_0_INT_FORCE			0x504c
361#define CED_DYN_CNT_CH2_IRQ			BIT(22)
362#define CED_DYN_CNT_CH1_IRQ			BIT(21)
363#define CED_DYN_CNT_CH0_IRQ			BIT(20)
364#define AVPUNIT_1_INT_STATUS			0x5050
365#define DEFRAMER_VSYNC_THR_REACHED_IRQ		BIT(1)
366#define AVPUNIT_1_INT_MASK_N			0x5054
367#define DEFRAMER_VSYNC_THR_REACHED_MASK_N	BIT(1)
368#define DEFRAMER_VSYNC_MASK_N			BIT(0)
369#define AVPUNIT_1_INT_CLEAR			0x5058
370#define DEFRAMER_VSYNC_THR_REACHED_CLEAR	BIT(1)
371#define PKT_0_INT_STATUS			0x5080
372#define PKTDEC_ACR_CHG_IRQ			BIT(3)
373#define PKT_0_INT_MASK_N			0x5084
374#define PKTDEC_ACR_CHG_MASK_N			BIT(3)
375#define PKT_0_INT_CLEAR				0x5088
376#define PKT_1_INT_STATUS			0x5090
377#define PKT_1_INT_MASK_N			0x5094
378#define PKT_1_INT_CLEAR				0x5098
379#define PKT_2_INT_STATUS			0x50a0
380#define PKTDEC_ACR_RCV_IRQ			BIT(3)
381#define PKT_2_INT_MASK_N			0x50a4
382#define PKTDEC_AVIIF_RCV_IRQ			BIT(11)
383#define PKTDEC_ACR_RCV_MASK_N			BIT(3)
384#define PKT_2_INT_CLEAR				0x50a8
385#define PKTDEC_AVIIF_RCV_CLEAR			BIT(11)
386#define PKTDEC_ACR_RCV_CLEAR			BIT(3)
387#define SCDC_INT_STATUS				0x50c0
388#define SCDC_INT_MASK_N				0x50c4
389#define SCDC_INT_CLEAR				0x50c8
390#define SCDCTMDSCCFG_CHG			BIT(2)
391
392#define CEC_INT_STATUS				0x5100
393#define CEC_INT_MASK_N				0x5104
394#define CEC_INT_CLEAR				0x5108
395
396#endif