dma2d.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * ST stm32 DMA2D - 2D Graphics Accelerator Driver
  4 *
  5 * Copyright (c) 2021 Dillon Min
  6 * Dillon Min, <dillon.minfei@gmail.com>
  7 *
  8 * based on s5p-g2d
  9 *
 10 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 11 * Kamil Debski, <k.debski@samsung.com>
 12 */
 13
 14#ifndef __DMA2D_H__
 15#define __DMA2D_H__
 16
 17#include <linux/platform_device.h>
 18#include <media/v4l2-device.h>
 19#include <media/v4l2-ctrls.h>
 20
 21#define DMA2D_NAME "stm-dma2d"
 22#define BUS_INFO "platform:stm-dma2d"
 23enum dma2d_op_mode {
 24	DMA2D_MODE_M2M,
 25	DMA2D_MODE_M2M_FPC,
 26	DMA2D_MODE_M2M_BLEND,
 27	DMA2D_MODE_R2M
 28};
 29
 30enum dma2d_cmode {
 31	/* output pfc cmode from ARGB888 to ARGB4444 */
 32	DMA2D_CMODE_ARGB8888,
 33	DMA2D_CMODE_RGB888,
 34	DMA2D_CMODE_RGB565,
 35	DMA2D_CMODE_ARGB1555,
 36	DMA2D_CMODE_ARGB4444,
 37	/* bg or fg pfc cmode from L8 to A4 */
 38	DMA2D_CMODE_L8,
 39	DMA2D_CMODE_AL44,
 40	DMA2D_CMODE_AL88,
 41	DMA2D_CMODE_L4,
 42	DMA2D_CMODE_A8,
 43	DMA2D_CMODE_A4
 44};
 45
 46enum dma2d_alpha_mode {
 47	DMA2D_ALPHA_MODE_NO_MODIF,
 48	DMA2D_ALPHA_MODE_REPLACE,
 49	DMA2D_ALPHA_MODE_COMBINE
 50};
 51
 52struct dma2d_fmt {
 53	u32	fourcc;
 54	int	depth;
 55	enum dma2d_cmode cmode;
 56};
 57
 58struct dma2d_frame {
 59	/* Original dimensions */
 60	u32	width;
 61	u32	height;
 62	/* Crop size */
 63	u32	c_width;
 64	u32	c_height;
 65	/* Offset */
 66	u32	o_width;
 67	u32	o_height;
 68	u32	bottom;
 69	u32	right;
 70	u16	line_offset;
 71	/* Image format */
 72	struct dma2d_fmt *fmt;
 73	/* [0]: blue
 74	 * [1]: green
 75	 * [2]: red
 76	 * [3]: alpha
 77	 */
 78	u8	a_rgb[4];
 79	/*
 80	 * AM[1:0] of DMA2D_FGPFCCR
 81	 */
 82	enum dma2d_alpha_mode a_mode;
 83	u32 size;
 84	unsigned int	sequence;
 85};
 86
 87struct dma2d_ctx {
 88	struct v4l2_fh fh;
 89	struct dma2d_dev	*dev;
 90	struct dma2d_frame	cap;
 91	struct dma2d_frame	out;
 92	struct dma2d_frame	bg;
 93	/*
 94	 * MODE[17:16] of DMA2D_CR
 95	 */
 96	enum dma2d_op_mode	op_mode;
 97	struct v4l2_ctrl_handler ctrl_handler;
 98	enum v4l2_colorspace	colorspace;
 99	enum v4l2_ycbcr_encoding ycbcr_enc;
100	enum v4l2_xfer_func	xfer_func;
101	enum v4l2_quantization	quant;
102};
103
104struct dma2d_dev {
105	struct v4l2_device	v4l2_dev;
106	struct v4l2_m2m_dev	*m2m_dev;
107	struct video_device	*vfd;
108	/* for device open/close etc */
109	struct mutex		mutex;
110	/* to avoid the conflict with device running and user setting
111	 * at the same time
112	 */
113	spinlock_t		ctrl_lock;
114	atomic_t		num_inst;
115	void __iomem		*regs;
116	struct clk		*gate;
117	struct dma2d_ctx	*curr;
118	int irq;
119};
120
121void dma2d_start(struct dma2d_dev *d);
122u32 dma2d_get_int(struct dma2d_dev *d);
123void dma2d_clear_int(struct dma2d_dev *d);
124void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm,
125		      dma_addr_t o_addr);
126void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm,
127		     dma_addr_t f_addr);
128void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm,
129		     dma_addr_t b_addr);
130void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode,
131			 u16 width, u16 height);
132
133#endif /* __DMA2D_H__ */