s5p_mfc_opr_v6.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
   4 *
   5 * Samsung MFC (Multi Function Codec - FIMV) driver
   6 * This file contains hw related functions.
   7 *
   8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9 *		http://www.samsung.com/
  10 */
  11
  12#undef DEBUG
  13
  14#include <linux/delay.h>
  15#include <linux/mm.h>
  16#include <linux/io.h>
  17#include <linux/jiffies.h>
  18#include <linux/firmware.h>
  19#include <linux/err.h>
  20#include <linux/sched.h>
  21#include <linux/dma-mapping.h>
  22
  23#include <asm/cacheflush.h>
  24
  25#include "s5p_mfc_common.h"
  26#include "s5p_mfc_cmd.h"
  27#include "s5p_mfc_intr.h"
  28#include "s5p_mfc_pm.h"
  29#include "s5p_mfc_debug.h"
  30#include "s5p_mfc_opr.h"
  31#include "s5p_mfc_opr_v6.h"
  32
  33/* #define S5P_MFC_DEBUG_REGWRITE  */
  34#ifdef S5P_MFC_DEBUG_REGWRITE
  35#undef writel
  36#define writel(v, r)							\
  37	do {								\
  38		pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v);	\
  39	__raw_writel(v, r);						\
  40	} while (0)
  41#endif /* S5P_MFC_DEBUG_REGWRITE */
  42
  43#define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
  44
  45/* Allocate temporary buffers for decoding */
  46static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
  47{
  48	/* NOP */
  49
  50	return 0;
  51}
  52
  53/* Release temporary buffers for decoding */
  54static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
  55{
  56	/* NOP */
  57}
  58
  59/* Allocate codec buffers */
  60static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
  61{
  62	struct s5p_mfc_dev *dev = ctx->dev;
  63	unsigned int mb_width, mb_height, width64, height32;
  64	unsigned int lcu_width = 0, lcu_height = 0;
  65	int ret;
  66
  67	mb_width = MB_WIDTH(ctx->img_width);
  68	mb_height = MB_HEIGHT(ctx->img_height);
  69	width64 = ALIGN(ctx->img_width, 64);
  70	height32 = ALIGN(ctx->img_height, 32);
  71
  72	if (ctx->type == MFCINST_DECODER) {
  73		mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
  74			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);
  75		mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
  76	} else if (ctx->type == MFCINST_ENCODER) {
  77		if (IS_MFCV10_PLUS(dev))
  78			ctx->tmv_buffer_size = 0;
  79		else if (IS_MFCV8_PLUS(dev))
  80			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  81			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
  82			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  83		else
  84			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  85			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
  86			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  87		if (IS_MFCV12(dev)) {
  88			lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
  89			lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
  90			if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC && ctx->is_10bit) {
  91				ctx->luma_dpb_size =
  92					width64 * height32 +
  93					ALIGN(DIV_ROUND_UP(lcu_width * 32, 4), 16) * height32 + 128;
  94				if (ctx->is_422)
  95					ctx->chroma_dpb_size =
  96						ctx->luma_dpb_size;
  97				else
  98					ctx->chroma_dpb_size =
  99						width64 * height32 / 2 +
 100						ALIGN(DIV_ROUND_UP(lcu_width *
 101							32, 4), 16) * height32 / 2 + 128;
 102			} else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC &&	ctx->is_10bit) {
 103				ctx->luma_dpb_size =
 104					ALIGN(ctx->img_width * 2, 128) * height32 + 64;
 105				ctx->chroma_dpb_size =
 106					ALIGN(ctx->img_width * 2, 128) * height32 / 2 + 64;
 107			} else {
 108				ctx->luma_dpb_size =
 109					width64 * height32 + 64;
 110				if (ctx->is_422)
 111					ctx->chroma_dpb_size =
 112						ctx->luma_dpb_size;
 113				else
 114					ctx->chroma_dpb_size =
 115						width64 * height32 / 2 + 64;
 116			}
 117			ctx->luma_dpb_size = ALIGN(ctx->luma_dpb_size + 256, SZ_2K);
 118			ctx->chroma_dpb_size = ALIGN(ctx->chroma_dpb_size + 256, SZ_2K);
 119		} else if (IS_MFCV10_PLUS(dev)) {
 120			lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
 121			lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
 122			if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
 123				ctx->luma_dpb_size =
 124					ALIGN((mb_width * 16), 64)
 125					* ALIGN((mb_height * 16), 32)
 126						+ 64;
 127				ctx->chroma_dpb_size =
 128					ALIGN((mb_width * 16), 64)
 129							* (mb_height * 8)
 130							+ 64;
 131			} else {
 132				ctx->luma_dpb_size =
 133					ALIGN((lcu_width * 32), 64)
 134					* ALIGN((lcu_height * 32), 32)
 135						+ 64;
 136				ctx->chroma_dpb_size =
 137					ALIGN((lcu_width * 32), 64)
 138							* (lcu_height * 16)
 139							+ 64;
 140			}
 141		} else {
 142			ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
 143					S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
 144					S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
 145			ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
 146					S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
 147					S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
 148		}
 149		if (IS_MFCV8_PLUS(dev))
 150			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
 151						ctx->img_width, ctx->img_height,
 152						mb_width, mb_height),
 153						S5P_FIMV_ME_BUFFER_ALIGN_V6);
 154		else
 155			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
 156						ctx->img_width, ctx->img_height,
 157						mb_width, mb_height),
 158						S5P_FIMV_ME_BUFFER_ALIGN_V6);
 159
 160		mfc_debug(2, "recon luma size: %zu chroma size: %zu\n",
 161			  ctx->luma_dpb_size, ctx->chroma_dpb_size);
 162	} else {
 163		return -EINVAL;
 164	}
 165
 166	/* Codecs have different memory requirements */
 167	switch (ctx->codec_mode) {
 168	case S5P_MFC_CODEC_H264_DEC:
 169	case S5P_MFC_CODEC_H264_MVC_DEC:
 170		if (IS_MFCV10_PLUS(dev))
 171			mfc_debug(2, "Use min scratch buffer size\n");
 172		else if (IS_MFCV8_PLUS(dev))
 173			ctx->scratch_buf_size =
 174				S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
 175					mb_width,
 176					mb_height);
 177		else
 178			ctx->scratch_buf_size =
 179				S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
 180					mb_width,
 181					mb_height);
 182		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 183				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 184		ctx->bank1.size =
 185			ctx->scratch_buf_size +
 186			(ctx->mv_count * ctx->mv_size);
 187		break;
 188	case S5P_MFC_CODEC_MPEG4_DEC:
 189		if (IS_MFCV10_PLUS(dev))
 190			mfc_debug(2, "Use min scratch buffer size\n");
 191		else if (IS_MFCV7_PLUS(dev)) {
 192			ctx->scratch_buf_size =
 193				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
 194						mb_width,
 195						mb_height);
 196		} else {
 197			ctx->scratch_buf_size =
 198				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
 199						mb_width,
 200						mb_height);
 201		}
 202
 203		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 204				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 205		ctx->bank1.size = ctx->scratch_buf_size;
 206		break;
 207	case S5P_MFC_CODEC_VC1RCV_DEC:
 208	case S5P_MFC_CODEC_VC1_DEC:
 209		if (IS_MFCV10_PLUS(dev))
 210			mfc_debug(2, "Use min scratch buffer size\n");
 211		else
 212			ctx->scratch_buf_size =
 213				S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
 214						mb_width,
 215						mb_height);
 216
 217		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 218				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 219		ctx->bank1.size = ctx->scratch_buf_size;
 220		break;
 221	case S5P_MFC_CODEC_MPEG2_DEC:
 222		ctx->bank1.size = 0;
 223		ctx->bank2.size = 0;
 224		break;
 225	case S5P_MFC_CODEC_H263_DEC:
 226		if (IS_MFCV10_PLUS(dev))
 227			mfc_debug(2, "Use min scratch buffer size\n");
 228		else
 229			ctx->scratch_buf_size =
 230				S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
 231						mb_width,
 232						mb_height);
 233		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 234				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 235		ctx->bank1.size = ctx->scratch_buf_size;
 236		break;
 237	case S5P_MFC_CODEC_VP8_DEC:
 238		if (IS_MFCV10_PLUS(dev))
 239			mfc_debug(2, "Use min scratch buffer size\n");
 240		else if (IS_MFCV8_PLUS(dev))
 241			ctx->scratch_buf_size =
 242				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
 243						mb_width,
 244						mb_height);
 245		else
 246			ctx->scratch_buf_size =
 247				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
 248						mb_width,
 249						mb_height);
 250		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 251				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 252		ctx->bank1.size = ctx->scratch_buf_size;
 253		break;
 254	case S5P_MFC_CODEC_HEVC_DEC:
 255		mfc_debug(2, "Use min scratch buffer size\n");
 256		ctx->bank1.size =
 257			ctx->scratch_buf_size +
 258			(ctx->mv_count * ctx->mv_size);
 259		break;
 260	case S5P_MFC_CODEC_VP9_DEC:
 261		mfc_debug(2, "Use min scratch buffer size\n");
 262		ctx->bank1.size =
 263			ctx->scratch_buf_size +
 264			DEC_VP9_STATIC_BUFFER_SIZE;
 265		break;
 266	case S5P_MFC_CODEC_H264_ENC:
 267		if (IS_MFCV12(dev)) {
 268			mfc_debug(2, "Use min scratch buffer size\n");
 269			ctx->me_buffer_size =
 270				ENC_V120_H264_ME_SIZE(mb_width, mb_height);
 271		} else if (IS_MFCV10_PLUS(dev)) {
 272			mfc_debug(2, "Use min scratch buffer size\n");
 273			ctx->me_buffer_size =
 274			ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
 275		} else if (IS_MFCV8_PLUS(dev))
 276			ctx->scratch_buf_size =
 277				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
 278					mb_width,
 279					mb_height);
 280		else
 281			ctx->scratch_buf_size =
 282				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
 283						mb_width,
 284						mb_height);
 285		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 286				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 287		ctx->bank1.size =
 288			ctx->scratch_buf_size + ctx->tmv_buffer_size +
 289			(ctx->pb_count * (ctx->luma_dpb_size +
 290			ctx->chroma_dpb_size + ctx->me_buffer_size));
 291		ctx->bank2.size = 0;
 292		break;
 293	case S5P_MFC_CODEC_MPEG4_ENC:
 294	case S5P_MFC_CODEC_H263_ENC:
 295		if (IS_MFCV12(dev)) {
 296			mfc_debug(2, "Use min scratch buffer size\n");
 297			ctx->me_buffer_size =
 298				ENC_V120_MPEG4_ME_SIZE(mb_width, mb_height);
 299		} else if (IS_MFCV10_PLUS(dev)) {
 300			mfc_debug(2, "Use min scratch buffer size\n");
 301			ctx->me_buffer_size =
 302				ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
 303							mb_height), 16);
 304		} else
 305			ctx->scratch_buf_size =
 306				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
 307						mb_width,
 308						mb_height);
 309		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 310					S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 311		ctx->bank1.size =
 312			ctx->scratch_buf_size + ctx->tmv_buffer_size +
 313			(ctx->pb_count * (ctx->luma_dpb_size +
 314			ctx->chroma_dpb_size + ctx->me_buffer_size));
 315		ctx->bank2.size = 0;
 316		break;
 317	case S5P_MFC_CODEC_VP8_ENC:
 318		if (IS_MFCV12(dev)) {
 319			mfc_debug(2, "Use min scratch buffer size\n");
 320			ctx->me_buffer_size =
 321				ENC_V120_VP8_ME_SIZE(mb_width, mb_height);
 322		} else if (IS_MFCV10_PLUS(dev)) {
 323			mfc_debug(2, "Use min scratch buffer size\n");
 324			ctx->me_buffer_size =
 325				ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
 326						16);
 327		} else if (IS_MFCV8_PLUS(dev))
 328			ctx->scratch_buf_size =
 329				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 330					mb_width,
 331					mb_height);
 332		else
 333			ctx->scratch_buf_size =
 334				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
 335						mb_width,
 336						mb_height);
 337		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 338				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 339		ctx->bank1.size =
 340			ctx->scratch_buf_size + ctx->tmv_buffer_size +
 341			(ctx->pb_count * (ctx->luma_dpb_size +
 342			ctx->chroma_dpb_size + ctx->me_buffer_size));
 343		ctx->bank2.size = 0;
 344		break;
 345	case S5P_MFC_CODEC_HEVC_ENC:
 346		if (IS_MFCV12(dev))
 347			ctx->me_buffer_size =
 348				ENC_V120_HEVC_ME_SIZE(lcu_width, lcu_height);
 349		else
 350			ctx->me_buffer_size =
 351				ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
 352		mfc_debug(2, "Use min scratch buffer size\n");
 353		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
 354		ctx->bank1.size =
 355			ctx->scratch_buf_size + ctx->tmv_buffer_size +
 356			(ctx->pb_count * (ctx->luma_dpb_size +
 357			ctx->chroma_dpb_size + ctx->me_buffer_size));
 358		ctx->bank2.size = 0;
 359		break;
 360	default:
 361		break;
 362	}
 363
 364	/* Allocate only if memory from bank 1 is necessary */
 365	if (ctx->bank1.size > 0) {
 366		ret = s5p_mfc_alloc_generic_buf(dev, BANK_L_CTX, &ctx->bank1);
 367		if (ret) {
 368			mfc_err("Failed to allocate Bank1 memory\n");
 369			return ret;
 370		}
 371		BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
 372	}
 373	return 0;
 374}
 375
 376/* Release buffers allocated for codec */
 377static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 378{
 379	s5p_mfc_release_generic_buf(ctx->dev, &ctx->bank1);
 380}
 381
 382/* Allocate memory for instance data buffer */
 383static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 384{
 385	struct s5p_mfc_dev *dev = ctx->dev;
 386	const struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 387	int ret;
 388
 389	mfc_debug_enter();
 390
 391	switch (ctx->codec_mode) {
 392	case S5P_MFC_CODEC_H264_DEC:
 393	case S5P_MFC_CODEC_H264_MVC_DEC:
 394	case S5P_MFC_CODEC_HEVC_DEC:
 395		ctx->ctx.size = buf_size->h264_dec_ctx;
 396		break;
 397	case S5P_MFC_CODEC_MPEG4_DEC:
 398	case S5P_MFC_CODEC_H263_DEC:
 399	case S5P_MFC_CODEC_VC1RCV_DEC:
 400	case S5P_MFC_CODEC_VC1_DEC:
 401	case S5P_MFC_CODEC_MPEG2_DEC:
 402	case S5P_MFC_CODEC_VP8_DEC:
 403	case S5P_MFC_CODEC_VP9_DEC:
 404		ctx->ctx.size = buf_size->other_dec_ctx;
 405		break;
 406	case S5P_MFC_CODEC_H264_ENC:
 407		ctx->ctx.size = buf_size->h264_enc_ctx;
 408		break;
 409	case S5P_MFC_CODEC_HEVC_ENC:
 410		ctx->ctx.size = buf_size->hevc_enc_ctx;
 411		break;
 412	case S5P_MFC_CODEC_MPEG4_ENC:
 413	case S5P_MFC_CODEC_H263_ENC:
 414	case S5P_MFC_CODEC_VP8_ENC:
 415		ctx->ctx.size = buf_size->other_enc_ctx;
 416		break;
 417	default:
 418		ctx->ctx.size = 0;
 419		mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
 420		break;
 421	}
 422
 423	ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->ctx);
 424	if (ret) {
 425		mfc_err("Failed to allocate instance buffer\n");
 426		return ret;
 427	}
 428
 429	memset(ctx->ctx.virt, 0, ctx->ctx.size);
 430	wmb();
 431
 432	mfc_debug_leave();
 433
 434	return 0;
 435}
 436
 437/* Release instance buffer */
 438static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 439{
 440	s5p_mfc_release_priv_buf(ctx->dev, &ctx->ctx);
 441}
 442
 443/* Allocate context buffers for SYS_INIT */
 444static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 445{
 446	const struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 447	int ret;
 448
 449	mfc_debug_enter();
 450
 451	dev->ctx_buf.size = buf_size->dev_ctx;
 452	ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->ctx_buf);
 453	if (ret) {
 454		mfc_err("Failed to allocate device context buffer\n");
 455		return ret;
 456	}
 457
 458	memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
 459	wmb();
 460
 461	mfc_debug_leave();
 462
 463	return 0;
 464}
 465
 466/* Release context buffers for SYS_INIT */
 467static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 468{
 469	s5p_mfc_release_priv_buf(dev, &dev->ctx_buf);
 470}
 471
 472static int calc_plane(int width, int height)
 473{
 474	int mbX, mbY;
 475
 476	mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 477	mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
 478
 479	if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
 480		mbY = (mbY + 1) / 2 * 2;
 481
 482	return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
 483		(mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 484}
 485
 486static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 487{
 488	struct s5p_mfc_dev *dev = ctx->dev;
 489	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 490	ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
 491	ctx->chroma_size_1 = 0;
 492	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
 493			"buffer dimensions: %dx%d\n", ctx->img_width,
 494			ctx->img_height, ctx->buf_width, ctx->buf_height);
 495
 496	switch (ctx->dst_fmt->fourcc) {
 497	case V4L2_PIX_FMT_NV12M:
 498	case V4L2_PIX_FMT_NV21M:
 499		ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 500		ctx->stride[1] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 501		ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);
 502		ctx->chroma_size = calc_plane(ctx->stride[1], (ctx->img_height / 2));
 503		break;
 504	case V4L2_PIX_FMT_YUV420M:
 505	case V4L2_PIX_FMT_YVU420M:
 506		ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 507		ctx->stride[1] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);
 508		ctx->stride[2] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);
 509		ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);
 510		ctx->chroma_size = calc_plane(ctx->stride[1], (ctx->img_height / 2));
 511		ctx->chroma_size_1 = calc_plane(ctx->stride[2], (ctx->img_height / 2));
 512		break;
 513	}
 514
 515	if (IS_MFCV8_PLUS(ctx->dev)) {
 516		/* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
 517		ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 518		ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 519		ctx->chroma_size_1 += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 520	}
 521
 522	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 523			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 524		if (IS_MFCV12(dev))
 525			ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 1024);
 526		else if (IS_MFCV10_PLUS(dev))
 527			ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 512);
 528		else
 529			ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 128);
 530
 531	} else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
 532		ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width, ctx->img_height);
 533		ctx->mv_size = ALIGN(ctx->mv_size, 32);
 534	} else {
 535		ctx->mv_size = 0;
 536	}
 537}
 538
 539static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
 540{
 541	unsigned int mb_width, mb_height;
 542
 543	mb_width = MB_WIDTH(ctx->img_width);
 544	mb_height = MB_HEIGHT(ctx->img_height);
 545
 546	if (IS_MFCV12(ctx->dev)) {
 547		switch (ctx->src_fmt->fourcc) {
 548		case V4L2_PIX_FMT_NV12M:
 549		case V4L2_PIX_FMT_NV21M:
 550			ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 551			ctx->stride[1] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 552			ctx->luma_size = ALIGN(ctx->stride[0] * ALIGN(ctx->img_height, 16), 256);
 553			ctx->chroma_size = ALIGN(ctx->stride[0] * ALIGN(ctx->img_height / 2, 16),
 554					256);
 555			break;
 556		case V4L2_PIX_FMT_YUV420M:
 557		case V4L2_PIX_FMT_YVU420M:
 558			ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 559			ctx->stride[1] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);
 560			ctx->stride[2] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);
 561			ctx->luma_size = ctx->stride[0] * ALIGN(ctx->img_height, 16);
 562			ctx->chroma_size =  ctx->stride[1] * ALIGN(ctx->img_height / 2, 16);
 563			ctx->chroma_size_1 =  ctx->stride[2] * ALIGN(ctx->img_height / 2, 16);
 564			break;
 565		}
 566		ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
 567		ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V12;
 568		ctx->chroma_size_1 += MFC_CHROMA_PAD_BYTES_V12;
 569	} else {
 570		ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 571		ctx->stride[0] = ctx->buf_width;
 572		ctx->stride[1] = ctx->buf_width;
 573		ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
 574		ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
 575		ctx->chroma_size_1 = 0;
 576		/* MFCv7 needs pad bytes for Luma and Chroma */
 577		if (IS_MFCV7_PLUS(ctx->dev)) {
 578			ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
 579			ctx->chroma_size += MFC_LUMA_PAD_BYTES_V7;
 580		}
 581	}
 582}
 583
 584/* Set registers for decoding stream buffer */
 585static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 586			int buf_addr, unsigned int start_num_byte,
 587			unsigned int strm_size)
 588{
 589	struct s5p_mfc_dev *dev = ctx->dev;
 590	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 591	const struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
 592
 593	mfc_debug_enter();
 594	mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
 595		"buf_size: 0x%08x (%d)\n",
 596		ctx->inst_no, buf_addr, strm_size, strm_size);
 597	writel(strm_size, mfc_regs->d_stream_data_size);
 598	writel(buf_addr, mfc_regs->d_cpb_buffer_addr);
 599	writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
 600	writel(start_num_byte, mfc_regs->d_cpb_buffer_offset);
 601
 602	mfc_debug_leave();
 603	return 0;
 604}
 605
 606/* Set decoding frame buffer */
 607static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 608{
 609	unsigned int frame_size, i;
 610	unsigned int frame_size_ch, frame_size_mv;
 611	struct s5p_mfc_dev *dev = ctx->dev;
 612	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 613	size_t buf_addr1;
 614	int buf_size1;
 615	int align_gap;
 616
 617	buf_addr1 = ctx->bank1.dma;
 618	buf_size1 = ctx->bank1.size;
 619
 620	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 621	mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
 622	mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
 623
 624	writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
 625	writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
 626	writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
 627	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
 628			V4L2_PIX_FMT_YVU420M)
 629		writel(ctx->chroma_size_1, mfc_regs->d_third_plane_dpb_size);
 630	writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
 631	writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
 632
 633	if (IS_MFCV8_PLUS(dev)) {
 634		writel(ctx->stride[0], mfc_regs->d_first_plane_dpb_stride_size);
 635		writel(ctx->stride[1], mfc_regs->d_second_plane_dpb_stride_size);
 636		if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
 637				V4L2_PIX_FMT_YVU420M)
 638			writel(ctx->stride[2], mfc_regs->d_third_plane_dpb_stride_size);
 639	}
 640
 641	buf_addr1 += ctx->scratch_buf_size;
 642	buf_size1 -= ctx->scratch_buf_size;
 643
 644	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
 645			ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC ||
 646			ctx->codec_mode == S5P_FIMV_CODEC_HEVC_DEC) {
 647		writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
 648		writel(ctx->mv_count, mfc_regs->d_num_mv);
 649	}
 650
 651	frame_size = ctx->luma_size;
 652	frame_size_ch = ctx->chroma_size;
 653	frame_size_mv = ctx->mv_size;
 654	mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
 655			frame_size, frame_size_ch, frame_size_mv);
 656
 657	for (i = 0; i < ctx->total_dpb_count; i++) {
 658		/* Bank2 */
 659		mfc_debug(2, "Luma %d: %zx\n", i,
 660					ctx->dst_bufs[i].cookie.raw.luma);
 661		writel(ctx->dst_bufs[i].cookie.raw.luma,
 662				mfc_regs->d_first_plane_dpb + i * 4);
 663		mfc_debug(2, "\tChroma %d: %zx\n", i,
 664					ctx->dst_bufs[i].cookie.raw.chroma);
 665		writel(ctx->dst_bufs[i].cookie.raw.chroma,
 666				mfc_regs->d_second_plane_dpb + i * 4);
 667		if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
 668				V4L2_PIX_FMT_YVU420M) {
 669			mfc_debug(2, "\tChroma_1 %d: %zx\n", i, ctx
 670					->dst_bufs[i].cookie.raw.chroma_1);
 671			writel(ctx->dst_bufs[i].cookie.raw.chroma_1, mfc_regs->d_third_plane_dpb +
 672					i * 4);
 673		}
 674	}
 675	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 676			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||
 677			ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
 678		for (i = 0; i < ctx->mv_count; i++) {
 679			/* To test alignment */
 680			align_gap = buf_addr1;
 681			buf_addr1 = ALIGN(buf_addr1, 16);
 682			align_gap = buf_addr1 - align_gap;
 683			buf_size1 -= align_gap;
 684
 685			mfc_debug(2, "\tBuf1: %zx, size: %d\n",
 686					buf_addr1, buf_size1);
 687			writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
 688			buf_addr1 += frame_size_mv;
 689			buf_size1 -= frame_size_mv;
 690		}
 691	}
 692	if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_DEC) {
 693		writel(buf_addr1, mfc_regs->d_static_buffer_addr);
 694		writel(DEC_VP9_STATIC_BUFFER_SIZE,
 695				mfc_regs->d_static_buffer_size);
 696		buf_addr1 += DEC_VP9_STATIC_BUFFER_SIZE;
 697		buf_size1 -= DEC_VP9_STATIC_BUFFER_SIZE;
 698	}
 699
 700	mfc_debug(2, "Buf1: %zx, buf_size1: %d (frames %d)\n",
 701			buf_addr1, buf_size1, ctx->total_dpb_count);
 702	if (buf_size1 < 0) {
 703		mfc_debug(2, "Not enough memory has been allocated.\n");
 704		return -ENOMEM;
 705	}
 706
 707	writel(ctx->inst_no, mfc_regs->instance_id);
 708	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 709			S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 710
 711	mfc_debug(2, "After setting buffers.\n");
 712	return 0;
 713}
 714
 715/* Set registers for encoding stream buffer */
 716static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 717		unsigned long addr, unsigned int size)
 718{
 719	struct s5p_mfc_dev *dev = ctx->dev;
 720	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 721
 722	writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
 723	writel(size, mfc_regs->e_stream_buffer_size);
 724
 725	mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%x\n",
 726		  addr, size);
 727
 728	return 0;
 729}
 730
 731static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 732		unsigned long y_addr, unsigned long c_addr,
 733		unsigned long c_1_addr)
 734{
 735	struct s5p_mfc_dev *dev = ctx->dev;
 736	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 737
 738	writel(y_addr, mfc_regs->e_source_first_plane_addr);
 739	writel(c_addr, mfc_regs->e_source_second_plane_addr);
 740	writel(c_1_addr, mfc_regs->e_source_third_plane_addr);
 741
 742	mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
 743	mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
 744	mfc_debug(2, "enc src cr buf addr: 0x%08lx\n", c_1_addr);
 745}
 746
 747static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 748		unsigned long *y_addr, unsigned long *c_addr,
 749		unsigned long *c_1_addr)
 750{
 751	struct s5p_mfc_dev *dev = ctx->dev;
 752	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 753	unsigned long enc_recon_y_addr, enc_recon_c_addr;
 754
 755	*y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr);
 756	*c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr);
 757	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==
 758			V4L2_PIX_FMT_YVU420M)
 759		*c_1_addr = readl(mfc_regs->e_encoded_source_third_plane_addr);
 760	else
 761		*c_1_addr = 0;
 762
 763	enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr);
 764	enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr);
 765
 766	mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr);
 767	mfc_debug(2, "recon c addr: 0x%08lx c_addr: 0x%08lx\n", enc_recon_c_addr, *c_addr);
 768}
 769
 770/* Set encoding ref & codec buffer */
 771static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
 772{
 773	struct s5p_mfc_dev *dev = ctx->dev;
 774	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 775	size_t buf_addr1;
 776	int i, buf_size1;
 777
 778	mfc_debug_enter();
 779
 780	buf_addr1 = ctx->bank1.dma;
 781	buf_size1 = ctx->bank1.size;
 782
 783	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 784
 785	if (IS_MFCV10_PLUS(dev)) {
 786		/* start address of per buffer is aligned */
 787		for (i = 0; i < ctx->pb_count; i++) {
 788			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
 789			buf_addr1 += ctx->luma_dpb_size;
 790			buf_size1 -= ctx->luma_dpb_size;
 791		}
 792		for (i = 0; i < ctx->pb_count; i++) {
 793			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
 794			buf_addr1 += ctx->chroma_dpb_size;
 795			buf_size1 -= ctx->chroma_dpb_size;
 796		}
 797		for (i = 0; i < ctx->pb_count; i++) {
 798			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
 799			buf_addr1 += ctx->me_buffer_size;
 800			buf_size1 -= ctx->me_buffer_size;
 801		}
 802	} else {
 803		for (i = 0; i < ctx->pb_count; i++) {
 804			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
 805			buf_addr1 += ctx->luma_dpb_size;
 806			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
 807			buf_addr1 += ctx->chroma_dpb_size;
 808			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
 809			buf_addr1 += ctx->me_buffer_size;
 810			buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size
 811					+ ctx->me_buffer_size);
 812		}
 813	}
 814
 815	writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
 816	writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
 817	buf_addr1 += ctx->scratch_buf_size;
 818	buf_size1 -= ctx->scratch_buf_size;
 819
 820	writel(buf_addr1, mfc_regs->e_tmv_buffer0);
 821	buf_addr1 += ctx->tmv_buffer_size >> 1;
 822	writel(buf_addr1, mfc_regs->e_tmv_buffer1);
 823	buf_addr1 += ctx->tmv_buffer_size >> 1;
 824	buf_size1 -= ctx->tmv_buffer_size;
 825
 826	mfc_debug(2, "Buf1: %zu, buf_size1: %d (ref frames %d)\n",
 827			buf_addr1, buf_size1, ctx->pb_count);
 828	if (buf_size1 < 0) {
 829		mfc_debug(2, "Not enough memory has been allocated.\n");
 830		return -ENOMEM;
 831	}
 832
 833	writel(ctx->inst_no, mfc_regs->instance_id);
 834	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 835			S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 836
 837	mfc_debug_leave();
 838
 839	return 0;
 840}
 841
 842static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
 843{
 844	struct s5p_mfc_dev *dev = ctx->dev;
 845	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 846
 847	/* multi-slice control */
 848	/* multi-slice MB number or bit size */
 849	writel(ctx->slice_mode, mfc_regs->e_mslice_mode);
 850	if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {
 851		writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
 852	} else if (ctx->slice_mode ==
 853			V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {
 854		writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
 855	} else {
 856		writel(0x0, mfc_regs->e_mslice_size_mb);
 857		writel(0x0, mfc_regs->e_mslice_size_bits);
 858	}
 859
 860	return 0;
 861}
 862
 863static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
 864{
 865	struct s5p_mfc_dev *dev = ctx->dev;
 866	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 867	const struct s5p_mfc_enc_params *p = &ctx->enc_params;
 868	unsigned int reg = 0;
 869
 870	mfc_debug_enter();
 871
 872	/* width */
 873	writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
 874	/* height */
 875	writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
 876
 877	/* cropped width */
 878	writel(ctx->img_width, mfc_regs->e_cropped_frame_width);
 879	/* cropped height */
 880	writel(ctx->img_height, mfc_regs->e_cropped_frame_height);
 881	/* cropped offset */
 882	writel(0x0, mfc_regs->e_frame_crop_offset);
 883
 884	/* pictype : IDR period */
 885	reg = 0;
 886	reg |= p->gop_size & 0xFFFF;
 887	writel(reg, mfc_regs->e_gop_config);
 888
 889	/* multi-slice control */
 890	/* multi-slice MB number or bit size */
 891	ctx->slice_mode = p->slice_mode;
 892	reg = 0;
 893	if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {
 894		reg |= (0x1 << 3);
 895		writel(reg, mfc_regs->e_enc_options);
 896		ctx->slice_size.mb = p->slice_mb;
 897	} else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {
 898		reg |= (0x1 << 3);
 899		writel(reg, mfc_regs->e_enc_options);
 900		ctx->slice_size.bits = p->slice_bit;
 901	} else {
 902		reg &= ~(0x1 << 3);
 903		writel(reg, mfc_regs->e_enc_options);
 904	}
 905
 906	s5p_mfc_set_slice_mode(ctx);
 907
 908	/* cyclic intra refresh */
 909	writel(p->intra_refresh_mb, mfc_regs->e_ir_size);
 910	reg = readl(mfc_regs->e_enc_options);
 911	if (p->intra_refresh_mb == 0)
 912		reg &= ~(0x1 << 4);
 913	else
 914		reg |= (0x1 << 4);
 915	writel(reg, mfc_regs->e_enc_options);
 916
 917	/* 'NON_REFERENCE_STORE_ENABLE' for debugging */
 918	reg = readl(mfc_regs->e_enc_options);
 919	reg &= ~(0x1 << 9);
 920	writel(reg, mfc_regs->e_enc_options);
 921
 922	/* memory structure cur. frame */
 923	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
 924		/* 0: Linear, 1: 2D tiled*/
 925		reg = readl(mfc_regs->e_enc_options);
 926		reg &= ~(0x1 << 7);
 927		writel(reg, mfc_regs->e_enc_options);
 928		/* 0: NV12(CbCr), 1: NV21(CrCb) */
 929		writel(0x0, mfc_regs->pixel_format);
 930	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
 931		/* 0: Linear, 1: 2D tiled*/
 932		reg = readl(mfc_regs->e_enc_options);
 933		reg &= ~(0x1 << 7);
 934		writel(reg, mfc_regs->e_enc_options);
 935		/* 0: NV12(CbCr), 1: NV21(CrCb) */
 936		writel(0x1, mfc_regs->pixel_format);
 937	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
 938		/* 0: Linear, 1: 2D tiled*/
 939		reg = readl(mfc_regs->e_enc_options);
 940		reg |= (0x1 << 7);
 941		writel(reg, mfc_regs->e_enc_options);
 942		/* 0: NV12(CbCr), 1: NV21(CrCb) */
 943		writel(0x0, mfc_regs->pixel_format);
 944	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
 945		/* 0: Linear, 1: 2D tiled*/
 946		reg = readl(mfc_regs->e_enc_options);
 947		reg &= ~(0x1 << 7);
 948		writel(reg, mfc_regs->e_enc_options);
 949		/* 2: YV12(CrCb), 3: I420(CrCb) */
 950		writel(0x2, mfc_regs->pixel_format);
 951	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M) {
 952		/* 0: Linear, 1: 2D tiled*/
 953		reg = readl(mfc_regs->e_enc_options);
 954		reg &= ~(0x1 << 7);
 955		writel(reg, mfc_regs->e_enc_options);
 956		/* 2: YV12(CrCb), 3: I420(CrCb) */
 957		writel(0x3, mfc_regs->pixel_format);
 958	}
 959
 960	/* memory structure recon. frame */
 961	/* 0: Linear, 1: 2D tiled */
 962	reg = readl(mfc_regs->e_enc_options);
 963	reg |= (0x1 << 8);
 964	writel(reg, mfc_regs->e_enc_options);
 965
 966	/* padding control & value */
 967	writel(0x0, mfc_regs->e_padding_ctrl);
 968	if (p->pad) {
 969		reg = 0;
 970		/** enable */
 971		reg |= (1UL << 31);
 972		/** cr value */
 973		reg |= ((p->pad_cr & 0xFF) << 16);
 974		/** cb value */
 975		reg |= ((p->pad_cb & 0xFF) << 8);
 976		/** y value */
 977		reg |= p->pad_luma & 0xFF;
 978		writel(reg, mfc_regs->e_padding_ctrl);
 979	}
 980
 981	/* rate control config. */
 982	reg = 0;
 983	/* frame-level rate control */
 984	reg |= ((p->rc_frame & 0x1) << 9);
 985	writel(reg, mfc_regs->e_rc_config);
 986
 987	/* bit rate */
 988	if (p->rc_frame)
 989		writel(p->rc_bitrate,
 990			mfc_regs->e_rc_bit_rate);
 991	else
 992		writel(1, mfc_regs->e_rc_bit_rate);
 993
 994	/* reaction coefficient */
 995	if (p->rc_frame) {
 996		if (IS_MFCV12(dev)) {
 997			/* loose CBR */
 998			if (p->rc_reaction_coeff < LOOSE_CBR_MAX)
 999				writel(1, mfc_regs->e_rc_mode);
1000			/* tight CBR */
1001			else if (p->rc_reaction_coeff < TIGHT_CBR_MAX)
1002				writel(0, mfc_regs->e_rc_mode);
1003			/* VBR */
1004			else
1005				writel(2, mfc_regs->e_rc_mode);
1006		} else {
1007			/* tight CBR */
1008			if (p->rc_reaction_coeff < TIGHT_CBR_MAX)
1009				writel(1, mfc_regs->e_rc_mode);
1010			/* loose CBR */
1011			else
1012				writel(2, mfc_regs->e_rc_mode);
1013		}
1014	}
1015
1016	/* seq header ctrl */
1017	reg = readl(mfc_regs->e_enc_options);
1018	reg &= ~(0x1 << 2);
1019	reg |= ((p->seq_hdr_mode & 0x1) << 2);
1020
1021	/* frame skip mode */
1022	reg &= ~(0x3);
1023	reg |= (p->frame_skip_mode & 0x3);
1024	writel(reg, mfc_regs->e_enc_options);
1025
1026	/* 'DROP_CONTROL_ENABLE', disable */
1027	reg = readl(mfc_regs->e_rc_config);
1028	reg &= ~(0x1 << 10);
1029	writel(reg, mfc_regs->e_rc_config);
1030
1031	/* setting for MV range [16, 256] */
1032	reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
1033	writel(reg, mfc_regs->e_mv_hor_range);
1034
1035	reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
1036	writel(reg, mfc_regs->e_mv_ver_range);
1037
1038	writel(0x0, mfc_regs->e_frame_insertion);
1039	writel(0x0, mfc_regs->e_roi_buffer_addr);
1040	writel(0x0, mfc_regs->e_param_change);
1041	writel(0x0, mfc_regs->e_rc_roi_ctrl);
1042	writel(0x0, mfc_regs->e_picture_tag);
1043
1044	writel(0x0, mfc_regs->e_bit_count_enable);
1045	writel(0x0, mfc_regs->e_max_bit_count);
1046	writel(0x0, mfc_regs->e_min_bit_count);
1047
1048	writel(0x0, mfc_regs->e_metadata_buffer_addr);
1049	writel(0x0, mfc_regs->e_metadata_buffer_size);
1050
1051	mfc_debug_leave();
1052
1053	return 0;
1054}
1055
1056static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1057{
1058	struct s5p_mfc_dev *dev = ctx->dev;
1059	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1060	struct s5p_mfc_enc_params *p = &ctx->enc_params;
1061	struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1062	unsigned int reg = 0;
1063	int i;
1064
1065	mfc_debug_enter();
1066
1067	s5p_mfc_set_enc_params(ctx);
1068
1069	/* pictype : number of B */
1070	reg = readl(mfc_regs->e_gop_config);
1071	reg &= ~(0x3 << 16);
1072	reg |= ((p->num_b_frame & 0x3) << 16);
1073	writel(reg, mfc_regs->e_gop_config);
1074
1075	/* UHD encoding case */
1076	if (ctx->img_width == 3840 && ctx->img_height == 2160) {
1077		if (p_h264->level < 51) {
1078			mfc_debug(2, "Set Level 5.1 for UHD\n");
1079			p_h264->level = 51;
1080		}
1081		if (p_h264->profile != 0x2) {
1082			mfc_debug(2, "Set High profile for UHD\n");
1083			p_h264->profile = 0x2;
1084		}
1085	}
1086
1087	/* profile & level */
1088	reg = 0;
1089	/** level */
1090	reg |= ((p_h264->level & 0xFF) << 8);
1091	/** profile - 0 ~ 3 */
1092	reg |= p_h264->profile & 0x3F;
1093	writel(reg, mfc_regs->e_picture_profile);
1094
1095	/* rate control config. */
1096	reg = readl(mfc_regs->e_rc_config);
1097	/** macroblock level rate control */
1098	reg &= ~(0x1 << 8);
1099	reg |= ((p->rc_mb & 0x1) << 8);
1100	writel(reg, mfc_regs->e_rc_config);
1101
1102	/** frame QP */
1103	reg &= ~(0x3F);
1104	reg |= p_h264->rc_frame_qp & 0x3F;
1105	writel(reg, mfc_regs->e_rc_config);
1106
1107	/* max & min value of QP */
1108	reg = 0;
1109	/** max QP */
1110	reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
1111	/** min QP */
1112	reg |= p_h264->rc_min_qp & 0x3F;
1113	writel(reg, mfc_regs->e_rc_qp_bound);
1114
1115	/* other QPs */
1116	writel(0x0, mfc_regs->e_fixed_picture_qp);
1117	if (!p->rc_frame && !p->rc_mb) {
1118		reg = 0;
1119		reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
1120		reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
1121		reg |= p_h264->rc_frame_qp & 0x3F;
1122		writel(reg, mfc_regs->e_fixed_picture_qp);
1123	}
1124
1125	/* frame rate */
1126	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1127		reg = 0;
1128		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1129		reg |= p->rc_framerate_denom & 0xFFFF;
1130		writel(reg, mfc_regs->e_rc_frame_rate);
1131	}
1132
1133	/* vbv buffer size */
1134	if (p->frame_skip_mode ==
1135			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1136		writel(p_h264->cpb_size & 0xFFFF,
1137				mfc_regs->e_vbv_buffer_size);
1138
1139		if (p->rc_frame)
1140			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1141	}
1142
1143	/* interlace */
1144	reg = 0;
1145	reg |= ((p_h264->interlace & 0x1) << 3);
1146	writel(reg, mfc_regs->e_h264_options);
1147
1148	/* height */
1149	if (p_h264->interlace) {
1150		writel(ctx->img_height >> 1,
1151				mfc_regs->e_frame_height); /* 32 align */
1152		/* cropped height */
1153		writel(ctx->img_height >> 1,
1154				mfc_regs->e_cropped_frame_height);
1155	}
1156
1157	/* loop filter ctrl */
1158	reg = readl(mfc_regs->e_h264_options);
1159	reg &= ~(0x3 << 1);
1160	reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
1161	writel(reg, mfc_regs->e_h264_options);
1162
1163	/* loopfilter alpha offset */
1164	if (p_h264->loop_filter_alpha < 0) {
1165		reg = 0x10;
1166		reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
1167	} else {
1168		reg = 0x00;
1169		reg |= (p_h264->loop_filter_alpha & 0xF);
1170	}
1171	writel(reg, mfc_regs->e_h264_lf_alpha_offset);
1172
1173	/* loopfilter beta offset */
1174	if (p_h264->loop_filter_beta < 0) {
1175		reg = 0x10;
1176		reg |= (0xFF - p_h264->loop_filter_beta) + 1;
1177	} else {
1178		reg = 0x00;
1179		reg |= (p_h264->loop_filter_beta & 0xF);
1180	}
1181	writel(reg, mfc_regs->e_h264_lf_beta_offset);
1182
1183	/* entropy coding mode */
1184	reg = readl(mfc_regs->e_h264_options);
1185	reg &= ~(0x1);
1186	reg |= p_h264->entropy_mode & 0x1;
1187	writel(reg, mfc_regs->e_h264_options);
1188
1189	/* number of ref. picture */
1190	reg = readl(mfc_regs->e_h264_options);
1191	reg &= ~(0x1 << 7);
1192	reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
1193	writel(reg, mfc_regs->e_h264_options);
1194
1195	/* 8x8 transform enable */
1196	reg = readl(mfc_regs->e_h264_options);
1197	reg &= ~(0x3 << 12);
1198	reg |= ((p_h264->_8x8_transform & 0x3) << 12);
1199	writel(reg, mfc_regs->e_h264_options);
1200
1201	/* macroblock adaptive scaling features */
1202	writel(0x0, mfc_regs->e_mb_rc_config);
1203	if (p->rc_mb) {
1204		reg = 0;
1205		/** dark region */
1206		reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
1207		/** smooth region */
1208		reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
1209		/** static region */
1210		reg |= ((p_h264->rc_mb_static & 0x1) << 1);
1211		/** high activity region */
1212		reg |= p_h264->rc_mb_activity & 0x1;
1213		writel(reg, mfc_regs->e_mb_rc_config);
1214	}
1215
1216	/* aspect ratio VUI */
1217	reg = readl(mfc_regs->e_h264_options);
1218	reg &= ~(0x1 << 5);
1219	reg |= ((p_h264->vui_sar & 0x1) << 5);
1220	writel(reg, mfc_regs->e_h264_options);
1221
1222	writel(0x0, mfc_regs->e_aspect_ratio);
1223	writel(0x0, mfc_regs->e_extended_sar);
1224	if (p_h264->vui_sar) {
1225		/* aspect ration IDC */
1226		reg = 0;
1227		reg |= p_h264->vui_sar_idc & 0xFF;
1228		writel(reg, mfc_regs->e_aspect_ratio);
1229		if (p_h264->vui_sar_idc == 0xFF) {
1230			/* extended SAR */
1231			reg = 0;
1232			reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
1233			reg |= p_h264->vui_ext_sar_height & 0xFFFF;
1234			writel(reg, mfc_regs->e_extended_sar);
1235		}
1236	}
1237
1238	/* intra picture period for H.264 open GOP */
1239	/* control */
1240	reg = readl(mfc_regs->e_h264_options);
1241	reg &= ~(0x1 << 4);
1242	reg |= ((p_h264->open_gop & 0x1) << 4);
1243	writel(reg, mfc_regs->e_h264_options);
1244
1245	/* value */
1246	writel(0x0, mfc_regs->e_h264_i_period);
1247	if (p_h264->open_gop) {
1248		reg = 0;
1249		reg |= p_h264->open_gop_size & 0xFFFF;
1250		writel(reg, mfc_regs->e_h264_i_period);
1251	}
1252
1253	/* 'WEIGHTED_BI_PREDICTION' for B is disable */
1254	reg = readl(mfc_regs->e_h264_options);
1255	reg &= ~(0x3 << 9);
1256	writel(reg, mfc_regs->e_h264_options);
1257
1258	/* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
1259	reg = readl(mfc_regs->e_h264_options);
1260	reg &= ~(0x1 << 14);
1261	writel(reg, mfc_regs->e_h264_options);
1262
1263	/* ASO */
1264	reg = readl(mfc_regs->e_h264_options);
1265	reg &= ~(0x1 << 6);
1266	reg |= ((p_h264->aso & 0x1) << 6);
1267	writel(reg, mfc_regs->e_h264_options);
1268
1269	/* hier qp enable */
1270	reg = readl(mfc_regs->e_h264_options);
1271	reg &= ~(0x1 << 8);
1272	reg |= ((p_h264->open_gop & 0x1) << 8);
1273	writel(reg, mfc_regs->e_h264_options);
1274	reg = 0;
1275	if (p_h264->hier_qp && p_h264->hier_qp_layer) {
1276		reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
1277		reg |= p_h264->hier_qp_layer & 0x7;
1278		writel(reg, mfc_regs->e_h264_num_t_layer);
1279		/* QP value for each layer */
1280		for (i = 0; i < p_h264->hier_qp_layer &&
1281				i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
1282			writel(p_h264->hier_qp_layer_qp[i],
1283				mfc_regs->e_h264_hierarchical_qp_layer0
1284				+ i * 4);
1285		}
1286	}
1287	/* number of coding layer should be zero when hierarchical is disable */
1288	writel(reg, mfc_regs->e_h264_num_t_layer);
1289
1290	/* frame packing SEI generation */
1291	reg = readl(mfc_regs->e_h264_options);
1292	reg &= ~(0x1 << 25);
1293	reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
1294	writel(reg, mfc_regs->e_h264_options);
1295	if (p_h264->sei_frame_packing) {
1296		reg = 0;
1297		/** current frame0 flag */
1298		reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
1299		/** arrangement type */
1300		reg |= p_h264->sei_fp_arrangement_type & 0x3;
1301		writel(reg, mfc_regs->e_h264_frame_packing_sei_info);
1302	}
1303
1304	if (p_h264->fmo) {
1305		switch (p_h264->fmo_map_type) {
1306		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
1307			if (p_h264->fmo_slice_grp > 4)
1308				p_h264->fmo_slice_grp = 4;
1309			for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
1310				writel(p_h264->fmo_run_len[i] - 1,
1311					mfc_regs->e_h264_fmo_run_length_minus1_0
1312					+ i * 4);
1313			break;
1314		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
1315			if (p_h264->fmo_slice_grp > 4)
1316				p_h264->fmo_slice_grp = 4;
1317			break;
1318		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1319		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1320			if (p_h264->fmo_slice_grp > 2)
1321				p_h264->fmo_slice_grp = 2;
1322			writel(p_h264->fmo_chg_dir & 0x1,
1323				mfc_regs->e_h264_fmo_slice_grp_change_dir);
1324			/* the valid range is 0 ~ number of macroblocks -1 */
1325			writel(p_h264->fmo_chg_rate,
1326			mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1327			break;
1328		default:
1329			mfc_err("Unsupported map type for FMO: %d\n",
1330					p_h264->fmo_map_type);
1331			p_h264->fmo_map_type = 0;
1332			p_h264->fmo_slice_grp = 1;
1333			break;
1334		}
1335
1336		writel(p_h264->fmo_map_type,
1337				mfc_regs->e_h264_fmo_slice_grp_map_type);
1338		writel(p_h264->fmo_slice_grp - 1,
1339				mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1340	} else {
1341		writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1342	}
1343
1344	mfc_debug_leave();
1345
1346	return 0;
1347}
1348
1349static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1350{
1351	struct s5p_mfc_dev *dev = ctx->dev;
1352	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1353	const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1354	const struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1355	unsigned int reg = 0;
1356
1357	mfc_debug_enter();
1358
1359	s5p_mfc_set_enc_params(ctx);
1360
1361	/* pictype : number of B */
1362	reg = readl(mfc_regs->e_gop_config);
1363	reg &= ~(0x3 << 16);
1364	reg |= ((p->num_b_frame & 0x3) << 16);
1365	writel(reg, mfc_regs->e_gop_config);
1366
1367	/* profile & level */
1368	reg = 0;
1369	/** level */
1370	reg |= ((p_mpeg4->level & 0xFF) << 8);
1371	/** profile - 0 ~ 1 */
1372	reg |= p_mpeg4->profile & 0x3F;
1373	writel(reg, mfc_regs->e_picture_profile);
1374
1375	/* rate control config. */
1376	reg = readl(mfc_regs->e_rc_config);
1377	/** macroblock level rate control */
1378	reg &= ~(0x1 << 8);
1379	reg |= ((p->rc_mb & 0x1) << 8);
1380	writel(reg, mfc_regs->e_rc_config);
1381
1382	/** frame QP */
1383	reg &= ~(0x3F);
1384	reg |= p_mpeg4->rc_frame_qp & 0x3F;
1385	writel(reg, mfc_regs->e_rc_config);
1386
1387	/* max & min value of QP */
1388	reg = 0;
1389	/** max QP */
1390	reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1391	/** min QP */
1392	reg |= p_mpeg4->rc_min_qp & 0x3F;
1393	writel(reg, mfc_regs->e_rc_qp_bound);
1394
1395	/* other QPs */
1396	writel(0x0, mfc_regs->e_fixed_picture_qp);
1397	if (!p->rc_frame && !p->rc_mb) {
1398		reg = 0;
1399		reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1400		reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1401		reg |= p_mpeg4->rc_frame_qp & 0x3F;
1402		writel(reg, mfc_regs->e_fixed_picture_qp);
1403	}
1404
1405	/* frame rate */
1406	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1407		reg = 0;
1408		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1409		reg |= p->rc_framerate_denom & 0xFFFF;
1410		writel(reg, mfc_regs->e_rc_frame_rate);
1411	}
1412
1413	/* vbv buffer size */
1414	if (p->frame_skip_mode ==
1415			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1416		writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1417
1418		if (p->rc_frame)
1419			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1420	}
1421
1422	/* Disable HEC */
1423	writel(0x0, mfc_regs->e_mpeg4_options);
1424	writel(0x0, mfc_regs->e_mpeg4_hec_period);
1425
1426	mfc_debug_leave();
1427
1428	return 0;
1429}
1430
1431static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1432{
1433	struct s5p_mfc_dev *dev = ctx->dev;
1434	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1435	const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1436	const struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1437	unsigned int reg = 0;
1438
1439	mfc_debug_enter();
1440
1441	s5p_mfc_set_enc_params(ctx);
1442
1443	/* profile & level */
1444	reg = 0;
1445	/** profile */
1446	reg |= (0x1 << 4);
1447	writel(reg, mfc_regs->e_picture_profile);
1448
1449	/* rate control config. */
1450	reg = readl(mfc_regs->e_rc_config);
1451	/** macroblock level rate control */
1452	reg &= ~(0x1 << 8);
1453	reg |= ((p->rc_mb & 0x1) << 8);
1454	writel(reg, mfc_regs->e_rc_config);
1455
1456	/** frame QP */
1457	reg &= ~(0x3F);
1458	reg |= p_h263->rc_frame_qp & 0x3F;
1459	writel(reg, mfc_regs->e_rc_config);
1460
1461	/* max & min value of QP */
1462	reg = 0;
1463	/** max QP */
1464	reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1465	/** min QP */
1466	reg |= p_h263->rc_min_qp & 0x3F;
1467	writel(reg, mfc_regs->e_rc_qp_bound);
1468
1469	/* other QPs */
1470	writel(0x0, mfc_regs->e_fixed_picture_qp);
1471	if (!p->rc_frame && !p->rc_mb) {
1472		reg = 0;
1473		reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1474		reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1475		reg |= p_h263->rc_frame_qp & 0x3F;
1476		writel(reg, mfc_regs->e_fixed_picture_qp);
1477	}
1478
1479	/* frame rate */
1480	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1481		reg = 0;
1482		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1483		reg |= p->rc_framerate_denom & 0xFFFF;
1484		writel(reg, mfc_regs->e_rc_frame_rate);
1485	}
1486
1487	/* vbv buffer size */
1488	if (p->frame_skip_mode ==
1489			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1490		writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1491
1492		if (p->rc_frame)
1493			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1494	}
1495
1496	mfc_debug_leave();
1497
1498	return 0;
1499}
1500
1501static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1502{
1503	struct s5p_mfc_dev *dev = ctx->dev;
1504	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1505	const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1506	const struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1507	unsigned int reg = 0;
1508	unsigned int val = 0;
1509
1510	mfc_debug_enter();
1511
1512	s5p_mfc_set_enc_params(ctx);
1513
1514	/* pictype : number of B */
1515	reg = readl(mfc_regs->e_gop_config);
1516	reg &= ~(0x3 << 16);
1517	reg |= ((p->num_b_frame & 0x3) << 16);
1518	writel(reg, mfc_regs->e_gop_config);
1519
1520	/* profile - 0 ~ 3 */
1521	reg = p_vp8->profile & 0x3;
1522	writel(reg, mfc_regs->e_picture_profile);
1523
1524	/* rate control config. */
1525	reg = readl(mfc_regs->e_rc_config);
1526	/** macroblock level rate control */
1527	reg &= ~(0x1 << 8);
1528	reg |= ((p->rc_mb & 0x1) << 8);
1529	writel(reg, mfc_regs->e_rc_config);
1530
1531	/* frame rate */
1532	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1533		reg = 0;
1534		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1535		reg |= p->rc_framerate_denom & 0xFFFF;
1536		writel(reg, mfc_regs->e_rc_frame_rate);
1537	}
1538
1539	/* frame QP */
1540	reg &= ~(0x7F);
1541	reg |= p_vp8->rc_frame_qp & 0x7F;
1542	writel(reg, mfc_regs->e_rc_config);
1543
1544	/* other QPs */
1545	writel(0x0, mfc_regs->e_fixed_picture_qp);
1546	if (!p->rc_frame && !p->rc_mb) {
1547		reg = 0;
1548		reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1549		reg |= p_vp8->rc_frame_qp & 0x7F;
1550		writel(reg, mfc_regs->e_fixed_picture_qp);
1551	}
1552
1553	/* max QP */
1554	reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1555	/* min QP */
1556	reg |= p_vp8->rc_min_qp & 0x7F;
1557	writel(reg, mfc_regs->e_rc_qp_bound);
1558
1559	/* vbv buffer size */
1560	if (p->frame_skip_mode ==
1561			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1562		writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1563
1564		if (p->rc_frame)
1565			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1566	}
1567
1568	/* VP8 specific params */
1569	reg = 0;
1570	reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1571	switch (p_vp8->num_partitions) {
1572	case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1573		val = 0;
1574		break;
1575	case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1576		val = 2;
1577		break;
1578	case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1579		val = 4;
1580		break;
1581	case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1582		val = 8;
1583		break;
1584	}
1585	reg |= (val & 0xF) << 3;
1586	reg |= (p_vp8->num_ref & 0x2);
1587	writel(reg, mfc_regs->e_vp8_options);
1588
1589	mfc_debug_leave();
1590
1591	return 0;
1592}
1593
1594static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
1595{
1596	struct s5p_mfc_dev *dev = ctx->dev;
1597	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1598	struct s5p_mfc_enc_params *p = &ctx->enc_params;
1599	struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
1600	unsigned int reg = 0;
1601	int i;
1602
1603	mfc_debug_enter();
1604
1605	s5p_mfc_set_enc_params(ctx);
1606
1607	/* pictype : number of B */
1608	reg = readl(mfc_regs->e_gop_config);
1609	/* num_b_frame - 0 ~ 2 */
1610	reg &= ~(0x3 << 16);
1611	reg |= (p->num_b_frame << 16);
1612	writel(reg, mfc_regs->e_gop_config);
1613
1614	/* UHD encoding case */
1615	if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
1616		p_hevc->level = 51;
1617		p_hevc->tier = 0;
1618	/* this tier can be changed */
1619	}
1620
1621	/* tier & level */
1622	reg = 0;
1623	/* profile */
1624	reg |= p_hevc->profile & 0x3;
1625	/* level */
1626	reg &= ~(0xFF << 8);
1627	reg |= (p_hevc->level << 8);
1628	/* tier - 0 ~ 1 */
1629	reg |= (p_hevc->tier << 16);
1630	writel(reg, mfc_regs->e_picture_profile);
1631
1632	switch (p_hevc->loopfilter) {
1633	case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED:
1634		p_hevc->loopfilter_disable = 1;
1635		break;
1636	case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED:
1637		p_hevc->loopfilter_disable = 0;
1638		p_hevc->loopfilter_across = 1;
1639		break;
1640	case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY:
1641		p_hevc->loopfilter_disable = 0;
1642		p_hevc->loopfilter_across = 0;
1643		break;
1644	}
1645
1646	/* max partition depth */
1647	reg = 0;
1648	reg |= (p_hevc->max_partition_depth & 0x1);
1649	reg |= (p_hevc->num_refs_for_p-1) << 2;
1650	reg |= (p_hevc->refreshtype & 0x3) << 3;
1651	reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
1652	reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
1653	reg |= (p_hevc->wavefront_enable & 0x1) << 7;
1654	reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
1655	reg |= (p_hevc->loopfilter_across & 0x1) << 9;
1656	reg |= (p_hevc->enable_ltr & 0x1) << 10;
1657	reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
1658	reg |= (p_hevc->general_pb_enable & 0x1) << 13;
1659	reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
1660	reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
1661	reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
1662	reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
1663	reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
1664	reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 23;
1665	reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
1666
1667	writel(reg, mfc_regs->e_hevc_options);
1668	/* refresh period */
1669	if (p_hevc->refreshtype) {
1670		reg = 0;
1671		reg |= (p_hevc->refreshperiod & 0xFFFF);
1672		writel(reg, mfc_regs->e_hevc_refresh_period);
1673	}
1674	/* loop filter setting */
1675	if (!(p_hevc->loopfilter_disable & 0x1)) {
1676		reg = 0;
1677		reg |= (p_hevc->lf_beta_offset_div2);
1678		writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
1679		reg = 0;
1680		reg |= (p_hevc->lf_tc_offset_div2);
1681		writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
1682	}
1683	/* hier qp enable */
1684	if (p_hevc->num_hier_layer) {
1685		reg = 0;
1686		reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
1687		reg |= p_hevc->num_hier_layer & 0x7;
1688		writel(reg, mfc_regs->e_num_t_layer);
1689		/* QP value for each layer */
1690		if (p_hevc->hier_qp_enable) {
1691			for (i = 0; i < 7; i++)
1692				writel(p_hevc->hier_qp_layer[i],
1693					mfc_regs->e_hier_qp_layer0 + i * 4);
1694		}
1695		if (p->rc_frame) {
1696			for (i = 0; i < 7; i++)
1697				writel(p_hevc->hier_bit_layer[i],
1698						mfc_regs->e_hier_bit_rate_layer0
1699						+ i * 4);
1700		}
1701	}
1702
1703	/* rate control config. */
1704	reg = readl(mfc_regs->e_rc_config);
1705	/* macroblock level rate control */
1706	reg &= ~(0x1 << 8);
1707	reg |= (p->rc_mb << 8);
1708	writel(reg, mfc_regs->e_rc_config);
1709	/* frame QP */
1710	reg &= ~(0xFF);
1711	reg |= p_hevc->rc_frame_qp;
1712	writel(reg, mfc_regs->e_rc_config);
1713
1714	/* frame rate */
1715	if (p->rc_frame) {
1716		reg = 0;
1717		reg &= ~(0xFFFF << 16);
1718		reg |= ((p_hevc->rc_framerate) << 16);
1719		reg &= ~(0xFFFF);
1720		reg |= FRAME_DELTA_DEFAULT;
1721		writel(reg, mfc_regs->e_rc_frame_rate);
1722	}
1723
1724	/* max & min value of QP */
1725	reg = 0;
1726	/* max QP */
1727	reg &= ~(0xFF << 8);
1728	reg |= (p_hevc->rc_max_qp << 8);
1729	/* min QP */
1730	reg &= ~(0xFF);
1731	reg |= p_hevc->rc_min_qp;
1732	writel(reg, mfc_regs->e_rc_qp_bound);
1733
1734	writel(0x0, mfc_regs->e_fixed_picture_qp);
1735	if (!p->rc_frame && !p->rc_mb) {
1736		reg = 0;
1737		reg &= ~(0xFF << 16);
1738		reg |= (p_hevc->rc_b_frame_qp << 16);
1739		reg &= ~(0xFF << 8);
1740		reg |= (p_hevc->rc_p_frame_qp << 8);
1741		reg &= ~(0xFF);
1742		reg |= p_hevc->rc_frame_qp;
1743		writel(reg, mfc_regs->e_fixed_picture_qp);
1744	}
1745	mfc_debug_leave();
1746
1747	return 0;
1748}
1749
1750/* Initialize decoding */
1751static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1752{
1753	struct s5p_mfc_dev *dev = ctx->dev;
1754	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1755	unsigned int reg = 0;
1756	int fmo_aso_ctrl = 0;
1757
1758	mfc_debug_enter();
1759	mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1760			S5P_FIMV_CH_SEQ_HEADER_V6);
1761	mfc_debug(2, "BUFs: %08x %08x %08x\n",
1762		  readl(mfc_regs->d_cpb_buffer_addr),
1763		  readl(mfc_regs->d_cpb_buffer_addr),
1764		  readl(mfc_regs->d_cpb_buffer_addr));
1765
1766	/* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1767	reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1768
1769	if (ctx->display_delay_enable) {
1770		reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1771		writel(ctx->display_delay, mfc_regs->d_display_delay);
1772	}
1773
1774	if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {
1775		writel(reg, mfc_regs->d_dec_options);
1776		reg = 0;
1777	}
1778
1779	/* Setup loop filter, for decoding this is only valid for MPEG4 */
1780	if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1781		mfc_debug(2, "Set loop filter to: %d\n",
1782				ctx->loop_filter_mpeg4);
1783		reg |= (ctx->loop_filter_mpeg4 <<
1784				S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1785	}
1786	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1787		reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1788
1789	if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))
1790		writel(reg, mfc_regs->d_init_buffer_options);
1791	else
1792		writel(reg, mfc_regs->d_dec_options);
1793
1794	/* 0: NV12(CbCr), 1: NV21(CrCb), 2: YV12(CrCb), 3: I420(CbCr) */
1795	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M)
1796		writel(0x3, mfc_regs->pixel_format);
1797	else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
1798		writel(0x2, mfc_regs->pixel_format);
1799	else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1800		writel(0x1, mfc_regs->pixel_format);
1801	else
1802		writel(0x0, mfc_regs->pixel_format);
1803
1804
1805	/* sei parse */
1806	writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1807
1808	writel(ctx->inst_no, mfc_regs->instance_id);
1809	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1810			S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1811
1812	mfc_debug_leave();
1813	return 0;
1814}
1815
1816static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1817{
1818	struct s5p_mfc_dev *dev = ctx->dev;
1819	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1820
1821	if (flush) {
1822		dev->curr_ctx = ctx->num;
1823		writel(ctx->inst_no, mfc_regs->instance_id);
1824		s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1825				S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1826	}
1827}
1828
1829/* Decode a single frame */
1830static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1831			enum s5p_mfc_decode_arg last_frame)
1832{
1833	struct s5p_mfc_dev *dev = ctx->dev;
1834	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1835
1836	writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1837	writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1838
1839	writel(ctx->inst_no, mfc_regs->instance_id);
1840	/* Issue different commands to instance basing on whether it
1841	 * is the last frame or not. */
1842	switch (last_frame) {
1843	case 0:
1844		s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1845				S5P_FIMV_CH_FRAME_START_V6, NULL);
1846		break;
1847	case 1:
1848		s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1849				S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1850		break;
1851	default:
1852		mfc_err("Unsupported last frame arg.\n");
1853		return -EINVAL;
1854	}
1855
1856	mfc_debug(2, "Decoding a usual frame.\n");
1857	return 0;
1858}
1859
1860static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1861{
1862	struct s5p_mfc_dev *dev = ctx->dev;
1863	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1864
1865	if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1866		s5p_mfc_set_enc_params_h264(ctx);
1867	else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1868		s5p_mfc_set_enc_params_mpeg4(ctx);
1869	else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1870		s5p_mfc_set_enc_params_h263(ctx);
1871	else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1872		s5p_mfc_set_enc_params_vp8(ctx);
1873	else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
1874		s5p_mfc_set_enc_params_hevc(ctx);
1875	else {
1876		mfc_err("Unknown codec for encoding (%x).\n",
1877			ctx->codec_mode);
1878		return -EINVAL;
1879	}
1880
1881	/* Set stride lengths for v7 & above */
1882	if (IS_MFCV7_PLUS(dev)) {
1883		writel(ctx->stride[0], mfc_regs->e_source_first_plane_stride);
1884		writel(ctx->stride[1], mfc_regs->e_source_second_plane_stride);
1885		if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==
1886				V4L2_PIX_FMT_YVU420M)
1887			writel(ctx->stride[2], mfc_regs->e_source_third_plane_stride);
1888	}
1889
1890	writel(ctx->inst_no, mfc_regs->instance_id);
1891	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1892			S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1893
1894	return 0;
1895}
1896
1897static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1898{
1899	struct s5p_mfc_dev *dev = ctx->dev;
1900	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1901	const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1902	const struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1903	int i;
1904
1905	if (p_h264->aso) {
1906		for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1907			writel(p_h264->aso_slice_order[i],
1908				mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1909		}
1910	}
1911	return 0;
1912}
1913
1914/* Encode a single frame */
1915static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1916{
1917	struct s5p_mfc_dev *dev = ctx->dev;
1918	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1919	int cmd;
1920
1921	mfc_debug(2, "++\n");
1922
1923	/* memory structure cur. frame */
1924
1925	if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1926		s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1927
1928	s5p_mfc_set_slice_mode(ctx);
1929
1930	if (ctx->state != MFCINST_FINISHING)
1931		cmd = S5P_FIMV_CH_FRAME_START_V6;
1932	else
1933		cmd = S5P_FIMV_CH_LAST_FRAME_V6;
1934
1935	writel(ctx->inst_no, mfc_regs->instance_id);
1936	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, cmd, NULL);
1937
1938	mfc_debug(2, "--\n");
1939
1940	return 0;
1941}
1942
1943static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1944{
1945	struct s5p_mfc_dev *dev = ctx->dev;
1946
1947	s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1948	dev->curr_ctx = ctx->num;
1949	s5p_mfc_decode_one_frame_v6(ctx, MFC_DEC_LAST_FRAME);
1950}
1951
1952static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1953{
1954	struct s5p_mfc_dev *dev = ctx->dev;
1955	struct s5p_mfc_buf *temp_vb;
1956	int last_frame = 0;
1957
1958	if (ctx->state == MFCINST_FINISHING) {
1959		last_frame = MFC_DEC_LAST_FRAME;
1960		s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1961		dev->curr_ctx = ctx->num;
1962		s5p_mfc_clean_ctx_int_flags(ctx);
1963		s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1964		return 0;
1965	}
1966
1967	/* Frames are being decoded */
1968	if (list_empty(&ctx->src_queue)) {
1969		mfc_debug(2, "No src buffers.\n");
1970		return -EAGAIN;
1971	}
1972	/* Get the next source buffer */
1973	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1974	temp_vb->flags |= MFC_BUF_FLAG_USED;
1975	s5p_mfc_set_dec_stream_buffer_v6(ctx,
1976		vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),
1977			ctx->consumed_stream,
1978			temp_vb->b->vb2_buf.planes[0].bytesused);
1979
1980	dev->curr_ctx = ctx->num;
1981	if (temp_vb->b->vb2_buf.planes[0].bytesused == 0) {
1982		last_frame = 1;
1983		mfc_debug(2, "Setting ctx->state to FINISHING\n");
1984		ctx->state = MFCINST_FINISHING;
1985	}
1986	s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1987
1988	return 0;
1989}
1990
1991static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1992{
1993	struct s5p_mfc_dev *dev = ctx->dev;
1994	struct s5p_mfc_buf *dst_mb;
1995	struct s5p_mfc_buf *src_mb;
1996	unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr;
1997	/*
1998	unsigned int src_y_size, src_c_size;
1999	*/
2000	unsigned int dst_size;
2001
2002	if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {
2003		mfc_debug(2, "no src buffers.\n");
2004		return -EAGAIN;
2005	}
2006
2007	if (list_empty(&ctx->dst_queue)) {
2008		mfc_debug(2, "no dst buffers.\n");
2009		return -EAGAIN;
2010	}
2011
2012	if (list_empty(&ctx->src_queue)) {
2013		/* send null frame */
2014		s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);
2015		src_mb = NULL;
2016	} else {
2017		src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
2018		src_mb->flags |= MFC_BUF_FLAG_USED;
2019		if (src_mb->b->vb2_buf.planes[0].bytesused == 0) {
2020			s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);
2021			ctx->state = MFCINST_FINISHING;
2022		} else {
2023			src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0);
2024			src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1);
2025			if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==
2026					V4L2_PIX_FMT_YVU420M)
2027				src_c_1_addr = vb2_dma_contig_plane_dma_addr
2028					(&src_mb->b->vb2_buf, 2);
2029			else
2030				src_c_1_addr = 0;
2031
2032			mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
2033			mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
2034
2035			s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr, src_c_1_addr);
2036			if (src_mb->flags & MFC_BUF_FLAG_EOS)
2037				ctx->state = MFCINST_FINISHING;
2038		}
2039	}
2040
2041	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
2042	dst_mb->flags |= MFC_BUF_FLAG_USED;
2043	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
2044	dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
2045
2046	s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
2047
2048	dev->curr_ctx = ctx->num;
2049	s5p_mfc_encode_one_frame_v6(ctx);
2050
2051	return 0;
2052}
2053
2054static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
2055{
2056	struct s5p_mfc_dev *dev = ctx->dev;
2057	struct s5p_mfc_buf *temp_vb;
2058
2059	/* Initializing decoding - parsing header */
2060	mfc_debug(2, "Preparing to init decoding.\n");
2061	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
2062	mfc_debug(2, "Header size: %d\n", temp_vb->b->vb2_buf.planes[0].bytesused);
2063	s5p_mfc_set_dec_stream_buffer_v6(ctx,
2064		vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), 0,
2065			temp_vb->b->vb2_buf.planes[0].bytesused);
2066	dev->curr_ctx = ctx->num;
2067	s5p_mfc_init_decode_v6(ctx);
2068}
2069
2070static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
2071{
2072	struct s5p_mfc_dev *dev = ctx->dev;
2073	struct s5p_mfc_buf *dst_mb;
2074	unsigned long dst_addr;
2075	unsigned int dst_size;
2076
2077	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
2078	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
2079	dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
2080	s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
2081	dev->curr_ctx = ctx->num;
2082	s5p_mfc_init_encode_v6(ctx);
2083}
2084
2085static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
2086{
2087	struct s5p_mfc_dev *dev = ctx->dev;
2088	int ret;
2089	/* Header was parsed now start processing
2090	 * First set the output frame buffers
2091	 * s5p_mfc_alloc_dec_buffers(ctx); */
2092
2093	if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
2094		mfc_err("It seems that not all destination buffers were\n"
2095			"mmapped.MFC requires that all destination are mmapped\n"
2096			"before starting processing.\n");
2097		return -EAGAIN;
2098	}
2099
2100	dev->curr_ctx = ctx->num;
2101	ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
2102	if (ret) {
2103		mfc_err("Failed to alloc frame mem.\n");
2104		ctx->state = MFCINST_ERROR;
2105	}
2106	return ret;
2107}
2108
2109static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
2110{
2111	struct s5p_mfc_dev *dev = ctx->dev;
2112	int ret;
2113
2114	ret = s5p_mfc_hw_call(ctx->dev->mfc_ops, alloc_codec_buffers, ctx);
2115	if (ret) {
2116		mfc_err("Failed to allocate encoding buffers\n");
2117		return -ENOMEM;
2118	}
2119	mfc_debug(2, "Allocated Internal Encoding Buffers\n");
2120
2121	dev->curr_ctx = ctx->num;
2122	ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
2123	if (ret) {
2124		mfc_err("Failed to alloc frame mem.\n");
2125		ctx->state = MFCINST_ERROR;
2126	}
2127	return ret;
2128}
2129
2130/* Try running an operation on hardware */
2131static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
2132{
2133	struct s5p_mfc_ctx *ctx;
2134	int new_ctx;
2135	unsigned int ret = 0;
2136
2137	mfc_debug(1, "Try run dev: %p\n", dev);
2138
2139	/* Check whether hardware is not running */
2140	if (test_and_set_bit(0, &dev->hw_lock) != 0) {
2141		/* This is perfectly ok, the scheduled ctx should wait */
2142		mfc_debug(1, "Couldn't lock HW.\n");
2143		return;
2144	}
2145
2146	/* Choose the context to run */
2147	new_ctx = s5p_mfc_get_new_ctx(dev);
2148	if (new_ctx < 0) {
2149		/* No contexts to run */
2150		if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
2151			mfc_err("Failed to unlock hardware.\n");
2152			return;
2153		}
2154
2155		mfc_debug(1, "No ctx is scheduled to be run.\n");
2156		return;
2157	}
2158
2159	mfc_debug(1, "New context: %d\n", new_ctx);
2160	ctx = dev->ctx[new_ctx];
2161	mfc_debug(1, "Setting new context to %p\n", ctx);
2162	/* Got context to run in ctx */
2163	mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
2164		ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
2165	mfc_debug(1, "ctx->state=%d\n", ctx->state);
2166	/* Last frame has already been sent to MFC
2167	 * Now obtaining frames from MFC buffer */
2168
2169	s5p_mfc_clock_on(dev);
2170	s5p_mfc_clean_ctx_int_flags(ctx);
2171
2172	if (ctx->type == MFCINST_DECODER) {
2173		switch (ctx->state) {
2174		case MFCINST_FINISHING:
2175			s5p_mfc_run_dec_last_frames(ctx);
2176			break;
2177		case MFCINST_RUNNING:
2178			ret = s5p_mfc_run_dec_frame(ctx);
2179			break;
2180		case MFCINST_INIT:
2181			ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
2182					ctx);
2183			break;
2184		case MFCINST_RETURN_INST:
2185			ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
2186					ctx);
2187			break;
2188		case MFCINST_GOT_INST:
2189			s5p_mfc_run_init_dec(ctx);
2190			break;
2191		case MFCINST_HEAD_PARSED:
2192			ret = s5p_mfc_run_init_dec_buffers(ctx);
2193			break;
2194		case MFCINST_FLUSH:
2195			s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
2196			break;
2197		case MFCINST_RES_CHANGE_INIT:
2198			s5p_mfc_run_dec_last_frames(ctx);
2199			break;
2200		case MFCINST_RES_CHANGE_FLUSH:
2201			s5p_mfc_run_dec_last_frames(ctx);
2202			break;
2203		case MFCINST_RES_CHANGE_END:
2204			mfc_debug(2, "Finished remaining frames after resolution change.\n");
2205			ctx->capture_state = QUEUE_FREE;
2206			mfc_debug(2, "Will re-init the codec`.\n");
2207			s5p_mfc_run_init_dec(ctx);
2208			break;
2209		default:
2210			ret = -EAGAIN;
2211		}
2212	} else if (ctx->type == MFCINST_ENCODER) {
2213		switch (ctx->state) {
2214		case MFCINST_FINISHING:
2215		case MFCINST_RUNNING:
2216			ret = s5p_mfc_run_enc_frame(ctx);
2217			break;
2218		case MFCINST_INIT:
2219			ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
2220					ctx);
2221			break;
2222		case MFCINST_RETURN_INST:
2223			ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
2224					ctx);
2225			break;
2226		case MFCINST_GOT_INST:
2227			s5p_mfc_run_init_enc(ctx);
2228			break;
2229		case MFCINST_HEAD_PRODUCED:
2230			ret = s5p_mfc_run_init_enc_buffers(ctx);
2231			break;
2232		case MFCINST_NAL_ABORT:
2233			mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
2234			s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc,
2235					dev, S5P_FIMV_H2R_CMD_NAL_ABORT_V6, NULL);
2236			break;
2237		default:
2238			ret = -EAGAIN;
2239		}
2240	} else {
2241		mfc_err("invalid context type: %d\n", ctx->type);
2242		ret = -EAGAIN;
2243	}
2244
2245	if (ret) {
2246		/* Free hardware lock */
2247		if (test_and_clear_bit(0, &dev->hw_lock) == 0)
2248			mfc_err("Failed to unlock hardware.\n");
2249
2250		/* This is in deed imporant, as no operation has been
2251		 * scheduled, reduce the clock count as no one will
2252		 * ever do this, because no interrupt related to this try_run
2253		 * will ever come from hardware. */
2254		s5p_mfc_clock_off(dev);
2255	}
2256}
2257
2258static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
2259{
2260	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
2261	writel(0, mfc_regs->risc2host_command);
2262	writel(0, mfc_regs->risc2host_int);
2263}
2264
2265static unsigned int
2266s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned long ofs)
2267{
2268	int ret;
2269
2270	s5p_mfc_clock_on(ctx->dev);
2271	ret = readl((void __iomem *)ofs);
2272	s5p_mfc_clock_off(ctx->dev);
2273
2274	return ret;
2275}
2276
2277static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
2278{
2279	return readl(dev->mfc_regs->d_display_first_plane_addr);
2280}
2281
2282static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
2283{
2284	return readl(dev->mfc_regs->d_decoded_first_plane_addr);
2285}
2286
2287static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
2288{
2289	return readl(dev->mfc_regs->d_display_status);
2290}
2291
2292static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
2293{
2294	return readl(dev->mfc_regs->d_decoded_status);
2295}
2296
2297static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
2298{
2299	return readl(dev->mfc_regs->d_decoded_frame_type) &
2300		S5P_FIMV_DECODE_FRAME_MASK_V6;
2301}
2302
2303static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
2304{
2305	struct s5p_mfc_dev *dev = ctx->dev;
2306	return readl(dev->mfc_regs->d_display_frame_type) &
2307		S5P_FIMV_DECODE_FRAME_MASK_V6;
2308}
2309
2310static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
2311{
2312	return readl(dev->mfc_regs->d_decoded_nal_size);
2313}
2314
2315static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
2316{
2317	return readl(dev->mfc_regs->risc2host_command) &
2318		S5P_FIMV_RISC2HOST_CMD_MASK;
2319}
2320
2321static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
2322{
2323	return readl(dev->mfc_regs->error_code);
2324}
2325
2326static int s5p_mfc_err_dec_v6(unsigned int err)
2327{
2328	return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
2329}
2330
2331static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
2332{
2333	return readl(dev->mfc_regs->d_display_frame_width);
2334}
2335
2336static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
2337{
2338	return readl(dev->mfc_regs->d_display_frame_height);
2339}
2340
2341static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
2342{
2343	return readl(dev->mfc_regs->d_min_num_dpb);
2344}
2345
2346static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
2347{
2348	return readl(dev->mfc_regs->d_min_num_mv);
2349}
2350
2351static int s5p_mfc_get_min_scratch_buf_size(struct s5p_mfc_dev *dev)
2352{
2353	return readl(dev->mfc_regs->d_min_scratch_buffer_size);
2354}
2355
2356static int s5p_mfc_get_e_min_scratch_buf_size(struct s5p_mfc_dev *dev)
2357{
2358	return readl(dev->mfc_regs->e_min_scratch_buffer_size);
2359}
2360
2361static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
2362{
2363	return readl(dev->mfc_regs->ret_instance_id);
2364}
2365
2366static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
2367{
2368	return readl(dev->mfc_regs->e_num_dpb);
2369}
2370
2371static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
2372{
2373	return readl(dev->mfc_regs->e_stream_size);
2374}
2375
2376static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
2377{
2378	return readl(dev->mfc_regs->e_slice_type);
2379}
2380
2381static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
2382{
2383	return s5p_mfc_read_info_v6(ctx,
2384		(__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top);
2385}
2386
2387static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
2388{
2389	return s5p_mfc_read_info_v6(ctx,
2390		(__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
2391}
2392
2393static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
2394{
2395	return s5p_mfc_read_info_v6(ctx,
2396		(__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1);
2397}
2398
2399static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
2400{
2401	return s5p_mfc_read_info_v6(ctx,
2402		(__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2);
2403}
2404
2405static struct s5p_mfc_regs mfc_regs;
2406
2407/* Initialize registers for MFC v6 onwards */
2408const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
2409{
2410	memset(&mfc_regs, 0, sizeof(mfc_regs));
2411
2412#define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))
2413#define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)
2414	/* codec common registers */
2415	R(risc_on, S5P_FIMV_RISC_ON_V6);
2416	R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);
2417	R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);
2418	R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);
2419	R(mfc_reset, S5P_FIMV_MFC_RESET_V6);
2420	R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);
2421	R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);
2422	R(firmware_version, S5P_FIMV_FW_VERSION_V6);
2423	R(instance_id, S5P_FIMV_INSTANCE_ID_V6);
2424	R(codec_type, S5P_FIMV_CODEC_TYPE_V6);
2425	R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
2426	R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
2427	R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);
2428	R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);
2429	R(error_code, S5P_FIMV_ERROR_CODE_V6);
2430
2431	/* decoder registers */
2432	R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);
2433	R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);
2434	R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
2435	R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);
2436	R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);
2437	R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);
2438	R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
2439	R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);
2440	R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);
2441	R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);
2442	R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
2443	R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
2444	R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
2445	R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);
2446	R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);
2447	R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);
2448	R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
2449	R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
2450	R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
2451	R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
2452	R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
2453	R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
2454	R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
2455	R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
2456	R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
2457	R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
2458	R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);
2459	R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
2460	R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);
2461	R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);
2462	R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);
2463	R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);
2464	R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);
2465	R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);
2466	R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);
2467	R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
2468	R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);
2469	R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);
2470	R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
2471	R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);
2472	R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);
2473	R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);
2474	R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);
2475	R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
2476
2477	/* encoder registers */
2478	R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);
2479	R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);
2480	R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
2481	R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
2482	R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
2483	R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);
2484	R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);
2485	R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
2486	R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
2487	R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
2488	R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);
2489	R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);
2490	R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);
2491	R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);
2492	R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);
2493	R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);
2494	R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);
2495	R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);
2496	R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);
2497	R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);
2498	R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);
2499	R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
2500	R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
2501	R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);
2502	R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);
2503	R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
2504	R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
2505	R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);
2506	R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
2507	R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
2508	R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);
2509	R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);
2510	R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);
2511	R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
2512	R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
2513	R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
2514	R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);
2515	R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);
2516	R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);
2517	R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);
2518	R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);
2519	R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
2520	R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);
2521	R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);
2522	R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
2523	R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
2524	R(e_encoded_source_first_plane_addr,
2525			S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
2526	R(e_encoded_source_second_plane_addr,
2527			S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
2528	R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);
2529	R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);
2530	R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);
2531	R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);
2532	R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
2533	R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
2534	R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);
2535	R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
2536	R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);
2537	R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);
2538	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);
2539	R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
2540	R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
2541	R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);
2542	R(e_h264_fmo_slice_grp_map_type,
2543			S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
2544	R(e_h264_fmo_num_slice_grp_minus1,
2545			S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
2546	R(e_h264_fmo_slice_grp_change_dir,
2547			S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
2548	R(e_h264_fmo_slice_grp_change_rate_minus1,
2549			S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
2550	R(e_h264_fmo_run_length_minus1_0,
2551			S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);
2552	R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);
2553	R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
2554	R(e_h264_hierarchical_qp_layer0,
2555			S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);
2556	R(e_h264_frame_packing_sei_info,
2557			S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
2558
2559	if (!IS_MFCV7_PLUS(dev))
2560		goto done;
2561
2562	/* Initialize registers used in MFC v7+ */
2563	R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
2564	R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
2565	R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);
2566	R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
2567	R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
2568	R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);
2569	R(e_encoded_source_first_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
2570	R(e_encoded_source_second_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
2571	R(e_encoded_source_third_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7);
2572	R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
2573
2574	if (!IS_MFCV8_PLUS(dev))
2575		goto done;
2576
2577	/* Initialize registers used in MFC v8 only.
2578	 * Also, over-write the registers which have
2579	 * a different offset for MFC v8. */
2580	R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8);
2581	R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8);
2582	R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8);
2583	R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);
2584	R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);
2585	R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);
2586	R(d_third_plane_dpb_size, S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8);
2587	R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);
2588	R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);
2589	R(d_first_plane_dpb_stride_size, S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);
2590	R(d_second_plane_dpb_stride_size, S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);
2591	R(d_third_plane_dpb_stride_size, S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8);
2592	R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);
2593	R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);
2594	R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);
2595	R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);
2596	R(d_third_plane_dpb, S5P_FIMV_D_THIRD_PLANE_DPB_V8);
2597	R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);
2598	R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);
2599	R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);
2600	R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8);
2601	R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8);
2602	R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8);
2603	R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8);
2604	R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8);
2605	R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8);
2606	R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8);
2607	R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8);
2608	R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8);
2609	R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8);
2610	R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8);
2611	R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8);
2612	R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8);
2613	R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8);
2614	R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8);
2615	R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8);
2616	R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);
2617	R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);
2618	R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);
2619	R(d_min_scratch_buffer_size, S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8);
2620
2621	/* encoder registers */
2622	R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);
2623	R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);
2624	R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);
2625	R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);
2626	R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);
2627	R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);
2628	R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);
2629	R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);
2630	R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);
2631	R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);
2632	R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);
2633	R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);
2634	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
2635	R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);
2636
2637	if (!IS_MFCV10_PLUS(dev))
2638		goto done;
2639
2640	/* Initialize registers used in MFC v10 only.
2641	 * Also, over-write the registers which have
2642	 * a different offset for MFC v10.
2643	 */
2644
2645	/* decoder registers */
2646	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
2647	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
2648
2649	/* encoder registers */
2650	R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
2651	R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
2652	R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
2653	R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
2654	R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
2655	R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
2656	R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
2657	R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
2658
2659done:
2660	return &mfc_regs;
2661#undef S5P_MFC_REG_ADDR
2662#undef R
2663}
2664
2665/* Initialize opr function pointers for MFC v6 */
2666static const struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
2667	.alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
2668	.release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
2669	.alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
2670	.release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
2671	.alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
2672	.release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
2673	.alloc_dev_context_buffer =
2674		s5p_mfc_alloc_dev_context_buffer_v6,
2675	.release_dev_context_buffer =
2676		s5p_mfc_release_dev_context_buffer_v6,
2677	.dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
2678	.enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
2679	.set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
2680	.set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
2681	.get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
2682	.try_run = s5p_mfc_try_run_v6,
2683	.clear_int_flags = s5p_mfc_clear_int_flags_v6,
2684	.get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
2685	.get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
2686	.get_dspl_status = s5p_mfc_get_dspl_status_v6,
2687	.get_dec_status = s5p_mfc_get_dec_status_v6,
2688	.get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
2689	.get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
2690	.get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
2691	.get_int_reason = s5p_mfc_get_int_reason_v6,
2692	.get_int_err = s5p_mfc_get_int_err_v6,
2693	.err_dec = s5p_mfc_err_dec_v6,
2694	.get_img_width = s5p_mfc_get_img_width_v6,
2695	.get_img_height = s5p_mfc_get_img_height_v6,
2696	.get_dpb_count = s5p_mfc_get_dpb_count_v6,
2697	.get_mv_count = s5p_mfc_get_mv_count_v6,
2698	.get_inst_no = s5p_mfc_get_inst_no_v6,
2699	.get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2700	.get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2701	.get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2702	.get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2703	.get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2704	.get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2705	.get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2706	.get_min_scratch_buf_size = s5p_mfc_get_min_scratch_buf_size,
2707	.get_e_min_scratch_buf_size = s5p_mfc_get_e_min_scratch_buf_size,
2708};
2709
2710const struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2711{
2712	return &s5p_mfc_ops_v6;
2713}