s5p_mfc_cmd_v6.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * linux/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c
  4 *
  5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  6 *		http://www.samsung.com/
  7 */
  8
  9#include "s5p_mfc_common.h"
 10
 11#include "s5p_mfc_cmd.h"
 12#include "s5p_mfc_debug.h"
 13#include "s5p_mfc_intr.h"
 14#include "s5p_mfc_opr.h"
 15#include "s5p_mfc_cmd_v6.h"
 16
 17static int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd)
 18{
 19	mfc_debug(2, "Issue the command: %d\n", cmd);
 20
 21	/* Reset RISC2HOST command */
 22	mfc_write(dev, 0x0, S5P_FIMV_RISC2HOST_CMD_V6);
 23
 24	/* Issue the command */
 25	mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD_V6);
 26	mfc_write(dev, 0x1, S5P_FIMV_HOST2RISC_INT_V6);
 27
 28	return 0;
 29}
 30
 31static int s5p_mfc_sys_init_cmd_v6(struct s5p_mfc_dev *dev)
 32{
 33	const struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 34	int ret;
 35
 36	ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_dev_context_buffer, dev);
 37	if (ret)
 38		return ret;
 39
 40	mfc_write(dev, dev->ctx_buf.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
 41	mfc_write(dev, buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
 42	return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SYS_INIT_V6);
 43}
 44
 45static int s5p_mfc_sleep_cmd_v6(struct s5p_mfc_dev *dev)
 46{
 47	return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SLEEP_V6);
 48}
 49
 50static int s5p_mfc_wakeup_cmd_v6(struct s5p_mfc_dev *dev)
 51{
 52	return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_WAKEUP_V6);
 53}
 54
 55/* Open a new instance and get its number */
 56static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
 57{
 58	struct s5p_mfc_dev *dev = ctx->dev;
 59	int codec_type;
 60
 61	mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode);
 62	dev->curr_ctx = ctx->num;
 63	switch (ctx->codec_mode) {
 64	case S5P_MFC_CODEC_H264_DEC:
 65		codec_type = S5P_FIMV_CODEC_H264_DEC_V6;
 66		break;
 67	case S5P_MFC_CODEC_H264_MVC_DEC:
 68		codec_type = S5P_FIMV_CODEC_H264_MVC_DEC_V6;
 69		break;
 70	case S5P_MFC_CODEC_VC1_DEC:
 71		codec_type = S5P_FIMV_CODEC_VC1_DEC_V6;
 72		break;
 73	case S5P_MFC_CODEC_MPEG4_DEC:
 74		codec_type = S5P_FIMV_CODEC_MPEG4_DEC_V6;
 75		break;
 76	case S5P_MFC_CODEC_MPEG2_DEC:
 77		codec_type = S5P_FIMV_CODEC_MPEG2_DEC_V6;
 78		break;
 79	case S5P_MFC_CODEC_H263_DEC:
 80		codec_type = S5P_FIMV_CODEC_H263_DEC_V6;
 81		break;
 82	case S5P_MFC_CODEC_VC1RCV_DEC:
 83		codec_type = S5P_FIMV_CODEC_VC1RCV_DEC_V6;
 84		break;
 85	case S5P_MFC_CODEC_VP8_DEC:
 86		codec_type = S5P_FIMV_CODEC_VP8_DEC_V6;
 87		break;
 88	case S5P_MFC_CODEC_HEVC_DEC:
 89		codec_type = S5P_FIMV_CODEC_HEVC_DEC;
 90		break;
 91	case S5P_MFC_CODEC_VP9_DEC:
 92		codec_type = S5P_FIMV_CODEC_VP9_DEC;
 93		break;
 94	case S5P_MFC_CODEC_H264_ENC:
 95		codec_type = S5P_FIMV_CODEC_H264_ENC_V6;
 96		break;
 97	case S5P_MFC_CODEC_H264_MVC_ENC:
 98		codec_type = S5P_FIMV_CODEC_H264_MVC_ENC_V6;
 99		break;
100	case S5P_MFC_CODEC_MPEG4_ENC:
101		codec_type = S5P_FIMV_CODEC_MPEG4_ENC_V6;
102		break;
103	case S5P_MFC_CODEC_H263_ENC:
104		codec_type = S5P_FIMV_CODEC_H263_ENC_V6;
105		break;
106	case S5P_MFC_CODEC_VP8_ENC:
107		codec_type = S5P_FIMV_CODEC_VP8_ENC_V7;
108		break;
109	case S5P_MFC_CODEC_HEVC_ENC:
110		codec_type = S5P_FIMV_CODEC_HEVC_ENC;
111		break;
112	default:
113		codec_type = S5P_FIMV_CODEC_NONE_V6;
114	}
115	mfc_write(dev, codec_type, S5P_FIMV_CODEC_TYPE_V6);
116	mfc_write(dev, ctx->ctx.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
117	mfc_write(dev, ctx->ctx.size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
118	mfc_write(dev, 0, S5P_FIMV_D_CRC_CTRL_V6); /* no crc */
119
120	return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6);
121}
122
123/* Close instance */
124static int s5p_mfc_close_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
125{
126	struct s5p_mfc_dev *dev = ctx->dev;
127	int ret = 0;
128
129	dev->curr_ctx = ctx->num;
130	if (ctx->state != MFCINST_FREE) {
131		mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
132		ret = s5p_mfc_cmd_host2risc_v6(dev,
133					S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6);
134	} else {
135		ret = -EINVAL;
136	}
137
138	return ret;
139}
140
141static int s5p_mfc_cmd_host2risc_v6_args(struct s5p_mfc_dev *dev, int cmd,
142				    const struct s5p_mfc_cmd_args *ignored)
143{
144	return s5p_mfc_cmd_host2risc_v6(dev, cmd);
145}
146
147/* Initialize cmd function pointers for MFC v6 */
148static const struct s5p_mfc_hw_cmds s5p_mfc_cmds_v6 = {
149	.cmd_host2risc = s5p_mfc_cmd_host2risc_v6_args,
150	.sys_init_cmd = s5p_mfc_sys_init_cmd_v6,
151	.sleep_cmd = s5p_mfc_sleep_cmd_v6,
152	.wakeup_cmd = s5p_mfc_wakeup_cmd_v6,
153	.open_inst_cmd = s5p_mfc_open_inst_cmd_v6,
154	.close_inst_cmd = s5p_mfc_close_inst_cmd_v6,
155};
156
157const struct s5p_mfc_hw_cmds *s5p_mfc_init_hw_cmds_v6(void)
158{
159	return &s5p_mfc_cmds_v6;
160}