s5p_mfc.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Samsung S5P Multi Format Codec v 5.1
   4 *
   5 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   6 * Kamil Debski, <k.debski@samsung.com>
   7 */
   8
   9#include <linux/clk.h>
  10#include <linux/delay.h>
  11#include <linux/interrupt.h>
  12#include <linux/io.h>
  13#include <linux/module.h>
  14#include <linux/platform_device.h>
  15#include <linux/sched.h>
  16#include <linux/slab.h>
  17#include <linux/videodev2.h>
  18#include <media/v4l2-event.h>
  19#include <linux/workqueue.h>
  20#include <linux/of.h>
  21#include <linux/of_device.h>
  22#include <linux/of_reserved_mem.h>
  23#include <media/videobuf2-v4l2.h>
  24#include "s5p_mfc_common.h"
  25#include "s5p_mfc_ctrl.h"
  26#include "s5p_mfc_debug.h"
  27#include "s5p_mfc_dec.h"
  28#include "s5p_mfc_enc.h"
  29#include "s5p_mfc_intr.h"
  30#include "s5p_mfc_iommu.h"
  31#include "s5p_mfc_opr.h"
  32#include "s5p_mfc_cmd.h"
  33#include "s5p_mfc_pm.h"
  34
  35#define S5P_MFC_DEC_NAME	"s5p-mfc-dec"
  36#define S5P_MFC_ENC_NAME	"s5p-mfc-enc"
  37
  38int mfc_debug_level;
  39module_param_named(debug, mfc_debug_level, int, 0644);
  40MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
  41
  42static char *mfc_mem_size;
  43module_param_named(mem, mfc_mem_size, charp, 0644);
  44MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
  45
  46/* Helper functions for interrupt processing */
  47
  48/* Remove from hw execution round robin */
  49void clear_work_bit(struct s5p_mfc_ctx *ctx)
  50{
  51	struct s5p_mfc_dev *dev = ctx->dev;
  52
  53	spin_lock(&dev->condlock);
  54	__clear_bit(ctx->num, &dev->ctx_work_bits);
  55	spin_unlock(&dev->condlock);
  56}
  57
  58/* Add to hw execution round robin */
  59void set_work_bit(struct s5p_mfc_ctx *ctx)
  60{
  61	struct s5p_mfc_dev *dev = ctx->dev;
  62
  63	spin_lock(&dev->condlock);
  64	__set_bit(ctx->num, &dev->ctx_work_bits);
  65	spin_unlock(&dev->condlock);
  66}
  67
  68/* Remove from hw execution round robin */
  69void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  70{
  71	struct s5p_mfc_dev *dev = ctx->dev;
  72	unsigned long flags;
  73
  74	spin_lock_irqsave(&dev->condlock, flags);
  75	__clear_bit(ctx->num, &dev->ctx_work_bits);
  76	spin_unlock_irqrestore(&dev->condlock, flags);
  77}
  78
  79/* Add to hw execution round robin */
  80void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  81{
  82	struct s5p_mfc_dev *dev = ctx->dev;
  83	unsigned long flags;
  84
  85	spin_lock_irqsave(&dev->condlock, flags);
  86	__set_bit(ctx->num, &dev->ctx_work_bits);
  87	spin_unlock_irqrestore(&dev->condlock, flags);
  88}
  89
  90int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
  91{
  92	unsigned long flags;
  93	int ctx;
  94
  95	spin_lock_irqsave(&dev->condlock, flags);
  96	ctx = dev->curr_ctx;
  97	do {
  98		ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
  99		if (ctx == dev->curr_ctx) {
 100			if (!test_bit(ctx, &dev->ctx_work_bits))
 101				ctx = -EAGAIN;
 102			break;
 103		}
 104	} while (!test_bit(ctx, &dev->ctx_work_bits));
 105	spin_unlock_irqrestore(&dev->condlock, flags);
 106
 107	return ctx;
 108}
 109
 110/* Wake up context wait_queue */
 111static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
 112			unsigned int err)
 113{
 114	ctx->int_cond = 1;
 115	ctx->int_type = reason;
 116	ctx->int_err = err;
 117	wake_up(&ctx->queue);
 118}
 119
 120/* Wake up device wait_queue */
 121static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
 122			unsigned int err)
 123{
 124	dev->int_cond = 1;
 125	dev->int_type = reason;
 126	dev->int_err = err;
 127	wake_up(&dev->queue);
 128}
 129
 130void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
 131{
 132	struct s5p_mfc_buf *b;
 133	int i;
 134
 135	while (!list_empty(lh)) {
 136		b = list_entry(lh->next, struct s5p_mfc_buf, list);
 137		for (i = 0; i < b->b->vb2_buf.num_planes; i++)
 138			vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
 139		vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
 140		list_del(&b->list);
 141	}
 142}
 143
 144static void s5p_mfc_watchdog(struct timer_list *t)
 145{
 146	struct s5p_mfc_dev *dev = timer_container_of(dev, t, watchdog_timer);
 147
 148	if (test_bit(0, &dev->hw_lock))
 149		atomic_inc(&dev->watchdog_cnt);
 150	if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
 151		/*
 152		 * This means that hw is busy and no interrupts were
 153		 * generated by hw for the Nth time of running this
 154		 * watchdog timer. This usually means a serious hw
 155		 * error. Now it is time to kill all instances and
 156		 * reset the MFC.
 157		 */
 158		mfc_err("Time out during waiting for HW\n");
 159		schedule_work(&dev->watchdog_work);
 160	}
 161	dev->watchdog_timer.expires = jiffies +
 162					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 163	add_timer(&dev->watchdog_timer);
 164}
 165
 166static void s5p_mfc_watchdog_worker(struct work_struct *work)
 167{
 168	struct s5p_mfc_dev *dev;
 169	struct s5p_mfc_ctx *ctx;
 170	unsigned long flags;
 171	int mutex_locked;
 172	int i, ret;
 173
 174	dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
 175
 176	mfc_err("Driver timeout error handling\n");
 177	/*
 178	 * Lock the mutex that protects open and release.
 179	 * This is necessary as they may load and unload firmware.
 180	 */
 181	mutex_locked = mutex_trylock(&dev->mfc_mutex);
 182	if (!mutex_locked)
 183		mfc_err("Error: some instance may be closing/opening\n");
 184	spin_lock_irqsave(&dev->irqlock, flags);
 185
 186	s5p_mfc_clock_off(dev);
 187
 188	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
 189		ctx = dev->ctx[i];
 190		if (!ctx)
 191			continue;
 192		ctx->state = MFCINST_ERROR;
 193		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
 194		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
 195		clear_work_bit(ctx);
 196		wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
 197	}
 198	clear_bit(0, &dev->hw_lock);
 199	spin_unlock_irqrestore(&dev->irqlock, flags);
 200
 201	/* De-init MFC */
 202	s5p_mfc_deinit_hw(dev);
 203
 204	/*
 205	 * Double check if there is at least one instance running.
 206	 * If no instance is in memory than no firmware should be present
 207	 */
 208	if (dev->num_inst > 0) {
 209		ret = s5p_mfc_load_firmware(dev);
 210		if (ret) {
 211			mfc_err("Failed to reload FW\n");
 212			goto unlock;
 213		}
 214		s5p_mfc_clock_on(dev);
 215		ret = s5p_mfc_init_hw(dev);
 216		s5p_mfc_clock_off(dev);
 217		if (ret)
 218			mfc_err("Failed to reinit FW\n");
 219	}
 220unlock:
 221	if (mutex_locked)
 222		mutex_unlock(&dev->mfc_mutex);
 223}
 224
 225static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
 226{
 227	struct s5p_mfc_buf *dst_buf;
 228	struct s5p_mfc_dev *dev = ctx->dev;
 229
 230	ctx->state = MFCINST_FINISHED;
 231	ctx->sequence++;
 232	while (!list_empty(&ctx->dst_queue)) {
 233		dst_buf = list_entry(ctx->dst_queue.next,
 234				     struct s5p_mfc_buf, list);
 235		mfc_debug(2, "Cleaning up buffer: %d\n",
 236					  dst_buf->b->vb2_buf.index);
 237		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
 238		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
 239		list_del(&dst_buf->list);
 240		dst_buf->flags |= MFC_BUF_FLAG_EOS;
 241		ctx->dst_queue_cnt--;
 242		dst_buf->b->sequence = (ctx->sequence++);
 243
 244		if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
 245			s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
 246			dst_buf->b->field = V4L2_FIELD_NONE;
 247		else
 248			dst_buf->b->field = V4L2_FIELD_INTERLACED;
 249		dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
 250
 251		ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
 252		vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
 253	}
 254}
 255
 256static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
 257{
 258	struct s5p_mfc_dev *dev = ctx->dev;
 259	struct s5p_mfc_buf *dst_buf, *src_buf;
 260	u32 dec_y_addr;
 261	unsigned int frame_type;
 262
 263	/* Make sure we actually have a new frame before continuing. */
 264	frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
 265	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
 266		return;
 267	dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
 268
 269	/*
 270	 * Copy timestamp / timecode from decoded src to dst and set
 271	 * appropriate flags.
 272	 */
 273	src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
 274	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 275		u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
 276
 277		if (addr == dec_y_addr) {
 278			dst_buf->b->timecode = src_buf->b->timecode;
 279			dst_buf->b->vb2_buf.timestamp =
 280						src_buf->b->vb2_buf.timestamp;
 281			dst_buf->b->flags &=
 282				~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 283			dst_buf->b->flags |=
 284				src_buf->b->flags
 285				& V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 286			switch (frame_type) {
 287			case S5P_FIMV_DECODE_FRAME_I_FRAME:
 288				dst_buf->b->flags |=
 289						V4L2_BUF_FLAG_KEYFRAME;
 290				break;
 291			case S5P_FIMV_DECODE_FRAME_P_FRAME:
 292				dst_buf->b->flags |=
 293						V4L2_BUF_FLAG_PFRAME;
 294				break;
 295			case S5P_FIMV_DECODE_FRAME_B_FRAME:
 296				dst_buf->b->flags |=
 297						V4L2_BUF_FLAG_BFRAME;
 298				break;
 299			default:
 300				/*
 301				 * Don't know how to handle
 302				 * S5P_FIMV_DECODE_FRAME_OTHER_FRAME.
 303				 */
 304				mfc_debug(2, "Unexpected frame type: %d\n",
 305						frame_type);
 306			}
 307			break;
 308		}
 309	}
 310}
 311
 312static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
 313{
 314	struct s5p_mfc_dev *dev = ctx->dev;
 315	struct s5p_mfc_buf  *dst_buf;
 316	u32 dspl_y_addr;
 317	unsigned int frame_type;
 318
 319	dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
 320	if (IS_MFCV6_PLUS(dev))
 321		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 322			get_disp_frame_type, ctx);
 323	else
 324		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 325			get_dec_frame_type, dev);
 326
 327	/* If frame is same as previous then skip and do not dequeue */
 328	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
 329		if (!ctx->after_packed_pb)
 330			ctx->sequence++;
 331		ctx->after_packed_pb = 0;
 332		return;
 333	}
 334	ctx->sequence++;
 335	/*
 336	 * The MFC returns address of the buffer, now we have to
 337	 * check which vb2_buffer does it correspond to
 338	 */
 339	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 340		u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
 341
 342		/* Check if this is the buffer we're looking for */
 343		if (addr == dspl_y_addr) {
 344			list_del(&dst_buf->list);
 345			ctx->dst_queue_cnt--;
 346			dst_buf->b->sequence = ctx->sequence;
 347			if (s5p_mfc_hw_call(dev->mfc_ops,
 348					get_pic_type_top, ctx) ==
 349				s5p_mfc_hw_call(dev->mfc_ops,
 350					get_pic_type_bot, ctx))
 351				dst_buf->b->field = V4L2_FIELD_NONE;
 352			else
 353				dst_buf->b->field =
 354							V4L2_FIELD_INTERLACED;
 355			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
 356						ctx->luma_size);
 357			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
 358						ctx->chroma_size);
 359			clear_bit(dst_buf->b->vb2_buf.index,
 360							&ctx->dec_dst_flag);
 361
 362			vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
 363				VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
 364
 365			break;
 366		}
 367	}
 368}
 369
 370/* Handle frame decoding interrupt */
 371static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
 372					unsigned int reason, unsigned int err)
 373{
 374	struct s5p_mfc_dev *dev = ctx->dev;
 375	unsigned int dst_frame_status;
 376	unsigned int dec_frame_status;
 377	struct s5p_mfc_buf *src_buf;
 378	unsigned int res_change;
 379
 380	dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 381				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 382	dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
 383				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 384	res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 385				& S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
 386				>> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
 387	mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
 388	if (ctx->state == MFCINST_RES_CHANGE_INIT)
 389		ctx->state = MFCINST_RES_CHANGE_FLUSH;
 390	if (res_change == S5P_FIMV_RES_INCREASE ||
 391		res_change == S5P_FIMV_RES_DECREASE) {
 392		ctx->state = MFCINST_RES_CHANGE_INIT;
 393		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 394		wake_up_ctx(ctx, reason, err);
 395		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 396		s5p_mfc_clock_off(dev);
 397		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 398		return;
 399	}
 400	if (ctx->dpb_flush_flag)
 401		ctx->dpb_flush_flag = 0;
 402
 403	/* All frames remaining in the buffer have been extracted  */
 404	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
 405		if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
 406			static const struct v4l2_event ev_src_ch = {
 407				.type = V4L2_EVENT_SOURCE_CHANGE,
 408				.u.src_change.changes =
 409					V4L2_EVENT_SRC_CH_RESOLUTION,
 410			};
 411
 412			s5p_mfc_handle_frame_all_extracted(ctx);
 413			ctx->state = MFCINST_RES_CHANGE_END;
 414			v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
 415
 416			goto leave_handle_frame;
 417		} else {
 418			s5p_mfc_handle_frame_all_extracted(ctx);
 419		}
 420	}
 421
 422	if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
 423		s5p_mfc_handle_frame_copy_time(ctx);
 424
 425	/* A frame has been decoded and is in the buffer  */
 426	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
 427	    dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
 428		s5p_mfc_handle_frame_new(ctx, err);
 429	} else {
 430		mfc_debug(2, "No frame decode\n");
 431	}
 432	/* Mark source buffer as complete */
 433	if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
 434		&& !list_empty(&ctx->src_queue)) {
 435		src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
 436								list);
 437		ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
 438						get_consumed_stream, dev);
 439		if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
 440			ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
 441			ctx->consumed_stream + STUFF_BYTE <
 442			src_buf->b->vb2_buf.planes[0].bytesused) {
 443			/* Run MFC again on the same buffer */
 444			mfc_debug(2, "Running again the same buffer\n");
 445			ctx->after_packed_pb = 1;
 446		} else {
 447			mfc_debug(2, "MFC needs next buffer\n");
 448			ctx->consumed_stream = 0;
 449			if (src_buf->flags & MFC_BUF_FLAG_EOS)
 450				ctx->state = MFCINST_FINISHING;
 451			list_del(&src_buf->list);
 452			ctx->src_queue_cnt--;
 453			if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
 454				vb2_buffer_done(&src_buf->b->vb2_buf,
 455						VB2_BUF_STATE_ERROR);
 456			else
 457				vb2_buffer_done(&src_buf->b->vb2_buf,
 458						VB2_BUF_STATE_DONE);
 459		}
 460	}
 461leave_handle_frame:
 462	if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
 463				    || ctx->dst_queue_cnt < ctx->pb_count)
 464		clear_work_bit(ctx);
 465	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 466	wake_up_ctx(ctx, reason, err);
 467	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 468	s5p_mfc_clock_off(dev);
 469	/* if suspending, wake up device and do not try_run again*/
 470	if (test_bit(0, &dev->enter_suspend))
 471		wake_up_dev(dev, reason, err);
 472	else
 473		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 474}
 475
 476/* Error handling for interrupt */
 477static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
 478		struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
 479{
 480	mfc_err("Interrupt Error: %08x\n", err);
 481
 482	if (ctx) {
 483		/* Error recovery is dependent on the state of context */
 484		switch (ctx->state) {
 485		case MFCINST_RES_CHANGE_INIT:
 486		case MFCINST_RES_CHANGE_FLUSH:
 487		case MFCINST_RES_CHANGE_END:
 488		case MFCINST_FINISHING:
 489		case MFCINST_FINISHED:
 490		case MFCINST_RUNNING:
 491			/*
 492			 * It is highly probable that an error occurred
 493			 * while decoding a frame
 494			 */
 495			clear_work_bit(ctx);
 496			ctx->state = MFCINST_ERROR;
 497			/* Mark all dst buffers as having an error */
 498			s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
 499			/* Mark all src buffers as having an error */
 500			s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
 501			wake_up_ctx(ctx, reason, err);
 502			break;
 503		default:
 504			clear_work_bit(ctx);
 505			ctx->state = MFCINST_ERROR;
 506			wake_up_ctx(ctx, reason, err);
 507			break;
 508		}
 509	}
 510	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 511	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 512	s5p_mfc_clock_off(dev);
 513	wake_up_dev(dev, reason, err);
 514}
 515
 516/* Header parsing interrupt handling */
 517static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
 518				 unsigned int reason, unsigned int err)
 519{
 520	struct s5p_mfc_dev *dev;
 521
 522	if (!ctx)
 523		return;
 524	dev = ctx->dev;
 525	if (ctx->c_ops->post_seq_start) {
 526		if (ctx->c_ops->post_seq_start(ctx))
 527			mfc_err("post_seq_start() failed\n");
 528	} else {
 529		ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
 530				dev);
 531		ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
 532				dev);
 533
 534		s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
 535
 536		ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
 537				dev);
 538		ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
 539				dev);
 540		if (FW_HAS_E_MIN_SCRATCH_BUF(dev))
 541			ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
 542						get_min_scratch_buf_size, dev);
 543		if (ctx->img_width == 0 || ctx->img_height == 0)
 544			ctx->state = MFCINST_ERROR;
 545		else
 546			ctx->state = MFCINST_HEAD_PARSED;
 547
 548		if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 549			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
 550				!list_empty(&ctx->src_queue)) {
 551			struct s5p_mfc_buf *src_buf;
 552
 553			src_buf = list_entry(ctx->src_queue.next,
 554					struct s5p_mfc_buf, list);
 555			if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
 556						dev) <
 557					src_buf->b->vb2_buf.planes[0].bytesused)
 558				ctx->head_processed = 0;
 559			else
 560				ctx->head_processed = 1;
 561		} else {
 562			ctx->head_processed = 1;
 563		}
 564	}
 565	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 566	clear_work_bit(ctx);
 567	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 568	s5p_mfc_clock_off(dev);
 569	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 570	wake_up_ctx(ctx, reason, err);
 571}
 572
 573/* Header parsing interrupt handling */
 574static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
 575				 unsigned int reason, unsigned int err)
 576{
 577	struct s5p_mfc_buf *src_buf;
 578	struct s5p_mfc_dev *dev;
 579
 580	if (!ctx)
 581		return;
 582	dev = ctx->dev;
 583	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 584	ctx->int_type = reason;
 585	ctx->int_err = err;
 586	ctx->int_cond = 1;
 587	clear_work_bit(ctx);
 588	if (err == 0) {
 589		ctx->state = MFCINST_RUNNING;
 590		if (!ctx->dpb_flush_flag && ctx->head_processed) {
 591			if (!list_empty(&ctx->src_queue)) {
 592				src_buf = list_entry(ctx->src_queue.next,
 593					     struct s5p_mfc_buf, list);
 594				list_del(&src_buf->list);
 595				ctx->src_queue_cnt--;
 596				vb2_buffer_done(&src_buf->b->vb2_buf,
 597						VB2_BUF_STATE_DONE);
 598			}
 599		} else {
 600			ctx->dpb_flush_flag = 0;
 601		}
 602		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 603
 604		s5p_mfc_clock_off(dev);
 605
 606		wake_up(&ctx->queue);
 607		if (ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
 608			set_work_bit_irqsave(ctx);
 609		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 610	} else {
 611		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 612
 613		s5p_mfc_clock_off(dev);
 614
 615		wake_up(&ctx->queue);
 616	}
 617}
 618
 619static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
 620{
 621	struct s5p_mfc_dev *dev = ctx->dev;
 622	struct s5p_mfc_buf *mb_entry;
 623
 624	mfc_debug(2, "Stream completed\n");
 625
 626	ctx->state = MFCINST_FINISHED;
 627
 628	if (!list_empty(&ctx->dst_queue)) {
 629		mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
 630									list);
 631		list_del(&mb_entry->list);
 632		ctx->dst_queue_cnt--;
 633		vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
 634		vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
 635	}
 636
 637	clear_work_bit(ctx);
 638
 639	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 640
 641	s5p_mfc_clock_off(dev);
 642	wake_up(&ctx->queue);
 643	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 644}
 645
 646/* Interrupt processing */
 647static irqreturn_t s5p_mfc_irq(int irq, void *priv)
 648{
 649	struct s5p_mfc_dev *dev = priv;
 650	struct s5p_mfc_ctx *ctx;
 651	unsigned int reason;
 652	unsigned int err;
 653
 654	mfc_debug_enter();
 655	/* Reset the timeout watchdog */
 656	atomic_set(&dev->watchdog_cnt, 0);
 657	spin_lock(&dev->irqlock);
 658	ctx = dev->ctx[dev->curr_ctx];
 659	/* Get the reason of interrupt and the error code */
 660	reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
 661	err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
 662	mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
 663	switch (reason) {
 664	case S5P_MFC_R2H_CMD_ERR_RET:
 665		/* An error has occurred */
 666		if (ctx->state == MFCINST_RUNNING &&
 667			(s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
 668				dev->warn_start ||
 669				err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
 670				err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
 671				err == S5P_FIMV_ERR_TIMEOUT))
 672			s5p_mfc_handle_frame(ctx, reason, err);
 673		else
 674			s5p_mfc_handle_error(dev, ctx, reason, err);
 675		clear_bit(0, &dev->enter_suspend);
 676		break;
 677
 678	case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
 679	case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
 680	case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
 681		if (ctx->c_ops->post_frame_start) {
 682			if (ctx->c_ops->post_frame_start(ctx))
 683				mfc_err("post_frame_start() failed\n");
 684
 685			if (ctx->state == MFCINST_FINISHING &&
 686						list_empty(&ctx->ref_queue)) {
 687				s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 688				s5p_mfc_handle_stream_complete(ctx);
 689				break;
 690			}
 691			s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 692			WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 693			s5p_mfc_clock_off(dev);
 694			wake_up_ctx(ctx, reason, err);
 695			s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 696		} else {
 697			s5p_mfc_handle_frame(ctx, reason, err);
 698		}
 699		break;
 700
 701	case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
 702		s5p_mfc_handle_seq_done(ctx, reason, err);
 703		break;
 704
 705	case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
 706		ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
 707		ctx->state = MFCINST_GOT_INST;
 708		goto irq_cleanup_hw;
 709
 710	case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
 711		ctx->inst_no = MFC_NO_INSTANCE_SET;
 712		ctx->state = MFCINST_FREE;
 713		goto irq_cleanup_hw;
 714
 715	case S5P_MFC_R2H_CMD_SYS_INIT_RET:
 716	case S5P_MFC_R2H_CMD_FW_STATUS_RET:
 717	case S5P_MFC_R2H_CMD_SLEEP_RET:
 718	case S5P_MFC_R2H_CMD_WAKEUP_RET:
 719		if (ctx)
 720			clear_work_bit(ctx);
 721		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 722		clear_bit(0, &dev->hw_lock);
 723		clear_bit(0, &dev->enter_suspend);
 724		wake_up_dev(dev, reason, err);
 725		break;
 726
 727	case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
 728		s5p_mfc_handle_init_buffers(ctx, reason, err);
 729		break;
 730
 731	case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
 732		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 733		ctx->int_type = reason;
 734		ctx->int_err = err;
 735		s5p_mfc_handle_stream_complete(ctx);
 736		break;
 737
 738	case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
 739		ctx->state = MFCINST_RUNNING;
 740		goto irq_cleanup_hw;
 741
 742	case S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET:
 743		ctx->state = MFCINST_NAL_ABORT;
 744		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 745		set_work_bit(ctx);
 746		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 747		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 748		break;
 749
 750	case S5P_MFC_R2H_CMD_NAL_ABORT_RET:
 751		ctx->state = MFCINST_ERROR;
 752		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
 753		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
 754		goto irq_cleanup_hw;
 755
 756	default:
 757		mfc_debug(2, "Unknown int reason\n");
 758		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 759	}
 760	spin_unlock(&dev->irqlock);
 761	mfc_debug_leave();
 762	return IRQ_HANDLED;
 763irq_cleanup_hw:
 764	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
 765	ctx->int_type = reason;
 766	ctx->int_err = err;
 767	ctx->int_cond = 1;
 768	if (test_and_clear_bit(0, &dev->hw_lock) == 0)
 769		mfc_err("Failed to unlock hw\n");
 770
 771	s5p_mfc_clock_off(dev);
 772	clear_work_bit(ctx);
 773	wake_up(&ctx->queue);
 774
 775	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 776	spin_unlock(&dev->irqlock);
 777	mfc_debug(2, "Exit via irq_cleanup_hw\n");
 778	return IRQ_HANDLED;
 779}
 780
 781/* Open an MFC node */
 782static int s5p_mfc_open(struct file *file)
 783{
 784	struct video_device *vdev = video_devdata(file);
 785	struct s5p_mfc_dev *dev = video_drvdata(file);
 786	struct s5p_mfc_ctx *ctx = NULL;
 787	struct vb2_queue *q;
 788	int ret = 0;
 789
 790	mfc_debug_enter();
 791	if (mutex_lock_interruptible(&dev->mfc_mutex)) {
 792		ret = -ERESTARTSYS;
 793		goto err_enter;
 794	}
 795	dev->num_inst++;	/* It is guarded by mfc_mutex in vfd */
 796	/* Allocate memory for context */
 797	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 798	if (!ctx) {
 799		ret = -ENOMEM;
 800		goto err_alloc;
 801	}
 802	init_waitqueue_head(&ctx->queue);
 803	v4l2_fh_init(&ctx->fh, vdev);
 804	v4l2_fh_add(&ctx->fh, file);
 805	ctx->dev = dev;
 806	INIT_LIST_HEAD(&ctx->src_queue);
 807	INIT_LIST_HEAD(&ctx->dst_queue);
 808	ctx->src_queue_cnt = 0;
 809	ctx->dst_queue_cnt = 0;
 810	ctx->is_422 = 0;
 811	ctx->is_10bit = 0;
 812	/* Get context number */
 813	ctx->num = 0;
 814	while (dev->ctx[ctx->num]) {
 815		ctx->num++;
 816		if (ctx->num >= MFC_NUM_CONTEXTS) {
 817			mfc_debug(2, "Too many open contexts\n");
 818			ret = -EBUSY;
 819			goto err_no_ctx;
 820		}
 821	}
 822	/* Mark context as idle */
 823	clear_work_bit_irqsave(ctx);
 824	dev->ctx[ctx->num] = ctx;
 825	if (vdev == dev->vfd_dec) {
 826		ctx->type = MFCINST_DECODER;
 827		ctx->c_ops = get_dec_codec_ops();
 828		s5p_mfc_dec_init(ctx);
 829		/* Setup ctrl handler */
 830		ret = s5p_mfc_dec_ctrls_setup(ctx);
 831		if (ret) {
 832			mfc_err("Failed to setup mfc controls\n");
 833			goto err_ctrls_setup;
 834		}
 835	} else if (vdev == dev->vfd_enc) {
 836		ctx->type = MFCINST_ENCODER;
 837		ctx->c_ops = get_enc_codec_ops();
 838		/* only for encoder */
 839		INIT_LIST_HEAD(&ctx->ref_queue);
 840		ctx->ref_queue_cnt = 0;
 841		s5p_mfc_enc_init(ctx);
 842		/* Setup ctrl handler */
 843		ret = s5p_mfc_enc_ctrls_setup(ctx);
 844		if (ret) {
 845			mfc_err("Failed to setup mfc controls\n");
 846			goto err_ctrls_setup;
 847		}
 848	} else {
 849		ret = -ENOENT;
 850		goto err_bad_node;
 851	}
 852	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
 853	ctx->inst_no = MFC_NO_INSTANCE_SET;
 854	/* Load firmware if this is the first instance */
 855	if (dev->num_inst == 1) {
 856		dev->watchdog_timer.expires = jiffies +
 857					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 858		add_timer(&dev->watchdog_timer);
 859		ret = s5p_mfc_power_on(dev);
 860		if (ret < 0) {
 861			mfc_err("power on failed\n");
 862			goto err_pwr_enable;
 863		}
 864		s5p_mfc_clock_on(dev);
 865		ret = s5p_mfc_load_firmware(dev);
 866		if (ret) {
 867			s5p_mfc_clock_off(dev);
 868			goto err_load_fw;
 869		}
 870		/* Init the FW */
 871		ret = s5p_mfc_init_hw(dev);
 872		s5p_mfc_clock_off(dev);
 873		if (ret)
 874			goto err_init_hw;
 875	}
 876	/* Init videobuf2 queue for CAPTURE */
 877	q = &ctx->vq_dst;
 878	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 879	q->drv_priv = ctx;
 880	q->lock = &dev->mfc_mutex;
 881	if (vdev == dev->vfd_dec) {
 882		q->io_modes = VB2_MMAP;
 883		q->ops = get_dec_queue_ops();
 884	} else if (vdev == dev->vfd_enc) {
 885		q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
 886		q->ops = get_enc_queue_ops();
 887	} else {
 888		ret = -ENOENT;
 889		goto err_queue_init;
 890	}
 891	/*
 892	 * We'll do mostly sequential access, so sacrifice TLB efficiency for
 893	 * faster allocation.
 894	 */
 895	q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
 896	q->mem_ops = &vb2_dma_contig_memops;
 897	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 898	ret = vb2_queue_init(q);
 899	if (ret) {
 900		mfc_err("Failed to initialize videobuf2 queue(capture)\n");
 901		goto err_queue_init;
 902	}
 903	/* Init videobuf2 queue for OUTPUT */
 904	q = &ctx->vq_src;
 905	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
 906	q->drv_priv = ctx;
 907	q->lock = &dev->mfc_mutex;
 908	if (vdev == dev->vfd_dec) {
 909		q->io_modes = VB2_MMAP;
 910		q->ops = get_dec_queue_ops();
 911	} else if (vdev == dev->vfd_enc) {
 912		q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
 913		q->ops = get_enc_queue_ops();
 914	} else {
 915		ret = -ENOENT;
 916		goto err_queue_init;
 917	}
 918	/* One way to indicate end-of-stream for MFC is to set the
 919	 * bytesused == 0. However by default videobuf2 handles bytesused
 920	 * equal to 0 as a special case and changes its value to the size
 921	 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
 922	 * will keep the value of bytesused intact.
 923	 */
 924	q->allow_zero_bytesused = 1;
 925
 926	/*
 927	 * We'll do mostly sequential access, so sacrifice TLB efficiency for
 928	 * faster allocation.
 929	 */
 930	q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
 931	q->mem_ops = &vb2_dma_contig_memops;
 932	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 933	ret = vb2_queue_init(q);
 934	if (ret) {
 935		mfc_err("Failed to initialize videobuf2 queue(output)\n");
 936		goto err_queue_init;
 937	}
 938	mutex_unlock(&dev->mfc_mutex);
 939	mfc_debug_leave();
 940	return ret;
 941	/* Deinit when failure occurred */
 942err_queue_init:
 943	if (dev->num_inst == 1)
 944		s5p_mfc_deinit_hw(dev);
 945err_init_hw:
 946err_load_fw:
 947err_pwr_enable:
 948	if (dev->num_inst == 1) {
 949		if (s5p_mfc_power_off(dev) < 0)
 950			mfc_err("power off failed\n");
 951		timer_delete_sync(&dev->watchdog_timer);
 952	}
 953err_ctrls_setup:
 954	s5p_mfc_dec_ctrls_delete(ctx);
 955err_bad_node:
 956	dev->ctx[ctx->num] = NULL;
 957err_no_ctx:
 958	v4l2_fh_del(&ctx->fh, file);
 959	v4l2_fh_exit(&ctx->fh);
 960	kfree(ctx);
 961err_alloc:
 962	dev->num_inst--;
 963	mutex_unlock(&dev->mfc_mutex);
 964err_enter:
 965	mfc_debug_leave();
 966	return ret;
 967}
 968
 969/* Release MFC context */
 970static int s5p_mfc_release(struct file *file)
 971{
 972	struct s5p_mfc_ctx *ctx = file_to_ctx(file);
 973	struct s5p_mfc_dev *dev = ctx->dev;
 974
 975	/* if dev is null, do cleanup that doesn't need dev */
 976	mfc_debug_enter();
 977	if (dev)
 978		mutex_lock(&dev->mfc_mutex);
 979	vb2_queue_release(&ctx->vq_src);
 980	vb2_queue_release(&ctx->vq_dst);
 981	if (dev) {
 982		s5p_mfc_clock_on(dev);
 983
 984		/* Mark context as idle */
 985		clear_work_bit_irqsave(ctx);
 986		/*
 987		 * If instance was initialised and not yet freed,
 988		 * return instance and free resources
 989		 */
 990		if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
 991			mfc_debug(2, "Has to free instance\n");
 992			s5p_mfc_close_mfc_inst(dev, ctx);
 993		}
 994		/* hardware locking scheme */
 995		if (dev->curr_ctx == ctx->num)
 996			clear_bit(0, &dev->hw_lock);
 997		dev->num_inst--;
 998		if (dev->num_inst == 0) {
 999			mfc_debug(2, "Last instance\n");
1000			s5p_mfc_deinit_hw(dev);
1001			timer_delete_sync(&dev->watchdog_timer);
1002			s5p_mfc_clock_off(dev);
1003			if (s5p_mfc_power_off(dev) < 0)
1004				mfc_err("Power off failed\n");
1005		} else {
1006			mfc_debug(2, "Shutting down clock\n");
1007			s5p_mfc_clock_off(dev);
1008		}
1009	}
1010	if (dev)
1011		dev->ctx[ctx->num] = NULL;
1012	s5p_mfc_dec_ctrls_delete(ctx);
1013	v4l2_fh_del(&ctx->fh, file);
1014	/* vdev is gone if dev is null */
1015	if (dev)
1016		v4l2_fh_exit(&ctx->fh);
1017	kfree(ctx);
1018	mfc_debug_leave();
1019	if (dev)
1020		mutex_unlock(&dev->mfc_mutex);
1021
1022	return 0;
1023}
1024
1025/* Poll */
1026static __poll_t s5p_mfc_poll(struct file *file,
1027				 struct poll_table_struct *wait)
1028{
1029	struct s5p_mfc_ctx *ctx = file_to_ctx(file);
1030	struct s5p_mfc_dev *dev = ctx->dev;
1031	struct vb2_queue *src_q, *dst_q;
1032	struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
1033	__poll_t rc = 0;
1034	unsigned long flags;
1035
1036	mutex_lock(&dev->mfc_mutex);
1037	src_q = &ctx->vq_src;
1038	dst_q = &ctx->vq_dst;
1039	/*
1040	 * There has to be at least one buffer queued on each queued_list, which
1041	 * means either in driver already or waiting for driver to claim it
1042	 * and start processing.
1043	 */
1044	if ((!vb2_is_streaming(src_q) || list_empty(&src_q->queued_list)) &&
1045	    (!vb2_is_streaming(dst_q) || list_empty(&dst_q->queued_list))) {
1046		rc = EPOLLERR;
1047		goto end;
1048	}
1049	mutex_unlock(&dev->mfc_mutex);
1050	poll_wait(file, &ctx->fh.wait, wait);
1051	poll_wait(file, &src_q->done_wq, wait);
1052	poll_wait(file, &dst_q->done_wq, wait);
1053	mutex_lock(&dev->mfc_mutex);
1054	if (v4l2_event_pending(&ctx->fh))
1055		rc |= EPOLLPRI;
1056	spin_lock_irqsave(&src_q->done_lock, flags);
1057	if (!list_empty(&src_q->done_list))
1058		src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1059								done_entry);
1060	if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1061				|| src_vb->state == VB2_BUF_STATE_ERROR))
1062		rc |= EPOLLOUT | EPOLLWRNORM;
1063	spin_unlock_irqrestore(&src_q->done_lock, flags);
1064	spin_lock_irqsave(&dst_q->done_lock, flags);
1065	if (!list_empty(&dst_q->done_list))
1066		dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1067								done_entry);
1068	if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1069				|| dst_vb->state == VB2_BUF_STATE_ERROR))
1070		rc |= EPOLLIN | EPOLLRDNORM;
1071	spin_unlock_irqrestore(&dst_q->done_lock, flags);
1072end:
1073	mutex_unlock(&dev->mfc_mutex);
1074	return rc;
1075}
1076
1077/* Mmap */
1078static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1079{
1080	struct s5p_mfc_ctx *ctx = file_to_ctx(file);
1081	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1082	int ret;
1083
1084	if (offset < DST_QUEUE_OFF_BASE) {
1085		mfc_debug(2, "mmapping source\n");
1086		ret = vb2_mmap(&ctx->vq_src, vma);
1087	} else {		/* capture */
1088		mfc_debug(2, "mmapping destination\n");
1089		vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1090		ret = vb2_mmap(&ctx->vq_dst, vma);
1091	}
1092	return ret;
1093}
1094
1095/* v4l2 ops */
1096static const struct v4l2_file_operations s5p_mfc_fops = {
1097	.owner = THIS_MODULE,
1098	.open = s5p_mfc_open,
1099	.release = s5p_mfc_release,
1100	.poll = s5p_mfc_poll,
1101	.unlocked_ioctl = video_ioctl2,
1102	.mmap = s5p_mfc_mmap,
1103};
1104
1105/* DMA memory related helper functions */
1106static void s5p_mfc_memdev_release(struct device *dev)
1107{
1108	of_reserved_mem_device_release(dev);
1109}
1110
1111static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1112					   const char *name, unsigned int idx)
1113{
1114	struct device *child;
1115	int ret;
1116
1117	child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL);
1118	if (!child)
1119		return NULL;
1120
1121	device_initialize(child);
1122	dev_set_name(child, "%s:%s", dev_name(dev), name);
1123	child->parent = dev;
1124	child->coherent_dma_mask = dev->coherent_dma_mask;
1125	child->dma_mask = dev->dma_mask;
1126	child->release = s5p_mfc_memdev_release;
1127	child->dma_parms = devm_kzalloc(dev, sizeof(*child->dma_parms),
1128					GFP_KERNEL);
1129	if (!child->dma_parms)
1130		goto err;
1131
1132	/*
1133	 * The memdevs are not proper OF platform devices, so in order for them
1134	 * to be treated as valid DMA masters we need a bit of a hack to force
1135	 * them to inherit the MFC node's DMA configuration.
1136	 */
1137	of_dma_configure(child, dev->of_node, true);
1138
1139	if (device_add(child) == 0) {
1140		ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1141							 idx);
1142		if (ret == 0)
1143			return child;
1144		device_del(child);
1145	}
1146err:
1147	put_device(child);
1148	return NULL;
1149}
1150
1151static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1152{
1153	struct device *dev = &mfc_dev->plat_dev->dev;
1154	void *bank2_virt;
1155	dma_addr_t bank2_dma_addr;
1156	unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1157	int ret;
1158
1159	/*
1160	 * Create and initialize virtual devices for accessing
1161	 * reserved memory regions.
1162	 */
1163	mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1164							   BANK_L_CTX);
1165	if (!mfc_dev->mem_dev[BANK_L_CTX])
1166		return -ENODEV;
1167	mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1168							   BANK_R_CTX);
1169	if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1170		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1171		return -ENODEV;
1172	}
1173
1174	/* Allocate memory for firmware and initialize both banks addresses */
1175	ret = s5p_mfc_alloc_firmware(mfc_dev);
1176	if (ret) {
1177		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1178		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1179		return ret;
1180	}
1181
1182	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1183
1184	bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1185				       align_size, &bank2_dma_addr, GFP_KERNEL);
1186	if (!bank2_virt) {
1187		s5p_mfc_release_firmware(mfc_dev);
1188		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1189		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1190		return -ENOMEM;
1191	}
1192
1193	/* Valid buffers passed to MFC encoder with LAST_FRAME command
1194	 * should not have address of bank2 - MFC will treat it as a null frame.
1195	 * To avoid such situation we set bank2 address below the pool address.
1196	 */
1197	mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1198
1199	dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1200			  bank2_dma_addr);
1201
1202	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1203					DMA_BIT_MASK(32));
1204	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1205					DMA_BIT_MASK(32));
1206
1207	return 0;
1208}
1209
1210static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1211{
1212	device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1213	device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1214	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1215	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1216}
1217
1218static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1219{
1220	struct device *dev = &mfc_dev->plat_dev->dev;
1221	unsigned long mem_size = SZ_4M;
1222
1223	if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1224		mem_size = SZ_8M;
1225
1226	if (mfc_mem_size)
1227		mem_size = memparse(mfc_mem_size, NULL);
1228
1229	mfc_dev->mem_bitmap = bitmap_zalloc(mem_size >> PAGE_SHIFT, GFP_KERNEL);
1230	if (!mfc_dev->mem_bitmap)
1231		return -ENOMEM;
1232
1233	mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1234					       &mfc_dev->mem_base, GFP_KERNEL);
1235	if (!mfc_dev->mem_virt) {
1236		bitmap_free(mfc_dev->mem_bitmap);
1237		dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1238			(mem_size / SZ_1M));
1239		return -ENOMEM;
1240	}
1241	mfc_dev->mem_size = mem_size;
1242	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1243	mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1244
1245	/*
1246	 * MFC hardware cannot handle 0 as a base address, so mark first 128K
1247	 * as used (to keep required base alignment) and adjust base address
1248	 */
1249	if (mfc_dev->mem_base == (dma_addr_t)0) {
1250		unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1251
1252		bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1253		mfc_dev->dma_base[BANK_L_CTX] += offset;
1254		mfc_dev->dma_base[BANK_R_CTX] += offset;
1255	}
1256
1257	/* Firmware allocation cannot fail in this case */
1258	s5p_mfc_alloc_firmware(mfc_dev);
1259
1260	mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1261	vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1262
1263	dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1264		 (mem_size / SZ_1M));
1265
1266	return 0;
1267}
1268
1269static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1270{
1271	struct device *dev = &mfc_dev->plat_dev->dev;
1272
1273	dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1274			  mfc_dev->mem_base);
1275	bitmap_free(mfc_dev->mem_bitmap);
1276	vb2_dma_contig_clear_max_seg_size(dev);
1277}
1278
1279static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1280{
1281	struct device *dev = &mfc_dev->plat_dev->dev;
1282
1283	if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1284		return s5p_mfc_configure_common_memory(mfc_dev);
1285	else
1286		return s5p_mfc_configure_2port_memory(mfc_dev);
1287}
1288
1289static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1290{
1291	struct device *dev = &mfc_dev->plat_dev->dev;
1292
1293	s5p_mfc_release_firmware(mfc_dev);
1294	if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1295		s5p_mfc_unconfigure_common_memory(mfc_dev);
1296	else
1297		s5p_mfc_unconfigure_2port_memory(mfc_dev);
1298}
1299
1300/* MFC probe function */
1301static int s5p_mfc_probe(struct platform_device *pdev)
1302{
1303	struct s5p_mfc_dev *dev;
1304	struct video_device *vfd;
1305	int ret;
1306
1307	pr_debug("%s++\n", __func__);
1308	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1309	if (!dev)
1310		return -ENOMEM;
1311
1312	spin_lock_init(&dev->irqlock);
1313	spin_lock_init(&dev->condlock);
1314	dev->plat_dev = pdev;
1315	if (!dev->plat_dev) {
1316		mfc_err("No platform data specified\n");
1317		return -ENODEV;
1318	}
1319
1320	dev->variant = of_device_get_match_data(&pdev->dev);
1321	if (!dev->variant) {
1322		dev_err(&pdev->dev, "Failed to get device MFC hardware variant information\n");
1323		return -ENOENT;
1324	}
1325
1326	dev->regs_base = devm_platform_ioremap_resource(pdev, 0);
1327	if (IS_ERR(dev->regs_base))
1328		return PTR_ERR(dev->regs_base);
1329
1330	ret = platform_get_irq(pdev, 0);
1331	if (ret < 0)
1332		return ret;
1333	dev->irq = ret;
1334	ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1335					0, pdev->name, dev);
1336	if (ret) {
1337		dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1338		return ret;
1339	}
1340
1341	ret = s5p_mfc_configure_dma_memory(dev);
1342	if (ret < 0) {
1343		dev_err(&pdev->dev, "failed to configure DMA memory\n");
1344		return ret;
1345	}
1346
1347	ret = s5p_mfc_init_pm(dev);
1348	if (ret < 0) {
1349		dev_err(&pdev->dev, "failed to get mfc clock source\n");
1350		goto err_dma;
1351	}
1352
1353	/*
1354	 * Load fails if fs isn't mounted. Try loading anyway.
1355	 * _open() will load it, it fails now. Ignore failure.
1356	 */
1357	s5p_mfc_load_firmware(dev);
1358
1359	mutex_init(&dev->mfc_mutex);
1360	init_waitqueue_head(&dev->queue);
1361	dev->hw_lock = 0;
1362	INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1363	atomic_set(&dev->watchdog_cnt, 0);
1364	timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0);
1365
1366	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1367	if (ret)
1368		goto err_v4l2_dev_reg;
1369
1370	/* decoder */
1371	vfd = video_device_alloc();
1372	if (!vfd) {
1373		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1374		ret = -ENOMEM;
1375		goto err_dec_alloc;
1376	}
1377	vfd->fops	= &s5p_mfc_fops;
1378	vfd->ioctl_ops	= get_dec_v4l2_ioctl_ops();
1379	vfd->release	= video_device_release;
1380	vfd->lock	= &dev->mfc_mutex;
1381	vfd->v4l2_dev	= &dev->v4l2_dev;
1382	vfd->vfl_dir	= VFL_DIR_M2M;
1383	vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1384	set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags);
1385	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1386	dev->vfd_dec	= vfd;
1387	video_set_drvdata(vfd, dev);
1388
1389	/* encoder */
1390	vfd = video_device_alloc();
1391	if (!vfd) {
1392		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1393		ret = -ENOMEM;
1394		goto err_enc_alloc;
1395	}
1396	vfd->fops	= &s5p_mfc_fops;
1397	vfd->ioctl_ops	= get_enc_v4l2_ioctl_ops();
1398	vfd->release	= video_device_release;
1399	vfd->lock	= &dev->mfc_mutex;
1400	vfd->v4l2_dev	= &dev->v4l2_dev;
1401	vfd->vfl_dir	= VFL_DIR_M2M;
1402	vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1403	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1404	dev->vfd_enc	= vfd;
1405	video_set_drvdata(vfd, dev);
1406	platform_set_drvdata(pdev, dev);
1407
1408	/* Initialize HW ops and commands based on MFC version */
1409	s5p_mfc_init_hw_ops(dev);
1410	s5p_mfc_init_hw_cmds(dev);
1411	s5p_mfc_init_regs(dev);
1412
1413	/* Register decoder and encoder */
1414	ret = video_register_device(dev->vfd_dec, VFL_TYPE_VIDEO, 0);
1415	if (ret) {
1416		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1417		goto err_dec_reg;
1418	}
1419	v4l2_info(&dev->v4l2_dev,
1420		  "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1421
1422	ret = video_register_device(dev->vfd_enc, VFL_TYPE_VIDEO, 0);
1423	if (ret) {
1424		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1425		goto err_enc_reg;
1426	}
1427	v4l2_info(&dev->v4l2_dev,
1428		  "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1429
1430	pr_debug("%s--\n", __func__);
1431	return 0;
1432
1433/* Deinit MFC if probe had failed */
1434err_enc_reg:
1435	video_unregister_device(dev->vfd_dec);
1436	dev->vfd_dec = NULL;
1437err_dec_reg:
1438	video_device_release(dev->vfd_enc);
1439err_enc_alloc:
1440	video_device_release(dev->vfd_dec);
1441err_dec_alloc:
1442	v4l2_device_unregister(&dev->v4l2_dev);
1443err_v4l2_dev_reg:
1444	s5p_mfc_final_pm(dev);
1445err_dma:
1446	s5p_mfc_unconfigure_dma_memory(dev);
1447
1448	pr_debug("%s-- with error\n", __func__);
1449	return ret;
1450
1451}
1452
1453/* Remove the driver */
1454static void s5p_mfc_remove(struct platform_device *pdev)
1455{
1456	struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1457	struct s5p_mfc_ctx *ctx;
1458	int i;
1459
1460	v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1461
1462	/*
1463	 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1464	 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1465	 * after s5p_mfc_remove() is run during unbind.
1466	 */
1467	mutex_lock(&dev->mfc_mutex);
1468	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1469		ctx = dev->ctx[i];
1470		if (!ctx)
1471			continue;
1472		/* clear ctx->dev */
1473		ctx->dev = NULL;
1474	}
1475	mutex_unlock(&dev->mfc_mutex);
1476
1477	timer_delete_sync(&dev->watchdog_timer);
1478	flush_work(&dev->watchdog_work);
1479
1480	video_unregister_device(dev->vfd_enc);
1481	video_unregister_device(dev->vfd_dec);
1482	v4l2_device_unregister(&dev->v4l2_dev);
1483	s5p_mfc_unconfigure_dma_memory(dev);
1484
1485	s5p_mfc_final_pm(dev);
1486}
1487
1488#ifdef CONFIG_PM_SLEEP
1489
1490static int s5p_mfc_suspend(struct device *dev)
1491{
1492	struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1493	int ret;
1494
1495	if (m_dev->num_inst == 0)
1496		return 0;
1497
1498	if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1499		mfc_err("Error: going to suspend for a second time\n");
1500		return -EIO;
1501	}
1502
1503	/* Check if we're processing then wait if it necessary. */
1504	while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1505		/* Try and lock the HW */
1506		/* Wait on the interrupt waitqueue */
1507		ret = wait_event_interruptible_timeout(m_dev->queue,
1508			m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1509		if (ret == 0) {
1510			mfc_err("Waiting for hardware to finish timed out\n");
1511			clear_bit(0, &m_dev->enter_suspend);
1512			return -EIO;
1513		}
1514	}
1515
1516	ret = s5p_mfc_sleep(m_dev);
1517	if (ret) {
1518		clear_bit(0, &m_dev->enter_suspend);
1519		clear_bit(0, &m_dev->hw_lock);
1520	}
1521	return ret;
1522}
1523
1524static int s5p_mfc_resume(struct device *dev)
1525{
1526	struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1527
1528	if (m_dev->num_inst == 0)
1529		return 0;
1530	return s5p_mfc_wakeup(m_dev);
1531}
1532#endif
1533
1534/* Power management */
1535static const struct dev_pm_ops s5p_mfc_pm_ops = {
1536	SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1537};
1538
1539static const struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1540	.h264_ctx	= MFC_H264_CTX_BUF_SIZE,
1541	.non_h264_ctx	= MFC_CTX_BUF_SIZE,
1542	.dsc		= DESC_BUF_SIZE,
1543	.shm		= SHARED_BUF_SIZE,
1544};
1545
1546static const struct s5p_mfc_buf_size buf_size_v5 = {
1547	.fw	= MAX_FW_SIZE,
1548	.cpb	= MAX_CPB_SIZE,
1549	.priv	= &mfc_buf_size_v5,
1550};
1551
1552static const struct s5p_mfc_variant mfc_drvdata_v5 = {
1553	.version	= MFC_VERSION,
1554	.version_bit	= MFC_V5_BIT,
1555	.port_num	= MFC_NUM_PORTS,
1556	.buf_size	= &buf_size_v5,
1557	.fw_name[0]	= "s5p-mfc.fw",
1558	.clk_names	= {"mfc", "sclk_mfc"},
1559	.num_clocks	= 2,
1560	.use_clock_gating = true,
1561};
1562
1563static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1564	.dev_ctx	= MFC_CTX_BUF_SIZE_V6,
1565	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V6,
1566	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1567	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V6,
1568	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1569};
1570
1571static const struct s5p_mfc_buf_size buf_size_v6 = {
1572	.fw	= MAX_FW_SIZE_V6,
1573	.cpb	= MAX_CPB_SIZE_V6,
1574	.priv	= &mfc_buf_size_v6,
1575};
1576
1577static const struct s5p_mfc_variant mfc_drvdata_v6 = {
1578	.version	= MFC_VERSION_V6,
1579	.version_bit	= MFC_V6_BIT,
1580	.port_num	= MFC_NUM_PORTS_V6,
1581	.buf_size	= &buf_size_v6,
1582	.fw_name[0]     = "s5p-mfc-v6.fw",
1583	/*
1584	 * v6-v2 firmware contains bug fixes and interface change
1585	 * for init buffer command
1586	 */
1587	.fw_name[1]     = "s5p-mfc-v6-v2.fw",
1588	.clk_names	= {"mfc"},
1589	.num_clocks	= 1,
1590};
1591
1592static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1593	.dev_ctx	= MFC_CTX_BUF_SIZE_V7,
1594	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V7,
1595	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1596	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V7,
1597	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1598};
1599
1600static const struct s5p_mfc_buf_size buf_size_v7 = {
1601	.fw	= MAX_FW_SIZE_V7,
1602	.cpb	= MAX_CPB_SIZE_V7,
1603	.priv	= &mfc_buf_size_v7,
1604};
1605
1606static const struct s5p_mfc_variant mfc_drvdata_v7 = {
1607	.version	= MFC_VERSION_V7,
1608	.version_bit	= MFC_V7_BIT,
1609	.port_num	= MFC_NUM_PORTS_V7,
1610	.buf_size	= &buf_size_v7,
1611	.fw_name[0]     = "s5p-mfc-v7.fw",
1612	.clk_names	= {"mfc"},
1613	.num_clocks	= 1,
1614};
1615
1616static const struct s5p_mfc_variant mfc_drvdata_v7_3250 = {
1617	.version        = MFC_VERSION_V7,
1618	.version_bit    = MFC_V7_BIT,
1619	.port_num       = MFC_NUM_PORTS_V7,
1620	.buf_size       = &buf_size_v7,
1621	.fw_name[0]     = "s5p-mfc-v7.fw",
1622	.clk_names      = {"mfc", "sclk_mfc"},
1623	.num_clocks     = 2,
1624};
1625
1626static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1627	.dev_ctx	= MFC_CTX_BUF_SIZE_V8,
1628	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V8,
1629	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1630	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V8,
1631	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1632};
1633
1634static const struct s5p_mfc_buf_size buf_size_v8 = {
1635	.fw	= MAX_FW_SIZE_V8,
1636	.cpb	= MAX_CPB_SIZE_V8,
1637	.priv	= &mfc_buf_size_v8,
1638};
1639
1640static const struct s5p_mfc_variant mfc_drvdata_v8 = {
1641	.version	= MFC_VERSION_V8,
1642	.version_bit	= MFC_V8_BIT,
1643	.port_num	= MFC_NUM_PORTS_V8,
1644	.buf_size	= &buf_size_v8,
1645	.fw_name[0]     = "s5p-mfc-v8.fw",
1646	.clk_names	= {"mfc"},
1647	.num_clocks	= 1,
1648};
1649
1650static const struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1651	.version	= MFC_VERSION_V8,
1652	.version_bit	= MFC_V8_BIT,
1653	.port_num	= MFC_NUM_PORTS_V8,
1654	.buf_size	= &buf_size_v8,
1655	.fw_name[0]     = "s5p-mfc-v8.fw",
1656	.clk_names	= {"pclk", "aclk", "aclk_xiu"},
1657	.num_clocks	= 3,
1658};
1659
1660static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
1661	.dev_ctx        = MFC_CTX_BUF_SIZE_V10,
1662	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
1663	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
1664	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
1665	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
1666	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
1667};
1668
1669static const struct s5p_mfc_buf_size buf_size_v10 = {
1670	.fw     = MAX_FW_SIZE_V10,
1671	.cpb    = MAX_CPB_SIZE_V10,
1672	.priv   = &mfc_buf_size_v10,
1673};
1674
1675static const struct s5p_mfc_variant mfc_drvdata_v10 = {
1676	.version        = MFC_VERSION_V10,
1677	.version_bit    = MFC_V10_BIT,
1678	.port_num       = MFC_NUM_PORTS_V10,
1679	.buf_size       = &buf_size_v10,
1680	.fw_name[0]     = "s5p-mfc-v10.fw",
1681};
1682
1683static struct s5p_mfc_buf_size_v6 mfc_buf_size_v12 = {
1684	.dev_ctx        = MFC_CTX_BUF_SIZE_V12,
1685	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V12,
1686	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V12,
1687	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V12,
1688	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V12,
1689	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V12,
1690};
1691
1692static struct s5p_mfc_buf_size buf_size_v12 = {
1693	.fw     = MAX_FW_SIZE_V12,
1694	.cpb    = MAX_CPB_SIZE_V12,
1695	.priv   = &mfc_buf_size_v12,
1696};
1697
1698static struct s5p_mfc_variant mfc_drvdata_v12 = {
1699	.version        = MFC_VERSION_V12,
1700	.version_bit    = MFC_V12_BIT,
1701	.port_num       = MFC_NUM_PORTS_V12,
1702	.buf_size       = &buf_size_v12,
1703	.fw_name[0]     = "s5p-mfc-v12.fw",
1704	.clk_names	= {"mfc"},
1705	.num_clocks	= 1,
1706};
1707
1708static const struct of_device_id exynos_mfc_match[] = {
1709	{
1710		.compatible = "samsung,mfc-v5",
1711		.data = &mfc_drvdata_v5,
1712	}, {
1713		.compatible = "samsung,mfc-v6",
1714		.data = &mfc_drvdata_v6,
1715	}, {
1716		.compatible = "samsung,mfc-v7",
1717		.data = &mfc_drvdata_v7,
1718	}, {
1719		.compatible = "samsung,exynos3250-mfc",
1720		.data = &mfc_drvdata_v7_3250,
1721	}, {
1722		.compatible = "samsung,mfc-v8",
1723		.data = &mfc_drvdata_v8,
1724	}, {
1725		.compatible = "samsung,exynos5433-mfc",
1726		.data = &mfc_drvdata_v8_5433,
1727	}, {
1728		.compatible = "samsung,mfc-v10",
1729		.data = &mfc_drvdata_v10,
1730	}, {
1731		.compatible = "tesla,fsd-mfc",
1732		.data = &mfc_drvdata_v12,
1733	},
1734	{},
1735};
1736MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1737
1738static struct platform_driver s5p_mfc_driver = {
1739	.probe		= s5p_mfc_probe,
1740	.remove		= s5p_mfc_remove,
1741	.driver	= {
1742		.name	= S5P_MFC_NAME,
1743		.pm	= &s5p_mfc_pm_ops,
1744		.of_match_table = exynos_mfc_match,
1745	},
1746};
1747
1748module_platform_driver(s5p_mfc_driver);
1749
1750MODULE_LICENSE("GPL");
1751MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1752MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1753