fimc-is-param.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
   4 *
   5 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
   6 *
   7 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
   8 *	    Sylwester Nawrocki <s.nawrocki@samsung.com>
   9 */
  10#ifndef FIMC_IS_PARAM_H_
  11#define FIMC_IS_PARAM_H_
  12
  13#include <linux/compiler.h>
  14
  15#define FIMC_IS_CONFIG_TIMEOUT		3000 /* ms */
  16#define IS_DEFAULT_WIDTH		1280
  17#define IS_DEFAULT_HEIGHT		720
  18
  19#define DEFAULT_PREVIEW_STILL_WIDTH	IS_DEFAULT_WIDTH
  20#define DEFAULT_PREVIEW_STILL_HEIGHT	IS_DEFAULT_HEIGHT
  21#define DEFAULT_CAPTURE_STILL_WIDTH	IS_DEFAULT_WIDTH
  22#define DEFAULT_CAPTURE_STILL_HEIGHT	IS_DEFAULT_HEIGHT
  23#define DEFAULT_PREVIEW_VIDEO_WIDTH	IS_DEFAULT_WIDTH
  24#define DEFAULT_PREVIEW_VIDEO_HEIGHT	IS_DEFAULT_HEIGHT
  25#define DEFAULT_CAPTURE_VIDEO_WIDTH	IS_DEFAULT_WIDTH
  26#define DEFAULT_CAPTURE_VIDEO_HEIGHT	IS_DEFAULT_HEIGHT
  27
  28#define DEFAULT_PREVIEW_STILL_FRAMERATE	30
  29#define DEFAULT_CAPTURE_STILL_FRAMERATE	15
  30#define DEFAULT_PREVIEW_VIDEO_FRAMERATE	30
  31#define DEFAULT_CAPTURE_VIDEO_FRAMERATE	30
  32
  33#define FIMC_IS_REGION_VER		124 /* IS REGION VERSION 1.24 */
  34#define FIMC_IS_PARAM_SIZE		(FIMC_IS_REGION_SIZE + 1)
  35#define FIMC_IS_MAGIC_NUMBER		0x01020304
  36#define FIMC_IS_PARAM_MAX_SIZE		64 /* in bytes */
  37#define FIMC_IS_PARAM_MAX_ENTRIES	(FIMC_IS_PARAM_MAX_SIZE / 4)
  38
  39/* The parameter bitmask bit definitions. */
  40enum is_param_bit {
  41	PARAM_GLOBAL_SHOTMODE,
  42	PARAM_SENSOR_CONTROL,
  43	PARAM_SENSOR_OTF_OUTPUT,
  44	PARAM_SENSOR_FRAME_RATE,
  45	PARAM_BUFFER_CONTROL,
  46	PARAM_BUFFER_OTF_INPUT,
  47	PARAM_BUFFER_OTF_OUTPUT,
  48	PARAM_ISP_CONTROL,
  49	PARAM_ISP_OTF_INPUT,
  50	PARAM_ISP_DMA1_INPUT,
  51	/* 10 */
  52	PARAM_ISP_DMA2_INPUT,
  53	PARAM_ISP_AA,
  54	PARAM_ISP_FLASH,
  55	PARAM_ISP_AWB,
  56	PARAM_ISP_IMAGE_EFFECT,
  57	PARAM_ISP_ISO,
  58	PARAM_ISP_ADJUST,
  59	PARAM_ISP_METERING,
  60	PARAM_ISP_AFC,
  61	PARAM_ISP_OTF_OUTPUT,
  62	/* 20 */
  63	PARAM_ISP_DMA1_OUTPUT,
  64	PARAM_ISP_DMA2_OUTPUT,
  65	PARAM_DRC_CONTROL,
  66	PARAM_DRC_OTF_INPUT,
  67	PARAM_DRC_DMA_INPUT,
  68	PARAM_DRC_OTF_OUTPUT,
  69	PARAM_SCALERC_CONTROL,
  70	PARAM_SCALERC_OTF_INPUT,
  71	PARAM_SCALERC_IMAGE_EFFECT,
  72	PARAM_SCALERC_INPUT_CROP,
  73	/* 30 */
  74	PARAM_SCALERC_OUTPUT_CROP,
  75	PARAM_SCALERC_OTF_OUTPUT,
  76	PARAM_SCALERC_DMA_OUTPUT,
  77	PARAM_ODC_CONTROL,
  78	PARAM_ODC_OTF_INPUT,
  79	PARAM_ODC_OTF_OUTPUT,
  80	PARAM_DIS_CONTROL,
  81	PARAM_DIS_OTF_INPUT,
  82	PARAM_DIS_OTF_OUTPUT,
  83	PARAM_TDNR_CONTROL,
  84	/* 40 */
  85	PARAM_TDNR_OTF_INPUT,
  86	PARAM_TDNR_1ST_FRAME,
  87	PARAM_TDNR_OTF_OUTPUT,
  88	PARAM_TDNR_DMA_OUTPUT,
  89	PARAM_SCALERP_CONTROL,
  90	PARAM_SCALERP_OTF_INPUT,
  91	PARAM_SCALERP_IMAGE_EFFECT,
  92	PARAM_SCALERP_INPUT_CROP,
  93	PARAM_SCALERP_OUTPUT_CROP,
  94	PARAM_SCALERP_ROTATION,
  95	/* 50 */
  96	PARAM_SCALERP_FLIP,
  97	PARAM_SCALERP_OTF_OUTPUT,
  98	PARAM_SCALERP_DMA_OUTPUT,
  99	PARAM_FD_CONTROL,
 100	PARAM_FD_OTF_INPUT,
 101	PARAM_FD_DMA_INPUT,
 102	PARAM_FD_CONFIG,
 103};
 104
 105/* Interrupt map */
 106#define	FIMC_IS_INT_GENERAL			0
 107#define	FIMC_IS_INT_FRAME_DONE_ISP		1
 108
 109/* Input */
 110
 111#define CONTROL_COMMAND_STOP			0
 112#define CONTROL_COMMAND_START			1
 113
 114#define CONTROL_BYPASS_DISABLE			0
 115#define CONTROL_BYPASS_ENABLE			1
 116
 117#define CONTROL_ERROR_NONE			0
 118
 119/* OTF (On-The-Fly) input interface commands */
 120#define OTF_INPUT_COMMAND_DISABLE		0
 121#define OTF_INPUT_COMMAND_ENABLE		1
 122
 123/* OTF input interface color formats */
 124enum oft_input_fmt {
 125	OTF_INPUT_FORMAT_BAYER			= 0, /* 1 channel */
 126	OTF_INPUT_FORMAT_YUV444			= 1, /* 3 channels */
 127	OTF_INPUT_FORMAT_YUV422			= 2, /* 3 channels */
 128	OTF_INPUT_FORMAT_YUV420			= 3, /* 3 channels */
 129	OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER	= 10,
 130	OTF_INPUT_FORMAT_BAYER_DMA		= 11,
 131};
 132
 133#define OTF_INPUT_ORDER_BAYER_GR_BG		0
 134
 135/* OTF input error codes */
 136#define OTF_INPUT_ERROR_NONE			0 /* Input setting is done */
 137
 138/* DMA input commands */
 139#define DMA_INPUT_COMMAND_DISABLE		0
 140#define DMA_INPUT_COMMAND_ENABLE		1
 141
 142/* DMA input color formats */
 143enum dma_input_fmt {
 144	DMA_INPUT_FORMAT_BAYER			= 0,
 145	DMA_INPUT_FORMAT_YUV444			= 1,
 146	DMA_INPUT_FORMAT_YUV422			= 2,
 147	DMA_INPUT_FORMAT_YUV420			= 3,
 148};
 149
 150enum dma_input_order {
 151	/* (for DMA_INPUT_PLANE_3) */
 152	DMA_INPUT_ORDER_NO	= 0,
 153	/* (only valid at DMA_INPUT_PLANE_2) */
 154	DMA_INPUT_ORDER_CBCR	= 1,
 155	/* (only valid at DMA_INPUT_PLANE_2) */
 156	DMA_INPUT_ORDER_CRCB	= 2,
 157	/* (only valid at DMA_INPUT_PLANE_1 & DMA_INPUT_FORMAT_YUV444) */
 158	DMA_INPUT_ORDER_YCBCR	= 3,
 159	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 160	DMA_INPUT_ORDER_YYCBCR	= 4,
 161	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 162	DMA_INPUT_ORDER_YCBYCR	= 5,
 163	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 164	DMA_INPUT_ORDER_YCRYCB	= 6,
 165	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 166	DMA_INPUT_ORDER_CBYCRY	= 7,
 167	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 168	DMA_INPUT_ORDER_CRYCBY	= 8,
 169	/* (only valid at DMA_INPUT_FORMAT_BAYER) */
 170	DMA_INPUT_ORDER_GR_BG	= 9
 171};
 172
 173#define DMA_INPUT_ERROR_NONE			0 /* DMA input setting
 174						     is done */
 175/*
 176 * Data output parameter definitions
 177 */
 178#define OTF_OUTPUT_CROP_DISABLE			0
 179#define OTF_OUTPUT_CROP_ENABLE			1
 180
 181#define OTF_OUTPUT_COMMAND_DISABLE		0
 182#define OTF_OUTPUT_COMMAND_ENABLE		1
 183
 184enum otf_output_fmt {
 185	OTF_OUTPUT_FORMAT_YUV444		= 1,
 186	OTF_OUTPUT_FORMAT_YUV422		= 2,
 187	OTF_OUTPUT_FORMAT_YUV420		= 3,
 188	OTF_OUTPUT_FORMAT_RGB			= 4,
 189};
 190
 191#define OTF_OUTPUT_ORDER_BAYER_GR_BG		0
 192
 193#define OTF_OUTPUT_ERROR_NONE			0 /* Output Setting is done */
 194
 195#define DMA_OUTPUT_COMMAND_DISABLE		0
 196#define DMA_OUTPUT_COMMAND_ENABLE		1
 197
 198enum dma_output_fmt {
 199	DMA_OUTPUT_FORMAT_BAYER			= 0,
 200	DMA_OUTPUT_FORMAT_YUV444		= 1,
 201	DMA_OUTPUT_FORMAT_YUV422		= 2,
 202	DMA_OUTPUT_FORMAT_YUV420		= 3,
 203	DMA_OUTPUT_FORMAT_RGB			= 4,
 204};
 205
 206enum dma_output_order {
 207	DMA_OUTPUT_ORDER_NO		= 0,
 208	/* for DMA_OUTPUT_PLANE_3 */
 209	DMA_OUTPUT_ORDER_CBCR		= 1,
 210	/* only valid at DMA_INPUT_PLANE_2) */
 211	DMA_OUTPUT_ORDER_CRCB		= 2,
 212	/* only valid at DMA_OUTPUT_PLANE_2) */
 213	DMA_OUTPUT_ORDER_YYCBCR		= 3,
 214	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 215	DMA_OUTPUT_ORDER_YCBYCR		= 4,
 216	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 217	DMA_OUTPUT_ORDER_YCRYCB		= 5,
 218	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 219	DMA_OUTPUT_ORDER_CBYCRY		= 6,
 220	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 221	DMA_OUTPUT_ORDER_CRYCBY		= 7,
 222	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 223	DMA_OUTPUT_ORDER_YCBCR		= 8,
 224	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 225	DMA_OUTPUT_ORDER_CRYCB		= 9,
 226	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 227	DMA_OUTPUT_ORDER_CRCBY		= 10,
 228	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 229	DMA_OUTPUT_ORDER_CBYCR		= 11,
 230	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 231	DMA_OUTPUT_ORDER_YCRCB		= 12,
 232	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 233	DMA_OUTPUT_ORDER_CBCRY		= 13,
 234	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 235	DMA_OUTPUT_ORDER_BGR		= 14,
 236	/* only valid at DMA_OUTPUT_FORMAT_RGB */
 237	DMA_OUTPUT_ORDER_GB_BG		= 15
 238	/* only valid at DMA_OUTPUT_FORMAT_BAYER */
 239};
 240
 241/* enum dma_output_notify_dma_done */
 242#define DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE	0
 243#define DMA_OUTPUT_NOTIFY_DMA_DONE_ENABLE	1
 244
 245/* DMA output error codes */
 246#define DMA_OUTPUT_ERROR_NONE			0 /* DMA output setting
 247						     is done */
 248
 249/* ----------------------  Global  ----------------------------------- */
 250#define GLOBAL_SHOTMODE_ERROR_NONE		0 /* shot-mode setting
 251						     is done */
 252/* 3A lock commands */
 253#define ISP_AA_COMMAND_START			0
 254#define ISP_AA_COMMAND_STOP			1
 255
 256/* 3A lock target */
 257#define ISP_AA_TARGET_AF			1
 258#define ISP_AA_TARGET_AE			2
 259#define ISP_AA_TARGET_AWB			4
 260
 261enum isp_af_mode {
 262	ISP_AF_MODE_MANUAL			= 0,
 263	ISP_AF_MODE_SINGLE			= 1,
 264	ISP_AF_MODE_CONTINUOUS			= 2,
 265	ISP_AF_MODE_TOUCH			= 3,
 266	ISP_AF_MODE_SLEEP			= 4,
 267	ISP_AF_MODE_INIT			= 5,
 268	ISP_AF_MODE_SET_CENTER_WINDOW		= 6,
 269	ISP_AF_MODE_SET_TOUCH_WINDOW		= 7
 270};
 271
 272/* Face AF commands */
 273#define ISP_AF_FACE_DISABLE			0
 274#define ISP_AF_FACE_ENABLE			1
 275
 276/* AF range */
 277#define ISP_AF_RANGE_NORMAL			0
 278#define ISP_AF_RANGE_MACRO			1
 279
 280/* AF sleep */
 281#define ISP_AF_SLEEP_OFF			0
 282#define ISP_AF_SLEEP_ON				1
 283
 284/* Continuous AF commands */
 285#define ISP_AF_CONTINUOUS_DISABLE		0
 286#define ISP_AF_CONTINUOUS_ENABLE		1
 287
 288/* ISP AF error codes */
 289#define ISP_AF_ERROR_NONE			0 /* AF mode change is done */
 290#define ISP_AF_ERROR_NONE_LOCK_DONE		1 /* AF lock is done */
 291
 292/* Flash commands */
 293#define ISP_FLASH_COMMAND_DISABLE		0
 294#define ISP_FLASH_COMMAND_MANUAL_ON		1 /* (forced flash) */
 295#define ISP_FLASH_COMMAND_AUTO			2
 296#define ISP_FLASH_COMMAND_TORCH			3 /* 3 sec */
 297
 298/* Flash red-eye commands */
 299#define ISP_FLASH_REDEYE_DISABLE		0
 300#define ISP_FLASH_REDEYE_ENABLE			1
 301
 302/* Flash error codes */
 303#define ISP_FLASH_ERROR_NONE			0 /* Flash setting is done */
 304
 305/* --------------------------  AWB  ------------------------------------ */
 306enum isp_awb_command {
 307	ISP_AWB_COMMAND_AUTO			= 0,
 308	ISP_AWB_COMMAND_ILLUMINATION		= 1,
 309	ISP_AWB_COMMAND_MANUAL			= 2
 310};
 311
 312enum isp_awb_illumination {
 313	ISP_AWB_ILLUMINATION_DAYLIGHT		= 0,
 314	ISP_AWB_ILLUMINATION_CLOUDY		= 1,
 315	ISP_AWB_ILLUMINATION_TUNGSTEN		= 2,
 316	ISP_AWB_ILLUMINATION_FLUORESCENT	= 3
 317};
 318
 319/* ISP AWN error codes */
 320#define ISP_AWB_ERROR_NONE			0 /* AWB setting is done */
 321
 322/* --------------------------  Effect  ----------------------------------- */
 323enum isp_imageeffect_command {
 324	ISP_IMAGE_EFFECT_DISABLE		= 0,
 325	ISP_IMAGE_EFFECT_MONOCHROME		= 1,
 326	ISP_IMAGE_EFFECT_NEGATIVE_MONO		= 2,
 327	ISP_IMAGE_EFFECT_NEGATIVE_COLOR		= 3,
 328	ISP_IMAGE_EFFECT_SEPIA			= 4
 329};
 330
 331/* Image effect error codes */
 332#define ISP_IMAGE_EFFECT_ERROR_NONE		0 /* Image effect setting
 333						     is done */
 334/* ISO commands */
 335#define ISP_ISO_COMMAND_AUTO			0
 336#define ISP_ISO_COMMAND_MANUAL			1
 337
 338/* ISO error codes */
 339#define ISP_ISO_ERROR_NONE			0 /* ISO setting is done */
 340
 341/* ISP adjust commands */
 342#define ISP_ADJUST_COMMAND_AUTO			(0 << 0)
 343#define ISP_ADJUST_COMMAND_MANUAL_CONTRAST	(1 << 0)
 344#define ISP_ADJUST_COMMAND_MANUAL_SATURATION	(1 << 1)
 345#define ISP_ADJUST_COMMAND_MANUAL_SHARPNESS	(1 << 2)
 346#define ISP_ADJUST_COMMAND_MANUAL_EXPOSURE	(1 << 3)
 347#define ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS	(1 << 4)
 348#define ISP_ADJUST_COMMAND_MANUAL_HUE		(1 << 5)
 349#define ISP_ADJUST_COMMAND_MANUAL_ALL		0x7f
 350
 351/* ISP adjustment error codes */
 352#define ISP_ADJUST_ERROR_NONE			0 /* Adjust setting is done */
 353
 354/*
 355 *  Exposure metering
 356 */
 357enum isp_metering_command {
 358	ISP_METERING_COMMAND_AVERAGE	= 0,
 359	ISP_METERING_COMMAND_SPOT	= 1,
 360	ISP_METERING_COMMAND_MATRIX	= 2,
 361	ISP_METERING_COMMAND_CENTER	= 3
 362};
 363
 364/* ISP metering error codes */
 365#define ISP_METERING_ERROR_NONE		0 /* Metering setting is done */
 366
 367/*
 368 * AFC
 369 */
 370enum isp_afc_command {
 371	ISP_AFC_COMMAND_DISABLE		= 0,
 372	ISP_AFC_COMMAND_AUTO		= 1,
 373	ISP_AFC_COMMAND_MANUAL		= 2,
 374};
 375
 376#define ISP_AFC_MANUAL_50HZ		50
 377#define ISP_AFC_MANUAL_60HZ		60
 378
 379/* ------------------------  SCENE MODE--------------------------------- */
 380enum isp_scene_mode {
 381	ISP_SCENE_NONE			= 0,
 382	ISP_SCENE_PORTRAIT		= 1,
 383	ISP_SCENE_LANDSCAPE		= 2,
 384	ISP_SCENE_SPORTS		= 3,
 385	ISP_SCENE_PARTYINDOOR		= 4,
 386	ISP_SCENE_BEACHSNOW		= 5,
 387	ISP_SCENE_SUNSET		= 6,
 388	ISP_SCENE_DAWN			= 7,
 389	ISP_SCENE_FALL			= 8,
 390	ISP_SCENE_NIGHT			= 9,
 391	ISP_SCENE_AGAINSTLIGHTWLIGHT	= 10,
 392	ISP_SCENE_AGAINSTLIGHTWOLIGHT	= 11,
 393	ISP_SCENE_FIRE			= 12,
 394	ISP_SCENE_TEXT			= 13,
 395	ISP_SCENE_CANDLE		= 14
 396};
 397
 398/* AFC error codes */
 399#define ISP_AFC_ERROR_NONE		0 /* AFC setting is done */
 400
 401/* ----------------------------  FD  ------------------------------------- */
 402enum fd_config_command {
 403	FD_CONFIG_COMMAND_MAXIMUM_NUMBER	= 0x1,
 404	FD_CONFIG_COMMAND_ROLL_ANGLE		= 0x2,
 405	FD_CONFIG_COMMAND_YAW_ANGLE		= 0x4,
 406	FD_CONFIG_COMMAND_SMILE_MODE		= 0x8,
 407	FD_CONFIG_COMMAND_BLINK_MODE		= 0x10,
 408	FD_CONFIG_COMMAND_EYES_DETECT		= 0x20,
 409	FD_CONFIG_COMMAND_MOUTH_DETECT		= 0x40,
 410	FD_CONFIG_COMMAND_ORIENTATION		= 0x80,
 411	FD_CONFIG_COMMAND_ORIENTATION_VALUE	= 0x100
 412};
 413
 414enum fd_config_roll_angle {
 415	FD_CONFIG_ROLL_ANGLE_BASIC		= 0,
 416	FD_CONFIG_ROLL_ANGLE_PRECISE_BASIC	= 1,
 417	FD_CONFIG_ROLL_ANGLE_SIDES		= 2,
 418	FD_CONFIG_ROLL_ANGLE_PRECISE_SIDES	= 3,
 419	FD_CONFIG_ROLL_ANGLE_FULL		= 4,
 420	FD_CONFIG_ROLL_ANGLE_PRECISE_FULL	= 5,
 421};
 422
 423enum fd_config_yaw_angle {
 424	FD_CONFIG_YAW_ANGLE_0			= 0,
 425	FD_CONFIG_YAW_ANGLE_45			= 1,
 426	FD_CONFIG_YAW_ANGLE_90			= 2,
 427	FD_CONFIG_YAW_ANGLE_45_90		= 3,
 428};
 429
 430/* Smile mode configuration */
 431#define FD_CONFIG_SMILE_MODE_DISABLE		0
 432#define FD_CONFIG_SMILE_MODE_ENABLE		1
 433
 434/* Blink mode configuration */
 435#define FD_CONFIG_BLINK_MODE_DISABLE		0
 436#define FD_CONFIG_BLINK_MODE_ENABLE		1
 437
 438/* Eyes detection configuration */
 439#define FD_CONFIG_EYES_DETECT_DISABLE		0
 440#define FD_CONFIG_EYES_DETECT_ENABLE		1
 441
 442/* Mouth detection configuration */
 443#define FD_CONFIG_MOUTH_DETECT_DISABLE		0
 444#define FD_CONFIG_MOUTH_DETECT_ENABLE		1
 445
 446#define FD_CONFIG_ORIENTATION_DISABLE		0
 447#define FD_CONFIG_ORIENTATION_ENABLE		1
 448
 449struct param_control {
 450	u32 cmd;
 451	u32 bypass;
 452	u32 buffer_address;
 453	u32 buffer_size;
 454	u32 skip_frames; /* only valid at ISP */
 455	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 6];
 456	u32 err;
 457};
 458
 459struct param_otf_input {
 460	u32 cmd;
 461	u32 width;
 462	u32 height;
 463	u32 format;
 464	u32 bitwidth;
 465	u32 order;
 466	u32 crop_offset_x;
 467	u32 crop_offset_y;
 468	u32 crop_width;
 469	u32 crop_height;
 470	u32 frametime_min;
 471	u32 frametime_max;
 472	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 13];
 473	u32 err;
 474};
 475
 476struct param_dma_input {
 477	u32 cmd;
 478	u32 width;
 479	u32 height;
 480	u32 format;
 481	u32 bitwidth;
 482	u32 plane;
 483	u32 order;
 484	u32 buffer_number;
 485	u32 buffer_address;
 486	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 10];
 487	u32 err;
 488};
 489
 490struct param_otf_output {
 491	u32 cmd;
 492	u32 width;
 493	u32 height;
 494	u32 format;
 495	u32 bitwidth;
 496	u32 order;
 497	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 7];
 498	u32 err;
 499};
 500
 501struct param_dma_output {
 502	u32 cmd;
 503	u32 width;
 504	u32 height;
 505	u32 format;
 506	u32 bitwidth;
 507	u32 plane;
 508	u32 order;
 509	u32 buffer_number;
 510	u32 buffer_address;
 511	u32 notify_dma_done;
 512	u32 dma_out_mask;
 513	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 12];
 514	u32 err;
 515};
 516
 517struct param_global_shotmode {
 518	u32 cmd;
 519	u32 skip_frames;
 520	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 521	u32 err;
 522};
 523
 524struct param_sensor_framerate {
 525	u32 frame_rate;
 526	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 527	u32 err;
 528};
 529
 530struct param_isp_aa {
 531	u32 cmd;
 532	u32 target;
 533	u32 mode;
 534	u32 scene;
 535	u32 sleep;
 536	u32 face;
 537	u32 touch_x;
 538	u32 touch_y;
 539	u32 manual_af_setting;
 540	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 10];
 541	u32 err;
 542};
 543
 544struct param_isp_flash {
 545	u32 cmd;
 546	u32 redeye;
 547	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 548	u32 err;
 549};
 550
 551struct param_isp_awb {
 552	u32 cmd;
 553	u32 illumination;
 554	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 555	u32 err;
 556};
 557
 558struct param_isp_imageeffect {
 559	u32 cmd;
 560	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 561	u32 err;
 562};
 563
 564struct param_isp_iso {
 565	u32 cmd;
 566	u32 value;
 567	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 568	u32 err;
 569};
 570
 571struct param_isp_adjust {
 572	u32 cmd;
 573	s32 contrast;
 574	s32 saturation;
 575	s32 sharpness;
 576	s32 exposure;
 577	s32 brightness;
 578	s32 hue;
 579	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 8];
 580	u32 err;
 581};
 582
 583struct param_isp_metering {
 584	u32 cmd;
 585	u32 win_pos_x;
 586	u32 win_pos_y;
 587	u32 win_width;
 588	u32 win_height;
 589	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 6];
 590	u32 err;
 591};
 592
 593struct param_isp_afc {
 594	u32 cmd;
 595	u32 manual;
 596	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 597	u32 err;
 598};
 599
 600struct param_scaler_imageeffect {
 601	u32 cmd;
 602	u32 arbitrary_cb;
 603	u32 arbitrary_cr;
 604	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 4];
 605	u32 err;
 606};
 607
 608struct param_scaler_input_crop {
 609	u32 cmd;
 610	u32 crop_offset_x;
 611	u32 crop_offset_y;
 612	u32 crop_width;
 613	u32 crop_height;
 614	u32 in_width;
 615	u32 in_height;
 616	u32 out_width;
 617	u32 out_height;
 618	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 10];
 619	u32 err;
 620};
 621
 622struct param_scaler_output_crop {
 623	u32 cmd;
 624	u32 crop_offset_x;
 625	u32 crop_offset_y;
 626	u32 crop_width;
 627	u32 crop_height;
 628	u32 out_format;
 629	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 7];
 630	u32 err;
 631};
 632
 633struct param_scaler_rotation {
 634	u32 cmd;
 635	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 636	u32 err;
 637};
 638
 639struct param_scaler_flip {
 640	u32 cmd;
 641	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 642	u32 err;
 643};
 644
 645struct param_3dnr_1stframe {
 646	u32 cmd;
 647	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 648	u32 err;
 649};
 650
 651struct param_fd_config {
 652	u32 cmd;
 653	u32 max_number;
 654	u32 roll_angle;
 655	u32 yaw_angle;
 656	u32 smile_mode;
 657	u32 blink_mode;
 658	u32 eye_detect;
 659	u32 mouth_detect;
 660	u32 orientation;
 661	u32 orientation_value;
 662	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 11];
 663	u32 err;
 664};
 665
 666struct global_param {
 667	struct param_global_shotmode	shotmode;
 668};
 669
 670struct sensor_param {
 671	struct param_control		control;
 672	struct param_otf_output		otf_output;
 673	struct param_sensor_framerate	frame_rate;
 674} __packed;
 675
 676struct buffer_param {
 677	struct param_control		control;
 678	struct param_otf_input		otf_input;
 679	struct param_otf_output		otf_output;
 680} __packed;
 681
 682struct isp_param {
 683	struct param_control		control;
 684	struct param_otf_input		otf_input;
 685	struct param_dma_input		dma1_input;
 686	struct param_dma_input		dma2_input;
 687	struct param_isp_aa		aa;
 688	struct param_isp_flash		flash;
 689	struct param_isp_awb		awb;
 690	struct param_isp_imageeffect	effect;
 691	struct param_isp_iso		iso;
 692	struct param_isp_adjust		adjust;
 693	struct param_isp_metering	metering;
 694	struct param_isp_afc		afc;
 695	struct param_otf_output		otf_output;
 696	struct param_dma_output		dma1_output;
 697	struct param_dma_output		dma2_output;
 698} __packed;
 699
 700struct drc_param {
 701	struct param_control		control;
 702	struct param_otf_input		otf_input;
 703	struct param_dma_input		dma_input;
 704	struct param_otf_output		otf_output;
 705} __packed;
 706
 707struct scalerc_param {
 708	struct param_control		control;
 709	struct param_otf_input		otf_input;
 710	struct param_scaler_imageeffect	effect;
 711	struct param_scaler_input_crop	input_crop;
 712	struct param_scaler_output_crop	output_crop;
 713	struct param_otf_output		otf_output;
 714	struct param_dma_output		dma_output;
 715} __packed;
 716
 717struct odc_param {
 718	struct param_control		control;
 719	struct param_otf_input		otf_input;
 720	struct param_otf_output		otf_output;
 721} __packed;
 722
 723struct dis_param {
 724	struct param_control		control;
 725	struct param_otf_output		otf_input;
 726	struct param_otf_output		otf_output;
 727} __packed;
 728
 729struct tdnr_param {
 730	struct param_control		control;
 731	struct param_otf_input		otf_input;
 732	struct param_3dnr_1stframe	frame;
 733	struct param_otf_output		otf_output;
 734	struct param_dma_output		dma_output;
 735} __packed;
 736
 737struct scalerp_param {
 738	struct param_control		control;
 739	struct param_otf_input		otf_input;
 740	struct param_scaler_imageeffect	effect;
 741	struct param_scaler_input_crop	input_crop;
 742	struct param_scaler_output_crop	output_crop;
 743	struct param_scaler_rotation	rotation;
 744	struct param_scaler_flip	flip;
 745	struct param_otf_output		otf_output;
 746	struct param_dma_output		dma_output;
 747} __packed;
 748
 749struct fd_param {
 750	struct param_control		control;
 751	struct param_otf_input		otf_input;
 752	struct param_dma_input		dma_input;
 753	struct param_fd_config		config;
 754} __packed;
 755
 756struct is_param_region {
 757	struct global_param		global;
 758	struct sensor_param		sensor;
 759	struct buffer_param		buf;
 760	struct isp_param		isp;
 761	struct drc_param		drc;
 762	struct scalerc_param		scalerc;
 763	struct odc_param		odc;
 764	struct dis_param		dis;
 765	struct tdnr_param		tdnr;
 766	struct scalerp_param		scalerp;
 767	struct fd_param			fd;
 768} __packed;
 769
 770#define NUMBER_OF_GAMMA_CURVE_POINTS	32
 771
 772struct is_tune_sensor {
 773	u32 exposure;
 774	u32 analog_gain;
 775	u32 frame_rate;
 776	u32 actuator_position;
 777};
 778
 779struct is_tune_gammacurve {
 780	u32 num_pts_x[NUMBER_OF_GAMMA_CURVE_POINTS];
 781	u32 num_pts_y_r[NUMBER_OF_GAMMA_CURVE_POINTS];
 782	u32 num_pts_y_g[NUMBER_OF_GAMMA_CURVE_POINTS];
 783	u32 num_pts_y_b[NUMBER_OF_GAMMA_CURVE_POINTS];
 784};
 785
 786struct is_tune_isp {
 787	/* Brightness level: range 0...100, default 7. */
 788	u32 brightness_level;
 789	/* Contrast level: range -127...127, default 0. */
 790	s32 contrast_level;
 791	/* Saturation level: range -127...127, default 0. */
 792	s32 saturation_level;
 793	s32 gamma_level;
 794	struct is_tune_gammacurve gamma_curve[4];
 795	/* Hue: range -127...127, default 0. */
 796	s32 hue;
 797	/* Sharpness blur: range -127...127, default 0. */
 798	s32 sharpness_blur;
 799	/* Despeckle : range -127~127, default : 0 */
 800	s32 despeckle;
 801	/* Edge color supression: range -127...127, default 0. */
 802	s32 edge_color_supression;
 803	/* Noise reduction: range -127...127, default 0. */
 804	s32 noise_reduction;
 805	/* (32 * 4 + 9) * 4 = 548 bytes */
 806} __packed;
 807
 808struct is_tune_region {
 809	struct is_tune_sensor sensor;
 810	struct is_tune_isp isp;
 811} __packed;
 812
 813struct rational {
 814	u32 num;
 815	u32 den;
 816};
 817
 818struct srational {
 819	s32 num;
 820	s32 den;
 821};
 822
 823#define FLASH_FIRED_SHIFT			0
 824#define FLASH_NOT_FIRED				0
 825#define FLASH_FIRED				1
 826
 827#define FLASH_STROBE_SHIFT			1
 828#define FLASH_STROBE_NO_DETECTION		0
 829#define FLASH_STROBE_RESERVED			1
 830#define FLASH_STROBE_RETURN_LIGHT_NOT_DETECTED	2
 831#define FLASH_STROBE_RETURN_LIGHT_DETECTED	3
 832
 833#define FLASH_MODE_SHIFT			3
 834#define FLASH_MODE_UNKNOWN			0
 835#define FLASH_MODE_COMPULSORY_FLASH_FIRING	1
 836#define FLASH_MODE_COMPULSORY_FLASH_SUPPRESSION	2
 837#define FLASH_MODE_AUTO_MODE			3
 838
 839#define FLASH_FUNCTION_SHIFT			5
 840#define FLASH_FUNCTION_PRESENT			0
 841#define FLASH_FUNCTION_NONE			1
 842
 843#define FLASH_RED_EYE_SHIFT			6
 844#define FLASH_RED_EYE_DISABLED			0
 845#define FLASH_RED_EYE_SUPPORTED			1
 846
 847enum apex_aperture_value {
 848	F1_0	= 0,
 849	F1_4	= 1,
 850	F2_0	= 2,
 851	F2_8	= 3,
 852	F4_0	= 4,
 853	F5_6	= 5,
 854	F8_9	= 6,
 855	F11_0	= 7,
 856	F16_0	= 8,
 857	F22_0	= 9,
 858	F32_0	= 10,
 859};
 860
 861struct exif_attribute {
 862	struct rational exposure_time;
 863	struct srational shutter_speed;
 864	u32 iso_speed_rating;
 865	u32 flash;
 866	struct srational brightness;
 867} __packed;
 868
 869struct is_frame_header {
 870	u32 valid;
 871	u32 bad_mark;
 872	u32 captured;
 873	u32 frame_number;
 874	struct exif_attribute exif;
 875} __packed;
 876
 877struct is_fd_rect {
 878	u32 offset_x;
 879	u32 offset_y;
 880	u32 width;
 881	u32 height;
 882};
 883
 884struct is_face_marker {
 885	u32 frame_number;
 886	struct is_fd_rect face;
 887	struct is_fd_rect left_eye;
 888	struct is_fd_rect right_eye;
 889	struct is_fd_rect mouth;
 890	u32 roll_angle;
 891	u32 yaw_angle;
 892	u32 confidence;
 893	s32 smile_level;
 894	s32 blink_level;
 895} __packed;
 896
 897#define MAX_FRAME_COUNT				8
 898#define MAX_FRAME_COUNT_PREVIEW			4
 899#define MAX_FRAME_COUNT_CAPTURE			1
 900#define MAX_FACE_COUNT				16
 901#define MAX_SHARED_COUNT			500
 902
 903struct is_region {
 904	struct is_param_region parameter;
 905	struct is_tune_region tune;
 906	struct is_frame_header header[MAX_FRAME_COUNT];
 907	struct is_face_marker face[MAX_FACE_COUNT];
 908	u32 shared[MAX_SHARED_COUNT];
 909} __packed;
 910
 911/* Offset to the ISP DMA2 output buffer address array. */
 912#define DMA2_OUTPUT_ADDR_ARRAY_OFFS \
 913	(offsetof(struct is_region, shared) + 32 * sizeof(u32))
 914
 915struct is_debug_frame_descriptor {
 916	u32 sensor_frame_time;
 917	u32 sensor_exposure_time;
 918	s32 sensor_analog_gain;
 919	/* monitor for AA */
 920	u32 req_lei;
 921
 922	u32 next_next_lei_exp;
 923	u32 next_next_lei_a_gain;
 924	u32 next_next_lei_d_gain;
 925	u32 next_next_lei_statlei;
 926	u32 next_next_lei_lei;
 927
 928	u32 dummy0;
 929};
 930
 931#define MAX_FRAMEDESCRIPTOR_CONTEXT_NUM	(30*20)	/* 600 frames */
 932#define MAX_VERSION_DISPLAY_BUF	32
 933
 934struct is_share_region {
 935	u32 frame_time;
 936	u32 exposure_time;
 937	s32 analog_gain;
 938
 939	u32 r_gain;
 940	u32 g_gain;
 941	u32 b_gain;
 942
 943	u32 af_position;
 944	u32 af_status;
 945	/* 0 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_NOMESSAGE */
 946	/* 1 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_REACHED */
 947	/* 2 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_UNABLETOREACH */
 948	/* 3 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_LOST */
 949	/* default : unknown */
 950	u32 af_scene_type;
 951
 952	u32 frame_descp_onoff_control;
 953	u32 frame_descp_update_done;
 954	u32 frame_descp_idx;
 955	u32 frame_descp_max_idx;
 956	struct is_debug_frame_descriptor
 957		dbg_frame_descp_ctx[MAX_FRAMEDESCRIPTOR_CONTEXT_NUM];
 958
 959	u32 chip_id;
 960	u32 chip_rev_no;
 961	u8 isp_fw_ver_no[MAX_VERSION_DISPLAY_BUF];
 962	u8 isp_fw_ver_date[MAX_VERSION_DISPLAY_BUF];
 963	u8 sirc_sdk_ver_no[MAX_VERSION_DISPLAY_BUF];
 964	u8 sirc_sdk_rev_no[MAX_VERSION_DISPLAY_BUF];
 965	u8 sirc_sdk_rev_date[MAX_VERSION_DISPLAY_BUF];
 966} __packed;
 967
 968struct is_debug_control {
 969	u32 write_point;	/* 0~ 500KB boundary */
 970	u32 assert_flag;	/* 0: Not invoked, 1: Invoked */
 971	u32 pabort_flag;	/* 0: Not invoked, 1: Invoked */
 972	u32 dabort_flag;	/* 0: Not invoked, 1: Invoked */
 973};
 974
 975struct sensor_open_extended {
 976	u32 actuator_type;
 977	u32 mclk;
 978	u32 mipi_lane_num;
 979	u32 mipi_speed;
 980	/* Skip setfile loading when fast_open_sensor is not 0 */
 981	u32 fast_open_sensor;
 982	/* Activating sensor self calibration mode (6A3) */
 983	u32 self_calibration_mode;
 984	/* This field is to adjust I2c clock based on ACLK200 */
 985	/* This value is varied in case of rev 0.2 */
 986	u32 i2c_sclk;
 987};
 988
 989struct fimc_is;
 990
 991int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is);
 992int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset);
 993void fimc_is_set_initial_params(struct fimc_is *is);
 994unsigned int __get_pending_param_count(struct fimc_is *is);
 995
 996int  __is_hw_update_params(struct fimc_is *is);
 997void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf);
 998void __is_set_sensor(struct fimc_is *is, int fps);
 999void __is_set_isp_aa_ae(struct fimc_is *is);
1000void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye);
1001void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val);
1002void __is_set_isp_effect(struct fimc_is *is, u32 cmd);
1003void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val);
1004void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val);
1005void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val);
1006void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val);
1007void __is_set_drc_control(struct fimc_is *is, u32 val);
1008void __is_set_fd_control(struct fimc_is *is, u32 val);
1009void __is_set_fd_config_maxface(struct fimc_is *is, u32 val);
1010void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val);
1011void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val);
1012void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val);
1013void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val);
1014void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val);
1015void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val);
1016void __is_set_fd_config_orientation(struct fimc_is *is, u32 val);
1017void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val);
1018void __is_set_isp_aa_af_mode(struct fimc_is *is, int cmd);
1019void __is_set_isp_aa_af_start_stop(struct fimc_is *is, int cmd);
1020
1021#endif