rkisp1-csi.c

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Rockchip ISP1 Driver - CSI-2 Receiver
  4 *
  5 * Copyright (C) 2019 Collabora, Ltd.
  6 * Copyright (C) 2022 Ideas on Board
  7 *
  8 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
  9 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
 10 */
 11
 12#include <linux/delay.h>
 13#include <linux/device.h>
 14#include <linux/lockdep.h>
 15#include <linux/phy/phy.h>
 16#include <linux/phy/phy-mipi-dphy.h>
 17
 18#include <media/v4l2-ctrls.h>
 19#include <media/v4l2-fwnode.h>
 20
 21#include "rkisp1-common.h"
 22#include "rkisp1-csi.h"
 23
 24#define RKISP1_CSI_DEV_NAME	RKISP1_DRIVER_NAME "_csi"
 25
 26#define RKISP1_CSI_DEF_FMT	MEDIA_BUS_FMT_SRGGB10_1X10
 27
 28static inline struct rkisp1_csi *to_rkisp1_csi(struct v4l2_subdev *sd)
 29{
 30	return container_of(sd, struct rkisp1_csi, sd);
 31}
 32
 33int rkisp1_csi_link_sensor(struct rkisp1_device *rkisp1, struct v4l2_subdev *sd,
 34			   struct rkisp1_sensor_async *s_asd,
 35			   unsigned int source_pad)
 36{
 37	struct rkisp1_csi *csi = &rkisp1->csi;
 38	int ret;
 39
 40	s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler,
 41						V4L2_CID_PIXEL_RATE);
 42	if (!s_asd->pixel_rate_ctrl) {
 43		dev_err(rkisp1->dev, "No pixel rate control in subdev %s\n",
 44			sd->name);
 45		return -EINVAL;
 46	}
 47
 48	/* Create the link from the sensor to the CSI receiver. */
 49	ret = media_create_pad_link(&sd->entity, source_pad,
 50				    &csi->sd.entity, RKISP1_CSI_PAD_SINK,
 51				    !s_asd->index ? MEDIA_LNK_FL_ENABLED : 0);
 52	if (ret) {
 53		dev_err(csi->rkisp1->dev, "failed to link src pad of %s\n",
 54			sd->name);
 55		return ret;
 56	}
 57
 58	return 0;
 59}
 60
 61static int rkisp1_csi_config(struct rkisp1_csi *csi,
 62			     const struct rkisp1_sensor_async *sensor,
 63			     const struct rkisp1_mbus_info *format)
 64{
 65	struct rkisp1_device *rkisp1 = csi->rkisp1;
 66	unsigned int lanes = sensor->lanes;
 67	u32 mipi_ctrl;
 68
 69	if (lanes < 1 || lanes > 4)
 70		return -EINVAL;
 71
 72	mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
 73		    RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
 74		    RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
 75		    RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA;
 76
 77	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, mipi_ctrl);
 78
 79	/* V12 could also use a newer csi2-host, but we don't want that yet */
 80	if (rkisp1->info->isp_ver == RKISP1_V12)
 81		rkisp1_write(rkisp1, RKISP1_CIF_ISP_CSI0_CTRL0, 0);
 82
 83	/* Configure Data Type and Virtual Channel */
 84	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL,
 85		     RKISP1_CIF_MIPI_DATA_SEL_DT(format->mipi_dt) |
 86		     RKISP1_CIF_MIPI_DATA_SEL_VC(0));
 87
 88	/* Clear MIPI interrupts */
 89	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0);
 90
 91	/*
 92	 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for
 93	 * isp bus may be dead when switch isp.
 94	 */
 95	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC,
 96		     RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI |
 97		     RKISP1_CIF_MIPI_ERR_DPHY |
 98		     RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
 99		     RKISP1_CIF_MIPI_ADD_DATA_OVFLW);
100
101	dev_dbg(rkisp1->dev, "\n  MIPI_CTRL 0x%08x\n"
102		"  MIPI_IMG_DATA_SEL 0x%08x\n"
103		"  MIPI_STATUS 0x%08x\n"
104		"  MIPI_IMSC 0x%08x\n",
105		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL),
106		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL),
107		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS),
108		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC));
109
110	return 0;
111}
112
113static void rkisp1_csi_enable(struct rkisp1_csi *csi)
114{
115	struct rkisp1_device *rkisp1 = csi->rkisp1;
116	u32 val;
117
118	val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
119	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
120		     val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA);
121}
122
123static void rkisp1_csi_disable(struct rkisp1_csi *csi)
124{
125	struct rkisp1_device *rkisp1 = csi->rkisp1;
126	u32 val;
127
128	/* Mask MIPI interrupts. */
129	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0);
130
131	/* Flush posted writes */
132	rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
133
134	/*
135	 * Wait until the IRQ handler has ended. The IRQ handler may get called
136	 * even after this, but it will return immediately as the MIPI
137	 * interrupts have been masked.
138	 */
139	synchronize_irq(rkisp1->irqs[RKISP1_IRQ_MIPI]);
140
141	/* Clear MIPI interrupt status */
142	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0);
143
144	val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
145	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
146		     val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA));
147}
148
149static int rkisp1_csi_start(struct rkisp1_csi *csi,
150			    const struct rkisp1_sensor_async *sensor,
151			    const struct rkisp1_mbus_info *format)
152{
153	struct rkisp1_device *rkisp1 = csi->rkisp1;
154	union phy_configure_opts opts;
155	struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
156	s64 pixel_clock;
157	int ret;
158
159	ret = rkisp1_csi_config(csi, sensor, format);
160	if (ret)
161		return ret;
162
163	pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl);
164	if (!pixel_clock) {
165		dev_err(rkisp1->dev, "Invalid pixel rate value\n");
166		return -EINVAL;
167	}
168
169	phy_mipi_dphy_get_default_config(pixel_clock, format->bus_width,
170					 sensor->lanes, cfg);
171	phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY);
172	phy_configure(csi->dphy, &opts);
173	phy_power_on(csi->dphy);
174
175	rkisp1_csi_enable(csi);
176
177	/*
178	 * CIF spec says to wait for sufficient time after enabling
179	 * the MIPI interface and before starting the sensor output.
180	 */
181	usleep_range(1000, 1200);
182
183	return 0;
184}
185
186static void rkisp1_csi_stop(struct rkisp1_csi *csi)
187{
188	rkisp1_csi_disable(csi);
189
190	phy_power_off(csi->dphy);
191}
192
193irqreturn_t rkisp1_csi_isr(int irq, void *ctx)
194{
195	struct device *dev = ctx;
196	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
197	u32 val, status;
198
199	if (!rkisp1->irqs_enabled)
200		return IRQ_NONE;
201
202	status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
203	if (!status)
204		return IRQ_NONE;
205
206	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, status);
207
208	/*
209	 * Disable DPHY errctrl interrupt, because this dphy
210	 * erctrl signal is asserted until the next changes
211	 * of line state. This time is may be too long and cpu
212	 * is hold in this interrupt.
213	 */
214	if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) {
215		val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
216		rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC,
217			     val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f));
218		rkisp1->csi.is_dphy_errctrl_disabled = true;
219	}
220
221	/*
222	 * Enable DPHY errctrl interrupt again, if mipi have receive
223	 * the whole frame without any error.
224	 */
225	if (status == RKISP1_CIF_MIPI_FRAME_END) {
226		/*
227		 * Enable DPHY errctrl interrupt again, if mipi have receive
228		 * the whole frame without any error.
229		 */
230		if (rkisp1->csi.is_dphy_errctrl_disabled) {
231			val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
232			val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f);
233			rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, val);
234			rkisp1->csi.is_dphy_errctrl_disabled = false;
235		}
236	} else {
237		rkisp1->debug.mipi_error++;
238	}
239
240	return IRQ_HANDLED;
241}
242
243/* ----------------------------------------------------------------------------
244 * Subdev pad operations
245 */
246
247static int rkisp1_csi_enum_mbus_code(struct v4l2_subdev *sd,
248				     struct v4l2_subdev_state *sd_state,
249				     struct v4l2_subdev_mbus_code_enum *code)
250{
251	unsigned int i;
252	int pos = 0;
253
254	if (code->pad == RKISP1_CSI_PAD_SRC) {
255		const struct v4l2_mbus_framefmt *sink_fmt;
256
257		if (code->index)
258			return -EINVAL;
259
260		sink_fmt = v4l2_subdev_state_get_format(sd_state,
261							RKISP1_CSI_PAD_SINK);
262		code->code = sink_fmt->code;
263
264		return 0;
265	}
266
267	for (i = 0; ; i++) {
268		const struct rkisp1_mbus_info *fmt =
269			rkisp1_mbus_info_get_by_index(i);
270
271		if (!fmt)
272			return -EINVAL;
273
274		if (!(fmt->direction & RKISP1_ISP_SD_SINK))
275			continue;
276
277		if (code->index == pos) {
278			code->code = fmt->mbus_code;
279			return 0;
280		}
281
282		pos++;
283	}
284
285	return -EINVAL;
286}
287
288static int rkisp1_csi_init_state(struct v4l2_subdev *sd,
289				 struct v4l2_subdev_state *sd_state)
290{
291	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
292
293	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK);
294	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SRC);
295
296	sink_fmt->width = RKISP1_DEFAULT_WIDTH;
297	sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
298	sink_fmt->field = V4L2_FIELD_NONE;
299	sink_fmt->code = RKISP1_CSI_DEF_FMT;
300
301	*src_fmt = *sink_fmt;
302
303	return 0;
304}
305
306static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,
307			      struct v4l2_subdev_state *sd_state,
308			      struct v4l2_subdev_format *fmt)
309{
310	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
311	const struct rkisp1_mbus_info *mbus_info;
312	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
313
314	/* The format on the source pad always matches the sink pad. */
315	if (fmt->pad == RKISP1_CSI_PAD_SRC)
316		return v4l2_subdev_get_fmt(sd, sd_state, fmt);
317
318	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK);
319
320	sink_fmt->code = fmt->format.code;
321
322	mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code);
323	if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) {
324		sink_fmt->code = RKISP1_CSI_DEF_FMT;
325		mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code);
326	}
327
328	sink_fmt->width = clamp_t(u32, fmt->format.width,
329				  RKISP1_ISP_MIN_WIDTH,
330				  csi->rkisp1->info->max_width);
331	sink_fmt->height = clamp_t(u32, fmt->format.height,
332				   RKISP1_ISP_MIN_HEIGHT,
333				   csi->rkisp1->info->max_height);
334
335	fmt->format = *sink_fmt;
336
337	/* Propagate the format to the source pad. */
338	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SRC);
339	*src_fmt = *sink_fmt;
340
341	return 0;
342}
343
344/* ----------------------------------------------------------------------------
345 * Subdev video operations
346 */
347
348static int rkisp1_csi_s_stream(struct v4l2_subdev *sd, int enable)
349{
350	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
351	struct rkisp1_device *rkisp1 = csi->rkisp1;
352	const struct v4l2_mbus_framefmt *sink_fmt;
353	const struct rkisp1_mbus_info *format;
354	struct rkisp1_sensor_async *source_asd;
355	struct v4l2_async_connection *asc;
356	struct v4l2_subdev_state *sd_state;
357	struct media_pad *source_pad;
358	struct v4l2_subdev *source;
359	int ret;
360
361	if (!enable) {
362		v4l2_subdev_call(csi->source, video, s_stream, false);
363
364		rkisp1_csi_stop(csi);
365
366		return 0;
367	}
368
369	source_pad = media_entity_remote_source_pad_unique(&sd->entity);
370	if (IS_ERR(source_pad)) {
371		dev_dbg(rkisp1->dev, "Failed to get source for CSI: %pe\n",
372			source_pad);
373		return -EPIPE;
374	}
375
376	source = media_entity_to_v4l2_subdev(source_pad->entity);
377	if (!source) {
378		/* This should really not happen, so is not worth a message. */
379		return -EPIPE;
380	}
381
382	asc = v4l2_async_connection_unique(source);
383	if (!asc)
384		return -EPIPE;
385
386	source_asd = container_of(asc, struct rkisp1_sensor_async, asd);
387	if (source_asd->mbus_type != V4L2_MBUS_CSI2_DPHY)
388		return -EINVAL;
389
390	sd_state = v4l2_subdev_lock_and_get_active_state(sd);
391	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK);
392	format = rkisp1_mbus_info_get_by_code(sink_fmt->code);
393	v4l2_subdev_unlock_state(sd_state);
394
395	ret = rkisp1_csi_start(csi, source_asd, format);
396	if (ret)
397		return ret;
398
399	ret = v4l2_subdev_call(source, video, s_stream, true);
400	if (ret) {
401		rkisp1_csi_stop(csi);
402		return ret;
403	}
404
405	csi->source = source;
406
407	return 0;
408}
409
410/* ----------------------------------------------------------------------------
411 * Registration
412 */
413
414static const struct media_entity_operations rkisp1_csi_media_ops = {
415	.link_validate = v4l2_subdev_link_validate,
416};
417
418static const struct v4l2_subdev_video_ops rkisp1_csi_video_ops = {
419	.s_stream = rkisp1_csi_s_stream,
420};
421
422static const struct v4l2_subdev_pad_ops rkisp1_csi_pad_ops = {
423	.enum_mbus_code = rkisp1_csi_enum_mbus_code,
424	.get_fmt = v4l2_subdev_get_fmt,
425	.set_fmt = rkisp1_csi_set_fmt,
426};
427
428static const struct v4l2_subdev_ops rkisp1_csi_ops = {
429	.video = &rkisp1_csi_video_ops,
430	.pad = &rkisp1_csi_pad_ops,
431};
432
433static const struct v4l2_subdev_internal_ops rkisp1_csi_internal_ops = {
434	.init_state = rkisp1_csi_init_state,
435};
436
437int rkisp1_csi_register(struct rkisp1_device *rkisp1)
438{
439	struct rkisp1_csi *csi = &rkisp1->csi;
440	struct media_pad *pads;
441	struct v4l2_subdev *sd;
442	int ret;
443
444	csi->rkisp1 = rkisp1;
445
446	sd = &csi->sd;
447	v4l2_subdev_init(sd, &rkisp1_csi_ops);
448	sd->internal_ops = &rkisp1_csi_internal_ops;
449	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
450	sd->entity.ops = &rkisp1_csi_media_ops;
451	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
452	sd->owner = THIS_MODULE;
453	strscpy(sd->name, RKISP1_CSI_DEV_NAME, sizeof(sd->name));
454
455	pads = csi->pads;
456	pads[RKISP1_CSI_PAD_SINK].flags = MEDIA_PAD_FL_SINK |
457					  MEDIA_PAD_FL_MUST_CONNECT;
458	pads[RKISP1_CSI_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE |
459					 MEDIA_PAD_FL_MUST_CONNECT;
460
461	ret = media_entity_pads_init(&sd->entity, RKISP1_CSI_PAD_NUM, pads);
462	if (ret)
463		goto err_entity_cleanup;
464
465	ret = v4l2_subdev_init_finalize(sd);
466	if (ret)
467		goto err_entity_cleanup;
468
469	ret = v4l2_device_register_subdev(&csi->rkisp1->v4l2_dev, sd);
470	if (ret) {
471		dev_err(sd->dev, "Failed to register csi receiver subdev\n");
472		goto err_subdev_cleanup;
473	}
474
475	return 0;
476
477err_subdev_cleanup:
478	v4l2_subdev_cleanup(sd);
479err_entity_cleanup:
480	media_entity_cleanup(&sd->entity);
481	csi->rkisp1 = NULL;
482	return ret;
483}
484
485void rkisp1_csi_unregister(struct rkisp1_device *rkisp1)
486{
487	struct rkisp1_csi *csi = &rkisp1->csi;
488
489	if (!csi->rkisp1)
490		return;
491
492	v4l2_device_unregister_subdev(&csi->sd);
493	v4l2_subdev_cleanup(&csi->sd);
494	media_entity_cleanup(&csi->sd.entity);
495}
496
497int rkisp1_csi_init(struct rkisp1_device *rkisp1)
498{
499	struct rkisp1_csi *csi = &rkisp1->csi;
500
501	csi->rkisp1 = rkisp1;
502
503	csi->dphy = devm_phy_get(rkisp1->dev, "dphy");
504	if (IS_ERR(csi->dphy))
505		return dev_err_probe(rkisp1->dev, PTR_ERR(csi->dphy),
506				     "Couldn't get the MIPI D-PHY\n");
507
508	phy_init(csi->dphy);
509
510	return 0;
511}
512
513void rkisp1_csi_cleanup(struct rkisp1_device *rkisp1)
514{
515	struct rkisp1_csi *csi = &rkisp1->csi;
516
517	phy_exit(csi->dphy);
518}