rkcif-regs.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Rockchip Camera Interface (CIF) Driver
  4 *
  5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
  6 * Copyright (C) 2023 Mehdi Djait <mehdi.djait@bootlin.com>
  7 * Copyright (C) 2025 Michael Riesch <michael.riesch@wolfvision.net>
  8 */
  9
 10#ifndef _RKCIF_REGS_H
 11#define _RKCIF_REGS_H
 12
 13#define RKCIF_REGISTER_NOTSUPPORTED		0x420000
 14#define RKCIF_FETCH_Y(VAL)			((VAL) & 0x1fff)
 15#define RKCIF_XY_COORD(x, y)			(((y) << 16) | (x))
 16
 17/* DVP register contents */
 18#define RKCIF_CTRL_ENABLE_CAPTURE		BIT(0)
 19#define RKCIF_CTRL_MODE_PINGPONG		BIT(1)
 20#define RKCIF_CTRL_MODE_LINELOOP		BIT(2)
 21#define RKCIF_CTRL_AXI_BURST_16			(0xf << 12)
 22
 23#define RKCIF_INTEN_FRAME_END_EN		BIT(0)
 24#define RKCIF_INTEN_LINE_ERR_EN			BIT(2)
 25#define RKCIF_INTEN_BUS_ERR_EN			BIT(6)
 26#define RKCIF_INTEN_SCL_ERR_EN			BIT(7)
 27#define RKCIF_INTEN_PST_INF_FRAME_END_EN	BIT(9)
 28
 29#define RKCIF_INTSTAT_CLS			0x3ff
 30#define RKCIF_INTSTAT_FRAME_END			BIT(0)
 31#define RKCIF_INTSTAT_LINE_END			BIT(1)
 32#define RKCIF_INTSTAT_LINE_ERR			BIT(2)
 33#define RKCIF_INTSTAT_PIX_ERR			BIT(3)
 34#define RKCIF_INTSTAT_DFIFO_OF			BIT(5)
 35#define RKCIF_INTSTAT_BUS_ERR			BIT(6)
 36#define RKCIF_INTSTAT_PRE_INF_FRAME_END		BIT(8)
 37#define RKCIF_INTSTAT_PST_INF_FRAME_END		BIT(9)
 38#define RKCIF_INTSTAT_FRAME_END_CLR		BIT(0)
 39#define RKCIF_INTSTAT_LINE_END_CLR		BIT(1)
 40#define RKCIF_INTSTAT_LINE_ERR_CLR		BIT(2)
 41#define RKCIF_INTSTAT_PST_INF_FRAME_END_CLR	BIT(9)
 42#define RKCIF_INTSTAT_ERR			0xfc
 43
 44#define RKCIF_FRAME_STAT_CLS			0x00
 45#define RKCIF_FRAME_FRM0_STAT_CLS		0x20
 46
 47#define RKCIF_FORMAT_VSY_HIGH_ACTIVE		BIT(0)
 48#define RKCIF_FORMAT_HSY_LOW_ACTIVE		BIT(1)
 49
 50#define RKCIF_FORMAT_INPUT_MODE_YUV		(0x00 << 2)
 51#define RKCIF_FORMAT_INPUT_MODE_PAL		(0x02 << 2)
 52#define RKCIF_FORMAT_INPUT_MODE_NTSC		(0x03 << 2)
 53#define RKCIF_FORMAT_INPUT_MODE_BT1120		(0x07 << 2)
 54#define RKCIF_FORMAT_INPUT_MODE_RAW		(0x04 << 2)
 55#define RKCIF_FORMAT_INPUT_MODE_JPEG		(0x05 << 2)
 56#define RKCIF_FORMAT_INPUT_MODE_MIPI		(0x06 << 2)
 57
 58#define RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY	(0x00 << 5)
 59#define RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU	(0x01 << 5)
 60#define RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY	(0x02 << 5)
 61#define RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV	(0x03 << 5)
 62#define RKCIF_FORMAT_YUV_INPUT_422		(0x00 << 7)
 63#define RKCIF_FORMAT_YUV_INPUT_420		BIT(7)
 64
 65#define RKCIF_FORMAT_INPUT_420_ORDER_ODD	BIT(8)
 66
 67#define RKCIF_FORMAT_CCIR_INPUT_ORDER_EVEN	BIT(9)
 68
 69#define RKCIF_FORMAT_RAW_DATA_WIDTH_8		(0x00 << 11)
 70#define RKCIF_FORMAT_RAW_DATA_WIDTH_10		(0x01 << 11)
 71#define RKCIF_FORMAT_RAW_DATA_WIDTH_12		(0x02 << 11)
 72
 73#define RKCIF_FORMAT_YUV_OUTPUT_422		(0x00 << 16)
 74#define RKCIF_FORMAT_YUV_OUTPUT_420		BIT(16)
 75
 76#define RKCIF_FORMAT_OUTPUT_420_ORDER_EVEN	(0x00 << 17)
 77#define RKCIF_FORMAT_OUTPUT_420_ORDER_ODD	BIT(17)
 78
 79#define RKCIF_FORMAT_RAWD_DATA_LITTLE_ENDIAN	(0x00 << 18)
 80#define RKCIF_FORMAT_RAWD_DATA_BIG_ENDIAN	BIT(18)
 81
 82#define RKCIF_FORMAT_UV_STORAGE_ORDER_UVUV	(0x00 << 19)
 83#define RKCIF_FORMAT_UV_STORAGE_ORDER_VUVU	BIT(19)
 84
 85#define RKCIF_FORMAT_BT1120_CLOCK_SINGLE_EDGES	(0x00 << 24)
 86#define RKCIF_FORMAT_BT1120_CLOCK_DOUBLE_EDGES	BIT(24)
 87#define RKCIF_FORMAT_BT1120_TRANSMIT_INTERFACE	(0x00 << 25)
 88#define RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS	BIT(25)
 89#define RKCIF_FORMAT_BT1120_YC_SWAP		BIT(26)
 90
 91#define RKCIF_SCL_CTRL_ENABLE_SCL_DOWN		BIT(0)
 92#define RKCIF_SCL_CTRL_ENABLE_SCL_UP		BIT(1)
 93#define RKCIF_SCL_CTRL_ENABLE_YUV_16BIT_BYPASS	BIT(4)
 94#define RKCIF_SCL_CTRL_ENABLE_RAW_16BIT_BYPASS	BIT(5)
 95#define RKCIF_SCL_CTRL_ENABLE_32BIT_BYPASS	BIT(6)
 96#define RKCIF_SCL_CTRL_DISABLE_32BIT_BYPASS	(0x00 << 6)
 97
 98#define RKCIF_INTSTAT_F0_READY			BIT(0)
 99#define RKCIF_INTSTAT_F1_READY			BIT(1)
100
101/* GRF register offsets and contents */
102#define RK3568_GRF_VI_CON0			0x340
103#define RK3568_GRF_VI_CON1			0x344
104#define RK3568_GRF_VI_STATUS0			0x348
105
106#define RK3568_GRF_VI_CON1_CIF_DATAPATH		BIT(9)
107#define RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM	GENMASK(6, 0)
108
109#define RK3568_GRF_WRITE_ENABLE(x)		((x) << 16)
110
111enum rkcif_dvp_register_index {
112	RKCIF_DVP_CTRL,
113	RKCIF_DVP_INTEN,
114	RKCIF_DVP_INTSTAT,
115	RKCIF_DVP_FOR,
116	RKCIF_DVP_LINE_NUM_ADDR,
117	RKCIF_DVP_FRM0_ADDR_Y,
118	RKCIF_DVP_FRM0_ADDR_UV,
119	RKCIF_DVP_FRM1_ADDR_Y,
120	RKCIF_DVP_FRM1_ADDR_UV,
121	RKCIF_DVP_VIR_LINE_WIDTH,
122	RKCIF_DVP_SET_SIZE,
123	RKCIF_DVP_SCL_CTRL,
124	RKCIF_DVP_CROP,
125	RKCIF_DVP_FRAME_STATUS,
126	RKCIF_DVP_LAST_LINE,
127	RKCIF_DVP_LAST_PIX,
128	RKCIF_DVP_REGISTER_MAX
129};
130
131enum rkcif_mipi_register_index {
132	RKCIF_MIPI_CTRL,
133	RKCIF_MIPI_INTEN,
134	RKCIF_MIPI_INTSTAT,
135	RKCIF_MIPI_REGISTER_MAX
136};
137
138enum rkcif_mipi_id_register_index {
139	RKCIF_MIPI_CTRL0,
140	RKCIF_MIPI_CTRL1,
141	RKCIF_MIPI_FRAME0_ADDR_Y,
142	RKCIF_MIPI_FRAME0_ADDR_UV,
143	RKCIF_MIPI_FRAME0_VLW_Y,
144	RKCIF_MIPI_FRAME0_VLW_UV,
145	RKCIF_MIPI_FRAME1_ADDR_Y,
146	RKCIF_MIPI_FRAME1_ADDR_UV,
147	RKCIF_MIPI_FRAME1_VLW_Y,
148	RKCIF_MIPI_FRAME1_VLW_UV,
149	RKCIF_MIPI_CROP_START,
150	RKCIF_MIPI_ID_REGISTER_MAX
151};
152
153#endif