rga.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) Rockchip Electronics Co., Ltd.
  4 * Author: Jacob Chen <jacob-chen@iotwrt.com>
  5 */
  6
  7#include <linux/clk.h>
  8#include <linux/debugfs.h>
  9#include <linux/delay.h>
 10#include <linux/fs.h>
 11#include <linux/interrupt.h>
 12#include <linux/module.h>
 13#include <linux/of.h>
 14#include <linux/pm_runtime.h>
 15#include <linux/reset.h>
 16#include <linux/sched.h>
 17#include <linux/slab.h>
 18#include <linux/timer.h>
 19
 20#include <linux/platform_device.h>
 21#include <media/v4l2-device.h>
 22#include <media/v4l2-event.h>
 23#include <media/v4l2-ioctl.h>
 24#include <media/v4l2-mem2mem.h>
 25#include <media/videobuf2-dma-sg.h>
 26#include <media/videobuf2-v4l2.h>
 27
 28#include "rga-hw.h"
 29#include "rga.h"
 30
 31static int debug;
 32module_param(debug, int, 0644);
 33
 34static void device_run(void *prv)
 35{
 36	struct rga_ctx *ctx = prv;
 37	struct rockchip_rga *rga = ctx->rga;
 38	struct vb2_v4l2_buffer *src, *dst;
 39	unsigned long flags;
 40
 41	spin_lock_irqsave(&rga->ctrl_lock, flags);
 42
 43	rga->curr = ctx;
 44
 45	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
 46	src->sequence = ctx->osequence++;
 47
 48	dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
 49
 50	rga_hw_start(rga, vb_to_rga(src), vb_to_rga(dst));
 51
 52	spin_unlock_irqrestore(&rga->ctrl_lock, flags);
 53}
 54
 55static irqreturn_t rga_isr(int irq, void *prv)
 56{
 57	struct rockchip_rga *rga = prv;
 58	int intr;
 59
 60	intr = rga_read(rga, RGA_INT) & 0xf;
 61
 62	rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
 63
 64	if (intr & 0x04) {
 65		struct vb2_v4l2_buffer *src, *dst;
 66		struct rga_ctx *ctx = rga->curr;
 67
 68		WARN_ON(!ctx);
 69
 70		rga->curr = NULL;
 71
 72		src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 73		dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 74
 75		WARN_ON(!src);
 76		WARN_ON(!dst);
 77
 78		v4l2_m2m_buf_copy_metadata(src, dst);
 79
 80		dst->sequence = ctx->csequence++;
 81
 82		v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
 83		v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
 84		v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
 85	}
 86
 87	return IRQ_HANDLED;
 88}
 89
 90static const struct v4l2_m2m_ops rga_m2m_ops = {
 91	.device_run = device_run,
 92};
 93
 94static int
 95queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
 96{
 97	struct rga_ctx *ctx = priv;
 98	int ret;
 99
100	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
101	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
102	src_vq->drv_priv = ctx;
103	src_vq->ops = &rga_qops;
104	src_vq->mem_ops = &vb2_dma_sg_memops;
105	src_vq->gfp_flags = __GFP_DMA32;
106	src_vq->buf_struct_size = sizeof(struct rga_vb_buffer);
107	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
108	src_vq->lock = &ctx->rga->mutex;
109	src_vq->dev = ctx->rga->v4l2_dev.dev;
110
111	ret = vb2_queue_init(src_vq);
112	if (ret)
113		return ret;
114
115	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
116	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
117	dst_vq->drv_priv = ctx;
118	dst_vq->ops = &rga_qops;
119	dst_vq->mem_ops = &vb2_dma_sg_memops;
120	dst_vq->gfp_flags = __GFP_DMA32;
121	dst_vq->buf_struct_size = sizeof(struct rga_vb_buffer);
122	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
123	dst_vq->lock = &ctx->rga->mutex;
124	dst_vq->dev = ctx->rga->v4l2_dev.dev;
125
126	return vb2_queue_init(dst_vq);
127}
128
129static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
130{
131	struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
132					   ctrl_handler);
133	unsigned long flags;
134
135	spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
136	switch (ctrl->id) {
137	case V4L2_CID_HFLIP:
138		ctx->hflip = ctrl->val;
139		break;
140	case V4L2_CID_VFLIP:
141		ctx->vflip = ctrl->val;
142		break;
143	case V4L2_CID_ROTATE:
144		ctx->rotate = ctrl->val;
145		break;
146	case V4L2_CID_BG_COLOR:
147		ctx->fill_color = ctrl->val;
148		break;
149	}
150	spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
151	return 0;
152}
153
154static const struct v4l2_ctrl_ops rga_ctrl_ops = {
155	.s_ctrl = rga_s_ctrl,
156};
157
158static int rga_setup_ctrls(struct rga_ctx *ctx)
159{
160	struct rockchip_rga *rga = ctx->rga;
161
162	v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
163
164	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
165			  V4L2_CID_HFLIP, 0, 1, 1, 0);
166
167	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
168			  V4L2_CID_VFLIP, 0, 1, 1, 0);
169
170	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
171			  V4L2_CID_ROTATE, 0, 270, 90, 0);
172
173	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
174			  V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
175
176	if (ctx->ctrl_handler.error) {
177		int err = ctx->ctrl_handler.error;
178
179		v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
180		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
181		return err;
182	}
183
184	return 0;
185}
186
187static struct rga_fmt formats[] = {
188	{
189		.fourcc = V4L2_PIX_FMT_ARGB32,
190		.color_swap = RGA_COLOR_ALPHA_SWAP,
191		.hw_format = RGA_COLOR_FMT_ABGR8888,
192		.depth = 32,
193		.uv_factor = 1,
194		.y_div = 1,
195		.x_div = 1,
196	},
197	{
198		.fourcc = V4L2_PIX_FMT_ABGR32,
199		.color_swap = RGA_COLOR_RB_SWAP,
200		.hw_format = RGA_COLOR_FMT_ABGR8888,
201		.depth = 32,
202		.uv_factor = 1,
203		.y_div = 1,
204		.x_div = 1,
205	},
206	{
207		.fourcc = V4L2_PIX_FMT_XBGR32,
208		.color_swap = RGA_COLOR_RB_SWAP,
209		.hw_format = RGA_COLOR_FMT_XBGR8888,
210		.depth = 32,
211		.uv_factor = 1,
212		.y_div = 1,
213		.x_div = 1,
214	},
215	{
216		.fourcc = V4L2_PIX_FMT_RGB24,
217		.color_swap = RGA_COLOR_NONE_SWAP,
218		.hw_format = RGA_COLOR_FMT_RGB888,
219		.depth = 24,
220		.uv_factor = 1,
221		.y_div = 1,
222		.x_div = 1,
223	},
224	{
225		.fourcc = V4L2_PIX_FMT_BGR24,
226		.color_swap = RGA_COLOR_RB_SWAP,
227		.hw_format = RGA_COLOR_FMT_RGB888,
228		.depth = 24,
229		.uv_factor = 1,
230		.y_div = 1,
231		.x_div = 1,
232	},
233	{
234		.fourcc = V4L2_PIX_FMT_ARGB444,
235		.color_swap = RGA_COLOR_RB_SWAP,
236		.hw_format = RGA_COLOR_FMT_ABGR4444,
237		.depth = 16,
238		.uv_factor = 1,
239		.y_div = 1,
240		.x_div = 1,
241	},
242	{
243		.fourcc = V4L2_PIX_FMT_ARGB555,
244		.color_swap = RGA_COLOR_RB_SWAP,
245		.hw_format = RGA_COLOR_FMT_ABGR1555,
246		.depth = 16,
247		.uv_factor = 1,
248		.y_div = 1,
249		.x_div = 1,
250	},
251	{
252		.fourcc = V4L2_PIX_FMT_RGB565,
253		.color_swap = RGA_COLOR_RB_SWAP,
254		.hw_format = RGA_COLOR_FMT_BGR565,
255		.depth = 16,
256		.uv_factor = 1,
257		.y_div = 1,
258		.x_div = 1,
259	},
260	{
261		.fourcc = V4L2_PIX_FMT_NV21,
262		.color_swap = RGA_COLOR_UV_SWAP,
263		.hw_format = RGA_COLOR_FMT_YUV420SP,
264		.depth = 12,
265		.uv_factor = 4,
266		.y_div = 2,
267		.x_div = 1,
268	},
269	{
270		.fourcc = V4L2_PIX_FMT_NV61,
271		.color_swap = RGA_COLOR_UV_SWAP,
272		.hw_format = RGA_COLOR_FMT_YUV422SP,
273		.depth = 16,
274		.uv_factor = 2,
275		.y_div = 1,
276		.x_div = 1,
277	},
278	{
279		.fourcc = V4L2_PIX_FMT_NV12,
280		.color_swap = RGA_COLOR_NONE_SWAP,
281		.hw_format = RGA_COLOR_FMT_YUV420SP,
282		.depth = 12,
283		.uv_factor = 4,
284		.y_div = 2,
285		.x_div = 1,
286	},
287	{
288		.fourcc = V4L2_PIX_FMT_NV12M,
289		.color_swap = RGA_COLOR_NONE_SWAP,
290		.hw_format = RGA_COLOR_FMT_YUV420SP,
291		.depth = 12,
292		.uv_factor = 4,
293		.y_div = 2,
294		.x_div = 1,
295	},
296	{
297		.fourcc = V4L2_PIX_FMT_NV16,
298		.color_swap = RGA_COLOR_NONE_SWAP,
299		.hw_format = RGA_COLOR_FMT_YUV422SP,
300		.depth = 16,
301		.uv_factor = 2,
302		.y_div = 1,
303		.x_div = 1,
304	},
305	{
306		.fourcc = V4L2_PIX_FMT_YUV420,
307		.color_swap = RGA_COLOR_NONE_SWAP,
308		.hw_format = RGA_COLOR_FMT_YUV420P,
309		.depth = 12,
310		.uv_factor = 4,
311		.y_div = 2,
312		.x_div = 2,
313	},
314	{
315		.fourcc = V4L2_PIX_FMT_YUV422P,
316		.color_swap = RGA_COLOR_NONE_SWAP,
317		.hw_format = RGA_COLOR_FMT_YUV422P,
318		.depth = 16,
319		.uv_factor = 2,
320		.y_div = 1,
321		.x_div = 2,
322	},
323	{
324		.fourcc = V4L2_PIX_FMT_YVU420,
325		.color_swap = RGA_COLOR_UV_SWAP,
326		.hw_format = RGA_COLOR_FMT_YUV420P,
327		.depth = 12,
328		.uv_factor = 4,
329		.y_div = 2,
330		.x_div = 2,
331	},
332};
333
334#define NUM_FORMATS ARRAY_SIZE(formats)
335
336static struct rga_fmt *rga_fmt_find(u32 pixelformat)
337{
338	unsigned int i;
339
340	for (i = 0; i < NUM_FORMATS; i++) {
341		if (formats[i].fourcc == pixelformat)
342			return &formats[i];
343	}
344	return NULL;
345}
346
347static struct rga_frame def_frame = {
348	.width = DEFAULT_WIDTH,
349	.height = DEFAULT_HEIGHT,
350	.colorspace = V4L2_COLORSPACE_DEFAULT,
351	.crop.left = 0,
352	.crop.top = 0,
353	.crop.width = DEFAULT_WIDTH,
354	.crop.height = DEFAULT_HEIGHT,
355	.fmt = &formats[0],
356};
357
358struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
359{
360	if (V4L2_TYPE_IS_OUTPUT(type))
361		return &ctx->in;
362	if (V4L2_TYPE_IS_CAPTURE(type))
363		return &ctx->out;
364	return ERR_PTR(-EINVAL);
365}
366
367static int rga_open(struct file *file)
368{
369	struct rockchip_rga *rga = video_drvdata(file);
370	struct rga_ctx *ctx = NULL;
371	int ret = 0;
372
373	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
374	if (!ctx)
375		return -ENOMEM;
376	ctx->rga = rga;
377	/* Set default formats */
378	ctx->in = def_frame;
379	ctx->out = def_frame;
380
381	v4l2_fill_pixfmt_mp(&ctx->in.pix,
382			    ctx->in.fmt->fourcc, ctx->out.width, ctx->out.height);
383	v4l2_fill_pixfmt_mp(&ctx->out.pix,
384			    ctx->out.fmt->fourcc, ctx->out.width, ctx->out.height);
385
386	if (mutex_lock_interruptible(&rga->mutex)) {
387		kfree(ctx);
388		return -ERESTARTSYS;
389	}
390	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
391	if (IS_ERR(ctx->fh.m2m_ctx)) {
392		ret = PTR_ERR(ctx->fh.m2m_ctx);
393		mutex_unlock(&rga->mutex);
394		kfree(ctx);
395		return ret;
396	}
397	v4l2_fh_init(&ctx->fh, video_devdata(file));
398	v4l2_fh_add(&ctx->fh, file);
399
400	rga_setup_ctrls(ctx);
401
402	/* Write the default values to the ctx struct */
403	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
404
405	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
406	mutex_unlock(&rga->mutex);
407
408	return 0;
409}
410
411static int rga_release(struct file *file)
412{
413	struct rga_ctx *ctx = file_to_rga_ctx(file);
414	struct rockchip_rga *rga = ctx->rga;
415
416	mutex_lock(&rga->mutex);
417
418	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
419
420	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
421	v4l2_fh_del(&ctx->fh, file);
422	v4l2_fh_exit(&ctx->fh);
423	kfree(ctx);
424
425	mutex_unlock(&rga->mutex);
426
427	return 0;
428}
429
430static const struct v4l2_file_operations rga_fops = {
431	.owner = THIS_MODULE,
432	.open = rga_open,
433	.release = rga_release,
434	.poll = v4l2_m2m_fop_poll,
435	.unlocked_ioctl = video_ioctl2,
436	.mmap = v4l2_m2m_fop_mmap,
437};
438
439static int
440vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
441{
442	strscpy(cap->driver, RGA_NAME, sizeof(cap->driver));
443	strscpy(cap->card, "rockchip-rga", sizeof(cap->card));
444	strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
445
446	return 0;
447}
448
449static int vidioc_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f)
450{
451	struct rga_fmt *fmt;
452
453	if (f->index >= NUM_FORMATS)
454		return -EINVAL;
455
456	fmt = &formats[f->index];
457	f->pixelformat = fmt->fourcc;
458
459	return 0;
460}
461
462static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
463{
464	struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp;
465	struct rga_ctx *ctx = file_to_rga_ctx(file);
466	struct rga_frame *frm;
467
468	frm = rga_get_frame(ctx, f->type);
469	if (IS_ERR(frm))
470		return PTR_ERR(frm);
471
472	v4l2_fill_pixfmt_mp(pix_fmt, frm->fmt->fourcc, frm->width, frm->height);
473
474	pix_fmt->field = V4L2_FIELD_NONE;
475	pix_fmt->colorspace = frm->colorspace;
476
477	return 0;
478}
479
480static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
481{
482	struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp;
483	struct rga_fmt *fmt;
484
485	fmt = rga_fmt_find(pix_fmt->pixelformat);
486	if (!fmt)
487		fmt = &formats[0];
488
489	pix_fmt->width = clamp(pix_fmt->width,
490			       (u32)MIN_WIDTH, (u32)MAX_WIDTH);
491	pix_fmt->height = clamp(pix_fmt->height,
492				(u32)MIN_HEIGHT, (u32)MAX_HEIGHT);
493
494	v4l2_fill_pixfmt_mp(pix_fmt, fmt->fourcc, pix_fmt->width, pix_fmt->height);
495	pix_fmt->field = V4L2_FIELD_NONE;
496
497	return 0;
498}
499
500static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
501{
502	struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp;
503	struct rga_ctx *ctx = file_to_rga_ctx(file);
504	struct rockchip_rga *rga = ctx->rga;
505	struct vb2_queue *vq;
506	struct rga_frame *frm;
507	int ret = 0;
508	int i;
509
510	/* Adjust all values accordingly to the hardware capabilities
511	 * and chosen format.
512	 */
513	ret = vidioc_try_fmt(file, priv, f);
514	if (ret)
515		return ret;
516	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
517	if (vb2_is_busy(vq)) {
518		v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
519		return -EBUSY;
520	}
521	frm = rga_get_frame(ctx, f->type);
522	if (IS_ERR(frm))
523		return PTR_ERR(frm);
524	frm->width = pix_fmt->width;
525	frm->height = pix_fmt->height;
526	frm->size = 0;
527	for (i = 0; i < pix_fmt->num_planes; i++)
528		frm->size += pix_fmt->plane_fmt[i].sizeimage;
529	frm->fmt = rga_fmt_find(pix_fmt->pixelformat);
530	frm->stride = pix_fmt->plane_fmt[0].bytesperline;
531	frm->colorspace = pix_fmt->colorspace;
532
533	/* Reset crop settings */
534	frm->crop.left = 0;
535	frm->crop.top = 0;
536	frm->crop.width = frm->width;
537	frm->crop.height = frm->height;
538
539	frm->pix = *pix_fmt;
540
541	v4l2_dbg(debug, 1, &rga->v4l2_dev,
542		 "[%s] fmt - %p4cc %dx%d (stride %d, sizeimage %d)\n",
543		  V4L2_TYPE_IS_OUTPUT(f->type) ? "OUTPUT" : "CAPTURE",
544		  &frm->fmt->fourcc, frm->width, frm->height,
545		  frm->stride, frm->size);
546
547	for (i = 0; i < pix_fmt->num_planes; i++) {
548		v4l2_dbg(debug, 1, &rga->v4l2_dev,
549			 "plane[%d]: size %d, bytesperline %d\n",
550			 i, pix_fmt->plane_fmt[i].sizeimage,
551			 pix_fmt->plane_fmt[i].bytesperline);
552	}
553
554	return 0;
555}
556
557static int vidioc_g_selection(struct file *file, void *priv,
558			      struct v4l2_selection *s)
559{
560	struct rga_ctx *ctx = file_to_rga_ctx(file);
561	struct rga_frame *f;
562	bool use_frame = false;
563
564	f = rga_get_frame(ctx, s->type);
565	if (IS_ERR(f))
566		return PTR_ERR(f);
567
568	switch (s->target) {
569	case V4L2_SEL_TGT_COMPOSE_DEFAULT:
570	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
571		if (!V4L2_TYPE_IS_CAPTURE(s->type))
572			return -EINVAL;
573		break;
574	case V4L2_SEL_TGT_CROP_DEFAULT:
575	case V4L2_SEL_TGT_CROP_BOUNDS:
576		if (!V4L2_TYPE_IS_OUTPUT(s->type))
577			return -EINVAL;
578		break;
579	case V4L2_SEL_TGT_COMPOSE:
580		if (!V4L2_TYPE_IS_CAPTURE(s->type))
581			return -EINVAL;
582		use_frame = true;
583		break;
584	case V4L2_SEL_TGT_CROP:
585		if (!V4L2_TYPE_IS_OUTPUT(s->type))
586			return -EINVAL;
587		use_frame = true;
588		break;
589	default:
590		return -EINVAL;
591	}
592
593	if (use_frame) {
594		s->r = f->crop;
595	} else {
596		s->r.left = 0;
597		s->r.top = 0;
598		s->r.width = f->width;
599		s->r.height = f->height;
600	}
601
602	return 0;
603}
604
605static int vidioc_s_selection(struct file *file, void *priv,
606			      struct v4l2_selection *s)
607{
608	struct rga_ctx *ctx = file_to_rga_ctx(file);
609	struct rockchip_rga *rga = ctx->rga;
610	struct rga_frame *f;
611	int ret = 0;
612
613	f = rga_get_frame(ctx, s->type);
614	if (IS_ERR(f))
615		return PTR_ERR(f);
616
617	switch (s->target) {
618	case V4L2_SEL_TGT_COMPOSE:
619		/*
620		 * COMPOSE target is only valid for capture buffer type, return
621		 * error for output buffer type
622		 */
623		if (!V4L2_TYPE_IS_CAPTURE(s->type))
624			return -EINVAL;
625		break;
626	case V4L2_SEL_TGT_CROP:
627		/*
628		 * CROP target is only valid for output buffer type, return
629		 * error for capture buffer type
630		 */
631		if (!V4L2_TYPE_IS_OUTPUT(s->type))
632			return -EINVAL;
633		break;
634	/*
635	 * bound and default crop/compose targets are invalid targets to
636	 * try/set
637	 */
638	default:
639		return -EINVAL;
640	}
641
642	if (s->r.top < 0 || s->r.left < 0) {
643		v4l2_dbg(debug, 1, &rga->v4l2_dev,
644			 "doesn't support negative values for top & left.\n");
645		return -EINVAL;
646	}
647
648	if (s->r.left + s->r.width > f->width ||
649	    s->r.top + s->r.height > f->height ||
650	    s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
651		v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
652		return -EINVAL;
653	}
654
655	f->crop = s->r;
656
657	return ret;
658}
659
660static const struct v4l2_ioctl_ops rga_ioctl_ops = {
661	.vidioc_querycap = vidioc_querycap,
662
663	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
664	.vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt,
665	.vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt,
666	.vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt,
667
668	.vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
669	.vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt,
670	.vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt,
671	.vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt,
672
673	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
674	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
675	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
676	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
677	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
678	.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
679	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
680
681	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
682	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
683
684	.vidioc_streamon = v4l2_m2m_ioctl_streamon,
685	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
686
687	.vidioc_g_selection = vidioc_g_selection,
688	.vidioc_s_selection = vidioc_s_selection,
689};
690
691static const struct video_device rga_videodev = {
692	.name = "rockchip-rga",
693	.fops = &rga_fops,
694	.ioctl_ops = &rga_ioctl_ops,
695	.minor = -1,
696	.release = video_device_release,
697	.vfl_dir = VFL_DIR_M2M,
698	.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
699};
700
701static int rga_enable_clocks(struct rockchip_rga *rga)
702{
703	int ret;
704
705	ret = clk_prepare_enable(rga->sclk);
706	if (ret) {
707		dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
708		return ret;
709	}
710
711	ret = clk_prepare_enable(rga->aclk);
712	if (ret) {
713		dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
714		goto err_disable_sclk;
715	}
716
717	ret = clk_prepare_enable(rga->hclk);
718	if (ret) {
719		dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
720		goto err_disable_aclk;
721	}
722
723	return 0;
724
725err_disable_aclk:
726	clk_disable_unprepare(rga->aclk);
727err_disable_sclk:
728	clk_disable_unprepare(rga->sclk);
729
730	return ret;
731}
732
733static void rga_disable_clocks(struct rockchip_rga *rga)
734{
735	clk_disable_unprepare(rga->sclk);
736	clk_disable_unprepare(rga->hclk);
737	clk_disable_unprepare(rga->aclk);
738}
739
740static int rga_parse_dt(struct rockchip_rga *rga)
741{
742	struct reset_control *core_rst, *axi_rst, *ahb_rst;
743
744	core_rst = devm_reset_control_get(rga->dev, "core");
745	if (IS_ERR(core_rst)) {
746		dev_err(rga->dev, "failed to get core reset controller\n");
747		return PTR_ERR(core_rst);
748	}
749
750	axi_rst = devm_reset_control_get(rga->dev, "axi");
751	if (IS_ERR(axi_rst)) {
752		dev_err(rga->dev, "failed to get axi reset controller\n");
753		return PTR_ERR(axi_rst);
754	}
755
756	ahb_rst = devm_reset_control_get(rga->dev, "ahb");
757	if (IS_ERR(ahb_rst)) {
758		dev_err(rga->dev, "failed to get ahb reset controller\n");
759		return PTR_ERR(ahb_rst);
760	}
761
762	reset_control_assert(core_rst);
763	udelay(1);
764	reset_control_deassert(core_rst);
765
766	reset_control_assert(axi_rst);
767	udelay(1);
768	reset_control_deassert(axi_rst);
769
770	reset_control_assert(ahb_rst);
771	udelay(1);
772	reset_control_deassert(ahb_rst);
773
774	rga->sclk = devm_clk_get(rga->dev, "sclk");
775	if (IS_ERR(rga->sclk)) {
776		dev_err(rga->dev, "failed to get sclk clock\n");
777		return PTR_ERR(rga->sclk);
778	}
779
780	rga->aclk = devm_clk_get(rga->dev, "aclk");
781	if (IS_ERR(rga->aclk)) {
782		dev_err(rga->dev, "failed to get aclk clock\n");
783		return PTR_ERR(rga->aclk);
784	}
785
786	rga->hclk = devm_clk_get(rga->dev, "hclk");
787	if (IS_ERR(rga->hclk)) {
788		dev_err(rga->dev, "failed to get hclk clock\n");
789		return PTR_ERR(rga->hclk);
790	}
791
792	return 0;
793}
794
795static int rga_probe(struct platform_device *pdev)
796{
797	struct rockchip_rga *rga;
798	struct video_device *vfd;
799	int ret = 0;
800	int irq;
801
802	if (!pdev->dev.of_node)
803		return -ENODEV;
804
805	rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
806	if (!rga)
807		return -ENOMEM;
808
809	rga->dev = &pdev->dev;
810	spin_lock_init(&rga->ctrl_lock);
811	mutex_init(&rga->mutex);
812
813	ret = rga_parse_dt(rga);
814	if (ret)
815		return dev_err_probe(&pdev->dev, ret, "Unable to parse OF data\n");
816
817	pm_runtime_enable(rga->dev);
818
819	rga->regs = devm_platform_ioremap_resource(pdev, 0);
820	if (IS_ERR(rga->regs)) {
821		ret = PTR_ERR(rga->regs);
822		goto err_put_clk;
823	}
824
825	irq = platform_get_irq(pdev, 0);
826	if (irq < 0) {
827		ret = irq;
828		goto err_put_clk;
829	}
830
831	ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
832			       dev_name(rga->dev), rga);
833	if (ret < 0) {
834		dev_err(rga->dev, "failed to request irq\n");
835		goto err_put_clk;
836	}
837
838	ret = dma_set_mask_and_coherent(rga->dev, DMA_BIT_MASK(32));
839	if (ret) {
840		dev_err(rga->dev, "32-bit DMA not supported");
841		goto err_put_clk;
842	}
843
844	ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
845	if (ret)
846		goto err_put_clk;
847	vfd = video_device_alloc();
848	if (!vfd) {
849		v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
850		ret = -ENOMEM;
851		goto unreg_v4l2_dev;
852	}
853	*vfd = rga_videodev;
854	vfd->lock = &rga->mutex;
855	vfd->v4l2_dev = &rga->v4l2_dev;
856
857	video_set_drvdata(vfd, rga);
858	rga->vfd = vfd;
859
860	platform_set_drvdata(pdev, rga);
861	rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
862	if (IS_ERR(rga->m2m_dev)) {
863		v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
864		ret = PTR_ERR(rga->m2m_dev);
865		goto rel_vdev;
866	}
867
868	ret = pm_runtime_resume_and_get(rga->dev);
869	if (ret < 0)
870		goto rel_m2m;
871
872	rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
873	rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
874
875	v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
876		  rga->version.major, rga->version.minor);
877
878	pm_runtime_put(rga->dev);
879
880	/* Create CMD buffer */
881	rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
882					   &rga->cmdbuf_phy, GFP_KERNEL,
883					   DMA_ATTR_WRITE_COMBINE);
884	if (!rga->cmdbuf_virt) {
885		ret = -ENOMEM;
886		goto rel_m2m;
887	}
888
889	def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
890	def_frame.size = def_frame.stride * def_frame.height;
891
892	ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
893	if (ret) {
894		v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
895		goto free_dma;
896	}
897
898	v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
899		  vfd->name, video_device_node_name(vfd));
900
901	return 0;
902
903free_dma:
904	dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
905		       rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
906rel_m2m:
907	v4l2_m2m_release(rga->m2m_dev);
908rel_vdev:
909	video_device_release(vfd);
910unreg_v4l2_dev:
911	v4l2_device_unregister(&rga->v4l2_dev);
912err_put_clk:
913	pm_runtime_disable(rga->dev);
914
915	return ret;
916}
917
918static void rga_remove(struct platform_device *pdev)
919{
920	struct rockchip_rga *rga = platform_get_drvdata(pdev);
921
922	dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
923		       rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
924
925	v4l2_info(&rga->v4l2_dev, "Removing\n");
926
927	v4l2_m2m_release(rga->m2m_dev);
928	video_unregister_device(rga->vfd);
929	v4l2_device_unregister(&rga->v4l2_dev);
930
931	pm_runtime_disable(rga->dev);
932}
933
934static int __maybe_unused rga_runtime_suspend(struct device *dev)
935{
936	struct rockchip_rga *rga = dev_get_drvdata(dev);
937
938	rga_disable_clocks(rga);
939
940	return 0;
941}
942
943static int __maybe_unused rga_runtime_resume(struct device *dev)
944{
945	struct rockchip_rga *rga = dev_get_drvdata(dev);
946
947	return rga_enable_clocks(rga);
948}
949
950static const struct dev_pm_ops rga_pm = {
951	SET_RUNTIME_PM_OPS(rga_runtime_suspend,
952			   rga_runtime_resume, NULL)
953};
954
955static const struct of_device_id rockchip_rga_match[] = {
956	{
957		.compatible = "rockchip,rk3288-rga",
958	},
959	{
960		.compatible = "rockchip,rk3399-rga",
961	},
962	{},
963};
964
965MODULE_DEVICE_TABLE(of, rockchip_rga_match);
966
967static struct platform_driver rga_pdrv = {
968	.probe = rga_probe,
969	.remove = rga_remove,
970	.driver = {
971		.name = RGA_NAME,
972		.pm = &rga_pm,
973		.of_match_table = rockchip_rga_match,
974	},
975};
976
977module_platform_driver(rga_pdrv);
978
979MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
980MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit");
981MODULE_LICENSE("GPL");