rzv2h-ivc.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Renesas RZ/V2H(P) Input Video Control Block driver
  4 *
  5 * Copyright (C) 2025 Ideas on Board Oy
  6 */
  7
  8#include <linux/clk.h>
  9#include <linux/list.h>
 10#include <linux/mutex.h>
 11#include <linux/reset.h>
 12#include <linux/spinlock.h>
 13#include <linux/types.h>
 14#include <linux/videodev2.h>
 15#include <linux/workqueue.h>
 16
 17#include <media/media-entity.h>
 18#include <media/v4l2-device.h>
 19#include <media/v4l2-subdev.h>
 20#include <media/videobuf2-core.h>
 21#include <media/videobuf2-v4l2.h>
 22
 23#define RZV2H_IVC_REG_AXIRX_PLNUM			0x0000
 24#define RZV2H_IVC_ONE_EXPOSURE				0x00
 25#define RZV2H_IVC_TWO_EXPOSURE				0x01
 26#define RZV2H_IVC_REG_AXIRX_PXFMT			0x0004
 27#define RZV2H_IVC_INPUT_FMT_MIPI			(0 << 16)
 28#define RZV2H_IVC_INPUT_FMT_CRU_PACKED			BIT(16)
 29#define RZV2H_IVC_PXFMT_DTYPE				GENMASK(7, 0)
 30#define RZV2H_IVC_REG_AXIRX_SADDL_P0			0x0010
 31#define RZV2H_IVC_REG_AXIRX_SADDH_P0			0x0014
 32#define RZV2H_IVC_REG_AXIRX_SADDL_P1			0x0018
 33#define RZV2H_IVC_REG_AXIRX_SADDH_P1			0x001c
 34#define RZV2H_IVC_REG_AXIRX_HSIZE			0x0020
 35#define RZV2H_IVC_REG_AXIRX_VSIZE			0x0024
 36#define RZV2H_IVC_REG_AXIRX_BLANK			0x0028
 37#define RZV2H_IVC_VBLANK(x)				((x) << 16)
 38#define RZV2H_IVC_REG_AXIRX_STRD			0x0030
 39#define RZV2H_IVC_REG_AXIRX_ISSU			0x0040
 40#define RZV2H_IVC_REG_AXIRX_ERACT			0x0048
 41#define RZV2H_IVC_REG_FM_CONTEXT			0x0100
 42#define RZV2H_IVC_SOFTWARE_CFG				0x00
 43#define RZV2H_IVC_SINGLE_CONTEXT_SW_HW_CFG		BIT(0)
 44#define RZV2H_IVC_MULTI_CONTEXT_SW_HW_CFG		BIT(1)
 45#define RZV2H_IVC_REG_FM_MCON				0x0104
 46#define RZV2H_IVC_REG_FM_FRCON				0x0108
 47#define RZV2H_IVC_REG_FM_STOP				0x010c
 48#define RZV2H_IVC_REG_FM_INT_EN				0x0120
 49#define RZV2H_IVC_VVAL_IFPE				BIT(0)
 50#define RZV2H_IVC_REG_FM_INT_STA			0x0124
 51#define RZV2H_IVC_REG_AXIRX_FIFOCAP0			0x0208
 52#define RZV2H_IVC_REG_CORE_CAPCON			0x020c
 53#define RZV2H_IVC_REG_CORE_FIFOCAP0			0x0228
 54#define RZV2H_IVC_REG_CORE_FIFOCAP1			0x022c
 55
 56#define RZV2H_IVC_MIN_WIDTH				640
 57#define RZV2H_IVC_MAX_WIDTH				4096
 58#define RZV2H_IVC_MIN_HEIGHT				480
 59#define RZV2H_IVC_MAX_HEIGHT				4096
 60#define RZV2H_IVC_DEFAULT_WIDTH				1920
 61#define RZV2H_IVC_DEFAULT_HEIGHT			1080
 62
 63#define RZV2H_IVC_NUM_HW_RESOURCES			3
 64
 65struct device;
 66
 67enum rzv2h_ivc_subdev_pads {
 68	RZV2H_IVC_SUBDEV_SINK_PAD,
 69	RZV2H_IVC_SUBDEV_SOURCE_PAD,
 70	RZV2H_IVC_NUM_SUBDEV_PADS
 71};
 72
 73struct rzv2h_ivc_format {
 74	u32 fourcc;
 75	/*
 76	 * The CRU packed pixel formats are bayer-order agnostic, so each could
 77	 * support any one of the 4 possible media bus formats.
 78	 */
 79	u32 mbus_codes[4];
 80	u8 dtype;
 81};
 82
 83struct rzv2h_ivc {
 84	struct device *dev;
 85	void __iomem *base;
 86	struct clk_bulk_data clks[RZV2H_IVC_NUM_HW_RESOURCES];
 87	struct reset_control_bulk_data resets[RZV2H_IVC_NUM_HW_RESOURCES];
 88	int irqnum;
 89	u8 vvalid_ifp;
 90
 91	struct {
 92		struct video_device dev;
 93		struct vb2_queue vb2q;
 94		struct media_pad pad;
 95	} vdev;
 96
 97	struct {
 98		struct v4l2_subdev sd;
 99		struct media_pad pads[RZV2H_IVC_NUM_SUBDEV_PADS];
100	} subdev;
101
102	struct {
103		/* Spinlock to guard buffer queue */
104		spinlock_t lock;
105		struct workqueue_struct *async_wq;
106		struct work_struct work;
107		struct list_head queue;
108		struct rzv2h_ivc_buf *curr;
109		unsigned int sequence;
110	} buffers;
111
112	struct {
113		struct v4l2_pix_format_mplane pix;
114		const struct rzv2h_ivc_format *fmt;
115	} format;
116
117	/* Mutex to provide to vb2 */
118	struct mutex lock;
119	/* Lock to protect the interrupt counter */
120	spinlock_t spinlock;
121};
122
123int rzv2h_ivc_init_vdev(struct rzv2h_ivc *ivc, struct v4l2_device *v4l2_dev);
124void rzv2h_deinit_video_dev_and_queue(struct rzv2h_ivc *ivc);
125void rzv2h_ivc_buffer_done(struct rzv2h_ivc *ivc);
126int rzv2h_ivc_initialise_subdevice(struct rzv2h_ivc *ivc);
127void rzv2h_ivc_deinit_subdevice(struct rzv2h_ivc *ivc);
128void rzv2h_ivc_write(struct rzv2h_ivc *ivc, u32 addr, u32 val);
129void rzv2h_ivc_update_bits(struct rzv2h_ivc *ivc, unsigned int addr,
130			   u32 mask, u32 val);