rzg2l-csi2.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver
   4 *
   5 * Copyright (C) 2022 Renesas Electronics Corp.
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/delay.h>
  10#include <linux/interrupt.h>
  11#include <linux/io.h>
  12#include <linux/module.h>
  13#include <linux/of.h>
  14#include <linux/of_graph.h>
  15#include <linux/platform_device.h>
  16#include <linux/pm_runtime.h>
  17#include <linux/reset.h>
  18#include <linux/sys_soc.h>
  19#include <linux/units.h>
  20
  21#include <media/v4l2-ctrls.h>
  22#include <media/v4l2-device.h>
  23#include <media/v4l2-fwnode.h>
  24#include <media/v4l2-mc.h>
  25#include <media/v4l2-subdev.h>
  26
  27/* LINK registers */
  28/* Module Configuration Register */
  29#define CSI2nMCG			0x0
  30#define CSI2nMCG_SDLN			GENMASK(11, 8)
  31
  32/* Module Control Register 0 */
  33#define CSI2nMCT0			0x10
  34#define CSI2nMCT0_VDLN(x)		((x) << 0)
  35
  36/* Module Control Register 2 */
  37#define CSI2nMCT2			0x18
  38#define CSI2nMCT2_FRRSKW(x)		((x) << 16)
  39#define CSI2nMCT2_FRRCLK(x)		((x) << 0)
  40
  41/* Module Control Register 3 */
  42#define CSI2nMCT3			0x1c
  43#define CSI2nMCT3_RXEN			BIT(0)
  44
  45/* Reset Control Register */
  46#define CSI2nRTCT			0x28
  47#define CSI2nRTCT_VSRST			BIT(0)
  48
  49/* Reset Status Register */
  50#define CSI2nRTST			0x2c
  51#define CSI2nRTST_VSRSTS		BIT(0)
  52
  53/* Receive Data Type Enable Low Register */
  54#define CSI2nDTEL			0x60
  55
  56/* Receive Data Type Enable High Register */
  57#define CSI2nDTEH			0x64
  58
  59/* DPHY registers */
  60/* D-PHY Control Register 0 */
  61#define CSIDPHYCTRL0			0x400
  62#define CSIDPHYCTRL0_EN_LDO1200		BIT(1)
  63#define CSIDPHYCTRL0_EN_BGR		BIT(0)
  64
  65/* D-PHY Timing Register 0 */
  66#define CSIDPHYTIM0			0x404
  67#define CSIDPHYTIM0_TCLK_MISS(x)	((x) << 24)
  68#define CSIDPHYTIM0_T_INIT(x)		((x) << 0)
  69
  70/* D-PHY Timing Register 1 */
  71#define CSIDPHYTIM1			0x408
  72#define CSIDPHYTIM1_THS_PREPARE(x)	((x) << 24)
  73#define CSIDPHYTIM1_TCLK_PREPARE(x)	((x) << 16)
  74#define CSIDPHYTIM1_THS_SETTLE(x)	((x) << 8)
  75#define CSIDPHYTIM1_TCLK_SETTLE(x)	((x) << 0)
  76
  77/* D-PHY Skew Adjustment Function */
  78#define CSIDPHYSKW0			0x460
  79#define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x)	((x) & 0x3)
  80#define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x)	(((x) & 0x3) << 4)
  81#define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x)	(((x) & 0x3) << 8)
  82#define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x)	(((x) & 0x3) << 12)
  83#define CSIDPHYSKW0_DEFAULT_SKW		(CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \
  84					 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \
  85					 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \
  86					 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1))
  87
  88/* DPHY registers on RZ/V2H(P) SoC */
  89#define CRUm_S_TIMCTL			0x41c
  90#define CRUm_S_TIMCTL_S_HSSETTLECTL(x)	((x) << 8)
  91
  92#define CRUm_S_DPHYCTL_MSB		0x434
  93#define CRUm_S_DPHYCTL_MSB_DESKEW	BIT(1)
  94
  95#define CRUm_SWAPCTL			0x438
  96
  97#define VSRSTS_RETRIES			20
  98
  99#define RZG2L_CSI2_DEFAULT_FMT		MEDIA_BUS_FMT_UYVY8_1X16
 100
 101enum rzg2l_csi2_pads {
 102	RZG2L_CSI2_SINK = 0,
 103	RZG2L_CSI2_SOURCE,
 104	NR_OF_RZG2L_CSI2_PAD,
 105};
 106
 107struct rzg2l_csi2 {
 108	struct device *dev;
 109	void __iomem *base;
 110	struct reset_control *presetn;
 111	struct reset_control *cmn_rstb;
 112	const struct rzg2l_csi2_info *info;
 113	struct clk *sysclk;
 114	struct clk *vclk;
 115	unsigned long vclk_rate;
 116
 117	struct v4l2_subdev subdev;
 118	struct media_pad pads[NR_OF_RZG2L_CSI2_PAD];
 119
 120	struct v4l2_async_notifier notifier;
 121	struct v4l2_subdev *remote_source;
 122
 123	unsigned short lanes;
 124	unsigned long hsfreq;
 125
 126	bool dphy_enabled;
 127};
 128
 129struct rzg2l_csi2_info {
 130	int (*dphy_enable)(struct rzg2l_csi2 *csi2);
 131	int (*dphy_disable)(struct rzg2l_csi2 *csi2);
 132	bool has_system_clk;
 133	unsigned int min_width;
 134	unsigned int min_height;
 135	unsigned int max_width;
 136	unsigned int max_height;
 137};
 138
 139struct rzg2l_csi2_timings {
 140	u32 t_init;
 141	u32 tclk_miss;
 142	u32 tclk_settle;
 143	u32 ths_settle;
 144	u32 tclk_prepare;
 145	u32 ths_prepare;
 146	u32 max_hsfreq;
 147};
 148
 149struct rzv2h_csi2_s_hssettlectl {
 150	unsigned int hsfreq;
 151	u16 s_hssettlectl;
 152};
 153
 154static const struct rzv2h_csi2_s_hssettlectl rzv2h_s_hssettlectl[] = {
 155	{   90,  1 }, {  130,  2 }, {  180,  3 },
 156	{  220,  4 }, {  270,  5 }, {  310,  6 },
 157	{  360,  7 }, {  400,  8 }, {  450,  9 },
 158	{  490, 10 }, {  540, 11 }, {  580, 12 },
 159	{  630, 13 }, {  670, 14 }, {  720, 15 },
 160	{  760, 16 }, {  810, 17 }, {  850, 18 },
 161	{  900, 19 }, {  940, 20 }, {  990, 21 },
 162	{ 1030, 22 }, { 1080, 23 }, { 1120, 24 },
 163	{ 1170, 25 }, { 1220, 26 }, { 1260, 27 },
 164	{ 1310, 28 }, { 1350, 29 }, { 1400, 30 },
 165	{ 1440, 31 }, { 1490, 32 }, { 1530, 33 },
 166	{ 1580, 34 }, { 1620, 35 }, { 1670, 36 },
 167	{ 1710, 37 }, { 1760, 38 }, { 1800, 39 },
 168	{ 1850, 40 }, { 1890, 41 }, { 1940, 42 },
 169	{ 1980, 43 }, { 2030, 44 }, { 2070, 45 },
 170	{ 2100, 46 },
 171};
 172
 173static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = {
 174	{
 175		.max_hsfreq = 80,
 176		.t_init = 79801,
 177		.tclk_miss = 4,
 178		.tclk_settle = 23,
 179		.ths_settle = 31,
 180		.tclk_prepare = 10,
 181		.ths_prepare = 19,
 182	},
 183	{
 184		.max_hsfreq = 125,
 185		.t_init = 79801,
 186		.tclk_miss = 4,
 187		.tclk_settle = 23,
 188		.ths_settle = 28,
 189		.tclk_prepare = 10,
 190		.ths_prepare = 19,
 191	},
 192	{
 193		.max_hsfreq = 250,
 194		.t_init = 79801,
 195		.tclk_miss = 4,
 196		.tclk_settle = 23,
 197		.ths_settle = 22,
 198		.tclk_prepare = 10,
 199		.ths_prepare = 16,
 200	},
 201	{
 202		.max_hsfreq = 360,
 203		.t_init = 79801,
 204		.tclk_miss = 4,
 205		.tclk_settle = 18,
 206		.ths_settle = 19,
 207		.tclk_prepare = 10,
 208		.ths_prepare = 10,
 209	},
 210	{
 211		.max_hsfreq = 1500,
 212		.t_init = 79801,
 213		.tclk_miss = 4,
 214		.tclk_settle = 18,
 215		.ths_settle = 18,
 216		.tclk_prepare = 10,
 217		.ths_prepare = 10,
 218	},
 219};
 220
 221struct rzg2l_csi2_format {
 222	u32 code;
 223	unsigned int bpp;
 224};
 225
 226static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = {
 227	{ .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16 },
 228	{ .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, },
 229	{ .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, },
 230	{ .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, },
 231	{ .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, },
 232	{ .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, },
 233	{ .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, },
 234	{ .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, },
 235	{ .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, },
 236	{ .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, },
 237	{ .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, },
 238	{ .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, },
 239	{ .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, },
 240	{ .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, },
 241	{ .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, },
 242	{ .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, },
 243	{ .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, },
 244};
 245
 246static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
 247{
 248	return container_of(sd, struct rzg2l_csi2, subdev);
 249}
 250
 251static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code)
 252{
 253	unsigned int i;
 254
 255	for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_formats); i++)
 256		if (rzg2l_csi2_formats[i].code == code)
 257			return &rzg2l_csi2_formats[i];
 258
 259	return NULL;
 260}
 261
 262static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
 263{
 264	return container_of(n, struct rzg2l_csi2, notifier);
 265}
 266
 267static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg)
 268{
 269	return ioread32(csi2->base + reg);
 270}
 271
 272static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg,
 273			     u32 data)
 274{
 275	iowrite32(data, csi2->base + reg);
 276}
 277
 278static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set)
 279{
 280	rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) | set);
 281}
 282
 283static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr)
 284{
 285	rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) & ~clr);
 286}
 287
 288static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2)
 289{
 290	struct v4l2_subdev *source = csi2->remote_source;
 291	const struct rzg2l_csi2_format *format;
 292	const struct v4l2_mbus_framefmt *fmt;
 293	struct v4l2_subdev_state *state;
 294	struct media_pad *remote_pad;
 295	u64 mbps;
 296	s64 ret;
 297
 298	if (!csi2->remote_source)
 299		return -ENODEV;
 300
 301	remote_pad = media_pad_remote_pad_unique(&csi2->pads[RZG2L_CSI2_SINK]);
 302	if (IS_ERR(remote_pad)) {
 303		dev_err(csi2->dev, "can't get source pad of %s (%pe)\n",
 304			csi2->remote_source->name, remote_pad);
 305		return PTR_ERR(remote_pad);
 306	}
 307
 308	state = v4l2_subdev_lock_and_get_active_state(&csi2->subdev);
 309	fmt = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);
 310	format = rzg2l_csi2_code_to_fmt(fmt->code);
 311	v4l2_subdev_unlock_state(state);
 312
 313	/* Read the link frequency from remote subdevice. */
 314	ret = v4l2_get_link_freq(remote_pad, format->bpp, csi2->lanes * 2);
 315	if (ret < 0) {
 316		dev_err(csi2->dev, "can't retrieve link freq from subdev %s\n",
 317			source->name);
 318		return -EINVAL;
 319	}
 320
 321	mbps = ret * 2;
 322	do_div(mbps, 1000000);
 323
 324	return mbps;
 325}
 326
 327/* -----------------------------------------------------------------------------
 328 * DPHY setting
 329 */
 330
 331static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2)
 332{
 333	int ret;
 334
 335	/* Reset the CRU (D-PHY) */
 336	ret = reset_control_assert(csi2->cmn_rstb);
 337	if (ret)
 338		return ret;
 339
 340	/* Stop the D-PHY clock */
 341	clk_disable_unprepare(csi2->sysclk);
 342
 343	/* Cancel the EN_LDO1200 register setting */
 344	rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);
 345
 346	/* Cancel the EN_BGR register setting */
 347	rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);
 348
 349	csi2->dphy_enabled = false;
 350
 351	return 0;
 352}
 353
 354static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2)
 355{
 356	const struct rzg2l_csi2_timings *dphy_timing;
 357	u32 dphytim0, dphytim1;
 358	unsigned int i;
 359	int mbps;
 360	int ret;
 361
 362	mbps = rzg2l_csi2_calc_mbps(csi2);
 363	if (mbps < 0)
 364		return mbps;
 365
 366	csi2->hsfreq = mbps;
 367
 368	/* Set DPHY timing parameters */
 369	for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_global_timings); ++i) {
 370		dphy_timing = &rzg2l_csi2_global_timings[i];
 371
 372		if (csi2->hsfreq <= dphy_timing->max_hsfreq)
 373			break;
 374	}
 375
 376	if (i >= ARRAY_SIZE(rzg2l_csi2_global_timings))
 377		return -EINVAL;
 378
 379	/* Set D-PHY timing parameters */
 380	dphytim0 = CSIDPHYTIM0_TCLK_MISS(dphy_timing->tclk_miss) |
 381			CSIDPHYTIM0_T_INIT(dphy_timing->t_init);
 382	dphytim1 = CSIDPHYTIM1_THS_PREPARE(dphy_timing->ths_prepare) |
 383			CSIDPHYTIM1_TCLK_PREPARE(dphy_timing->tclk_prepare) |
 384			CSIDPHYTIM1_THS_SETTLE(dphy_timing->ths_settle) |
 385			CSIDPHYTIM1_TCLK_SETTLE(dphy_timing->tclk_settle);
 386	rzg2l_csi2_write(csi2, CSIDPHYTIM0, dphytim0);
 387	rzg2l_csi2_write(csi2, CSIDPHYTIM1, dphytim1);
 388
 389	/* Enable D-PHY power control 0 */
 390	rzg2l_csi2_write(csi2, CSIDPHYSKW0, CSIDPHYSKW0_DEFAULT_SKW);
 391
 392	/* Set the EN_BGR bit */
 393	rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);
 394
 395	/* Delay 20us to be stable */
 396	usleep_range(20, 40);
 397
 398	/* Enable D-PHY power control 1 */
 399	rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);
 400
 401	/* Delay 10us to be stable */
 402	usleep_range(10, 20);
 403
 404	/* Start supplying the internal clock for the D-PHY block */
 405	ret = clk_prepare_enable(csi2->sysclk);
 406	if (ret)
 407		rzg2l_csi2_dphy_disable(csi2);
 408
 409	csi2->dphy_enabled = true;
 410
 411	return ret;
 412}
 413
 414static const struct rzg2l_csi2_info rzg2l_csi2_info = {
 415	.dphy_enable = rzg2l_csi2_dphy_enable,
 416	.dphy_disable = rzg2l_csi2_dphy_disable,
 417	.has_system_clk = true,
 418	.min_width = 320,
 419	.min_height = 240,
 420	.max_width = 2800,
 421	.max_height = 4095,
 422};
 423
 424static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on)
 425{
 426	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 427
 428	if (on)
 429		return csi2->info->dphy_enable(csi2);
 430
 431	return csi2->info->dphy_disable(csi2);
 432}
 433
 434static int rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2)
 435{
 436	unsigned long vclk_rate = csi2->vclk_rate / HZ_PER_MHZ;
 437	u32 frrskw, frrclk, frrskw_coeff, frrclk_coeff;
 438
 439	/* Select data lanes */
 440	rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes));
 441
 442	frrskw_coeff = 3 * vclk_rate * 8;
 443	frrclk_coeff = frrskw_coeff / 2;
 444	frrskw = DIV_ROUND_UP(frrskw_coeff, csi2->hsfreq);
 445	frrclk = DIV_ROUND_UP(frrclk_coeff, csi2->hsfreq);
 446	rzg2l_csi2_write(csi2, CSI2nMCT2, CSI2nMCT2_FRRSKW(frrskw) |
 447			 CSI2nMCT2_FRRCLK(frrclk));
 448
 449	/*
 450	 * Select data type.
 451	 * FS, FE, LS, LE, Generic Short Packet Codes 1 to 8,
 452	 * Generic Long Packet Data Types 1 to 4 YUV422 8-bit,
 453	 * RGB565, RGB888, RAW8 to RAW20, User-defined 8-bit
 454	 * data types 1 to 8
 455	 */
 456	rzg2l_csi2_write(csi2, CSI2nDTEL, 0xf778ff0f);
 457	rzg2l_csi2_write(csi2, CSI2nDTEH, 0x00ffff1f);
 458
 459	clk_disable_unprepare(csi2->vclk);
 460
 461	/* Enable LINK reception */
 462	rzg2l_csi2_write(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);
 463
 464	return clk_prepare_enable(csi2->vclk);
 465}
 466
 467static int rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2)
 468{
 469	unsigned int timeout = VSRSTS_RETRIES;
 470
 471	/* Stop LINK reception */
 472	rzg2l_csi2_clr(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);
 473
 474	/* Request a software reset of the LINK Video Pixel Interface */
 475	rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST);
 476
 477	/* Make sure CSI2nRTST.VSRSTS bit is cleared */
 478	while (--timeout) {
 479		if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS))
 480			break;
 481		usleep_range(100, 200);
 482	}
 483
 484	if (!timeout)
 485		dev_err(csi2->dev, "Clearing CSI2nRTST.VSRSTS timed out\n");
 486
 487	return 0;
 488}
 489
 490static int rzv2h_csi2_dphy_disable(struct rzg2l_csi2 *csi2)
 491{
 492	int ret;
 493
 494	/* Reset the CRU (D-PHY) */
 495	ret = reset_control_assert(csi2->cmn_rstb);
 496	if (ret)
 497		return ret;
 498
 499	csi2->dphy_enabled = false;
 500
 501	return 0;
 502}
 503
 504static int rzv2h_csi2_dphy_enable(struct rzg2l_csi2 *csi2)
 505{
 506	unsigned int i;
 507	u16 hssettle;
 508	int mbps;
 509
 510	mbps = rzg2l_csi2_calc_mbps(csi2);
 511	if (mbps < 0)
 512		return mbps;
 513
 514	csi2->hsfreq = mbps;
 515
 516	for (i = 0; i < ARRAY_SIZE(rzv2h_s_hssettlectl); i++) {
 517		if (csi2->hsfreq <= rzv2h_s_hssettlectl[i].hsfreq)
 518			break;
 519	}
 520
 521	if (i == ARRAY_SIZE(rzv2h_s_hssettlectl))
 522		return -EINVAL;
 523
 524	rzg2l_csi2_write(csi2, CRUm_SWAPCTL, 0);
 525
 526	hssettle = rzv2h_s_hssettlectl[i].s_hssettlectl;
 527	rzg2l_csi2_write(csi2, CRUm_S_TIMCTL,
 528			 CRUm_S_TIMCTL_S_HSSETTLECTL(hssettle));
 529
 530	if (csi2->hsfreq > 1500)
 531		rzg2l_csi2_set(csi2, CRUm_S_DPHYCTL_MSB,
 532			       CRUm_S_DPHYCTL_MSB_DESKEW);
 533	else
 534		rzg2l_csi2_clr(csi2, CRUm_S_DPHYCTL_MSB,
 535			       CRUm_S_DPHYCTL_MSB_DESKEW);
 536
 537	csi2->dphy_enabled = true;
 538
 539	return 0;
 540}
 541
 542static const struct rzg2l_csi2_info rzv2h_csi2_info = {
 543	.dphy_enable = rzv2h_csi2_dphy_enable,
 544	.dphy_disable = rzv2h_csi2_dphy_disable,
 545	.has_system_clk = false,
 546	.min_width = 320,
 547	.min_height = 240,
 548	.max_width = 4096,
 549	.max_height = 4096,
 550};
 551
 552static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on)
 553{
 554	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 555	int ret;
 556
 557	if (on)
 558		ret = rzg2l_csi2_mipi_link_enable(csi2);
 559	else
 560		ret = rzg2l_csi2_mipi_link_disable(csi2);
 561
 562	return ret;
 563}
 564
 565static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable)
 566{
 567	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 568	int s_stream_ret = 0;
 569	int ret;
 570
 571	if (enable) {
 572		ret = pm_runtime_resume_and_get(csi2->dev);
 573		if (ret)
 574			return ret;
 575
 576		ret = rzg2l_csi2_mipi_link_setting(sd, 1);
 577		if (ret)
 578			goto err_pm_put;
 579
 580		ret = reset_control_deassert(csi2->cmn_rstb);
 581		if (ret)
 582			goto err_mipi_link_disable;
 583	}
 584
 585	ret = v4l2_subdev_call(csi2->remote_source, video, s_stream, enable);
 586	if (ret)
 587		s_stream_ret = ret;
 588
 589	if (enable && ret)
 590		goto err_assert_rstb;
 591
 592	if (!enable) {
 593		ret = rzg2l_csi2_dphy_setting(sd, 0);
 594		if (ret && !s_stream_ret)
 595			s_stream_ret = ret;
 596		ret = rzg2l_csi2_mipi_link_setting(sd, 0);
 597		if (ret && !s_stream_ret)
 598			s_stream_ret = ret;
 599
 600		pm_runtime_put_sync(csi2->dev);
 601	}
 602
 603	return s_stream_ret;
 604
 605err_assert_rstb:
 606	reset_control_assert(csi2->cmn_rstb);
 607err_mipi_link_disable:
 608	rzg2l_csi2_mipi_link_setting(sd, 0);
 609err_pm_put:
 610	pm_runtime_put_sync(csi2->dev);
 611	return ret;
 612}
 613
 614static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags)
 615{
 616	return rzg2l_csi2_dphy_setting(sd, 1);
 617}
 618
 619static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd)
 620{
 621	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 622
 623	/*
 624	 * In ideal case D-PHY will be disabled in s_stream(0) callback
 625	 * as mentioned in the HW manual. The below will only happen when
 626	 * pre_streamon succeeds and further down the line s_stream(1)
 627	 * fails so we need to undo things in post_streamoff.
 628	 */
 629	if (csi2->dphy_enabled)
 630		return rzg2l_csi2_dphy_setting(sd, 0);
 631
 632	return 0;
 633}
 634
 635static int rzg2l_csi2_set_format(struct v4l2_subdev *sd,
 636				 struct v4l2_subdev_state *state,
 637				 struct v4l2_subdev_format *fmt)
 638{
 639	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 640	struct v4l2_mbus_framefmt *src_format;
 641	struct v4l2_mbus_framefmt *sink_format;
 642
 643	src_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SOURCE);
 644	if (fmt->pad == RZG2L_CSI2_SOURCE) {
 645		fmt->format = *src_format;
 646		return 0;
 647	}
 648
 649	sink_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);
 650
 651	if (!rzg2l_csi2_code_to_fmt(fmt->format.code))
 652		sink_format->code = rzg2l_csi2_formats[0].code;
 653	else
 654		sink_format->code = fmt->format.code;
 655
 656	sink_format->field = V4L2_FIELD_NONE;
 657	sink_format->colorspace = fmt->format.colorspace;
 658	sink_format->xfer_func = fmt->format.xfer_func;
 659	sink_format->ycbcr_enc = fmt->format.ycbcr_enc;
 660	sink_format->quantization = fmt->format.quantization;
 661	sink_format->width = clamp_t(u32, fmt->format.width,
 662				     csi2->info->min_width,
 663				     csi2->info->max_width);
 664	sink_format->height = clamp_t(u32, fmt->format.height,
 665				     csi2->info->min_height,
 666				     csi2->info->max_height);
 667	fmt->format = *sink_format;
 668
 669	/* propagate format to source pad */
 670	*src_format = *sink_format;
 671
 672	return 0;
 673}
 674
 675static int rzg2l_csi2_init_state(struct v4l2_subdev *sd,
 676				 struct v4l2_subdev_state *sd_state)
 677{
 678	struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, };
 679	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 680
 681	fmt.format.width = csi2->info->min_width;
 682	fmt.format.height = csi2->info->min_height;
 683	fmt.format.field = V4L2_FIELD_NONE;
 684	fmt.format.code = RZG2L_CSI2_DEFAULT_FMT;
 685	fmt.format.colorspace = V4L2_COLORSPACE_SRGB;
 686	fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
 687	fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT;
 688	fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT;
 689
 690	return rzg2l_csi2_set_format(sd, sd_state, &fmt);
 691}
 692
 693static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd,
 694				     struct v4l2_subdev_state *sd_state,
 695				     struct v4l2_subdev_mbus_code_enum *code)
 696{
 697	if (code->index >= ARRAY_SIZE(rzg2l_csi2_formats))
 698		return -EINVAL;
 699
 700	code->code = rzg2l_csi2_formats[code->index].code;
 701
 702	return 0;
 703}
 704
 705static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd,
 706				      struct v4l2_subdev_state *sd_state,
 707				      struct v4l2_subdev_frame_size_enum *fse)
 708{
 709	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 710
 711	if (fse->index != 0)
 712		return -EINVAL;
 713
 714	if (!rzg2l_csi2_code_to_fmt(fse->code))
 715		return -EINVAL;
 716
 717	fse->min_width = csi2->info->min_width;
 718	fse->min_height = csi2->info->min_height;
 719	fse->max_width = csi2->info->max_width;
 720	fse->max_height = csi2->info->max_height;
 721
 722	return 0;
 723}
 724
 725static int rzg2l_csi2_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
 726				     struct v4l2_mbus_frame_desc *fd)
 727{
 728	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
 729	struct media_pad *remote_pad;
 730
 731	if (!csi2->remote_source)
 732		return -ENODEV;
 733
 734	remote_pad = media_pad_remote_pad_unique(&csi2->pads[RZG2L_CSI2_SINK]);
 735	if (IS_ERR(remote_pad)) {
 736		dev_err(csi2->dev, "can't get source pad of %s (%pe)\n",
 737			csi2->remote_source->name, remote_pad);
 738		return PTR_ERR(remote_pad);
 739	}
 740	return v4l2_subdev_call(csi2->remote_source, pad, get_frame_desc,
 741				remote_pad->index, fd);
 742}
 743
 744static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = {
 745	.s_stream = rzg2l_csi2_s_stream,
 746	.pre_streamon = rzg2l_csi2_pre_streamon,
 747	.post_streamoff = rzg2l_csi2_post_streamoff,
 748};
 749
 750static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = {
 751	.enum_mbus_code = rzg2l_csi2_enum_mbus_code,
 752	.enum_frame_size = rzg2l_csi2_enum_frame_size,
 753	.set_fmt = rzg2l_csi2_set_format,
 754	.get_fmt = v4l2_subdev_get_fmt,
 755	.get_frame_desc = rzg2l_csi2_get_frame_desc,
 756};
 757
 758static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = {
 759	.video	= &rzg2l_csi2_video_ops,
 760	.pad	= &rzg2l_csi2_pad_ops,
 761};
 762
 763static const struct v4l2_subdev_internal_ops rzg2l_csi2_internal_ops = {
 764	.init_state = rzg2l_csi2_init_state,
 765};
 766
 767/* -----------------------------------------------------------------------------
 768 * Async handling and registration of subdevices and links.
 769 */
 770
 771static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier,
 772				   struct v4l2_subdev *subdev,
 773				   struct v4l2_async_connection *asd)
 774{
 775	struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);
 776
 777	csi2->remote_source = subdev;
 778
 779	dev_dbg(csi2->dev, "Bound subdev: %s pad\n", subdev->name);
 780
 781	return media_create_pad_link(&subdev->entity, RZG2L_CSI2_SINK,
 782				     &csi2->subdev.entity, 0,
 783				     MEDIA_LNK_FL_ENABLED |
 784				     MEDIA_LNK_FL_IMMUTABLE);
 785}
 786
 787static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier,
 788				     struct v4l2_subdev *subdev,
 789				     struct v4l2_async_connection *asd)
 790{
 791	struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);
 792
 793	csi2->remote_source = NULL;
 794
 795	dev_dbg(csi2->dev, "Unbind subdev %s\n", subdev->name);
 796}
 797
 798static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = {
 799	.bound = rzg2l_csi2_notify_bound,
 800	.unbind = rzg2l_csi2_notify_unbind,
 801};
 802
 803static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2,
 804				 struct v4l2_fwnode_endpoint *vep)
 805{
 806	/* Only port 0 endpoint 0 is valid. */
 807	if (vep->base.port || vep->base.id)
 808		return -ENOTCONN;
 809
 810	csi2->lanes = vep->bus.mipi_csi2.num_data_lanes;
 811
 812	return 0;
 813}
 814
 815static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2)
 816{
 817	struct v4l2_fwnode_endpoint v4l2_ep = {
 818		.bus_type = V4L2_MBUS_CSI2_DPHY
 819	};
 820	struct v4l2_async_connection *asd;
 821	struct fwnode_handle *fwnode;
 822	struct fwnode_handle *ep;
 823	int ret;
 824
 825	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0, 0);
 826	if (!ep) {
 827		dev_err(csi2->dev, "Not connected to subdevice\n");
 828		return -EINVAL;
 829	}
 830
 831	ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
 832	if (ret) {
 833		dev_err(csi2->dev, "Could not parse v4l2 endpoint\n");
 834		fwnode_handle_put(ep);
 835		return -EINVAL;
 836	}
 837
 838	ret = rzg2l_csi2_parse_v4l2(csi2, &v4l2_ep);
 839	if (ret) {
 840		fwnode_handle_put(ep);
 841		return ret;
 842	}
 843
 844	fwnode = fwnode_graph_get_remote_endpoint(ep);
 845	fwnode_handle_put(ep);
 846
 847	v4l2_async_subdev_nf_init(&csi2->notifier, &csi2->subdev);
 848	csi2->notifier.ops = &rzg2l_csi2_notify_ops;
 849
 850	asd = v4l2_async_nf_add_fwnode(&csi2->notifier, fwnode,
 851				       struct v4l2_async_connection);
 852	fwnode_handle_put(fwnode);
 853	if (IS_ERR(asd))
 854		return PTR_ERR(asd);
 855
 856	ret = v4l2_async_nf_register(&csi2->notifier);
 857	if (ret)
 858		v4l2_async_nf_cleanup(&csi2->notifier);
 859
 860	return ret;
 861}
 862
 863static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2)
 864{
 865	int lanes;
 866	int ret;
 867
 868	if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) {
 869		dev_err(csi2->dev, "Unsupported number of data-lanes: %u\n",
 870			csi2->lanes);
 871		return -EINVAL;
 872	}
 873
 874	ret = pm_runtime_resume_and_get(csi2->dev);
 875	if (ret)
 876		return ret;
 877
 878	/* Checking the maximum lanes support for CSI-2 module */
 879	lanes = (rzg2l_csi2_read(csi2, CSI2nMCG) & CSI2nMCG_SDLN) >> 8;
 880	if (lanes < csi2->lanes) {
 881		dev_err(csi2->dev,
 882			"Failed to support %d data lanes\n", csi2->lanes);
 883		ret = -EINVAL;
 884	}
 885
 886	pm_runtime_put_sync(csi2->dev);
 887
 888	return ret;
 889}
 890
 891/* -----------------------------------------------------------------------------
 892 * Platform Device Driver.
 893 */
 894
 895static const struct media_entity_operations rzg2l_csi2_entity_ops = {
 896	.link_validate = v4l2_subdev_link_validate,
 897};
 898
 899static int rzg2l_csi2_probe(struct platform_device *pdev)
 900{
 901	struct device *dev = &pdev->dev;
 902	struct rzg2l_csi2 *csi2;
 903	int ret;
 904
 905	csi2 = devm_kzalloc(dev, sizeof(*csi2), GFP_KERNEL);
 906	if (!csi2)
 907		return -ENOMEM;
 908
 909	csi2->info = of_device_get_match_data(dev);
 910	if (!csi2->info)
 911		return dev_err_probe(dev, -EINVAL, "Failed to get OF match data\n");
 912
 913	csi2->base = devm_platform_ioremap_resource(pdev, 0);
 914	if (IS_ERR(csi2->base))
 915		return PTR_ERR(csi2->base);
 916
 917	csi2->cmn_rstb = devm_reset_control_get_exclusive(dev, "cmn-rstb");
 918	if (IS_ERR(csi2->cmn_rstb))
 919		return dev_err_probe(dev, PTR_ERR(csi2->cmn_rstb),
 920				     "Failed to get cpg cmn-rstb\n");
 921
 922	csi2->presetn = devm_reset_control_get_shared(dev, "presetn");
 923	if (IS_ERR(csi2->presetn))
 924		return dev_err_probe(dev, PTR_ERR(csi2->presetn),
 925				     "Failed to get cpg presetn\n");
 926
 927	if (csi2->info->has_system_clk) {
 928		csi2->sysclk = devm_clk_get(dev, "system");
 929		if (IS_ERR(csi2->sysclk))
 930			return dev_err_probe(dev, PTR_ERR(csi2->sysclk),
 931					     "Failed to get system clk\n");
 932	}
 933
 934	csi2->vclk = devm_clk_get(dev, "video");
 935	if (IS_ERR(csi2->vclk))
 936		return dev_err_probe(dev, PTR_ERR(csi2->vclk),
 937				     "Failed to get video clock\n");
 938	csi2->vclk_rate = clk_get_rate(csi2->vclk);
 939
 940	csi2->dev = dev;
 941
 942	platform_set_drvdata(pdev, csi2);
 943
 944	ret = rzg2l_csi2_parse_dt(csi2);
 945	if (ret)
 946		return ret;
 947
 948	ret = devm_pm_runtime_enable(dev);
 949	if (ret)
 950		return ret;
 951
 952	ret = rzg2l_validate_csi2_lanes(csi2);
 953	if (ret)
 954		return ret;
 955
 956	csi2->subdev.dev = dev;
 957	v4l2_subdev_init(&csi2->subdev, &rzg2l_csi2_subdev_ops);
 958	csi2->subdev.internal_ops = &rzg2l_csi2_internal_ops;
 959	v4l2_set_subdevdata(&csi2->subdev, dev);
 960	snprintf(csi2->subdev.name, sizeof(csi2->subdev.name),
 961		 "csi-%s", dev_name(dev));
 962	csi2->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
 963
 964	csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
 965	csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops;
 966
 967	csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK |
 968					    MEDIA_PAD_FL_MUST_CONNECT;
 969	/*
 970	 * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual
 971	 * channels should be implemented by streams API which is under
 972	 * development lets hardcode to VC0 for now.
 973	 */
 974	csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE |
 975					      MEDIA_PAD_FL_MUST_CONNECT;
 976	ret = media_entity_pads_init(&csi2->subdev.entity, ARRAY_SIZE(csi2->pads),
 977				     csi2->pads);
 978	if (ret)
 979		return ret;
 980
 981	ret = v4l2_subdev_init_finalize(&csi2->subdev);
 982	if (ret < 0)
 983		goto error_async;
 984
 985	ret = v4l2_async_register_subdev(&csi2->subdev);
 986	if (ret < 0)
 987		goto error_subdev;
 988
 989	return 0;
 990
 991error_subdev:
 992	v4l2_subdev_cleanup(&csi2->subdev);
 993error_async:
 994	v4l2_async_nf_unregister(&csi2->notifier);
 995	v4l2_async_nf_cleanup(&csi2->notifier);
 996	media_entity_cleanup(&csi2->subdev.entity);
 997
 998	return ret;
 999}
1000
1001static void rzg2l_csi2_remove(struct platform_device *pdev)
1002{
1003	struct rzg2l_csi2 *csi2 = platform_get_drvdata(pdev);
1004
1005	v4l2_async_nf_unregister(&csi2->notifier);
1006	v4l2_async_nf_cleanup(&csi2->notifier);
1007	v4l2_async_unregister_subdev(&csi2->subdev);
1008	v4l2_subdev_cleanup(&csi2->subdev);
1009	media_entity_cleanup(&csi2->subdev.entity);
1010}
1011
1012static int rzg2l_csi2_pm_runtime_suspend(struct device *dev)
1013{
1014	struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);
1015
1016	reset_control_assert(csi2->presetn);
1017
1018	return 0;
1019}
1020
1021static int rzg2l_csi2_pm_runtime_resume(struct device *dev)
1022{
1023	struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);
1024
1025	return reset_control_deassert(csi2->presetn);
1026}
1027
1028static const struct dev_pm_ops rzg2l_csi2_pm_ops = {
1029	RUNTIME_PM_OPS(rzg2l_csi2_pm_runtime_suspend,
1030		       rzg2l_csi2_pm_runtime_resume, NULL)
1031};
1032
1033static const struct of_device_id rzg2l_csi2_of_table[] = {
1034	{
1035		.compatible = "renesas,r9a09g057-csi2",
1036		.data = &rzv2h_csi2_info,
1037	},
1038	{
1039		.compatible = "renesas,rzg2l-csi2",
1040		.data = &rzg2l_csi2_info,
1041	},
1042	{ /* sentinel */ }
1043};
1044MODULE_DEVICE_TABLE(of, rzg2l_csi2_of_table);
1045
1046static struct platform_driver rzg2l_csi2_pdrv = {
1047	.remove = rzg2l_csi2_remove,
1048	.probe	= rzg2l_csi2_probe,
1049	.driver	= {
1050		.name = "rzg2l-csi2",
1051		.of_match_table = rzg2l_csi2_of_table,
1052		.pm = pm_ptr(&rzg2l_csi2_pm_ops),
1053	},
1054};
1055
1056module_platform_driver(rzg2l_csi2_pdrv);
1057
1058MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
1059MODULE_DESCRIPTION("Renesas RZ/G2L MIPI CSI2 receiver driver");
1060MODULE_LICENSE("GPL");