rzg2l-cru-regs.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/*
  3 * rzg2l-cru-regs.h--RZ/G2L (and alike SoCs) CRU Registers Definitions
  4 *
  5 * Copyright (C) 2024 Renesas Electronics Corp.
  6 */
  7
  8#ifndef __RZG2L_CRU_REGS_H__
  9#define __RZG2L_CRU_REGS_H__
 10
 11/* HW CRU Registers Definition */
 12
 13#define CRUnCTRL_VINSEL(x)		((x) << 0)
 14
 15#define CRUnIE_EFE			BIT(17)
 16
 17#define CRUnIE2_FSxE(x)			BIT(((x) * 3))
 18#define CRUnIE2_FExE(x)			BIT(((x) * 3) + 1)
 19
 20#define CRUnINTS_SFS			BIT(16)
 21
 22#define CRUnINTS2_FSxS(x)		BIT(((x) * 3))
 23
 24#define CRUnRST_VRESETN			BIT(0)
 25
 26/* Memory Bank Base Address (Lower) Register for CRU Image Data */
 27#define AMnMBxADDRL(x)			(AMnMB1ADDRL + (x) * 2)
 28
 29/* Memory Bank Base Address (Higher) Register for CRU Image Data */
 30#define AMnMBxADDRH(x)			(AMnMB1ADDRH + (x) * 2)
 31
 32#define AMnMBVALID_MBVALID(x)		GENMASK(x, 0)
 33
 34#define AMnMBS_MBSTS			0x7
 35
 36#define AMnAXIATTR_AXILEN_MASK		GENMASK(3, 0)
 37#define AMnAXIATTR_AXILEN		(0xf)
 38
 39#define AMnFIFOPNTR_FIFOWPNTR		GENMASK(7, 0)
 40#define AMnFIFOPNTR_FIFOWPNTR_B0	AMnFIFOPNTR_FIFOWPNTR
 41#define AMnFIFOPNTR_FIFOWPNTR_B1	GENMASK(15, 8)
 42#define AMnFIFOPNTR_FIFORPNTR_Y		GENMASK(23, 16)
 43#define AMnFIFOPNTR_FIFORPNTR_B0	AMnFIFOPNTR_FIFORPNTR_Y
 44#define AMnFIFOPNTR_FIFORPNTR_B1	GENMASK(31, 24)
 45
 46#define AMnIS_IS_MASK			GENMASK(14, 7)
 47#define AMnIS_IS(x)			((x) << 7)
 48
 49#define AMnAXISTP_AXI_STOP		BIT(0)
 50
 51#define AMnAXISTPACK_AXI_STOP_ACK	BIT(0)
 52
 53#define ICnEN_ICEN			BIT(0)
 54
 55#define ICnSVC_SVC0(x)			(x)
 56#define ICnSVC_SVC1(x)			((x) << 4)
 57#define ICnSVC_SVC2(x)			((x) << 8)
 58#define ICnSVC_SVC3(x)			((x) << 12)
 59
 60#define ICnMC_CSCTHR			BIT(5)
 61#define ICnMC_INF(x)			((x) << 16)
 62#define ICnMC_VCSEL(x)			((x) << 22)
 63#define ICnMC_INF_MASK			GENMASK(21, 16)
 64
 65#define ICnMS_IA			BIT(2)
 66
 67#define ICnDMR_YCMODE_UYVY		(1 << 4)
 68
 69enum rzg2l_cru_common_regs {
 70	CRUnCTRL,	/* CRU Control */
 71	CRUnIE,		/* CRU Interrupt Enable */
 72	CRUnIE2,	/* CRU Interrupt Enable(2) */
 73	CRUnINTS,	/* CRU Interrupt Status */
 74	CRUnINTS2,	/* CRU Interrupt Status(2) */
 75	CRUnRST,	/* CRU Reset */
 76	AMnMB1ADDRL,	/* Bank 1 Address (Lower) for CRU Image Data */
 77	AMnMB1ADDRH,	/* Bank 1 Address (Higher) for CRU Image Data */
 78	AMnMB2ADDRL,    /* Bank 2 Address (Lower) for CRU Image Data */
 79	AMnMB2ADDRH,    /* Bank 2 Address (Higher) for CRU Image Data */
 80	AMnMB3ADDRL,    /* Bank 3 Address (Lower) for CRU Image Data */
 81	AMnMB3ADDRH,    /* Bank 3 Address (Higher) for CRU Image Data */
 82	AMnMB4ADDRL,    /* Bank 4 Address (Lower) for CRU Image Data */
 83	AMnMB4ADDRH,    /* Bank 4 Address (Higher) for CRU Image Data */
 84	AMnMB5ADDRL,    /* Bank 5 Address (Lower) for CRU Image Data */
 85	AMnMB5ADDRH,    /* Bank 5 Address (Higher) for CRU Image Data */
 86	AMnMB6ADDRL,    /* Bank 6 Address (Lower) for CRU Image Data */
 87	AMnMB6ADDRH,    /* Bank 6 Address (Higher) for CRU Image Data */
 88	AMnMB7ADDRL,    /* Bank 7 Address (Lower) for CRU Image Data */
 89	AMnMB7ADDRH,    /* Bank 7 Address (Higher) for CRU Image Data */
 90	AMnMB8ADDRL,    /* Bank 8 Address (Lower) for CRU Image Data */
 91	AMnMB8ADDRH,    /* Bank 8 Address (Higher) for CRU Image Data */
 92	AMnMBVALID,	/* Memory Bank Enable for CRU Image Data */
 93	AMnMBS,		/* Memory Bank Status for CRU Image Data */
 94	AMnMADRSL,	/* VD Memory Address Lower Status Register */
 95	AMnMADRSH,	/* VD Memory Address Higher Status Register */
 96	AMnAXIATTR,	/* AXI Master Transfer Setting Register for CRU Image Data */
 97	AMnFIFOPNTR,	/* AXI Master FIFO Pointer for CRU Image Data */
 98	AMnAXISTP,	/* AXI Master Transfer Stop for CRU Image Data */
 99	AMnAXISTPACK,	/* AXI Master Transfer Stop Status for CRU Image Data */
100	AMnIS,		/* Image Stride Setting Register */
101	ICnEN,		/* CRU Image Processing Enable */
102	ICnSVCNUM,	/* CRU SVC Number Register */
103	ICnSVC,		/* CRU VC Select Register */
104	ICnMC,		/* CRU Image Processing Main Control */
105	ICnIPMC_C0,	/* CRU Image Converter Main Control 0 */
106	ICnMS,		/* CRU Module Status */
107	ICnDMR,		/* CRU Data Output Mode */
108	RZG2L_CRU_MAX_REG,
109};
110
111#endif /* __RZG2L_CRU_REGS_H__ */