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rcar-csi2.c
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linux-6.19.14/drivers/media/platform/renesas/rcar-csi2.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Renesas R-Car MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <linux/delay.h> 9#include <linux/interrupt.h> 10#include <linux/io.h> 11#include <linux/math64.h> 12#include <linux/module.h> 13#include <linux/of.h> 14#include <linux/of_graph.h> 15#include <linux/platform_device.h> 16#include <linux/pm_runtime.h> 17#include <linux/reset.h> 18#include <linux/sys_soc.h> 19#include <linux/units.h> 20 21#include <media/mipi-csi2.h> 22#include <media/v4l2-ctrls.h> 23#include <media/v4l2-device.h> 24#include <media/v4l2-fwnode.h> 25#include <media/v4l2-mc.h> 26#include <media/v4l2-subdev.h> 27 28struct rcar_csi2; 29 30/* Register offsets and bits */ 31 32/* Control Timing Select */ 33#define TREF_REG 0x00 34#define TREF_TREF BIT(0) 35 36/* Software Reset */ 37#define SRST_REG 0x04 38#define SRST_SRST BIT(0) 39 40/* PHY Operation Control */ 41#define PHYCNT_REG 0x08 42#define PHYCNT_SHUTDOWNZ BIT(17) 43#define PHYCNT_RSTZ BIT(16) 44#define PHYCNT_ENABLECLK BIT(4) 45#define PHYCNT_ENABLE_3 BIT(3) 46#define PHYCNT_ENABLE_2 BIT(2) 47#define PHYCNT_ENABLE_1 BIT(1) 48#define PHYCNT_ENABLE_0 BIT(0) 49 50/* Checksum Control */ 51#define CHKSUM_REG 0x0c 52#define CHKSUM_ECC_EN BIT(1) 53#define CHKSUM_CRC_EN BIT(0) 54 55/* 56 * Channel Data Type Select 57 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 58 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 59 */ 60#define VCDT_REG 0x10 61#define VCDT2_REG 0x14 62#define VCDT_VCDTN_EN BIT(15) 63#define VCDT_SEL_VC(n) (((n) & 0x3) << 8) 64#define VCDT_SEL_DTN_ON BIT(6) 65#define VCDT_SEL_DT(n) (((n) & 0x3f) << 0) 66 67/* Frame Data Type Select */ 68#define FRDT_REG 0x18 69 70/* Field Detection Control */ 71#define FLD_REG 0x1c 72#define FLD_FLD_NUM(n) (((n) & 0xff) << 16) 73#define FLD_DET_SEL(n) (((n) & 0x3) << 4) 74#define FLD_FLD_EN4 BIT(3) 75#define FLD_FLD_EN3 BIT(2) 76#define FLD_FLD_EN2 BIT(1) 77#define FLD_FLD_EN BIT(0) 78 79/* Automatic Standby Control */ 80#define ASTBY_REG 0x20 81 82/* Long Data Type Setting 0 */ 83#define LNGDT0_REG 0x28 84 85/* Long Data Type Setting 1 */ 86#define LNGDT1_REG 0x2c 87 88/* Interrupt Enable */ 89#define INTEN_REG 0x30 90#define INTEN_INT_AFIFO_OF BIT(27) 91#define INTEN_INT_ERRSOTHS BIT(4) 92#define INTEN_INT_ERRSOTSYNCHS BIT(3) 93 94/* Interrupt Source Mask */ 95#define INTCLOSE_REG 0x34 96 97/* Interrupt Status Monitor */ 98#define INTSTATE_REG 0x38 99#define INTSTATE_INT_ULPS_START BIT(7) 100#define INTSTATE_INT_ULPS_END BIT(6) 101 102/* Interrupt Error Status Monitor */ 103#define INTERRSTATE_REG 0x3c 104 105/* Short Packet Data */ 106#define SHPDAT_REG 0x40 107 108/* Short Packet Count */ 109#define SHPCNT_REG 0x44 110 111/* LINK Operation Control */ 112#define LINKCNT_REG 0x48 113#define LINKCNT_MONITOR_EN BIT(31) 114#define LINKCNT_REG_MONI_PACT_EN BIT(25) 115#define LINKCNT_ICLK_NONSTOP BIT(24) 116 117/* Lane Swap */ 118#define LSWAP_REG 0x4c 119#define LSWAP_L3SEL(n) (((n) & 0x3) << 6) 120#define LSWAP_L2SEL(n) (((n) & 0x3) << 4) 121#define LSWAP_L1SEL(n) (((n) & 0x3) << 2) 122#define LSWAP_L0SEL(n) (((n) & 0x3) << 0) 123 124/* PHY Test Interface Write Register */ 125#define PHTW_REG 0x50 126#define PHTW_DWEN BIT(24) 127#define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16) 128#define PHTW_CWEN BIT(8) 129#define PHTW_TESTDIN_CODE(n) ((n & 0xff)) 130 131#define PHYFRX_REG 0x64 132#define PHYFRX_FORCERX_MODE_3 BIT(3) 133#define PHYFRX_FORCERX_MODE_2 BIT(2) 134#define PHYFRX_FORCERX_MODE_1 BIT(1) 135#define PHYFRX_FORCERX_MODE_0 BIT(0) 136 137/* V4H BASE registers */ 138#define V4H_N_LANES_REG 0x0004 139#define V4H_CSI2_RESETN_REG 0x0008 140 141#define V4H_PHY_MODE_REG 0x001c 142#define V4H_PHY_MODE_DPHY 0 143#define V4H_PHY_MODE_CPHY 1 144 145#define V4H_PHY_SHUTDOWNZ_REG 0x0040 146#define V4H_DPHY_RSTZ_REG 0x0044 147#define V4H_FLDC_REG 0x0804 148#define V4H_FLDD_REG 0x0808 149#define V4H_IDIC_REG 0x0810 150 151#define V4H_PHY_EN_REG 0x2000 152#define V4H_PHY_EN_ENABLE_3 BIT(7) 153#define V4H_PHY_EN_ENABLE_2 BIT(6) 154#define V4H_PHY_EN_ENABLE_1 BIT(5) 155#define V4H_PHY_EN_ENABLE_0 BIT(4) 156#define V4H_PHY_EN_ENABLE_CLK BIT(0) 157 158#define V4H_ST_PHYST_REG 0x2814 159#define V4H_ST_PHYST_ST_PHY_READY BIT(31) 160#define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3) 161#define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2) 162#define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1) 163#define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0) 164 165/* V4H PPI registers */ 166#define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */ 167#define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822 168#define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c 169#define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02 170#define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04 171#define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06 172#define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a 173#define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c 174#define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10 175#define V4H_PPI_RW_DDLCAL_CFG_n_REG(n) (0x21c40 + ((n) * 2)) /* n = 0 - 7 */ 176#define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c 177#define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80 178#define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0 179 180/* V4H CORE registers */ 181 182#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, n) (0x22040 + ((l) * 0x400) + ((n) * 2)) 183#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_3_REG(l, n) (0x22060 + ((l) * 0x400) + ((n) * 2)) 184#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_4_REG(l, n) (0x22080 + ((l) * 0x400) + ((n) * 2)) 185 186#define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */ 187#define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */ 188#define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */ 189#define V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG 0x23fe0 190 191#define V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, n) (0x26000 + ((l) * 0x400) + ((n) * 2)) 192#define V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, n) (0x26080 + ((l) * 0x400) + ((n) * 2)) 193#define V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, n) (0x26100 + ((l) * 0x400) + ((n) * 2)) 194#define V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(4, (n)) 195#define V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(4, (n)) 196 197/* V4H C-PHY */ 198#define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */ 199#define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */ 200#define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */ 201#define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0x2a000 202#define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080 203#define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */ 204#define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400 205#define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480 206#define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */ 207#define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c 208#define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800 209#define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880 210#define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */ 211 212struct rcsi2_cphy_setting { 213 u16 msps; 214 u16 rx2; 215 u16 trio0; 216 u16 trio1; 217 u16 trio2; 218 u16 lane27; 219 u16 lane29; 220}; 221 222static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = { 223 { .msps = 80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .lane29 = 0x0a24 }, 224 { .msps = 100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .lane29 = 0x0a24 }, 225 { .msps = 200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .lane29 = 0x0a44 }, 226 { .msps = 300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .lane29 = 0x0a44 }, 227 { .msps = 400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .lane29 = 0x0a64 }, 228 { .msps = 500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .lane29 = 0x0a64 }, 229 { .msps = 600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .lane29 = 0x0a64 }, 230 { .msps = 700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .lane29 = 0x0a84 }, 231 { .msps = 800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .lane29 = 0x0a84 }, 232 { .msps = 900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .lane29 = 0x0a84 }, 233 { .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .lane29 = 0x0a84 }, 234 { .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .lane29 = 0x0a84 }, 235 { .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0a84 }, 236 { .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0aa4 }, 237 { .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 238 { .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 239 { .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 240 { .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 241 { .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 242 { .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 243 { .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 244 { .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 245 { .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 246 { .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 247 { .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 248 { .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0aa4 }, 249 { .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 250 { .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 251 { .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 252 { .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 253 { .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 254 { .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 255 { .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 256 { .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 257 { .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 258 { .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 259 { /* sentinel */ }, 260}; 261 262/* V4M registers */ 263#define V4M_OVR1_REG 0x0848 264#define V4M_OVR1_FORCERXMODE_3 BIT(12) 265#define V4M_OVR1_FORCERXMODE_2 BIT(11) 266#define V4M_OVR1_FORCERXMODE_1 BIT(10) 267#define V4M_OVR1_FORCERXMODE_0 BIT(9) 268 269#define V4M_FRXM_REG 0x2004 270#define V4M_FRXM_FORCERXMODE_3 BIT(3) 271#define V4M_FRXM_FORCERXMODE_2 BIT(2) 272#define V4M_FRXM_FORCERXMODE_1 BIT(1) 273#define V4M_FRXM_FORCERXMODE_0 BIT(0) 274 275#define V4M_PHYPLL_REG 0x02050 276#define V4M_CSI0CLKFCPR_REG 0x02054 277#define V4M_PHTW_REG 0x02060 278#define V4M_PHTR_REG 0x02064 279#define V4M_PHTC_REG 0x02068 280 281struct phtw_value { 282 u8 data; 283 u8 code; 284}; 285 286struct rcsi2_mbps_info { 287 u16 mbps; 288 u8 reg; 289 u16 osc_freq; /* V4M */ 290}; 291 292static const struct rcsi2_mbps_info phtw_mbps_v3u[] = { 293 { .mbps = 1500, .reg = 0xcc }, 294 { .mbps = 1550, .reg = 0x1d }, 295 { .mbps = 1600, .reg = 0x27 }, 296 { .mbps = 1650, .reg = 0x30 }, 297 { .mbps = 1700, .reg = 0x39 }, 298 { .mbps = 1750, .reg = 0x42 }, 299 { .mbps = 1800, .reg = 0x4b }, 300 { .mbps = 1850, .reg = 0x55 }, 301 { .mbps = 1900, .reg = 0x5e }, 302 { .mbps = 1950, .reg = 0x67 }, 303 { .mbps = 2000, .reg = 0x71 }, 304 { .mbps = 2050, .reg = 0x79 }, 305 { .mbps = 2100, .reg = 0x83 }, 306 { .mbps = 2150, .reg = 0x8c }, 307 { .mbps = 2200, .reg = 0x95 }, 308 { .mbps = 2250, .reg = 0x9e }, 309 { .mbps = 2300, .reg = 0xa7 }, 310 { .mbps = 2350, .reg = 0xb0 }, 311 { .mbps = 2400, .reg = 0xba }, 312 { .mbps = 2450, .reg = 0xc3 }, 313 { .mbps = 2500, .reg = 0xcc }, 314 { /* sentinel */ }, 315}; 316 317static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = { 318 { .mbps = 80, .reg = 0x86 }, 319 { .mbps = 90, .reg = 0x86 }, 320 { .mbps = 100, .reg = 0x87 }, 321 { .mbps = 110, .reg = 0x87 }, 322 { .mbps = 120, .reg = 0x88 }, 323 { .mbps = 130, .reg = 0x88 }, 324 { .mbps = 140, .reg = 0x89 }, 325 { .mbps = 150, .reg = 0x89 }, 326 { .mbps = 160, .reg = 0x8a }, 327 { .mbps = 170, .reg = 0x8a }, 328 { .mbps = 180, .reg = 0x8b }, 329 { .mbps = 190, .reg = 0x8b }, 330 { .mbps = 205, .reg = 0x8c }, 331 { .mbps = 220, .reg = 0x8d }, 332 { .mbps = 235, .reg = 0x8e }, 333 { .mbps = 250, .reg = 0x8e }, 334 { /* sentinel */ }, 335}; 336 337static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = { 338 { .mbps = 80, .reg = 0x00 }, 339 { .mbps = 90, .reg = 0x20 }, 340 { .mbps = 100, .reg = 0x40 }, 341 { .mbps = 110, .reg = 0x02 }, 342 { .mbps = 130, .reg = 0x22 }, 343 { .mbps = 140, .reg = 0x42 }, 344 { .mbps = 150, .reg = 0x04 }, 345 { .mbps = 170, .reg = 0x24 }, 346 { .mbps = 180, .reg = 0x44 }, 347 { .mbps = 200, .reg = 0x06 }, 348 { .mbps = 220, .reg = 0x26 }, 349 { .mbps = 240, .reg = 0x46 }, 350 { .mbps = 250, .reg = 0x08 }, 351 { .mbps = 270, .reg = 0x28 }, 352 { .mbps = 300, .reg = 0x0a }, 353 { .mbps = 330, .reg = 0x2a }, 354 { .mbps = 360, .reg = 0x4a }, 355 { .mbps = 400, .reg = 0x0c }, 356 { .mbps = 450, .reg = 0x2c }, 357 { .mbps = 500, .reg = 0x0e }, 358 { .mbps = 550, .reg = 0x2e }, 359 { .mbps = 600, .reg = 0x10 }, 360 { .mbps = 650, .reg = 0x30 }, 361 { .mbps = 700, .reg = 0x12 }, 362 { .mbps = 750, .reg = 0x32 }, 363 { .mbps = 800, .reg = 0x52 }, 364 { .mbps = 850, .reg = 0x72 }, 365 { .mbps = 900, .reg = 0x14 }, 366 { .mbps = 950, .reg = 0x34 }, 367 { .mbps = 1000, .reg = 0x54 }, 368 { .mbps = 1050, .reg = 0x74 }, 369 { .mbps = 1125, .reg = 0x16 }, 370 { /* sentinel */ }, 371}; 372 373/* PHY Test Interface Clear */ 374#define PHTC_REG 0x58 375#define PHTC_TESTCLR BIT(0) 376 377/* PHY Frequency Control */ 378#define PHYPLL_REG 0x68 379#define PHYPLL_HSFREQRANGE(n) ((n) << 16) 380 381static const struct rcsi2_mbps_info hsfreqrange_v3u[] = { 382 { .mbps = 80, .reg = 0x00 }, 383 { .mbps = 90, .reg = 0x10 }, 384 { .mbps = 100, .reg = 0x20 }, 385 { .mbps = 110, .reg = 0x30 }, 386 { .mbps = 120, .reg = 0x01 }, 387 { .mbps = 130, .reg = 0x11 }, 388 { .mbps = 140, .reg = 0x21 }, 389 { .mbps = 150, .reg = 0x31 }, 390 { .mbps = 160, .reg = 0x02 }, 391 { .mbps = 170, .reg = 0x12 }, 392 { .mbps = 180, .reg = 0x22 }, 393 { .mbps = 190, .reg = 0x32 }, 394 { .mbps = 205, .reg = 0x03 }, 395 { .mbps = 220, .reg = 0x13 }, 396 { .mbps = 235, .reg = 0x23 }, 397 { .mbps = 250, .reg = 0x33 }, 398 { .mbps = 275, .reg = 0x04 }, 399 { .mbps = 300, .reg = 0x14 }, 400 { .mbps = 325, .reg = 0x25 }, 401 { .mbps = 350, .reg = 0x35 }, 402 { .mbps = 400, .reg = 0x05 }, 403 { .mbps = 450, .reg = 0x16 }, 404 { .mbps = 500, .reg = 0x26 }, 405 { .mbps = 550, .reg = 0x37 }, 406 { .mbps = 600, .reg = 0x07 }, 407 { .mbps = 650, .reg = 0x18 }, 408 { .mbps = 700, .reg = 0x28 }, 409 { .mbps = 750, .reg = 0x39 }, 410 { .mbps = 800, .reg = 0x09 }, 411 { .mbps = 850, .reg = 0x19 }, 412 { .mbps = 900, .reg = 0x29 }, 413 { .mbps = 950, .reg = 0x3a }, 414 { .mbps = 1000, .reg = 0x0a }, 415 { .mbps = 1050, .reg = 0x1a }, 416 { .mbps = 1100, .reg = 0x2a }, 417 { .mbps = 1150, .reg = 0x3b }, 418 { .mbps = 1200, .reg = 0x0b }, 419 { .mbps = 1250, .reg = 0x1b }, 420 { .mbps = 1300, .reg = 0x2b }, 421 { .mbps = 1350, .reg = 0x3c }, 422 { .mbps = 1400, .reg = 0x0c }, 423 { .mbps = 1450, .reg = 0x1c }, 424 { .mbps = 1500, .reg = 0x2c }, 425 { .mbps = 1550, .reg = 0x3d }, 426 { .mbps = 1600, .reg = 0x0d }, 427 { .mbps = 1650, .reg = 0x1d }, 428 { .mbps = 1700, .reg = 0x2e }, 429 { .mbps = 1750, .reg = 0x3e }, 430 { .mbps = 1800, .reg = 0x0e }, 431 { .mbps = 1850, .reg = 0x1e }, 432 { .mbps = 1900, .reg = 0x2f }, 433 { .mbps = 1950, .reg = 0x3f }, 434 { .mbps = 2000, .reg = 0x0f }, 435 { .mbps = 2050, .reg = 0x40 }, 436 { .mbps = 2100, .reg = 0x41 }, 437 { .mbps = 2150, .reg = 0x42 }, 438 { .mbps = 2200, .reg = 0x43 }, 439 { .mbps = 2300, .reg = 0x45 }, 440 { .mbps = 2350, .reg = 0x46 }, 441 { .mbps = 2400, .reg = 0x47 }, 442 { .mbps = 2450, .reg = 0x48 }, 443 { .mbps = 2500, .reg = 0x49 }, 444 { /* sentinel */ }, 445}; 446 447static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = { 448 { .mbps = 80, .reg = 0x00 }, 449 { .mbps = 90, .reg = 0x10 }, 450 { .mbps = 100, .reg = 0x20 }, 451 { .mbps = 110, .reg = 0x30 }, 452 { .mbps = 120, .reg = 0x01 }, 453 { .mbps = 130, .reg = 0x11 }, 454 { .mbps = 140, .reg = 0x21 }, 455 { .mbps = 150, .reg = 0x31 }, 456 { .mbps = 160, .reg = 0x02 }, 457 { .mbps = 170, .reg = 0x12 }, 458 { .mbps = 180, .reg = 0x22 }, 459 { .mbps = 190, .reg = 0x32 }, 460 { .mbps = 205, .reg = 0x03 }, 461 { .mbps = 220, .reg = 0x13 }, 462 { .mbps = 235, .reg = 0x23 }, 463 { .mbps = 250, .reg = 0x33 }, 464 { .mbps = 275, .reg = 0x04 }, 465 { .mbps = 300, .reg = 0x14 }, 466 { .mbps = 325, .reg = 0x25 }, 467 { .mbps = 350, .reg = 0x35 }, 468 { .mbps = 400, .reg = 0x05 }, 469 { .mbps = 450, .reg = 0x16 }, 470 { .mbps = 500, .reg = 0x26 }, 471 { .mbps = 550, .reg = 0x37 }, 472 { .mbps = 600, .reg = 0x07 }, 473 { .mbps = 650, .reg = 0x18 }, 474 { .mbps = 700, .reg = 0x28 }, 475 { .mbps = 750, .reg = 0x39 }, 476 { .mbps = 800, .reg = 0x09 }, 477 { .mbps = 850, .reg = 0x19 }, 478 { .mbps = 900, .reg = 0x29 }, 479 { .mbps = 950, .reg = 0x3a }, 480 { .mbps = 1000, .reg = 0x0a }, 481 { .mbps = 1050, .reg = 0x1a }, 482 { .mbps = 1100, .reg = 0x2a }, 483 { .mbps = 1150, .reg = 0x3b }, 484 { .mbps = 1200, .reg = 0x0b }, 485 { .mbps = 1250, .reg = 0x1b }, 486 { .mbps = 1300, .reg = 0x2b }, 487 { .mbps = 1350, .reg = 0x3c }, 488 { .mbps = 1400, .reg = 0x0c }, 489 { .mbps = 1450, .reg = 0x1c }, 490 { .mbps = 1500, .reg = 0x2c }, 491 { /* sentinel */ }, 492}; 493 494static const struct rcsi2_mbps_info hsfreqrange_m3w[] = { 495 { .mbps = 80, .reg = 0x00 }, 496 { .mbps = 90, .reg = 0x10 }, 497 { .mbps = 100, .reg = 0x20 }, 498 { .mbps = 110, .reg = 0x30 }, 499 { .mbps = 120, .reg = 0x01 }, 500 { .mbps = 130, .reg = 0x11 }, 501 { .mbps = 140, .reg = 0x21 }, 502 { .mbps = 150, .reg = 0x31 }, 503 { .mbps = 160, .reg = 0x02 }, 504 { .mbps = 170, .reg = 0x12 }, 505 { .mbps = 180, .reg = 0x22 }, 506 { .mbps = 190, .reg = 0x32 }, 507 { .mbps = 205, .reg = 0x03 }, 508 { .mbps = 220, .reg = 0x13 }, 509 { .mbps = 235, .reg = 0x23 }, 510 { .mbps = 250, .reg = 0x33 }, 511 { .mbps = 275, .reg = 0x04 }, 512 { .mbps = 300, .reg = 0x14 }, 513 { .mbps = 325, .reg = 0x05 }, 514 { .mbps = 350, .reg = 0x15 }, 515 { .mbps = 400, .reg = 0x25 }, 516 { .mbps = 450, .reg = 0x06 }, 517 { .mbps = 500, .reg = 0x16 }, 518 { .mbps = 550, .reg = 0x07 }, 519 { .mbps = 600, .reg = 0x17 }, 520 { .mbps = 650, .reg = 0x08 }, 521 { .mbps = 700, .reg = 0x18 }, 522 { .mbps = 750, .reg = 0x09 }, 523 { .mbps = 800, .reg = 0x19 }, 524 { .mbps = 850, .reg = 0x29 }, 525 { .mbps = 900, .reg = 0x39 }, 526 { .mbps = 950, .reg = 0x0a }, 527 { .mbps = 1000, .reg = 0x1a }, 528 { .mbps = 1050, .reg = 0x2a }, 529 { .mbps = 1100, .reg = 0x3a }, 530 { .mbps = 1150, .reg = 0x0b }, 531 { .mbps = 1200, .reg = 0x1b }, 532 { .mbps = 1250, .reg = 0x2b }, 533 { .mbps = 1300, .reg = 0x3b }, 534 { .mbps = 1350, .reg = 0x0c }, 535 { .mbps = 1400, .reg = 0x1c }, 536 { .mbps = 1450, .reg = 0x2c }, 537 { .mbps = 1500, .reg = 0x3c }, 538 { /* sentinel */ }, 539}; 540 541static const struct rcsi2_mbps_info hsfreqrange_v4m[] = { 542 { .mbps = 80, .reg = 0x00, .osc_freq = 0x01a9 }, 543 { .mbps = 90, .reg = 0x10, .osc_freq = 0x01a9 }, 544 { .mbps = 100, .reg = 0x20, .osc_freq = 0x01a9 }, 545 { .mbps = 110, .reg = 0x30, .osc_freq = 0x01a9 }, 546 { .mbps = 120, .reg = 0x01, .osc_freq = 0x01a9 }, 547 { .mbps = 130, .reg = 0x11, .osc_freq = 0x01a9 }, 548 { .mbps = 140, .reg = 0x21, .osc_freq = 0x01a9 }, 549 { .mbps = 150, .reg = 0x31, .osc_freq = 0x01a9 }, 550 { .mbps = 160, .reg = 0x02, .osc_freq = 0x01a9 }, 551 { .mbps = 170, .reg = 0x12, .osc_freq = 0x01a9 }, 552 { .mbps = 180, .reg = 0x22, .osc_freq = 0x01a9 }, 553 { .mbps = 190, .reg = 0x32, .osc_freq = 0x01a9 }, 554 { .mbps = 205, .reg = 0x03, .osc_freq = 0x01a9 }, 555 { .mbps = 220, .reg = 0x13, .osc_freq = 0x01a9 }, 556 { .mbps = 235, .reg = 0x23, .osc_freq = 0x01a9 }, 557 { .mbps = 250, .reg = 0x33, .osc_freq = 0x01a9 }, 558 { .mbps = 275, .reg = 0x04, .osc_freq = 0x01a9 }, 559 { .mbps = 300, .reg = 0x14, .osc_freq = 0x01a9 }, 560 { .mbps = 325, .reg = 0x25, .osc_freq = 0x01a9 }, 561 { .mbps = 350, .reg = 0x35, .osc_freq = 0x01a9 }, 562 { .mbps = 400, .reg = 0x05, .osc_freq = 0x01a9 }, 563 { .mbps = 450, .reg = 0x16, .osc_freq = 0x01a9 }, 564 { .mbps = 500, .reg = 0x26, .osc_freq = 0x01a9 }, 565 { .mbps = 550, .reg = 0x37, .osc_freq = 0x01a9 }, 566 { .mbps = 600, .reg = 0x07, .osc_freq = 0x01a9 }, 567 { .mbps = 650, .reg = 0x18, .osc_freq = 0x01a9 }, 568 { .mbps = 700, .reg = 0x28, .osc_freq = 0x01a9 }, 569 { .mbps = 750, .reg = 0x39, .osc_freq = 0x01a9 }, 570 { .mbps = 800, .reg = 0x09, .osc_freq = 0x01a9 }, 571 { .mbps = 850, .reg = 0x19, .osc_freq = 0x01a9 }, 572 { .mbps = 900, .reg = 0x29, .osc_freq = 0x01a9 }, 573 { .mbps = 950, .reg = 0x3a, .osc_freq = 0x01a9 }, 574 { .mbps = 1000, .reg = 0x0a, .osc_freq = 0x01a9 }, 575 { .mbps = 1050, .reg = 0x1a, .osc_freq = 0x01a9 }, 576 { .mbps = 1100, .reg = 0x2a, .osc_freq = 0x01a9 }, 577 { .mbps = 1150, .reg = 0x3b, .osc_freq = 0x01a9 }, 578 { .mbps = 1200, .reg = 0x0b, .osc_freq = 0x01a9 }, 579 { .mbps = 1250, .reg = 0x1b, .osc_freq = 0x01a9 }, 580 { .mbps = 1300, .reg = 0x2b, .osc_freq = 0x01a9 }, 581 { .mbps = 1350, .reg = 0x3c, .osc_freq = 0x01a9 }, 582 { .mbps = 1400, .reg = 0x0c, .osc_freq = 0x01a9 }, 583 { .mbps = 1450, .reg = 0x1c, .osc_freq = 0x01a9 }, 584 { .mbps = 1500, .reg = 0x2c, .osc_freq = 0x01a9 }, 585 { .mbps = 1550, .reg = 0x3d, .osc_freq = 0x0108 }, 586 { .mbps = 1600, .reg = 0x0d, .osc_freq = 0x0110 }, 587 { .mbps = 1650, .reg = 0x1d, .osc_freq = 0x0119 }, 588 { .mbps = 1700, .reg = 0x2e, .osc_freq = 0x0121 }, 589 { .mbps = 1750, .reg = 0x3e, .osc_freq = 0x012a }, 590 { .mbps = 1800, .reg = 0x0e, .osc_freq = 0x0132 }, 591 { .mbps = 1850, .reg = 0x1e, .osc_freq = 0x013b }, 592 { .mbps = 1900, .reg = 0x2f, .osc_freq = 0x0143 }, 593 { .mbps = 1950, .reg = 0x3f, .osc_freq = 0x014c }, 594 { .mbps = 2000, .reg = 0x0f, .osc_freq = 0x0154 }, 595 { .mbps = 2050, .reg = 0x40, .osc_freq = 0x015d }, 596 { .mbps = 2100, .reg = 0x41, .osc_freq = 0x0165 }, 597 { .mbps = 2150, .reg = 0x42, .osc_freq = 0x016e }, 598 { .mbps = 2200, .reg = 0x43, .osc_freq = 0x0176 }, 599 { .mbps = 2250, .reg = 0x44, .osc_freq = 0x017f }, 600 { .mbps = 2300, .reg = 0x45, .osc_freq = 0x0187 }, 601 { .mbps = 2350, .reg = 0x46, .osc_freq = 0x0190 }, 602 { .mbps = 2400, .reg = 0x47, .osc_freq = 0x0198 }, 603 { .mbps = 2450, .reg = 0x48, .osc_freq = 0x01a1 }, 604 { .mbps = 2500, .reg = 0x49, .osc_freq = 0x01a9 }, 605 { /* sentinel */ }, 606}; 607 608/* PHY ESC Error Monitor */ 609#define PHEERM_REG 0x74 610 611/* PHY Clock Lane Monitor */ 612#define PHCLM_REG 0x78 613#define PHCLM_STOPSTATECKL BIT(0) 614 615/* PHY Data Lane Monitor */ 616#define PHDLM_REG 0x7c 617 618/* CSI0CLK Frequency Configuration Preset Register */ 619#define CSI0CLKFCPR_REG 0x260 620#define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16) 621 622struct rcar_csi2_format { 623 u32 code; 624 unsigned int datatype; 625 unsigned int bpp; 626}; 627 628static const struct rcar_csi2_format rcar_csi2_formats[] = { 629 { 630 .code = MEDIA_BUS_FMT_RGB888_1X24, 631 .datatype = MIPI_CSI2_DT_RGB888, 632 .bpp = 24, 633 }, { 634 .code = MEDIA_BUS_FMT_UYVY8_1X16, 635 .datatype = MIPI_CSI2_DT_YUV422_8B, 636 .bpp = 16, 637 }, { 638 .code = MEDIA_BUS_FMT_YUYV8_1X16, 639 .datatype = MIPI_CSI2_DT_YUV422_8B, 640 .bpp = 16, 641 }, { 642 .code = MEDIA_BUS_FMT_UYVY8_2X8, 643 .datatype = MIPI_CSI2_DT_YUV422_8B, 644 .bpp = 16, 645 }, { 646 .code = MEDIA_BUS_FMT_YUYV10_2X10, 647 .datatype = MIPI_CSI2_DT_YUV422_8B, 648 .bpp = 20, 649 }, { 650 .code = MEDIA_BUS_FMT_Y8_1X8, 651 .datatype = MIPI_CSI2_DT_RAW8, 652 .bpp = 8, 653 }, { 654 .code = MEDIA_BUS_FMT_Y10_1X10, 655 .datatype = MIPI_CSI2_DT_RAW10, 656 .bpp = 10, 657 }, { 658 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 659 .datatype = MIPI_CSI2_DT_RAW8, 660 .bpp = 8, 661 }, { 662 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 663 .datatype = MIPI_CSI2_DT_RAW8, 664 .bpp = 8, 665 }, { 666 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 667 .datatype = MIPI_CSI2_DT_RAW8, 668 .bpp = 8, 669 }, { 670 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 671 .datatype = MIPI_CSI2_DT_RAW8, 672 .bpp = 8, 673 }, { 674 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 675 .datatype = MIPI_CSI2_DT_RAW10, 676 .bpp = 10, 677 }, { 678 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 679 .datatype = MIPI_CSI2_DT_RAW10, 680 .bpp = 10, 681 }, { 682 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 683 .datatype = MIPI_CSI2_DT_RAW10, 684 .bpp = 10, 685 }, { 686 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 687 .datatype = MIPI_CSI2_DT_RAW10, 688 .bpp = 10, 689 }, { 690 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 691 .datatype = MIPI_CSI2_DT_RAW12, 692 .bpp = 12, 693 }, { 694 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 695 .datatype = MIPI_CSI2_DT_RAW12, 696 .bpp = 12, 697 }, { 698 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 699 .datatype = MIPI_CSI2_DT_RAW12, 700 .bpp = 12, 701 }, { 702 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 703 .datatype = MIPI_CSI2_DT_RAW12, 704 .bpp = 12, 705 }, 706}; 707 708static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) 709{ 710 unsigned int i; 711 712 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) 713 if (rcar_csi2_formats[i].code == code) 714 return &rcar_csi2_formats[i]; 715 716 return NULL; 717} 718 719struct rcsi2_cphy_line_order { 720 enum v4l2_mbus_csi2_cphy_line_orders_type order; 721 u16 cfg; 722 u16 ctrl29; 723}; 724 725static const struct rcsi2_cphy_line_order rcsi2_cphy_line_orders[] = { 726 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ABC, .cfg = 0x0, .ctrl29 = 0x0 }, 727 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ACB, .cfg = 0xa, .ctrl29 = 0x1 }, 728 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BAC, .cfg = 0xc, .ctrl29 = 0x1 }, 729 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BCA, .cfg = 0x5, .ctrl29 = 0x0 }, 730 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CAB, .cfg = 0x3, .ctrl29 = 0x0 }, 731 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CBA, .cfg = 0x9, .ctrl29 = 0x1 } 732}; 733 734enum rcar_csi2_pads { 735 RCAR_CSI2_SINK, 736 RCAR_CSI2_SOURCE_VC0, 737 RCAR_CSI2_SOURCE_VC1, 738 RCAR_CSI2_SOURCE_VC2, 739 RCAR_CSI2_SOURCE_VC3, 740 NR_OF_RCAR_CSI2_PAD, 741}; 742 743struct rcsi2_register_layout { 744 unsigned int phtw; 745 unsigned int phypll; 746}; 747 748struct rcar_csi2_info { 749 const struct rcsi2_register_layout *regs; 750 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); 751 int (*phy_post_init)(struct rcar_csi2 *priv); 752 int (*start_receiver)(struct rcar_csi2 *priv, 753 struct v4l2_subdev_state *state); 754 void (*enter_standby)(struct rcar_csi2 *priv); 755 const struct rcsi2_mbps_info *hsfreqrange; 756 unsigned int csi0clkfreqrange; 757 unsigned int num_channels; 758 bool clear_ulps; 759 bool use_isp; 760 bool support_dphy; 761 bool support_cphy; 762}; 763 764struct rcar_csi2 { 765 struct device *dev; 766 void __iomem *base; 767 const struct rcar_csi2_info *info; 768 struct reset_control *rstc; 769 770 struct v4l2_subdev subdev; 771 struct media_pad pads[NR_OF_RCAR_CSI2_PAD]; 772 773 struct v4l2_async_notifier notifier; 774 struct v4l2_subdev *remote; 775 unsigned int remote_pad; 776 777 int channel_vc[4]; 778 779 int stream_count; 780 781 bool cphy; 782 unsigned short lanes; 783 unsigned char lane_swap[4]; 784 enum v4l2_mbus_csi2_cphy_line_orders_type line_orders[3]; 785}; 786 787static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 788{ 789 return container_of(sd, struct rcar_csi2, subdev); 790} 791 792static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 793{ 794 return container_of(n, struct rcar_csi2, notifier); 795} 796 797static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv) 798{ 799 /* Used together with R-Car ISP: one sink and one source pad. */ 800 if (priv->info->use_isp) 801 return 2; 802 803 /* Used together with R-Car VIN: one sink and four source pads. */ 804 return 5; 805} 806 807static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) 808{ 809 return ioread32(priv->base + reg); 810} 811 812static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) 813{ 814 iowrite32(data, priv->base + reg); 815} 816 817static u16 rcsi2_read16(struct rcar_csi2 *priv, unsigned int reg) 818{ 819 return ioread16(priv->base + reg); 820} 821 822static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data) 823{ 824 iowrite16(data, priv->base + reg); 825} 826 827static void rcsi2_modify16(struct rcar_csi2 *priv, unsigned int reg, u16 data, u16 mask) 828{ 829 u16 val; 830 831 val = rcsi2_read16(priv, reg) & ~mask; 832 rcsi2_write16(priv, reg, val | data); 833} 834 835static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) 836{ 837 unsigned int timeout; 838 839 rcsi2_write(priv, priv->info->regs->phtw, 840 PHTW_DWEN | PHTW_TESTDIN_DATA(data) | 841 PHTW_CWEN | PHTW_TESTDIN_CODE(code)); 842 843 /* Wait for DWEN and CWEN to be cleared by hardware. */ 844 for (timeout = 0; timeout <= 20; timeout++) { 845 if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN))) 846 return 0; 847 848 usleep_range(1000, 2000); 849 } 850 851 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); 852 853 return -ETIMEDOUT; 854} 855 856static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, 857 const struct phtw_value *values, 858 unsigned int size) 859{ 860 int ret; 861 862 for (unsigned int i = 0; i < size; i++) { 863 ret = rcsi2_phtw_write(priv, values[i].data, values[i].code); 864 if (ret) 865 return ret; 866 } 867 868 return 0; 869} 870 871static const struct rcsi2_mbps_info * 872rcsi2_mbps_to_info(struct rcar_csi2 *priv, 873 const struct rcsi2_mbps_info *infotable, unsigned int mbps) 874{ 875 const struct rcsi2_mbps_info *info; 876 const struct rcsi2_mbps_info *prev = NULL; 877 878 if (mbps < infotable->mbps) 879 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", 880 mbps, infotable->mbps); 881 882 for (info = infotable; info->mbps != 0; info++) { 883 if (info->mbps >= mbps) 884 break; 885 prev = info; 886 } 887 888 if (!info->mbps) { 889 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 890 return NULL; 891 } 892 893 if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps))) 894 info = prev; 895 896 return info; 897} 898 899static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) 900{ 901 rcsi2_write(priv, PHYCNT_REG, 0); 902 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); 903} 904 905static void rcsi2_enter_standby(struct rcar_csi2 *priv) 906{ 907 if (priv->info->enter_standby) 908 priv->info->enter_standby(priv); 909 910 reset_control_assert(priv->rstc); 911 usleep_range(100, 150); 912 pm_runtime_put(priv->dev); 913} 914 915static int rcsi2_exit_standby(struct rcar_csi2 *priv) 916{ 917 int ret; 918 919 ret = pm_runtime_resume_and_get(priv->dev); 920 if (ret < 0) 921 return ret; 922 923 reset_control_deassert(priv->rstc); 924 925 return 0; 926} 927 928static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, 929 unsigned int lanes) 930{ 931 unsigned int timeout; 932 933 /* Wait for the clock and data lanes to enter LP-11 state. */ 934 for (timeout = 0; timeout <= 20; timeout++) { 935 const u32 lane_mask = (1 << lanes) - 1; 936 937 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) && 938 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) 939 return 0; 940 941 usleep_range(1000, 2000); 942 } 943 944 dev_err(priv->dev, "Timeout waiting for LP-11 state\n"); 945 946 return -ETIMEDOUT; 947} 948 949static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) 950{ 951 const struct rcsi2_mbps_info *info; 952 953 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 954 if (!info) 955 return -ERANGE; 956 957 rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(info->reg)); 958 959 return 0; 960} 961 962static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, 963 unsigned int lanes) 964{ 965 struct media_pad *remote_pad; 966 struct v4l2_subdev *source; 967 s64 freq; 968 u64 mbps; 969 970 if (!priv->remote) 971 return -ENODEV; 972 973 source = priv->remote; 974 remote_pad = &source->entity.pads[priv->remote_pad]; 975 976 freq = v4l2_get_link_freq(remote_pad, bpp, 2 * lanes); 977 if (freq < 0) { 978 int ret = (int)freq; 979 980 dev_err(priv->dev, "failed to get link freq for %s: %d\n", 981 source->name, ret); 982 983 return ret; 984 } 985 986 mbps = div_u64(freq * 2, MEGA); 987 988 return mbps; 989} 990 991static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, 992 unsigned int *lanes) 993{ 994 struct v4l2_mbus_config mbus_config = { 0 }; 995 int ret; 996 997 *lanes = priv->lanes; 998 999 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config, 1000 priv->remote_pad, &mbus_config); 1001 if (ret == -ENOIOCTLCMD) { 1002 dev_dbg(priv->dev, "No remote mbus configuration available\n"); 1003 return 0; 1004 } 1005 1006 if (ret) { 1007 dev_err(priv->dev, "Failed to get remote mbus configuration\n"); 1008 return ret; 1009 } 1010 1011 switch (mbus_config.type) { 1012 case V4L2_MBUS_CSI2_CPHY: 1013 if (!priv->cphy) 1014 return -EINVAL; 1015 break; 1016 case V4L2_MBUS_CSI2_DPHY: 1017 if (priv->cphy) 1018 return -EINVAL; 1019 break; 1020 default: 1021 dev_err(priv->dev, "Unsupported media bus type %u\n", 1022 mbus_config.type); 1023 return -EINVAL; 1024 } 1025 1026 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) { 1027 dev_err(priv->dev, 1028 "Unsupported mbus config: too many data lanes %u\n", 1029 mbus_config.bus.mipi_csi2.num_data_lanes); 1030 return -EINVAL; 1031 } 1032 1033 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes; 1034 1035 return 0; 1036} 1037 1038static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv, 1039 struct v4l2_subdev_state *state) 1040{ 1041 const struct rcar_csi2_format *format; 1042 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; 1043 const struct v4l2_mbus_framefmt *fmt; 1044 unsigned int lanes; 1045 unsigned int i; 1046 int mbps, ret; 1047 1048 /* Use the format on the sink pad to compute the receiver config. */ 1049 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1050 1051 dev_dbg(priv->dev, "Input size (%ux%u%c)\n", 1052 fmt->width, fmt->height, 1053 fmt->field == V4L2_FIELD_NONE ? 'p' : 'i'); 1054 1055 /* Code is validated in set_fmt. */ 1056 format = rcsi2_code_to_fmt(fmt->code); 1057 if (!format) 1058 return -EINVAL; 1059 1060 /* 1061 * Enable all supported CSI-2 channels with virtual channel and 1062 * data type matching. 1063 * 1064 * NOTE: It's not possible to get individual datatype for each 1065 * source virtual channel. Once this is possible in V4L2 1066 * it should be used here. 1067 */ 1068 for (i = 0; i < priv->info->num_channels; i++) { 1069 u32 vcdt_part; 1070 1071 if (priv->channel_vc[i] < 0) 1072 continue; 1073 1074 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN | 1075 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype); 1076 1077 /* Store in correct reg and offset. */ 1078 if (i < 2) 1079 vcdt |= vcdt_part << ((i % 2) * 16); 1080 else 1081 vcdt2 |= vcdt_part << ((i % 2) * 16); 1082 } 1083 1084 if (fmt->field == V4L2_FIELD_ALTERNATE) 1085 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2 1086 | FLD_FLD_EN; 1087 1088 /* 1089 * Get the number of active data lanes inspecting the remote mbus 1090 * configuration. 1091 */ 1092 ret = rcsi2_get_active_lanes(priv, &lanes); 1093 if (ret) 1094 return ret; 1095 1096 phycnt = PHYCNT_ENABLECLK; 1097 phycnt |= (1 << lanes) - 1; 1098 1099 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1100 if (mbps < 0) 1101 return mbps; 1102 1103 /* Enable interrupts. */ 1104 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS 1105 | INTEN_INT_ERRSOTSYNCHS); 1106 1107 /* Init */ 1108 rcsi2_write(priv, TREF_REG, TREF_TREF); 1109 rcsi2_write(priv, PHTC_REG, 0); 1110 1111 /* Configure */ 1112 if (!priv->info->use_isp) { 1113 rcsi2_write(priv, VCDT_REG, vcdt); 1114 if (vcdt2) 1115 rcsi2_write(priv, VCDT2_REG, vcdt2); 1116 } 1117 1118 /* Lanes are zero indexed. */ 1119 rcsi2_write(priv, LSWAP_REG, 1120 LSWAP_L0SEL(priv->lane_swap[0] - 1) | 1121 LSWAP_L1SEL(priv->lane_swap[1] - 1) | 1122 LSWAP_L2SEL(priv->lane_swap[2] - 1) | 1123 LSWAP_L3SEL(priv->lane_swap[3] - 1)); 1124 1125 /* Start */ 1126 if (priv->info->init_phtw) { 1127 ret = priv->info->init_phtw(priv, mbps); 1128 if (ret) 1129 return ret; 1130 } 1131 1132 if (priv->info->hsfreqrange) { 1133 ret = rcsi2_set_phypll(priv, mbps); 1134 if (ret) 1135 return ret; 1136 } 1137 1138 if (priv->info->csi0clkfreqrange) 1139 rcsi2_write(priv, CSI0CLKFCPR_REG, 1140 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1141 1142 if (priv->info->use_isp) 1143 rcsi2_write(priv, PHYFRX_REG, 1144 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 | 1145 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0); 1146 1147 rcsi2_write(priv, PHYCNT_REG, phycnt); 1148 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN | 1149 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP); 1150 rcsi2_write(priv, FLD_REG, fld); 1151 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ); 1152 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ); 1153 1154 ret = rcsi2_wait_phy_start(priv, lanes); 1155 if (ret) 1156 return ret; 1157 1158 if (priv->info->use_isp) 1159 rcsi2_write(priv, PHYFRX_REG, 0); 1160 1161 /* Run post PHY start initialization, if needed. */ 1162 if (priv->info->phy_post_init) { 1163 ret = priv->info->phy_post_init(priv); 1164 if (ret) 1165 return ret; 1166 } 1167 1168 /* Clear Ultra Low Power interrupt. */ 1169 if (priv->info->clear_ulps) 1170 rcsi2_write(priv, INTSTATE_REG, 1171 INTSTATE_INT_ULPS_START | 1172 INTSTATE_INT_ULPS_END); 1173 return 0; 1174} 1175 1176static void rsci2_set_line_order(struct rcar_csi2 *priv, 1177 enum v4l2_mbus_csi2_cphy_line_orders_type order, 1178 unsigned int cfgreg, unsigned int ctrlreg) 1179{ 1180 const struct rcsi2_cphy_line_order *info = NULL; 1181 1182 for (unsigned int i = 0; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) { 1183 if (rcsi2_cphy_line_orders[i].order == order) { 1184 info = &rcsi2_cphy_line_orders[i]; 1185 break; 1186 } 1187 } 1188 1189 if (!info) 1190 return; 1191 1192 rcsi2_modify16(priv, cfgreg, info->cfg, 0x000f); 1193 rcsi2_modify16(priv, ctrlreg, info->ctrl29, 0x0100); 1194} 1195 1196static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match) 1197{ 1198 unsigned int timeout; 1199 u32 status; 1200 1201 for (timeout = 0; timeout <= 10; timeout++) { 1202 status = rcsi2_read(priv, V4H_ST_PHYST_REG); 1203 if ((status & match) == match) 1204 return 0; 1205 1206 usleep_range(1000, 2000); 1207 } 1208 1209 return -ETIMEDOUT; 1210} 1211 1212static const struct rcsi2_cphy_setting * 1213rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) 1214{ 1215 const struct rcsi2_cphy_setting *conf; 1216 int msps; 1217 1218 /* Adjust for C-PHY symbols, divide by 2.8. */ 1219 msps = div_u64(mbps * 5, 14); 1220 1221 for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) { 1222 if (conf->msps > msps) 1223 break; 1224 } 1225 1226 if (!conf->msps) { 1227 dev_err(priv->dev, "Unsupported PHY speed for msps setting (%u Msps)", msps); 1228 return NULL; 1229 } 1230 1231 /* C-PHY specific */ 1232 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0155); 1233 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), 0x0068); 1234 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0010); 1235 1236 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_LP_0_REG, 0x463c); 1237 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_LP_0_REG, 0x463c); 1238 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_LP_0_REG, 0x463c); 1239 1240 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(0), 0x00d5); 1241 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(0), 0x00d5); 1242 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(0), 0x00d5); 1243 1244 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(1), 0x0013); 1245 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(1), 0x0013); 1246 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(1), 0x0013); 1247 1248 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(5), 0x0013); 1249 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(5), 0x0013); 1250 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(5), 0x0013); 1251 1252 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(6), 0x000a); 1253 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(6), 0x000a); 1254 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(6), 0x000a); 1255 1256 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(2), conf->rx2); 1257 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2); 1258 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2); 1259 1260 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 2), 0x0001); 1261 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 2), 0); 1262 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 2), 0x0001); 1263 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(3, 2), 0x0001); 1264 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(4, 2), 0); 1265 1266 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0); 1267 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0); 1268 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(0), conf->trio0); 1269 1270 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(2), conf->trio2); 1271 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(2), conf->trio2); 1272 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(2), conf->trio2); 1273 1274 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(1), conf->trio1); 1275 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(1), conf->trio1); 1276 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(1), conf->trio1); 1277 1278 /* Configure data line order. */ 1279 rsci2_set_line_order(priv, priv->line_orders[0], 1280 V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG, 1281 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 9)); 1282 rsci2_set_line_order(priv, priv->line_orders[1], 1283 V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG, 1284 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 9)); 1285 rsci2_set_line_order(priv, priv->line_orders[2], 1286 V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG, 1287 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 9)); 1288 1289 /* TODO: This registers is not documented. */ 1290 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000); 1291 1292 return conf; 1293} 1294 1295struct rcsi2_d_phy_setting_v4h_lut_value { 1296 unsigned int mbps; 1297 unsigned char cfg_1; 1298 unsigned char cfg_5_94; 1299 unsigned char cfg_5_30; 1300 unsigned char lane_ctrl_2_8; 1301 unsigned char rw_hs_rx_3_83; 1302 unsigned char rw_hs_rx_3_20; 1303 unsigned char rw_hs_rx_6; 1304 unsigned char rw_hs_rx_1; 1305}; 1306 1307static const struct rcsi2_d_phy_setting_v4h_lut_value * 1308rcsi2_d_phy_setting_v4h_lut_lookup(int mbps) 1309{ 1310 static const struct rcsi2_d_phy_setting_v4h_lut_value values[] = { 1311 { 4500, 0x3f, 0x07, 0x00, 0x01, 0x02, 0x01, 0x0d, 0x10 }, 1312 { 4000, 0x47, 0x08, 0x01, 0x01, 0x05, 0x01, 0x0f, 0x0d }, 1313 { 3600, 0x4f, 0x09, 0x01, 0x01, 0x06, 0x01, 0x10, 0x0b }, 1314 { 3230, 0x57, 0x0a, 0x01, 0x01, 0x06, 0x01, 0x12, 0x09 }, 1315 { 3000, 0x47, 0x08, 0x00, 0x00, 0x03, 0x01, 0x0f, 0x0c }, 1316 { 2700, 0x4f, 0x09, 0x01, 0x00, 0x06, 0x01, 0x10, 0x0b }, 1317 { 2455, 0x57, 0x0a, 0x01, 0x00, 0x06, 0x01, 0x12, 0x09 }, 1318 { 2250, 0x5f, 0x0b, 0x01, 0x00, 0x08, 0x01, 0x13, 0x08 }, 1319 { 2077, 0x67, 0x0c, 0x01, 0x00, 0x06, 0x02, 0x15, 0x0d }, 1320 { 1929, 0x6f, 0x0d, 0x02, 0x00, 0x06, 0x02, 0x17, 0x0d }, 1321 { 1800, 0x77, 0x0e, 0x02, 0x00, 0x06, 0x02, 0x18, 0x0d }, 1322 { 1688, 0x7f, 0x0f, 0x02, 0x00, 0x08, 0x02, 0x1a, 0x0d }, 1323 { 1588, 0x87, 0x10, 0x02, 0x00, 0x08, 0x02, 0x1b, 0x0d }, 1324 { 1500, 0x8f, 0x11, 0x03, 0x00, 0x08, 0x02, 0x1d, 0x0c }, 1325 }; 1326 1327 for (unsigned int i = 0; i < ARRAY_SIZE(values); i++) 1328 if (mbps >= values[i].mbps) 1329 return &values[i]; 1330 1331 return NULL; 1332} 1333 1334static int rcsi2_d_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) 1335{ 1336 const struct rcsi2_d_phy_setting_v4h_lut_value *lut = 1337 rcsi2_d_phy_setting_v4h_lut_lookup(mbps); 1338 u16 val; 1339 1340 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0000); 1341 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), mbps > 1500 ? 0x0028 : 0x0068); 1342 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0050); 1343 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(0), 0x0063); 1344 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(7), 0x1132); 1345 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(1), 0x1340); 1346 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(2), 0x4b13); 1347 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(4), 0x000a); 1348 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(6), 0x800a); 1349 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(7), 0x1109); 1350 1351 if (mbps > 1500) { 1352 val = DIV_ROUND_UP(5 * mbps, 64); 1353 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(3), val); 1354 } 1355 1356 if (lut) { 1357 rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(1), 1358 lut->cfg_1, 0x00ff); 1359 rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(5), 1360 lut->cfg_5_94 << 4, 0x03f0); 1361 rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(5), 1362 lut->cfg_5_30 << 0, 0x000f); 1363 1364 for (unsigned int l = 0; l < 5; l++) 1365 rcsi2_modify16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 8), 1366 lut->lane_ctrl_2_8 << 12, 0x1000); 1367 } 1368 1369 for (unsigned int l = 0; l < 4; l++) 1370 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, 0), 0x463c); 1371 1372 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 2), 0x0000); 1373 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 2), 0x0000); 1374 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 2), 0x0001); 1375 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(3, 2), 0x0000); 1376 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(4, 2), 0x0000); 1377 1378 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(6), 0x0009); 1379 1380 val = mbps > 1500 ? 0x0800 : 0x0802; 1381 for (unsigned int l = 0; l < 5; l++) 1382 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 12), val); 1383 1384 val = mbps > 1500 ? 0x0000 : 0x0002; 1385 for (unsigned int l = 0; l < 5; l++) 1386 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 13), val); 1387 1388 if (mbps >= 80) { 1389 /* 2560: 6, 1280: 5, 640: 4, 320: 3, 160: 2, 80: 1 */ 1390 val = ilog2(mbps / 80) + 1; 1391 rcsi2_modify16(priv, 1392 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 9), 1393 val << 5, 0xe0); 1394 } 1395 1396 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(0), 0x091c); 1397 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(7), 0x3b06); 1398 1399 val = DIV_ROUND_UP(1200, mbps) + 12; 1400 for (unsigned int l = 0; l < 4; l++) 1401 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 0), val << 8, 0xf0); 1402 1403 val = mbps > 1500 ? 0x0004 : 0x0008; 1404 for (unsigned int l = 0; l < 4; l++) 1405 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, 1), val); 1406 1407 val = mbps > 2500 ? 0x669a : mbps > 1500 ? 0xe69a : 0xe69b; 1408 for (unsigned int l = 0; l < 4; l++) 1409 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 2), val); 1410 1411 for (unsigned int l = 0; l < 4; l++) 1412 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, 0), 0x163c); 1413 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(0), 0x163c); 1414 1415 if (lut) { 1416 for (unsigned int l = 0; l < 4; l++) 1417 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 1), 1418 lut->rw_hs_rx_1, 0xff); 1419 } 1420 1421 for (unsigned int l = 0; l < 4; l++) 1422 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 3), 0x9209); 1423 1424 for (unsigned int l = 0; l < 4; l++) 1425 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 4), 0x0096); 1426 1427 for (unsigned int l = 0; l < 4; l++) 1428 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 5), 0x0100); 1429 1430 for (unsigned int l = 0; l < 4; l++) 1431 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 6), 0x2d02); 1432 1433 for (unsigned int l = 0; l < 4; l++) 1434 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 7), 0x1b06); 1435 1436 if (lut) { 1437 /* 1438 * Documentation LUT have two values but document writing both 1439 * values in a single write. 1440 */ 1441 for (unsigned int l = 0; l < 4; l++) 1442 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 3), 1443 lut->rw_hs_rx_3_83 << 3 | lut->rw_hs_rx_3_20, 0x1ff); 1444 1445 for (unsigned int l = 0; l < 4; l++) 1446 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 6), 1447 lut->rw_hs_rx_6 << 8, 0xff00); 1448 } 1449 1450 static const u16 deskew_fine[] = { 1451 0x0404, 0x040c, 0x0414, 0x041c, 0x0423, 0x0429, 0x0430, 0x043a, 1452 0x0445, 0x044a, 0x0450, 0x045a, 0x0465, 0x0469, 0x0472, 0x047a, 1453 0x0485, 0x0489, 0x0490, 0x049a, 0x04a4, 0x04ac, 0x04b4, 0x04bc, 1454 0x04c4, 0x04cc, 0x04d4, 0x04dc, 0x04e4, 0x04ec, 0x04f4, 0x04fc, 1455 0x0504, 0x050c, 0x0514, 0x051c, 0x0523, 0x0529, 0x0530, 0x053a, 1456 0x0545, 0x054a, 0x0550, 0x055a, 0x0565, 0x0569, 0x0572, 0x057a, 1457 0x0585, 0x0589, 0x0590, 0x059a, 0x05a4, 0x05ac, 0x05b4, 0x05bc, 1458 0x05c4, 0x05cc, 0x05d4, 0x05dc, 0x05e4, 0x05ec, 0x05f4, 0x05fc, 1459 0x0604, 0x060c, 0x0614, 0x061c, 0x0623, 0x0629, 0x0632, 0x063a, 1460 0x0645, 0x064a, 0x0650, 0x065a, 0x0665, 0x0669, 0x0672, 0x067a, 1461 0x0685, 0x0689, 0x0690, 0x069a, 0x06a4, 0x06ac, 0x06b4, 0x06bc, 1462 0x06c4, 0x06cc, 0x06d4, 0x06dc, 0x06e4, 0x06ec, 0x06f4, 0x06fc, 1463 0x0704, 0x070c, 0x0714, 0x071c, 0x0723, 0x072a, 0x0730, 0x073a, 1464 0x0745, 0x074a, 0x0750, 0x075a, 0x0765, 0x0769, 0x0772, 0x077a, 1465 0x0785, 0x0789, 0x0790, 0x079a, 0x07a4, 0x07ac, 0x07b4, 0x07bc, 1466 0x07c4, 0x07cc, 0x07d4, 0x07dc, 0x07e4, 0x07ec, 0x07f4, 0x07fc, 1467 }; 1468 1469 for (unsigned int i = 0; i < ARRAY_SIZE(deskew_fine); i++) { 1470 rcsi2_write16(priv, V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG, 1471 deskew_fine[i]); 1472 } 1473 1474 return 0; 1475} 1476 1477static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, 1478 struct v4l2_subdev_state *state) 1479{ 1480 const struct rcsi2_cphy_setting *cphy = NULL; 1481 const struct rcar_csi2_format *format; 1482 const struct v4l2_mbus_framefmt *fmt; 1483 unsigned int lanes; 1484 int mbps; 1485 int ret; 1486 1487 /* Use the format on the sink pad to compute the receiver config. */ 1488 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1489 format = rcsi2_code_to_fmt(fmt->code); 1490 if (!format) 1491 return -EINVAL; 1492 1493 ret = rcsi2_get_active_lanes(priv, &lanes); 1494 if (ret) 1495 return ret; 1496 1497 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1498 if (mbps < 0) 1499 return mbps; 1500 1501 /* T0: Reset LINK and PHY*/ 1502 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1503 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1504 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1505 1506 /* T1: PHY static setting */ 1507 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | 1508 V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | 1509 V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); 1510 rcsi2_write(priv, V4H_FLDC_REG, 0); 1511 rcsi2_write(priv, V4H_FLDD_REG, 0); 1512 rcsi2_write(priv, V4H_IDIC_REG, 0); 1513 rcsi2_write(priv, V4H_PHY_MODE_REG, 1514 priv->cphy ? V4H_PHY_MODE_CPHY : V4H_PHY_MODE_DPHY); 1515 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1516 1517 rcsi2_write(priv, V4M_FRXM_REG, 1518 V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | 1519 V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); 1520 rcsi2_write(priv, V4M_OVR1_REG, 1521 V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | 1522 V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); 1523 1524 /* T2: Reset CSI2 */ 1525 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1526 1527 /* Registers static setting through APB */ 1528 /* Common setting */ 1529 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(10), 0x0030); 1530 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(2), 0x1444); 1531 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd); 1532 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233); 1533 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027); 1534 rcsi2_write16(priv, V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG, 0x01f4); 1535 rcsi2_write16(priv, V4H_PPI_RW_TERMCAL_CFG_0_REG, 0x0013); 1536 rcsi2_write16(priv, V4H_PPI_RW_OFFSETCAL_CFG_0_REG, 0x0003); 1537 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG, 0x004f); 1538 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_REG, 0x0320); 1539 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG, 0x000f); 1540 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG, 0xfe18); 1541 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG, 0x0c3c); 1542 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105); 1543 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000); 1544 rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003); 1545 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(0), 0x0000); 1546 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(1), 0x0400); 1547 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(3), 0x41f6); 1548 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(0), 0x0000); 1549 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(3), 0x43f6); 1550 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x3000); 1551 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(7), 0x0000); 1552 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x7000); 1553 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(7), 0x0000); 1554 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(5), 0x4000); 1555 1556 /* T3: PHY settings */ 1557 if (priv->cphy) { 1558 cphy = rcsi2_c_phy_setting_v4h(priv, mbps); 1559 if (!cphy) 1560 return -ERANGE; 1561 } else { 1562 ret = rcsi2_d_phy_setting_v4h(priv, mbps); 1563 if (ret) 1564 return ret; 1565 } 1566 1567 /* T4: Leave Shutdown mode */ 1568 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1569 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1570 1571 /* T5: Wait for calibration */ 1572 if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) { 1573 dev_err(priv->dev, "PHY calibration failed\n"); 1574 return -ETIMEDOUT; 1575 } 1576 1577 /* T6: Analog programming */ 1578 if (priv->cphy) { 1579 for (unsigned int l = 0; l < 3; l++) { 1580 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 9), 1581 cphy->lane29); 1582 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 7), 1583 cphy->lane27); 1584 } 1585 } else { 1586 u16 val_2_9 = mbps > 2500 ? 0x14 : mbps > 1500 ? 0x04 : 0x00; 1587 u16 val_2_15 = mbps > 1500 ? 0x03 : 0x00; 1588 1589 for (unsigned int l = 0; l < 5; l++) { 1590 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 9), 1591 val_2_9); 1592 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 15), 1593 val_2_15); 1594 } 1595 } 1596 1597 /* T7: Wait for stop state */ 1598 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1599 V4H_ST_PHYST_ST_STOPSTATE_1 | 1600 V4H_ST_PHYST_ST_STOPSTATE_2 | 1601 V4H_ST_PHYST_ST_STOPSTATE_3); 1602 1603 /* T8: De-assert FRXM */ 1604 rcsi2_write(priv, V4M_FRXM_REG, 0); 1605 1606 return 0; 1607} 1608 1609static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int mbps) 1610{ 1611 unsigned int timeout; 1612 int ret; 1613 1614 static const struct phtw_value step1[] = { 1615 { .data = 0x00, .code = 0x00 }, 1616 { .data = 0x00, .code = 0x1e }, 1617 }; 1618 1619 /* Shutdown and reset PHY. */ 1620 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1621 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1622 1623 /* Start internal calibration (POR). */ 1624 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1625 if (ret) 1626 return ret; 1627 1628 /* Wait for POR to complete. */ 1629 for (timeout = 10; timeout > 0; timeout--) { 1630 if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000) 1631 break; 1632 usleep_range(1000, 2000); 1633 } 1634 1635 if (!timeout) { 1636 dev_err(priv->dev, "D-PHY calibration failed\n"); 1637 return -ETIMEDOUT; 1638 } 1639 1640 return 0; 1641} 1642 1643static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps) 1644{ 1645 const struct rcsi2_mbps_info *info; 1646 struct phtw_value steps[] = { 1647 { .data = 0x00, .code = 0x00 }, 1648 { .code = 0xe2 }, /* Data filled in below. */ 1649 { .code = 0xe3 }, /* Data filled in below. */ 1650 { .data = 0x01, .code = 0xe4 }, 1651 }; 1652 1653 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 1654 if (!info) 1655 return -ERANGE; 1656 1657 /* Fill in data for command. */ 1658 steps[1].data = (info->osc_freq & 0x00ff) >> 0; 1659 steps[2].data = (info->osc_freq & 0x0f00) >> 8; 1660 1661 return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps)); 1662} 1663 1664static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps) 1665{ 1666 int ret; 1667 1668 static const struct phtw_value step1[] = { 1669 { .data = 0x00, .code = 0x00 }, 1670 { .data = 0x3c, .code = 0x08 }, 1671 }; 1672 1673 static const struct phtw_value step2[] = { 1674 { .data = 0x00, .code = 0x00 }, 1675 { .data = 0x80, .code = 0xe0 }, 1676 { .data = 0x31, .code = 0xe1 }, 1677 { .data = 0x06, .code = 0x00 }, 1678 { .data = 0x11, .code = 0x11 }, 1679 { .data = 0x08, .code = 0x00 }, 1680 { .data = 0x11, .code = 0x11 }, 1681 { .data = 0x0a, .code = 0x00 }, 1682 { .data = 0x11, .code = 0x11 }, 1683 { .data = 0x0c, .code = 0x00 }, 1684 { .data = 0x11, .code = 0x11 }, 1685 { .data = 0x01, .code = 0x00 }, 1686 { .data = 0x31, .code = 0xaa }, 1687 { .data = 0x05, .code = 0x00 }, 1688 { .data = 0x05, .code = 0x09 }, 1689 { .data = 0x07, .code = 0x00 }, 1690 { .data = 0x05, .code = 0x09 }, 1691 { .data = 0x09, .code = 0x00 }, 1692 { .data = 0x05, .code = 0x09 }, 1693 { .data = 0x0b, .code = 0x00 }, 1694 { .data = 0x05, .code = 0x09 }, 1695 }; 1696 1697 static const struct phtw_value step3[] = { 1698 { .data = 0x01, .code = 0x00 }, 1699 { .data = 0x06, .code = 0xab }, 1700 }; 1701 1702 if (priv->info->hsfreqrange) { 1703 ret = rcsi2_set_phypll(priv, mbps); 1704 if (ret) 1705 return ret; 1706 1707 ret = rcsi2_set_osc_freq(priv, mbps); 1708 if (ret) 1709 return ret; 1710 } 1711 1712 if (mbps <= 1500) { 1713 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1714 if (ret) 1715 return ret; 1716 } 1717 1718 if (priv->info->csi0clkfreqrange) 1719 rcsi2_write(priv, V4M_CSI0CLKFCPR_REG, 1720 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1721 1722 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | 1723 V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | 1724 V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); 1725 1726 if (mbps > 1500) { 1727 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 1728 if (ret) 1729 return ret; 1730 } 1731 1732 return rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); 1733} 1734 1735static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv, 1736 struct v4l2_subdev_state *state) 1737{ 1738 const struct rcar_csi2_format *format; 1739 const struct v4l2_mbus_framefmt *fmt; 1740 unsigned int lanes; 1741 int mbps; 1742 int ret; 1743 1744 /* Calculate parameters */ 1745 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1746 format = rcsi2_code_to_fmt(fmt->code); 1747 if (!format) 1748 return -EINVAL; 1749 1750 ret = rcsi2_get_active_lanes(priv, &lanes); 1751 if (ret) 1752 return ret; 1753 1754 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1755 if (mbps < 0) 1756 return mbps; 1757 1758 /* Reset LINK and PHY */ 1759 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1760 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1761 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1762 rcsi2_write(priv, V4M_PHTC_REG, PHTC_TESTCLR); 1763 1764 /* PHY static setting */ 1765 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); 1766 rcsi2_write(priv, V4H_FLDC_REG, 0); 1767 rcsi2_write(priv, V4H_FLDD_REG, 0); 1768 rcsi2_write(priv, V4H_IDIC_REG, 0); 1769 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_DPHY); 1770 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1771 1772 rcsi2_write(priv, V4M_FRXM_REG, 1773 V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | 1774 V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); 1775 rcsi2_write(priv, V4M_OVR1_REG, 1776 V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | 1777 V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); 1778 1779 /* Reset CSI2 */ 1780 rcsi2_write(priv, V4M_PHTC_REG, 0); 1781 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1782 1783 /* Common settings */ 1784 ret = rcsi2_init_common_v4m(priv, mbps); 1785 if (ret) 1786 return ret; 1787 1788 /* D-PHY settings */ 1789 ret = rcsi2_d_phy_setting_v4m(priv, mbps); 1790 if (ret) 1791 return ret; 1792 1793 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1794 V4H_ST_PHYST_ST_STOPSTATE_1 | 1795 V4H_ST_PHYST_ST_STOPSTATE_2 | 1796 V4H_ST_PHYST_ST_STOPSTATE_3); 1797 1798 rcsi2_write(priv, V4M_FRXM_REG, 0); 1799 1800 return 0; 1801} 1802 1803static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) 1804{ 1805 int ret; 1806 1807 ret = rcsi2_exit_standby(priv); 1808 if (ret < 0) 1809 return ret; 1810 1811 ret = priv->info->start_receiver(priv, state); 1812 if (ret) { 1813 rcsi2_enter_standby(priv); 1814 return ret; 1815 } 1816 1817 ret = v4l2_subdev_enable_streams(priv->remote, priv->remote_pad, 1818 BIT_ULL(0)); 1819 if (ret) { 1820 rcsi2_enter_standby(priv); 1821 return ret; 1822 } 1823 1824 return 0; 1825} 1826 1827static void rcsi2_stop(struct rcar_csi2 *priv) 1828{ 1829 rcsi2_enter_standby(priv); 1830 v4l2_subdev_disable_streams(priv->remote, priv->remote_pad, BIT_ULL(0)); 1831} 1832 1833static int rcsi2_enable_streams(struct v4l2_subdev *sd, 1834 struct v4l2_subdev_state *state, u32 source_pad, 1835 u64 source_streams_mask) 1836{ 1837 struct rcar_csi2 *priv = sd_to_csi2(sd); 1838 int ret = 0; 1839 1840 if (source_streams_mask != 1) 1841 return -EINVAL; 1842 1843 if (!priv->remote) 1844 return -ENODEV; 1845 1846 if (priv->stream_count == 0) { 1847 ret = rcsi2_start(priv, state); 1848 if (ret) 1849 return ret; 1850 } 1851 1852 priv->stream_count += 1; 1853 1854 return ret; 1855} 1856 1857static int rcsi2_disable_streams(struct v4l2_subdev *sd, 1858 struct v4l2_subdev_state *state, 1859 u32 source_pad, u64 source_streams_mask) 1860{ 1861 struct rcar_csi2 *priv = sd_to_csi2(sd); 1862 int ret = 0; 1863 1864 if (source_streams_mask != 1) 1865 return -EINVAL; 1866 1867 if (!priv->remote) 1868 return -ENODEV; 1869 1870 if (priv->stream_count == 1) 1871 rcsi2_stop(priv); 1872 1873 priv->stream_count -= 1; 1874 1875 return ret; 1876} 1877 1878static int rcsi2_set_pad_format(struct v4l2_subdev *sd, 1879 struct v4l2_subdev_state *state, 1880 struct v4l2_subdev_format *format) 1881{ 1882 struct rcar_csi2 *priv = sd_to_csi2(sd); 1883 unsigned int num_pads = rcsi2_num_pads(priv); 1884 1885 if (format->pad > RCAR_CSI2_SINK) 1886 return v4l2_subdev_get_fmt(sd, state, format); 1887 1888 if (!rcsi2_code_to_fmt(format->format.code)) 1889 format->format.code = rcar_csi2_formats[0].code; 1890 1891 *v4l2_subdev_state_get_format(state, format->pad) = format->format; 1892 1893 /* Propagate the format to the source pads. */ 1894 for (unsigned int i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 1895 *v4l2_subdev_state_get_format(state, i) = format->format; 1896 1897 return 0; 1898} 1899 1900static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = { 1901 .enable_streams = rcsi2_enable_streams, 1902 .disable_streams = rcsi2_disable_streams, 1903 1904 .set_fmt = rcsi2_set_pad_format, 1905 .get_fmt = v4l2_subdev_get_fmt, 1906}; 1907 1908static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = { 1909 .pad = &rcar_csi2_pad_ops, 1910}; 1911 1912static int rcsi2_init_state(struct v4l2_subdev *sd, 1913 struct v4l2_subdev_state *state) 1914{ 1915 struct rcar_csi2 *priv = sd_to_csi2(sd); 1916 unsigned int num_pads = rcsi2_num_pads(priv); 1917 1918 static const struct v4l2_mbus_framefmt rcar_csi2_default_fmt = { 1919 .width = 1920, 1920 .height = 1080, 1921 .code = MEDIA_BUS_FMT_RGB888_1X24, 1922 .colorspace = V4L2_COLORSPACE_SRGB, 1923 .field = V4L2_FIELD_NONE, 1924 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 1925 .quantization = V4L2_QUANTIZATION_DEFAULT, 1926 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 1927 }; 1928 1929 for (unsigned int i = RCAR_CSI2_SINK; i < num_pads; i++) 1930 *v4l2_subdev_state_get_format(state, i) = rcar_csi2_default_fmt; 1931 1932 return 0; 1933} 1934 1935static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = { 1936 .init_state = rcsi2_init_state, 1937}; 1938 1939static irqreturn_t rcsi2_irq(int irq, void *data) 1940{ 1941 struct rcar_csi2 *priv = data; 1942 u32 status, err_status; 1943 1944 status = rcsi2_read(priv, INTSTATE_REG); 1945 err_status = rcsi2_read(priv, INTERRSTATE_REG); 1946 1947 if (!status) 1948 return IRQ_HANDLED; 1949 1950 rcsi2_write(priv, INTSTATE_REG, status); 1951 1952 if (!err_status) 1953 return IRQ_HANDLED; 1954 1955 rcsi2_write(priv, INTERRSTATE_REG, err_status); 1956 1957 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n"); 1958 1959 return IRQ_WAKE_THREAD; 1960} 1961 1962static irqreturn_t rcsi2_irq_thread(int irq, void *data) 1963{ 1964 struct v4l2_subdev_state *state; 1965 struct rcar_csi2 *priv = data; 1966 1967 state = v4l2_subdev_lock_and_get_active_state(&priv->subdev); 1968 1969 rcsi2_stop(priv); 1970 usleep_range(1000, 2000); 1971 if (rcsi2_start(priv, state)) 1972 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n"); 1973 1974 v4l2_subdev_unlock_state(state); 1975 1976 return IRQ_HANDLED; 1977} 1978 1979/* ----------------------------------------------------------------------------- 1980 * Async handling and registration of subdevices and links. 1981 */ 1982 1983static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, 1984 struct v4l2_subdev *subdev, 1985 struct v4l2_async_connection *asc) 1986{ 1987 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1988 int pad; 1989 1990 pad = media_entity_get_fwnode_pad(&subdev->entity, asc->match.fwnode, 1991 MEDIA_PAD_FL_SOURCE); 1992 if (pad < 0) { 1993 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name); 1994 return pad; 1995 } 1996 1997 priv->remote = subdev; 1998 priv->remote_pad = pad; 1999 2000 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad); 2001 2002 return media_create_pad_link(&subdev->entity, pad, 2003 &priv->subdev.entity, 0, 2004 MEDIA_LNK_FL_ENABLED | 2005 MEDIA_LNK_FL_IMMUTABLE); 2006} 2007 2008static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, 2009 struct v4l2_subdev *subdev, 2010 struct v4l2_async_connection *asc) 2011{ 2012 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 2013 2014 priv->remote = NULL; 2015 2016 dev_dbg(priv->dev, "Unbind %s\n", subdev->name); 2017} 2018 2019static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = { 2020 .bound = rcsi2_notify_bound, 2021 .unbind = rcsi2_notify_unbind, 2022}; 2023 2024static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, 2025 struct v4l2_fwnode_endpoint *vep) 2026{ 2027 unsigned int i; 2028 2029 /* Only port 0 endpoint 0 is valid. */ 2030 if (vep->base.port || vep->base.id) 2031 return -ENOTCONN; 2032 2033 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; 2034 2035 switch (vep->bus_type) { 2036 case V4L2_MBUS_CSI2_DPHY: 2037 if (!priv->info->support_dphy) { 2038 dev_err(priv->dev, "D-PHY not supported\n"); 2039 return -EINVAL; 2040 } 2041 2042 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { 2043 dev_err(priv->dev, 2044 "Unsupported number of data-lanes for D-PHY: %u\n", 2045 priv->lanes); 2046 return -EINVAL; 2047 } 2048 2049 priv->cphy = false; 2050 break; 2051 case V4L2_MBUS_CSI2_CPHY: 2052 if (!priv->info->support_cphy) { 2053 dev_err(priv->dev, "C-PHY not supported\n"); 2054 return -EINVAL; 2055 } 2056 2057 if (priv->lanes != 3) { 2058 dev_err(priv->dev, 2059 "Unsupported number of data-lanes for C-PHY: %u\n", 2060 priv->lanes); 2061 return -EINVAL; 2062 } 2063 2064 priv->cphy = true; 2065 break; 2066 default: 2067 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); 2068 return -EINVAL; 2069 } 2070 2071 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { 2072 priv->lane_swap[i] = i < priv->lanes ? 2073 vep->bus.mipi_csi2.data_lanes[i] : i; 2074 2075 /* Check for valid lane number. */ 2076 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) { 2077 dev_err(priv->dev, "data-lanes must be in 1-4 range\n"); 2078 return -EINVAL; 2079 } 2080 } 2081 2082 for (i = 0; i < ARRAY_SIZE(priv->line_orders); i++) 2083 priv->line_orders[i] = vep->bus.mipi_csi2.line_orders[i]; 2084 2085 return 0; 2086} 2087 2088static int rcsi2_parse_dt(struct rcar_csi2 *priv) 2089{ 2090 struct v4l2_async_connection *asc; 2091 struct fwnode_handle *fwnode; 2092 struct fwnode_handle *ep; 2093 struct v4l2_fwnode_endpoint v4l2_ep = { 2094 .bus_type = V4L2_MBUS_UNKNOWN, 2095 }; 2096 int ret; 2097 2098 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0); 2099 if (!ep) { 2100 dev_err(priv->dev, "Not connected to subdevice\n"); 2101 return -EINVAL; 2102 } 2103 2104 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 2105 if (ret) { 2106 dev_err(priv->dev, "Could not parse v4l2 endpoint\n"); 2107 fwnode_handle_put(ep); 2108 return -EINVAL; 2109 } 2110 2111 ret = rcsi2_parse_v4l2(priv, &v4l2_ep); 2112 if (ret) { 2113 fwnode_handle_put(ep); 2114 return ret; 2115 } 2116 2117 fwnode = fwnode_graph_get_remote_endpoint(ep); 2118 fwnode_handle_put(ep); 2119 2120 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode)); 2121 2122 v4l2_async_subdev_nf_init(&priv->notifier, &priv->subdev); 2123 priv->notifier.ops = &rcar_csi2_notify_ops; 2124 2125 asc = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode, 2126 struct v4l2_async_connection); 2127 fwnode_handle_put(fwnode); 2128 if (IS_ERR(asc)) 2129 return PTR_ERR(asc); 2130 2131 ret = v4l2_async_nf_register(&priv->notifier); 2132 if (ret) 2133 v4l2_async_nf_cleanup(&priv->notifier); 2134 2135 return ret; 2136} 2137 2138/* ----------------------------------------------------------------------------- 2139 * PHTW initialization sequences. 2140 * 2141 * NOTE: Magic values are from the datasheet and lack documentation. 2142 */ 2143 2144static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, 2145 const struct rcsi2_mbps_info *values, u8 code) 2146{ 2147 const struct rcsi2_mbps_info *info; 2148 2149 info = rcsi2_mbps_to_info(priv, values, mbps); 2150 if (!info) 2151 return -ERANGE; 2152 2153 return rcsi2_phtw_write(priv, info->reg, code); 2154} 2155 2156static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, 2157 unsigned int mbps) 2158{ 2159 static const struct phtw_value step1[] = { 2160 { .data = 0xcc, .code = 0xe2 }, 2161 { .data = 0x01, .code = 0xe3 }, 2162 { .data = 0x11, .code = 0xe4 }, 2163 { .data = 0x01, .code = 0xe5 }, 2164 { .data = 0x10, .code = 0x04 }, 2165 }; 2166 2167 static const struct phtw_value step2[] = { 2168 { .data = 0x38, .code = 0x08 }, 2169 { .data = 0x01, .code = 0x00 }, 2170 { .data = 0x4b, .code = 0xac }, 2171 { .data = 0x03, .code = 0x00 }, 2172 { .data = 0x80, .code = 0x07 }, 2173 }; 2174 2175 int ret; 2176 2177 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 2178 if (ret) 2179 return ret; 2180 2181 if (mbps != 0 && mbps <= 250) { 2182 ret = rcsi2_phtw_write(priv, 0x39, 0x05); 2183 if (ret) 2184 return ret; 2185 2186 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n, 2187 0xf1); 2188 if (ret) 2189 return ret; 2190 } 2191 2192 return rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 2193} 2194 2195static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) 2196{ 2197 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps); 2198} 2199 2200static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) 2201{ 2202 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); 2203} 2204 2205static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) 2206{ 2207 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); 2208} 2209 2210static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) 2211{ 2212 static const struct phtw_value step1[] = { 2213 { .data = 0xee, .code = 0x34 }, 2214 { .data = 0xee, .code = 0x44 }, 2215 { .data = 0xee, .code = 0x54 }, 2216 { .data = 0xee, .code = 0x84 }, 2217 { .data = 0xee, .code = 0x94 }, 2218 }; 2219 2220 return rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 2221} 2222 2223static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, 2224 unsigned int mbps) 2225{ 2226 /* In case of 1500Mbps or less */ 2227 static const struct phtw_value step1[] = { 2228 { .data = 0xcc, .code = 0xe2 }, 2229 }; 2230 2231 static const struct phtw_value step2[] = { 2232 { .data = 0x01, .code = 0xe3 }, 2233 { .data = 0x11, .code = 0xe4 }, 2234 { .data = 0x01, .code = 0xe5 }, 2235 }; 2236 2237 /* In case of 1500Mbps or less */ 2238 static const struct phtw_value step3[] = { 2239 { .data = 0x38, .code = 0x08 }, 2240 }; 2241 2242 static const struct phtw_value step4[] = { 2243 { .data = 0x01, .code = 0x00 }, 2244 { .data = 0x4b, .code = 0xac }, 2245 { .data = 0x03, .code = 0x00 }, 2246 { .data = 0x80, .code = 0x07 }, 2247 }; 2248 2249 int ret; 2250 2251 if (mbps != 0 && mbps <= 1500) 2252 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 2253 else 2254 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); 2255 if (ret) 2256 return ret; 2257 2258 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 2259 if (ret) 2260 return ret; 2261 2262 if (mbps != 0 && mbps <= 1500) { 2263 ret = rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); 2264 if (ret) 2265 return ret; 2266 } 2267 2268 ret = rcsi2_phtw_write_array(priv, step4, ARRAY_SIZE(step4)); 2269 if (ret) 2270 return ret; 2271 2272 return ret; 2273} 2274 2275/* ----------------------------------------------------------------------------- 2276 * Platform Device Driver. 2277 */ 2278 2279static int rcsi2_link_setup(struct media_entity *entity, 2280 const struct media_pad *local, 2281 const struct media_pad *remote, u32 flags) 2282{ 2283 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 2284 struct rcar_csi2 *priv = sd_to_csi2(sd); 2285 struct video_device *vdev; 2286 int channel, vc; 2287 u32 id; 2288 2289 if (!is_media_entity_v4l2_video_device(remote->entity)) { 2290 dev_err(priv->dev, "Remote is not a video device\n"); 2291 return -EINVAL; 2292 } 2293 2294 vdev = media_entity_to_video_device(remote->entity); 2295 2296 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) { 2297 dev_err(priv->dev, "No renesas,id, can't configure routing\n"); 2298 return -EINVAL; 2299 } 2300 2301 channel = id % 4; 2302 2303 if (flags & MEDIA_LNK_FL_ENABLED) { 2304 if (media_pad_remote_pad_first(local)) { 2305 dev_dbg(priv->dev, 2306 "Each VC can only be routed to one output channel\n"); 2307 return -EINVAL; 2308 } 2309 2310 vc = local->index - 1; 2311 2312 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n", 2313 vc, id, channel); 2314 } else { 2315 vc = -1; 2316 } 2317 2318 priv->channel_vc[channel] = vc; 2319 2320 return 0; 2321} 2322 2323static const struct media_entity_operations rcar_csi2_entity_ops = { 2324 .link_setup = rcsi2_link_setup, 2325 .link_validate = v4l2_subdev_link_validate, 2326}; 2327 2328static int rcsi2_probe_resources(struct rcar_csi2 *priv, 2329 struct platform_device *pdev) 2330{ 2331 int irq, ret; 2332 2333 priv->base = devm_platform_ioremap_resource(pdev, 0); 2334 if (IS_ERR(priv->base)) 2335 return PTR_ERR(priv->base); 2336 2337 irq = platform_get_irq(pdev, 0); 2338 if (irq < 0) 2339 return irq; 2340 2341 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq, 2342 rcsi2_irq_thread, IRQF_SHARED, 2343 KBUILD_MODNAME, priv); 2344 if (ret) 2345 return ret; 2346 2347 priv->rstc = devm_reset_control_get(&pdev->dev, NULL); 2348 2349 return PTR_ERR_OR_ZERO(priv->rstc); 2350} 2351 2352static const struct rcsi2_register_layout rcsi2_registers_gen3 = { 2353 .phtw = PHTW_REG, 2354 .phypll = PHYPLL_REG, 2355}; 2356 2357static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { 2358 .regs = &rcsi2_registers_gen3, 2359 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2360 .start_receiver = rcsi2_start_receiver_gen3, 2361 .enter_standby = rcsi2_enter_standby_gen3, 2362 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2363 .csi0clkfreqrange = 0x20, 2364 .num_channels = 4, 2365 .clear_ulps = true, 2366 .support_dphy = true, 2367}; 2368 2369static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { 2370 .regs = &rcsi2_registers_gen3, 2371 .init_phtw = rcsi2_init_phtw_h3es2, 2372 .start_receiver = rcsi2_start_receiver_gen3, 2373 .enter_standby = rcsi2_enter_standby_gen3, 2374 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2375 .csi0clkfreqrange = 0x20, 2376 .num_channels = 4, 2377 .clear_ulps = true, 2378 .support_dphy = true, 2379}; 2380 2381static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { 2382 .regs = &rcsi2_registers_gen3, 2383 .start_receiver = rcsi2_start_receiver_gen3, 2384 .enter_standby = rcsi2_enter_standby_gen3, 2385 .hsfreqrange = hsfreqrange_m3w, 2386 .num_channels = 4, 2387 .support_dphy = true, 2388}; 2389 2390static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { 2391 .regs = &rcsi2_registers_gen3, 2392 .start_receiver = rcsi2_start_receiver_gen3, 2393 .enter_standby = rcsi2_enter_standby_gen3, 2394 .hsfreqrange = hsfreqrange_m3w, 2395 .num_channels = 4, 2396 .support_dphy = true, 2397}; 2398 2399static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { 2400 .regs = &rcsi2_registers_gen3, 2401 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2402 .start_receiver = rcsi2_start_receiver_gen3, 2403 .enter_standby = rcsi2_enter_standby_gen3, 2404 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2405 .csi0clkfreqrange = 0x20, 2406 .num_channels = 4, 2407 .clear_ulps = true, 2408 .support_dphy = true, 2409}; 2410 2411static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { 2412 .regs = &rcsi2_registers_gen3, 2413 .init_phtw = rcsi2_init_phtw_v3m_e3, 2414 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2415 .start_receiver = rcsi2_start_receiver_gen3, 2416 .enter_standby = rcsi2_enter_standby_gen3, 2417 .num_channels = 4, 2418 .support_dphy = true, 2419}; 2420 2421static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { 2422 .regs = &rcsi2_registers_gen3, 2423 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2424 .start_receiver = rcsi2_start_receiver_gen3, 2425 .enter_standby = rcsi2_enter_standby_gen3, 2426 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2427 .csi0clkfreqrange = 0x20, 2428 .clear_ulps = true, 2429 .support_dphy = true, 2430}; 2431 2432static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { 2433 .regs = &rcsi2_registers_gen3, 2434 .init_phtw = rcsi2_init_phtw_v3m_e3, 2435 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2436 .start_receiver = rcsi2_start_receiver_gen3, 2437 .enter_standby = rcsi2_enter_standby_gen3, 2438 .num_channels = 2, 2439 .support_dphy = true, 2440}; 2441 2442static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { 2443 .regs = &rcsi2_registers_gen3, 2444 .init_phtw = rcsi2_init_phtw_v3u, 2445 .start_receiver = rcsi2_start_receiver_gen3, 2446 .enter_standby = rcsi2_enter_standby_gen3, 2447 .hsfreqrange = hsfreqrange_v3u, 2448 .csi0clkfreqrange = 0x20, 2449 .clear_ulps = true, 2450 .use_isp = true, 2451 .support_dphy = true, 2452}; 2453 2454static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = { 2455 .regs = &rcsi2_registers_gen3, 2456 .start_receiver = rcsi2_start_receiver_v4h, 2457 .use_isp = true, 2458 .support_cphy = true, 2459 .support_dphy = true, 2460}; 2461 2462static const struct rcsi2_register_layout rcsi2_registers_v4m = { 2463 .phtw = V4M_PHTW_REG, 2464 .phypll = V4M_PHYPLL_REG, 2465}; 2466 2467static const struct rcar_csi2_info rcar_csi2_info_r8a779h0 = { 2468 .regs = &rcsi2_registers_v4m, 2469 .start_receiver = rcsi2_start_receiver_v4m, 2470 .hsfreqrange = hsfreqrange_v4m, 2471 .csi0clkfreqrange = 0x0c, 2472 .use_isp = true, 2473 .support_dphy = true, 2474}; 2475 2476static const struct of_device_id rcar_csi2_of_table[] = { 2477 { 2478 .compatible = "renesas,r8a774a1-csi2", 2479 .data = &rcar_csi2_info_r8a7796, 2480 }, 2481 { 2482 .compatible = "renesas,r8a774b1-csi2", 2483 .data = &rcar_csi2_info_r8a77965, 2484 }, 2485 { 2486 .compatible = "renesas,r8a774c0-csi2", 2487 .data = &rcar_csi2_info_r8a77990, 2488 }, 2489 { 2490 .compatible = "renesas,r8a774e1-csi2", 2491 .data = &rcar_csi2_info_r8a7795, 2492 }, 2493 { 2494 .compatible = "renesas,r8a7795-csi2", 2495 .data = &rcar_csi2_info_r8a7795, 2496 }, 2497 { 2498 .compatible = "renesas,r8a7796-csi2", 2499 .data = &rcar_csi2_info_r8a7796, 2500 }, 2501 { 2502 .compatible = "renesas,r8a77961-csi2", 2503 .data = &rcar_csi2_info_r8a77961, 2504 }, 2505 { 2506 .compatible = "renesas,r8a77965-csi2", 2507 .data = &rcar_csi2_info_r8a77965, 2508 }, 2509 { 2510 .compatible = "renesas,r8a77970-csi2", 2511 .data = &rcar_csi2_info_r8a77970, 2512 }, 2513 { 2514 .compatible = "renesas,r8a77980-csi2", 2515 .data = &rcar_csi2_info_r8a77980, 2516 }, 2517 { 2518 .compatible = "renesas,r8a77990-csi2", 2519 .data = &rcar_csi2_info_r8a77990, 2520 }, 2521 { 2522 .compatible = "renesas,r8a779a0-csi2", 2523 .data = &rcar_csi2_info_r8a779a0, 2524 }, 2525 { 2526 .compatible = "renesas,r8a779g0-csi2", 2527 .data = &rcar_csi2_info_r8a779g0, 2528 }, 2529 { 2530 .compatible = "renesas,r8a779h0-csi2", 2531 .data = &rcar_csi2_info_r8a779h0, 2532 }, 2533 { /* sentinel */ }, 2534}; 2535MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); 2536 2537static const struct soc_device_attribute r8a7795[] = { 2538 { 2539 .soc_id = "r8a7795", .revision = "ES2.*", 2540 .data = &rcar_csi2_info_r8a7795es2, 2541 }, 2542 { /* sentinel */ } 2543}; 2544 2545static int rcsi2_probe(struct platform_device *pdev) 2546{ 2547 const struct soc_device_attribute *attr; 2548 struct rcar_csi2 *priv; 2549 unsigned int i, num_pads; 2550 int ret; 2551 2552 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2553 if (!priv) 2554 return -ENOMEM; 2555 2556 priv->info = of_device_get_match_data(&pdev->dev); 2557 2558 /* 2559 * The different ES versions of r8a7795 (H3) behave differently but 2560 * share the same compatible string. 2561 */ 2562 attr = soc_device_match(r8a7795); 2563 if (attr) 2564 priv->info = attr->data; 2565 2566 priv->dev = &pdev->dev; 2567 2568 priv->stream_count = 0; 2569 2570 ret = rcsi2_probe_resources(priv, pdev); 2571 if (ret) { 2572 dev_err(priv->dev, "Failed to get resources\n"); 2573 return ret; 2574 } 2575 2576 platform_set_drvdata(pdev, priv); 2577 2578 ret = rcsi2_parse_dt(priv); 2579 if (ret) 2580 return ret; 2581 2582 priv->subdev.owner = THIS_MODULE; 2583 priv->subdev.dev = &pdev->dev; 2584 priv->subdev.internal_ops = &rcar_csi2_internal_ops; 2585 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops); 2586 v4l2_set_subdevdata(&priv->subdev, &pdev->dev); 2587 snprintf(priv->subdev.name, sizeof(priv->subdev.name), "%s %s", 2588 KBUILD_MODNAME, dev_name(&pdev->dev)); 2589 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 2590 2591 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 2592 priv->subdev.entity.ops = &rcar_csi2_entity_ops; 2593 2594 num_pads = rcsi2_num_pads(priv); 2595 2596 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 2597 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 2598 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE; 2599 2600 ret = media_entity_pads_init(&priv->subdev.entity, num_pads, 2601 priv->pads); 2602 if (ret) 2603 goto error_async; 2604 2605 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++) 2606 priv->channel_vc[i] = -1; 2607 2608 pm_runtime_enable(&pdev->dev); 2609 2610 ret = v4l2_subdev_init_finalize(&priv->subdev); 2611 if (ret) 2612 goto error_pm_runtime; 2613 2614 ret = v4l2_async_register_subdev(&priv->subdev); 2615 if (ret < 0) 2616 goto error_subdev; 2617 2618 dev_info(priv->dev, "%d lanes found\n", priv->lanes); 2619 2620 return 0; 2621 2622error_subdev: 2623 v4l2_subdev_cleanup(&priv->subdev); 2624error_pm_runtime: 2625 pm_runtime_disable(&pdev->dev); 2626error_async: 2627 v4l2_async_nf_unregister(&priv->notifier); 2628 v4l2_async_nf_cleanup(&priv->notifier); 2629 2630 return ret; 2631} 2632 2633static void rcsi2_remove(struct platform_device *pdev) 2634{ 2635 struct rcar_csi2 *priv = platform_get_drvdata(pdev); 2636 2637 v4l2_async_nf_unregister(&priv->notifier); 2638 v4l2_async_nf_cleanup(&priv->notifier); 2639 v4l2_async_unregister_subdev(&priv->subdev); 2640 v4l2_subdev_cleanup(&priv->subdev); 2641 2642 pm_runtime_disable(&pdev->dev); 2643} 2644 2645static struct platform_driver rcar_csi2_pdrv = { 2646 .remove = rcsi2_remove, 2647 .probe = rcsi2_probe, 2648 .driver = { 2649 .name = "rcar-csi2", 2650 .suppress_bind_attrs = true, 2651 .of_match_table = rcar_csi2_of_table, 2652 }, 2653}; 2654 2655module_platform_driver(rcar_csi2_pdrv); 2656 2657MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>"); 2658MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver"); 2659MODULE_LICENSE("GPL");
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