iris_state.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#ifndef __IRIS_STATE_H__
  7#define __IRIS_STATE_H__
  8
  9struct iris_inst;
 10
 11/**
 12 * enum iris_core_state
 13 *
 14 * @IRIS_CORE_DEINIT: default state.
 15 * @IRIS_CORE_INIT:   core state with core initialized. FW loaded and
 16 *                   HW brought out of reset, shared queues established
 17 *                   between host driver and firmware.
 18 * @IRIS_CORE_ERROR:  error state.
 19 *
 20 *        -----------
 21 *             |
 22 *             V
 23 *        -----------
 24 *   +--->| DEINIT  |<---+
 25 *   |   -----------    |
 26 *   |         |        |
 27 *   |         v        |
 28 *   |   -----------    |
 29 *   |     /     \      |
 30 *   |    /       \     |
 31 *   |   /         \    |
 32 *   |  v           v   v
 33 * -----------    -----------
 34 * |  INIT  |--->|  ERROR  |
 35 * -----------    -----------
 36 */
 37enum iris_core_state {
 38	IRIS_CORE_DEINIT,
 39	IRIS_CORE_INIT,
 40	IRIS_CORE_ERROR,
 41};
 42
 43/**
 44 * enum iris_inst_state
 45 *
 46 * @IRIS_INST_INIT: video instance is opened.
 47 * @IRIS_INST_INPUT_STREAMING: stream on is completed on output plane.
 48 * @IRIS_INST_OUTPUT_STREAMING: stream on is completed on capture plane.
 49 * @IRIS_INST_STREAMING: stream on is completed on both output and capture planes.
 50 * @IRIS_INST_DEINIT: video instance is closed.
 51 * @IRIS_INST_ERROR: error state.
 52 *                    |
 53 *                    V
 54 *             -------------
 55 *   +--------|     INIT    |----------+
 56 *   |         -------------           |
 57 *   |            ^   ^                |
 58 *   |           /      \              |
 59 *   |          /        \             |
 60 *   |         v          v            |
 61 *   |   -----------    -----------    |
 62 *   |   |   INPUT         OUTPUT  |   |
 63 *   |---| STREAMING     STREAMING |---|
 64 *   |   -----------    -----------    |
 65 *   |       ^            ^            |
 66 *   |         \          /            |
 67 *   |          \        /             |
 68 *   |           v      v              |
 69 *   |         -------------           |
 70 *   |--------|  STREAMING |-----------|
 71 *   |        -------------            |
 72 *   |               |                 |
 73 *   |               |                 |
 74 *   |               v                 |
 75 *   |          -----------            |
 76 *   +-------->|  DEINIT   |<----------+
 77 *   |          -----------            |
 78 *   |               |                 |
 79 *   |               |                 |
 80 *   |               v                 |
 81 *   |          ----------             |
 82 *   +-------->|   ERROR |<------------+
 83 *              ----------
 84 */
 85enum iris_inst_state {
 86	IRIS_INST_DEINIT,
 87	IRIS_INST_INIT,
 88	IRIS_INST_INPUT_STREAMING,
 89	IRIS_INST_OUTPUT_STREAMING,
 90	IRIS_INST_STREAMING,
 91	IRIS_INST_ERROR,
 92};
 93
 94#define IRIS_INST_SUB_STATES		8
 95#define IRIS_INST_MAX_SUB_STATE_VALUE	((1 << IRIS_INST_SUB_STATES) - 1)
 96
 97/**
 98 * enum iris_inst_sub_state
 99 *
100 * @IRIS_INST_SUB_FIRST_IPSC: indicates source change is received from firmware
101 *			     when output port is not yet streaming.
102 * @IRIS_INST_SUB_DRC: indicates source change is received from firmware
103 *		      when output port is streaming and source change event is
104 *		      sent to client.
105 * @IRIS_INST_SUB_DRC_LAST: indicates last buffer is received from firmware
106 *                         as part of source change.
107 * @IRIS_INST_SUB_DRAIN: indicates drain is in progress.
108 * @IRIS_INST_SUB_DRAIN_LAST: indicates last buffer is received from firmware
109 *                           as part of drain sequence.
110 * @IRIS_INST_SUB_INPUT_PAUSE: source change is received form firmware. This
111 *                            indicates that firmware is paused to process
112 *                            any further input frames.
113 * @IRIS_INST_SUB_OUTPUT_PAUSE: last buffer is received form firmware as part
114 *                             of drc sequence. This indicates that
115 *                             firmware is paused to process any further output frames.
116 * @IRIS_INST_SUB_LOAD_RESOURCES: indicates all the resources have been loaded by the
117 *                               firmware and it is ready for processing.
118 */
119enum iris_inst_sub_state {
120	IRIS_INST_SUB_FIRST_IPSC	= BIT(0),
121	IRIS_INST_SUB_DRC		= BIT(1),
122	IRIS_INST_SUB_DRC_LAST		= BIT(2),
123	IRIS_INST_SUB_DRAIN		= BIT(3),
124	IRIS_INST_SUB_DRAIN_LAST	= BIT(4),
125	IRIS_INST_SUB_INPUT_PAUSE	= BIT(5),
126	IRIS_INST_SUB_OUTPUT_PAUSE	= BIT(6),
127	IRIS_INST_SUB_LOAD_RESOURCES	= BIT(7),
128};
129
130int iris_inst_change_state(struct iris_inst *inst,
131			   enum iris_inst_state request_state);
132int iris_inst_change_sub_state(struct iris_inst *inst,
133			       enum iris_inst_sub_state clear_sub_state,
134			       enum iris_inst_sub_state set_sub_state);
135
136int iris_inst_state_change_streamon(struct iris_inst *inst, u32 plane);
137int iris_inst_state_change_streamoff(struct iris_inst *inst, u32 plane);
138int iris_inst_sub_state_change_drc(struct iris_inst *inst);
139int iris_inst_sub_state_change_drain_last(struct iris_inst *inst);
140int iris_inst_sub_state_change_drc_last(struct iris_inst *inst);
141int iris_inst_sub_state_change_pause(struct iris_inst *inst, u32 plane);
142bool iris_allow_cmd(struct iris_inst *inst, u32 cmd);
143bool iris_drc_pending(struct iris_inst *inst);
144bool iris_drain_pending(struct iris_inst *inst);
145
146#endif