iris_platform_gen2.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
   4 * Copyright (c) 2025 Linaro Ltd
   5 */
   6
   7#include "iris_core.h"
   8#include "iris_ctrls.h"
   9#include "iris_hfi_gen2.h"
  10#include "iris_hfi_gen2_defines.h"
  11#include "iris_platform_common.h"
  12#include "iris_vpu_buffer.h"
  13#include "iris_vpu_common.h"
  14
  15#include "iris_platform_qcs8300.h"
  16#include "iris_platform_sm8650.h"
  17#include "iris_platform_sm8750.h"
  18
  19#define VIDEO_ARCH_LX 1
  20#define BITRATE_MAX				245000000
  21
  22static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
  23	{
  24		.cap_id = PROFILE_H264,
  25		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
  26		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
  27		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
  28				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
  29				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
  30				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
  31				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
  32		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
  33		.hfi_id = HFI_PROP_PROFILE,
  34		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
  35		.set = iris_set_u32_enum,
  36	},
  37	{
  38		.cap_id = PROFILE_HEVC,
  39		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
  40		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
  41		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
  42				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
  43		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
  44		.hfi_id = HFI_PROP_PROFILE,
  45		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
  46		.set = iris_set_u32_enum,
  47	},
  48	{
  49		.cap_id = PROFILE_VP9,
  50		.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
  51		.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
  52		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
  53				BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
  54		.value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
  55		.hfi_id = HFI_PROP_PROFILE,
  56		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
  57		.set = iris_set_u32_enum,
  58	},
  59	{
  60		.cap_id = LEVEL_H264,
  61		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
  62		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
  63		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
  64				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
  65				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
  66				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
  67				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
  68				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
  69				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
  70				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
  71				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
  72				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
  73				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
  74				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
  75				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
  76				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
  77				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
  78				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
  79				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
  80				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) |
  81				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) |
  82				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2),
  83		.value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
  84		.hfi_id = HFI_PROP_LEVEL,
  85		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
  86		.set = iris_set_u32_enum,
  87	},
  88	{
  89		.cap_id = LEVEL_HEVC,
  90		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
  91		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
  92		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
  93				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
  94				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
  95				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
  96				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
  97				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
  98				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
  99				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
 100				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
 101				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
 102				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
 103				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
 104				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
 105		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1,
 106		.hfi_id = HFI_PROP_LEVEL,
 107		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 108		.set = iris_set_u32_enum,
 109	},
 110	{
 111		.cap_id = LEVEL_VP9,
 112		.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
 113		.max = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
 114		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
 115				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
 116				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
 117				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
 118				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
 119				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
 120				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
 121				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
 122				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
 123				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
 124				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) |
 125				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0),
 126		.value = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
 127		.hfi_id = HFI_PROP_LEVEL,
 128		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 129		.set = iris_set_u32_enum,
 130	},
 131	{
 132		.cap_id = TIER,
 133		.min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
 134		.max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
 135		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
 136				BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
 137		.value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
 138		.hfi_id = HFI_PROP_TIER,
 139		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 140		.set = iris_set_u32_enum,
 141	},
 142	{
 143		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
 144		.min = DEFAULT_MAX_HOST_BUF_COUNT,
 145		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
 146		.step_or_mask = 1,
 147		.value = DEFAULT_MAX_HOST_BUF_COUNT,
 148		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
 149		.flags = CAP_FLAG_INPUT_PORT,
 150		.set = iris_set_u32,
 151	},
 152	{
 153		.cap_id = STAGE,
 154		.min = STAGE_1,
 155		.max = STAGE_2,
 156		.step_or_mask = 1,
 157		.value = STAGE_2,
 158		.hfi_id = HFI_PROP_STAGE,
 159		.set = iris_set_stage,
 160	},
 161	{
 162		.cap_id = PIPE,
 163		/* .max, .min and .value are set via platform data */
 164		.step_or_mask = 1,
 165		.hfi_id = HFI_PROP_PIPE,
 166		.set = iris_set_pipe,
 167	},
 168	{
 169		.cap_id = POC,
 170		.min = 0,
 171		.max = 2,
 172		.step_or_mask = 1,
 173		.value = 1,
 174		.hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
 175	},
 176	{
 177		.cap_id = CODED_FRAMES,
 178		.min = CODED_FRAMES_PROGRESSIVE,
 179		.max = CODED_FRAMES_PROGRESSIVE,
 180		.step_or_mask = 0,
 181		.value = CODED_FRAMES_PROGRESSIVE,
 182		.hfi_id = HFI_PROP_CODED_FRAMES,
 183	},
 184	{
 185		.cap_id = BIT_DEPTH,
 186		.min = BIT_DEPTH_8,
 187		.max = BIT_DEPTH_8,
 188		.step_or_mask = 1,
 189		.value = BIT_DEPTH_8,
 190		.hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
 191	},
 192	{
 193		.cap_id = RAP_FRAME,
 194		.min = 0,
 195		.max = 1,
 196		.step_or_mask = 1,
 197		.value = 1,
 198		.hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
 199		.flags = CAP_FLAG_INPUT_PORT,
 200		.set = iris_set_u32,
 201	},
 202};
 203
 204static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
 205	{
 206		.cap_id = PROFILE_H264,
 207		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
 208		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
 209		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
 210				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
 211				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
 212				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
 213				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
 214		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
 215		.hfi_id = HFI_PROP_PROFILE,
 216		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 217		.set = iris_set_profile,
 218	},
 219	{
 220		.cap_id = PROFILE_HEVC,
 221		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
 222		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
 223		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
 224				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
 225				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
 226		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
 227		.hfi_id = HFI_PROP_PROFILE,
 228		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 229		.set = iris_set_profile,
 230	},
 231	{
 232		.cap_id = LEVEL_H264,
 233		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
 234		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
 235		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
 236				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
 237				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
 238				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
 239				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
 240				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
 241				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
 242				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
 243				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
 244				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
 245				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
 246				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
 247				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
 248				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
 249				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
 250				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
 251				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
 252				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
 253		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
 254		.hfi_id = HFI_PROP_LEVEL,
 255		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 256		.set = iris_set_level,
 257	},
 258	{
 259		.cap_id = LEVEL_HEVC,
 260		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
 261		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
 262		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
 263				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
 264				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
 265				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
 266				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
 267				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
 268				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
 269				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
 270				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
 271				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
 272				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
 273				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
 274				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
 275		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
 276		.hfi_id = HFI_PROP_LEVEL,
 277		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 278		.set = iris_set_level,
 279	},
 280	{
 281		.cap_id = STAGE,
 282		.min = STAGE_1,
 283		.max = STAGE_2,
 284		.step_or_mask = 1,
 285		.value = STAGE_2,
 286		.hfi_id = HFI_PROP_STAGE,
 287		.set = iris_set_stage,
 288	},
 289	{
 290		.cap_id = HEADER_MODE,
 291		.min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
 292		.max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
 293		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
 294				BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
 295		.value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
 296		.hfi_id = HFI_PROP_SEQ_HEADER_MODE,
 297		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 298		.set = iris_set_header_mode_gen2,
 299	},
 300	{
 301		.cap_id = PREPEND_SPSPPS_TO_IDR,
 302		.min = 0,
 303		.max = 1,
 304		.step_or_mask = 1,
 305		.value = 0,
 306	},
 307	{
 308		.cap_id = BITRATE,
 309		.min = 1,
 310		.max = BITRATE_MAX,
 311		.step_or_mask = 1,
 312		.value = BITRATE_DEFAULT,
 313		.hfi_id = HFI_PROP_TOTAL_BITRATE,
 314		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 315			CAP_FLAG_DYNAMIC_ALLOWED,
 316		.set = iris_set_bitrate,
 317	},
 318	{
 319		.cap_id = BITRATE_PEAK,
 320		.min = 1,
 321		.max = BITRATE_MAX,
 322		.step_or_mask = 1,
 323		.value = BITRATE_DEFAULT,
 324		.hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
 325		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 326			CAP_FLAG_DYNAMIC_ALLOWED,
 327		.set = iris_set_peak_bitrate,
 328	},
 329	{
 330		.cap_id = BITRATE_MODE,
 331		.min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
 332		.max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
 333		.step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
 334				BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
 335		.value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
 336		.hfi_id = HFI_PROP_RATE_CONTROL,
 337		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 338		.set = iris_set_bitrate_mode_gen2,
 339	},
 340	{
 341		.cap_id = FRAME_SKIP_MODE,
 342		.min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
 343		.max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
 344		.step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
 345				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
 346				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
 347		.value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
 348		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 349	},
 350	{
 351		.cap_id = FRAME_RC_ENABLE,
 352		.min = 0,
 353		.max = 1,
 354		.step_or_mask = 1,
 355		.value = 1,
 356	},
 357	{
 358		.cap_id = GOP_SIZE,
 359		.min = 0,
 360		.max = INT_MAX,
 361		.step_or_mask = 1,
 362		.value = 2 * DEFAULT_FPS - 1,
 363		.hfi_id = HFI_PROP_MAX_GOP_FRAMES,
 364		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 365			CAP_FLAG_DYNAMIC_ALLOWED,
 366		.set = iris_set_u32,
 367	},
 368	{
 369		.cap_id = ENTROPY_MODE,
 370		.min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
 371		.max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
 372		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
 373				BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
 374		.value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
 375		.hfi_id = HFI_PROP_CABAC_SESSION,
 376		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 377		.set = iris_set_entropy_mode_gen2,
 378	},
 379	{
 380		.cap_id = MIN_FRAME_QP_H264,
 381		.min = MIN_QP_8BIT,
 382		.max = MAX_QP,
 383		.step_or_mask = 1,
 384		.value = MIN_QP_8BIT,
 385		.hfi_id = HFI_PROP_MIN_QP_PACKED,
 386		.flags = CAP_FLAG_OUTPUT_PORT,
 387		.set = iris_set_min_qp,
 388	},
 389	{
 390		.cap_id = MIN_FRAME_QP_HEVC,
 391		.min = MIN_QP_8BIT,
 392		.max = MAX_QP,
 393		.step_or_mask = 1,
 394		.value = MIN_QP_8BIT,
 395		.hfi_id = HFI_PROP_MIN_QP_PACKED,
 396		.flags = CAP_FLAG_OUTPUT_PORT,
 397		.set = iris_set_min_qp,
 398	},
 399	{
 400		.cap_id = MAX_FRAME_QP_H264,
 401		.min = MIN_QP_8BIT,
 402		.max = MAX_QP,
 403		.step_or_mask = 1,
 404		.value = MAX_QP,
 405		.hfi_id = HFI_PROP_MAX_QP_PACKED,
 406		.flags = CAP_FLAG_OUTPUT_PORT,
 407		.set = iris_set_max_qp,
 408	},
 409	{
 410		.cap_id = MAX_FRAME_QP_HEVC,
 411		.min = MIN_QP_8BIT,
 412		.max = MAX_QP,
 413		.step_or_mask = 1,
 414		.value = MAX_QP,
 415		.hfi_id = HFI_PROP_MAX_QP_PACKED,
 416		.flags = CAP_FLAG_OUTPUT_PORT,
 417		.set = iris_set_max_qp,
 418	},
 419	{
 420		.cap_id = I_FRAME_MIN_QP_H264,
 421		.min = MIN_QP_8BIT,
 422		.max = MAX_QP,
 423		.step_or_mask = 1,
 424		.value = MIN_QP_8BIT,
 425	},
 426	{
 427		.cap_id = I_FRAME_MIN_QP_HEVC,
 428		.min = MIN_QP_8BIT,
 429		.max = MAX_QP,
 430		.step_or_mask = 1,
 431		.value = MIN_QP_8BIT,
 432	},
 433	{
 434		.cap_id = P_FRAME_MIN_QP_H264,
 435		.min = MIN_QP_8BIT,
 436		.max = MAX_QP,
 437		.step_or_mask = 1,
 438		.value = MIN_QP_8BIT,
 439	},
 440	{
 441		.cap_id = P_FRAME_MIN_QP_HEVC,
 442		.min = MIN_QP_8BIT,
 443		.max = MAX_QP,
 444		.step_or_mask = 1,
 445		.value = MIN_QP_8BIT,
 446	},
 447	{
 448		.cap_id = B_FRAME_MIN_QP_H264,
 449		.min = MIN_QP_8BIT,
 450		.max = MAX_QP,
 451		.step_or_mask = 1,
 452		.value = MIN_QP_8BIT,
 453	},
 454	{
 455		.cap_id = B_FRAME_MIN_QP_HEVC,
 456		.min = MIN_QP_8BIT,
 457		.max = MAX_QP,
 458		.step_or_mask = 1,
 459		.value = MIN_QP_8BIT,
 460	},
 461	{
 462		.cap_id = I_FRAME_MAX_QP_H264,
 463		.min = MIN_QP_8BIT,
 464		.max = MAX_QP,
 465		.step_or_mask = 1,
 466		.value = MAX_QP,
 467	},
 468	{
 469		.cap_id = I_FRAME_MAX_QP_HEVC,
 470		.min = MIN_QP_8BIT,
 471		.max = MAX_QP,
 472		.step_or_mask = 1,
 473		.value = MAX_QP,
 474	},
 475	{
 476		.cap_id = P_FRAME_MAX_QP_H264,
 477		.min = MIN_QP_8BIT,
 478		.max = MAX_QP,
 479		.step_or_mask = 1,
 480		.value = MAX_QP,
 481	},
 482	{
 483		.cap_id = P_FRAME_MAX_QP_HEVC,
 484		.min = MIN_QP_8BIT,
 485		.max = MAX_QP,
 486		.step_or_mask = 1,
 487		.value = MAX_QP,
 488	},
 489	{
 490		.cap_id = B_FRAME_MAX_QP_H264,
 491		.min = MIN_QP_8BIT,
 492		.max = MAX_QP,
 493		.step_or_mask = 1,
 494		.value = MAX_QP,
 495	},
 496	{
 497		.cap_id = B_FRAME_MAX_QP_HEVC,
 498		.min = MIN_QP_8BIT,
 499		.max = MAX_QP,
 500		.step_or_mask = 1,
 501		.value = MAX_QP,
 502	},
 503	{
 504		.cap_id = I_FRAME_QP_H264,
 505		.min = MIN_QP_8BIT,
 506		.max = MAX_QP,
 507		.step_or_mask = 1,
 508		.value = DEFAULT_QP,
 509		.hfi_id = HFI_PROP_QP_PACKED,
 510		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 511			CAP_FLAG_DYNAMIC_ALLOWED,
 512		.set = iris_set_frame_qp,
 513	},
 514	{
 515		.cap_id = I_FRAME_QP_HEVC,
 516		.min = MIN_QP_8BIT,
 517		.max = MAX_QP,
 518		.step_or_mask = 1,
 519		.value = DEFAULT_QP,
 520		.hfi_id = HFI_PROP_QP_PACKED,
 521		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 522			CAP_FLAG_DYNAMIC_ALLOWED,
 523		.set = iris_set_frame_qp,
 524	},
 525	{
 526		.cap_id = P_FRAME_QP_H264,
 527		.min = MIN_QP_8BIT,
 528		.max = MAX_QP,
 529		.step_or_mask = 1,
 530		.value = DEFAULT_QP,
 531		.hfi_id = HFI_PROP_QP_PACKED,
 532		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 533			CAP_FLAG_DYNAMIC_ALLOWED,
 534		.set = iris_set_frame_qp,
 535	},
 536	{
 537		.cap_id = P_FRAME_QP_HEVC,
 538		.min = MIN_QP_8BIT,
 539		.max = MAX_QP,
 540		.step_or_mask = 1,
 541		.value = DEFAULT_QP,
 542		.hfi_id = HFI_PROP_QP_PACKED,
 543		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 544			CAP_FLAG_DYNAMIC_ALLOWED,
 545		.set = iris_set_frame_qp,
 546	},
 547	{
 548		.cap_id = B_FRAME_QP_H264,
 549		.min = MIN_QP_8BIT,
 550		.max = MAX_QP,
 551		.step_or_mask = 1,
 552		.value = DEFAULT_QP,
 553		.hfi_id = HFI_PROP_QP_PACKED,
 554		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 555			CAP_FLAG_DYNAMIC_ALLOWED,
 556		.set = iris_set_frame_qp,
 557	},
 558	{
 559		.cap_id = B_FRAME_QP_HEVC,
 560		.min = MIN_QP_8BIT,
 561		.max = MAX_QP,
 562		.step_or_mask = 1,
 563		.value = DEFAULT_QP,
 564		.hfi_id = HFI_PROP_QP_PACKED,
 565		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
 566			CAP_FLAG_DYNAMIC_ALLOWED,
 567		.set = iris_set_frame_qp,
 568	},
 569	{
 570		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
 571		.min = DEFAULT_MAX_HOST_BUF_COUNT,
 572		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
 573		.step_or_mask = 1,
 574		.value = DEFAULT_MAX_HOST_BUF_COUNT,
 575		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
 576		.flags = CAP_FLAG_INPUT_PORT,
 577		.set = iris_set_u32,
 578	},
 579	{
 580		.cap_id = OUTPUT_BUF_HOST_MAX_COUNT,
 581		.min = DEFAULT_MAX_HOST_BUF_COUNT,
 582		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
 583		.step_or_mask = 1,
 584		.value = DEFAULT_MAX_HOST_BUF_COUNT,
 585		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
 586		.flags = CAP_FLAG_OUTPUT_PORT,
 587		.set = iris_set_u32,
 588	},
 589};
 590
 591static struct platform_inst_caps platform_inst_cap_sm8550 = {
 592	.min_frame_width = 96,
 593	.max_frame_width = 8192,
 594	.min_frame_height = 96,
 595	.max_frame_height = 8192,
 596	.max_mbpf = (8192 * 4352) / 256,
 597	.mb_cycles_vpp = 200,
 598	.mb_cycles_fw = 489583,
 599	.mb_cycles_fw_vpp = 66234,
 600	.num_comv = 0,
 601	.max_frame_rate = MAXIMUM_FPS,
 602	.max_operating_rate = MAXIMUM_FPS,
 603};
 604
 605static void iris_set_sm8550_preset_registers(struct iris_core *core)
 606{
 607	writel(0x0, core->reg_base + 0xB0088);
 608}
 609
 610static const struct icc_info sm8550_icc_table[] = {
 611	{ "cpu-cfg",    1000, 1000     },
 612	{ "video-mem",  1000, 15000000 },
 613};
 614
 615static const char * const sm8550_clk_reset_table[] = { "bus" };
 616
 617static const struct bw_info sm8550_bw_table_dec[] = {
 618	{ ((4096 * 2160) / 256) * 60, 1608000 },
 619	{ ((4096 * 2160) / 256) * 30,  826000 },
 620	{ ((1920 * 1080) / 256) * 60,  567000 },
 621	{ ((1920 * 1080) / 256) * 30,  294000 },
 622};
 623
 624static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
 625
 626static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
 627
 628static const struct platform_clk_data sm8550_clk_table[] = {
 629	{IRIS_AXI_CLK,  "iface"        },
 630	{IRIS_CTRL_CLK, "core"         },
 631	{IRIS_HW_CLK,   "vcodec0_core" },
 632};
 633
 634static struct ubwc_config_data ubwc_config_sm8550 = {
 635	.max_channels = 8,
 636	.mal_length = 32,
 637	.highest_bank_bit = 16,
 638	.bank_swzl_level = 0,
 639	.bank_swz2_level = 1,
 640	.bank_swz3_level = 1,
 641	.bank_spreading = 1,
 642};
 643
 644static struct tz_cp_config tz_cp_config_sm8550 = {
 645	.cp_start = 0,
 646	.cp_size = 0x25800000,
 647	.cp_nonpixel_start = 0x01000000,
 648	.cp_nonpixel_size = 0x24800000,
 649};
 650
 651static const u32 sm8550_vdec_input_config_params_default[] = {
 652	HFI_PROP_BITSTREAM_RESOLUTION,
 653	HFI_PROP_CROP_OFFSETS,
 654	HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
 655	HFI_PROP_CODED_FRAMES,
 656	HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT,
 657	HFI_PROP_PIC_ORDER_CNT_TYPE,
 658	HFI_PROP_PROFILE,
 659	HFI_PROP_LEVEL,
 660	HFI_PROP_SIGNAL_COLOR_INFO,
 661};
 662
 663static const u32 sm8550_vdec_input_config_param_hevc[] = {
 664	HFI_PROP_BITSTREAM_RESOLUTION,
 665	HFI_PROP_CROP_OFFSETS,
 666	HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
 667	HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT,
 668	HFI_PROP_PROFILE,
 669	HFI_PROP_LEVEL,
 670	HFI_PROP_TIER,
 671	HFI_PROP_SIGNAL_COLOR_INFO,
 672};
 673
 674static const u32 sm8550_vdec_input_config_param_vp9[] = {
 675	HFI_PROP_BITSTREAM_RESOLUTION,
 676	HFI_PROP_CROP_OFFSETS,
 677	HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
 678	HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT,
 679	HFI_PROP_PROFILE,
 680	HFI_PROP_LEVEL,
 681};
 682
 683static const u32 sm8550_venc_input_config_params[] = {
 684	HFI_PROP_COLOR_FORMAT,
 685	HFI_PROP_RAW_RESOLUTION,
 686	HFI_PROP_CROP_OFFSETS,
 687	HFI_PROP_LINEAR_STRIDE_SCANLINE,
 688	HFI_PROP_SIGNAL_COLOR_INFO,
 689};
 690
 691static const u32 sm8550_vdec_output_config_params[] = {
 692	HFI_PROP_OPB_ENABLE,
 693	HFI_PROP_COLOR_FORMAT,
 694	HFI_PROP_LINEAR_STRIDE_SCANLINE,
 695};
 696
 697static const u32 sm8550_venc_output_config_params[] = {
 698	HFI_PROP_BITSTREAM_RESOLUTION,
 699	HFI_PROP_CROP_OFFSETS,
 700	HFI_PROP_FRAME_RATE,
 701};
 702
 703static const u32 sm8550_vdec_subscribe_input_properties[] = {
 704	HFI_PROP_NO_OUTPUT,
 705};
 706
 707static const u32 sm8550_vdec_subscribe_output_properties_avc[] = {
 708	HFI_PROP_PICTURE_TYPE,
 709	HFI_PROP_CABAC_SESSION,
 710};
 711
 712static const u32 sm8550_vdec_subscribe_output_properties_hevc[] = {
 713	HFI_PROP_PICTURE_TYPE,
 714};
 715
 716static const u32 sm8550_vdec_subscribe_output_properties_vp9[] = {
 717	HFI_PROP_PICTURE_TYPE,
 718};
 719
 720static const u32 sm8550_dec_ip_int_buf_tbl[] = {
 721	BUF_BIN,
 722	BUF_COMV,
 723	BUF_NON_COMV,
 724	BUF_LINE,
 725};
 726
 727static const u32 sm8550_dec_op_int_buf_tbl[] = {
 728	BUF_DPB,
 729};
 730
 731static const u32 sm8550_enc_op_int_buf_tbl[] = {
 732	BUF_BIN,
 733	BUF_COMV,
 734	BUF_NON_COMV,
 735	BUF_LINE,
 736	BUF_SCRATCH_2,
 737};
 738
 739const struct iris_platform_data sm8550_data = {
 740	.get_instance = iris_hfi_gen2_get_instance,
 741	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
 742	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
 743	.get_vpu_buffer_size = iris_vpu_buf_size,
 744	.vpu_ops = &iris_vpu3_ops,
 745	.set_preset_registers = iris_set_sm8550_preset_registers,
 746	.icc_tbl = sm8550_icc_table,
 747	.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
 748	.clk_rst_tbl = sm8550_clk_reset_table,
 749	.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
 750	.bw_tbl_dec = sm8550_bw_table_dec,
 751	.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
 752	.pmdomain_tbl = sm8550_pmdomain_table,
 753	.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
 754	.opp_pd_tbl = sm8550_opp_pd_table,
 755	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
 756	.clk_tbl = sm8550_clk_table,
 757	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
 758	/* Upper bound of DMA address range */
 759	.dma_mask = 0xe0000000 - 1,
 760	.fwname = "qcom/vpu/vpu30_p4.mbn",
 761	.pas_id = IRIS_PAS_ID,
 762	.inst_caps = &platform_inst_cap_sm8550,
 763	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
 764	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
 765	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
 766	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
 767	.tz_cp_config_data = &tz_cp_config_sm8550,
 768	.core_arch = VIDEO_ARCH_LX,
 769	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
 770	.ubwc_config = &ubwc_config_sm8550,
 771	.num_vpp_pipe = 4,
 772	.max_session_count = 16,
 773	.max_core_mbpf = NUM_MBS_8K * 2,
 774	.max_core_mbps = ((7680 * 4320) / 256) * 60,
 775	.dec_input_config_params_default =
 776		sm8550_vdec_input_config_params_default,
 777	.dec_input_config_params_default_size =
 778		ARRAY_SIZE(sm8550_vdec_input_config_params_default),
 779	.dec_input_config_params_hevc =
 780		sm8550_vdec_input_config_param_hevc,
 781	.dec_input_config_params_hevc_size =
 782		ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
 783	.dec_input_config_params_vp9 =
 784		sm8550_vdec_input_config_param_vp9,
 785	.dec_input_config_params_vp9_size =
 786		ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
 787	.dec_output_config_params =
 788		sm8550_vdec_output_config_params,
 789	.dec_output_config_params_size =
 790		ARRAY_SIZE(sm8550_vdec_output_config_params),
 791
 792	.enc_input_config_params =
 793		sm8550_venc_input_config_params,
 794	.enc_input_config_params_size =
 795		ARRAY_SIZE(sm8550_venc_input_config_params),
 796	.enc_output_config_params =
 797		sm8550_venc_output_config_params,
 798	.enc_output_config_params_size =
 799		ARRAY_SIZE(sm8550_venc_output_config_params),
 800
 801	.dec_input_prop = sm8550_vdec_subscribe_input_properties,
 802	.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
 803	.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
 804	.dec_output_prop_avc_size =
 805		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
 806	.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
 807	.dec_output_prop_hevc_size =
 808		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
 809	.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
 810	.dec_output_prop_vp9_size =
 811		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
 812
 813	.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
 814	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
 815	.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
 816	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
 817
 818	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
 819	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
 820};
 821
 822/*
 823 * Shares most of SM8550 data except:
 824 * - vpu_ops to iris_vpu33_ops
 825 * - clk_rst_tbl to sm8650_clk_reset_table
 826 * - controller_rst_tbl to sm8650_controller_reset_table
 827 * - fwname to "qcom/vpu/vpu33_p4.mbn"
 828 */
 829const struct iris_platform_data sm8650_data = {
 830	.get_instance = iris_hfi_gen2_get_instance,
 831	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
 832	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
 833	.get_vpu_buffer_size = iris_vpu33_buf_size,
 834	.vpu_ops = &iris_vpu33_ops,
 835	.set_preset_registers = iris_set_sm8550_preset_registers,
 836	.icc_tbl = sm8550_icc_table,
 837	.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
 838	.clk_rst_tbl = sm8650_clk_reset_table,
 839	.clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
 840	.controller_rst_tbl = sm8650_controller_reset_table,
 841	.controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),
 842	.bw_tbl_dec = sm8550_bw_table_dec,
 843	.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
 844	.pmdomain_tbl = sm8550_pmdomain_table,
 845	.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
 846	.opp_pd_tbl = sm8550_opp_pd_table,
 847	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
 848	.clk_tbl = sm8550_clk_table,
 849	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
 850	/* Upper bound of DMA address range */
 851	.dma_mask = 0xe0000000 - 1,
 852	.fwname = "qcom/vpu/vpu33_p4.mbn",
 853	.pas_id = IRIS_PAS_ID,
 854	.inst_caps = &platform_inst_cap_sm8550,
 855	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
 856	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
 857	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
 858	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
 859	.tz_cp_config_data = &tz_cp_config_sm8550,
 860	.core_arch = VIDEO_ARCH_LX,
 861	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
 862	.ubwc_config = &ubwc_config_sm8550,
 863	.num_vpp_pipe = 4,
 864	.max_session_count = 16,
 865	.max_core_mbpf = NUM_MBS_8K * 2,
 866	.max_core_mbps = ((7680 * 4320) / 256) * 60,
 867	.dec_input_config_params_default =
 868		sm8550_vdec_input_config_params_default,
 869	.dec_input_config_params_default_size =
 870		ARRAY_SIZE(sm8550_vdec_input_config_params_default),
 871	.dec_input_config_params_hevc =
 872		sm8550_vdec_input_config_param_hevc,
 873	.dec_input_config_params_hevc_size =
 874		ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
 875	.dec_input_config_params_vp9 =
 876		sm8550_vdec_input_config_param_vp9,
 877	.dec_input_config_params_vp9_size =
 878		ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
 879	.dec_output_config_params =
 880		sm8550_vdec_output_config_params,
 881	.dec_output_config_params_size =
 882		ARRAY_SIZE(sm8550_vdec_output_config_params),
 883
 884	.enc_input_config_params =
 885		sm8550_venc_input_config_params,
 886	.enc_input_config_params_size =
 887		ARRAY_SIZE(sm8550_venc_input_config_params),
 888	.enc_output_config_params =
 889		sm8550_venc_output_config_params,
 890	.enc_output_config_params_size =
 891		ARRAY_SIZE(sm8550_venc_output_config_params),
 892
 893	.dec_input_prop = sm8550_vdec_subscribe_input_properties,
 894	.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
 895	.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
 896	.dec_output_prop_avc_size =
 897		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
 898	.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
 899	.dec_output_prop_hevc_size =
 900		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
 901	.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
 902	.dec_output_prop_vp9_size =
 903		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
 904
 905	.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
 906	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
 907	.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
 908	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
 909
 910	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
 911	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
 912};
 913
 914const struct iris_platform_data sm8750_data = {
 915	.get_instance = iris_hfi_gen2_get_instance,
 916	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
 917	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
 918	.get_vpu_buffer_size = iris_vpu33_buf_size,
 919	.vpu_ops = &iris_vpu35_ops,
 920	.set_preset_registers = iris_set_sm8550_preset_registers,
 921	.icc_tbl = sm8550_icc_table,
 922	.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
 923	.clk_rst_tbl = sm8750_clk_reset_table,
 924	.clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),
 925	.bw_tbl_dec = sm8550_bw_table_dec,
 926	.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
 927	.pmdomain_tbl = sm8550_pmdomain_table,
 928	.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
 929	.opp_pd_tbl = sm8550_opp_pd_table,
 930	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
 931	.clk_tbl = sm8750_clk_table,
 932	.clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
 933	/* Upper bound of DMA address range */
 934	.dma_mask = 0xe0000000 - 1,
 935	.fwname = "qcom/vpu/vpu35_p4.mbn",
 936	.pas_id = IRIS_PAS_ID,
 937	.inst_caps = &platform_inst_cap_sm8550,
 938	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
 939	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
 940	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
 941	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
 942	.tz_cp_config_data = &tz_cp_config_sm8550,
 943	.core_arch = VIDEO_ARCH_LX,
 944	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
 945	.ubwc_config = &ubwc_config_sm8550,
 946	.num_vpp_pipe = 4,
 947	.max_session_count = 16,
 948	.max_core_mbpf = NUM_MBS_8K * 2,
 949	.max_core_mbps = ((7680 * 4320) / 256) * 60,
 950	.dec_input_config_params_default =
 951		sm8550_vdec_input_config_params_default,
 952	.dec_input_config_params_default_size =
 953		ARRAY_SIZE(sm8550_vdec_input_config_params_default),
 954	.dec_input_config_params_hevc =
 955		sm8550_vdec_input_config_param_hevc,
 956	.dec_input_config_params_hevc_size =
 957		ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
 958	.dec_input_config_params_vp9 =
 959		sm8550_vdec_input_config_param_vp9,
 960	.dec_input_config_params_vp9_size =
 961		ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
 962	.dec_output_config_params =
 963		sm8550_vdec_output_config_params,
 964	.dec_output_config_params_size =
 965		ARRAY_SIZE(sm8550_vdec_output_config_params),
 966
 967	.enc_input_config_params =
 968		sm8550_venc_input_config_params,
 969	.enc_input_config_params_size =
 970		ARRAY_SIZE(sm8550_venc_input_config_params),
 971	.enc_output_config_params =
 972		sm8550_venc_output_config_params,
 973	.enc_output_config_params_size =
 974		ARRAY_SIZE(sm8550_venc_output_config_params),
 975
 976	.dec_input_prop = sm8550_vdec_subscribe_input_properties,
 977	.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
 978	.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
 979	.dec_output_prop_avc_size =
 980		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
 981	.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
 982	.dec_output_prop_hevc_size =
 983		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
 984	.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
 985	.dec_output_prop_vp9_size =
 986		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
 987
 988	.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
 989	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
 990	.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
 991	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
 992
 993	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
 994	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
 995};
 996
 997/*
 998 * Shares most of SM8550 data except:
 999 * - inst_caps to platform_inst_cap_qcs8300
1000 */
1001const struct iris_platform_data qcs8300_data = {
1002	.get_instance = iris_hfi_gen2_get_instance,
1003	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
1004	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
1005	.get_vpu_buffer_size = iris_vpu_buf_size,
1006	.vpu_ops = &iris_vpu3_ops,
1007	.set_preset_registers = iris_set_sm8550_preset_registers,
1008	.icc_tbl = sm8550_icc_table,
1009	.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
1010	.clk_rst_tbl = sm8550_clk_reset_table,
1011	.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
1012	.bw_tbl_dec = sm8550_bw_table_dec,
1013	.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
1014	.pmdomain_tbl = sm8550_pmdomain_table,
1015	.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
1016	.opp_pd_tbl = sm8550_opp_pd_table,
1017	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
1018	.clk_tbl = sm8550_clk_table,
1019	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
1020	/* Upper bound of DMA address range */
1021	.dma_mask = 0xe0000000 - 1,
1022	.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
1023	.pas_id = IRIS_PAS_ID,
1024	.inst_caps = &platform_inst_cap_qcs8300,
1025	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
1026	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
1027	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
1028	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
1029	.tz_cp_config_data = &tz_cp_config_sm8550,
1030	.core_arch = VIDEO_ARCH_LX,
1031	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
1032	.ubwc_config = &ubwc_config_sm8550,
1033	.num_vpp_pipe = 2,
1034	.max_session_count = 16,
1035	.max_core_mbpf = ((4096 * 2176) / 256) * 4,
1036	.max_core_mbps = (((3840 * 2176) / 256) * 120),
1037	.dec_input_config_params_default =
1038		sm8550_vdec_input_config_params_default,
1039	.dec_input_config_params_default_size =
1040		ARRAY_SIZE(sm8550_vdec_input_config_params_default),
1041	.dec_input_config_params_hevc =
1042		sm8550_vdec_input_config_param_hevc,
1043	.dec_input_config_params_hevc_size =
1044		ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
1045	.dec_input_config_params_vp9 =
1046		sm8550_vdec_input_config_param_vp9,
1047	.dec_input_config_params_vp9_size =
1048		ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
1049	.dec_output_config_params =
1050		sm8550_vdec_output_config_params,
1051	.dec_output_config_params_size =
1052		ARRAY_SIZE(sm8550_vdec_output_config_params),
1053
1054	.enc_input_config_params =
1055		sm8550_venc_input_config_params,
1056	.enc_input_config_params_size =
1057		ARRAY_SIZE(sm8550_venc_input_config_params),
1058	.enc_output_config_params =
1059		sm8550_venc_output_config_params,
1060	.enc_output_config_params_size =
1061		ARRAY_SIZE(sm8550_venc_output_config_params),
1062
1063	.dec_input_prop = sm8550_vdec_subscribe_input_properties,
1064	.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
1065	.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
1066	.dec_output_prop_avc_size =
1067		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
1068	.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
1069	.dec_output_prop_hevc_size =
1070		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
1071	.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
1072	.dec_output_prop_vp9_size =
1073		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
1074
1075	.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
1076	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
1077	.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
1078	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
1079
1080	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
1081	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
1082};