iris_platform_gen1.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#include "iris_core.h"
  7#include "iris_ctrls.h"
  8#include "iris_platform_common.h"
  9#include "iris_resources.h"
 10#include "iris_hfi_gen1.h"
 11#include "iris_hfi_gen1_defines.h"
 12#include "iris_vpu_buffer.h"
 13#include "iris_vpu_common.h"
 14
 15#include "iris_platform_sc7280.h"
 16
 17#define BITRATE_MIN		32000
 18#define BITRATE_MAX		160000000
 19#define BITRATE_PEAK_DEFAULT	(BITRATE_DEFAULT * 2)
 20#define BITRATE_STEP		100
 21
 22static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
 23	{
 24		.cap_id = PIPE,
 25		/* .max, .min and .value are set via platform data */
 26		.step_or_mask = 1,
 27		.hfi_id = HFI_PROPERTY_PARAM_WORK_ROUTE,
 28		.set = iris_set_pipe,
 29	},
 30	{
 31		.cap_id = STAGE,
 32		.min = STAGE_1,
 33		.max = STAGE_2,
 34		.step_or_mask = 1,
 35		.value = STAGE_2,
 36		.hfi_id = HFI_PROPERTY_PARAM_WORK_MODE,
 37		.set = iris_set_stage,
 38	},
 39};
 40
 41static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
 42	{
 43		.cap_id = STAGE,
 44		.min = STAGE_1,
 45		.max = STAGE_2,
 46		.step_or_mask = 1,
 47		.value = STAGE_2,
 48		.hfi_id = HFI_PROPERTY_PARAM_WORK_MODE,
 49		.set = iris_set_stage,
 50	},
 51	{
 52		.cap_id = PROFILE_H264,
 53		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
 54		.max = V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH,
 55		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
 56				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
 57				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
 58				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
 59				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH) |
 60				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH),
 61		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
 62		.hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
 63		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 64		.set = iris_set_profile_level_gen1,
 65	},
 66	{
 67		.cap_id = PROFILE_HEVC,
 68		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
 69		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
 70		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
 71				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
 72				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
 73		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
 74		.hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
 75		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
 76		.set = iris_set_profile_level_gen1,
 77	},
 78	{
 79		.cap_id = LEVEL_H264,
 80		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
 81		.max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
 82		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
 83				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
 84				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
 85				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
 86				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
 87				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
 88				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
 89				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
 90				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
 91				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
 92				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
 93				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
 94				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
 95				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
 96				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
 97				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
 98		.value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
 99		.hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
100		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
101		.set = iris_set_profile_level_gen1,
102	},
103	{
104		.cap_id = LEVEL_HEVC,
105		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
106		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
107		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
108				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
109				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
110				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
111				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
112				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
113				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
114				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
115				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
116				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
117				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
118				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
119				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
120		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
121		.hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
122		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
123		.set = iris_set_profile_level_gen1,
124	},
125	{
126		.cap_id = HEADER_MODE,
127		.min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
128		.max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
129		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
130				BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
131		.value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
132		.hfi_id = HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER,
133		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
134		.set = iris_set_header_mode_gen1,
135	},
136	{
137		.cap_id = BITRATE,
138		.min = BITRATE_MIN,
139		.max = BITRATE_MAX,
140		.step_or_mask = BITRATE_STEP,
141		.value = BITRATE_DEFAULT,
142		.hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE,
143		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
144			CAP_FLAG_DYNAMIC_ALLOWED,
145		.set = iris_set_bitrate,
146	},
147	{
148		.cap_id = BITRATE_MODE,
149		.min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
150		.max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
151		.step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
152				BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
153		.value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
154		.hfi_id = HFI_PROPERTY_PARAM_VENC_RATE_CONTROL,
155		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
156		.set = iris_set_bitrate_mode_gen1,
157	},
158	{
159		.cap_id = FRAME_SKIP_MODE,
160		.min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
161		.max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
162		.step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
163				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
164		.value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
165		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
166	},
167	{
168		.cap_id = FRAME_RC_ENABLE,
169		.min = 0,
170		.max = 1,
171		.step_or_mask = 1,
172		.value = 1,
173	},
174	{
175		.cap_id = GOP_SIZE,
176		.min = 0,
177		.max = (1 << 16) - 1,
178		.step_or_mask = 1,
179		.value = 30,
180		.set = iris_set_u32
181	},
182	{
183		.cap_id = ENTROPY_MODE,
184		.min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
185		.max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
186		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
187				BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
188		.value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
189		.hfi_id = HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL,
190		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
191		.set = iris_set_entropy_mode_gen1,
192	},
193	{
194		.cap_id = MIN_FRAME_QP_H264,
195		.min = MIN_QP_8BIT,
196		.max = MAX_QP,
197		.step_or_mask = 1,
198		.value = MIN_QP_8BIT,
199		.hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
200		.flags = CAP_FLAG_OUTPUT_PORT,
201		.set = iris_set_qp_range,
202	},
203	{
204		.cap_id = MIN_FRAME_QP_HEVC,
205		.min = MIN_QP_8BIT,
206		.max = MAX_QP_HEVC,
207		.step_or_mask = 1,
208		.value = MIN_QP_8BIT,
209		.hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
210		.flags = CAP_FLAG_OUTPUT_PORT,
211		.set = iris_set_qp_range,
212	},
213	{
214		.cap_id = MAX_FRAME_QP_H264,
215		.min = MIN_QP_8BIT,
216		.max = MAX_QP,
217		.step_or_mask = 1,
218		.value = MAX_QP,
219		.hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
220		.flags = CAP_FLAG_OUTPUT_PORT,
221		.set = iris_set_qp_range,
222	},
223	{
224		.cap_id = MAX_FRAME_QP_HEVC,
225		.min = MIN_QP_8BIT,
226		.max = MAX_QP_HEVC,
227		.step_or_mask = 1,
228		.value = MAX_QP_HEVC,
229		.hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
230		.flags = CAP_FLAG_OUTPUT_PORT,
231		.set = iris_set_qp_range,
232	},
233};
234
235static struct platform_inst_caps platform_inst_cap_sm8250 = {
236	.min_frame_width = 128,
237	.max_frame_width = 8192,
238	.min_frame_height = 128,
239	.max_frame_height = 8192,
240	.max_mbpf = 138240,
241	.mb_cycles_vsp = 25,
242	.mb_cycles_vpp = 200,
243	.max_frame_rate = MAXIMUM_FPS,
244	.max_operating_rate = MAXIMUM_FPS,
245};
246
247static void iris_set_sm8250_preset_registers(struct iris_core *core)
248{
249	writel(0x0, core->reg_base + 0xB0088);
250}
251
252static const struct icc_info sm8250_icc_table[] = {
253	{ "cpu-cfg",    1000, 1000     },
254	{ "video-mem",  1000, 15000000 },
255};
256
257static const char * const sm8250_clk_reset_table[] = { "bus", "core" };
258
259static const struct bw_info sm8250_bw_table_dec[] = {
260	{ ((4096 * 2160) / 256) * 60, 2403000 },
261	{ ((4096 * 2160) / 256) * 30, 1224000 },
262	{ ((1920 * 1080) / 256) * 60,  812000 },
263	{ ((1920 * 1080) / 256) * 30,  416000 },
264};
265
266static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" };
267
268static const char * const sm8250_opp_pd_table[] = { "mx" };
269
270static const struct platform_clk_data sm8250_clk_table[] = {
271	{IRIS_AXI_CLK,  "iface"        },
272	{IRIS_CTRL_CLK, "core"         },
273	{IRIS_HW_CLK,   "vcodec0_core" },
274};
275
276static struct tz_cp_config tz_cp_config_sm8250 = {
277	.cp_start = 0,
278	.cp_size = 0x25800000,
279	.cp_nonpixel_start = 0x01000000,
280	.cp_nonpixel_size = 0x24800000,
281};
282
283static const u32 sm8250_vdec_input_config_param_default[] = {
284	HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE,
285	HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT,
286	HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO,
287	HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL,
288	HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM,
289	HFI_PROPERTY_PARAM_FRAME_SIZE,
290	HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL,
291	HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE,
292};
293
294static const u32 sm8250_venc_input_config_param[] = {
295	HFI_PROPERTY_CONFIG_FRAME_RATE,
296	HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO,
297	HFI_PROPERTY_PARAM_FRAME_SIZE,
298	HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT,
299	HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL,
300};
301
302static const u32 sm8250_dec_ip_int_buf_tbl[] = {
303	BUF_BIN,
304	BUF_SCRATCH_1,
305};
306
307static const u32 sm8250_dec_op_int_buf_tbl[] = {
308	BUF_DPB,
309};
310
311static const u32 sm8250_enc_ip_int_buf_tbl[] = {
312	BUF_BIN,
313	BUF_SCRATCH_1,
314	BUF_SCRATCH_2,
315};
316
317const struct iris_platform_data sm8250_data = {
318	.get_instance = iris_hfi_gen1_get_instance,
319	.init_hfi_command_ops = &iris_hfi_gen1_command_ops_init,
320	.init_hfi_response_ops = iris_hfi_gen1_response_ops_init,
321	.get_vpu_buffer_size = iris_vpu_buf_size,
322	.vpu_ops = &iris_vpu2_ops,
323	.set_preset_registers = iris_set_sm8250_preset_registers,
324	.icc_tbl = sm8250_icc_table,
325	.icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
326	.clk_rst_tbl = sm8250_clk_reset_table,
327	.clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table),
328	.bw_tbl_dec = sm8250_bw_table_dec,
329	.bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
330	.pmdomain_tbl = sm8250_pmdomain_table,
331	.pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
332	.opp_pd_tbl = sm8250_opp_pd_table,
333	.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
334	.clk_tbl = sm8250_clk_table,
335	.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
336	/* Upper bound of DMA address range */
337	.dma_mask = 0xe0000000 - 1,
338	.fwname = "qcom/vpu-1.0/venus.mbn",
339	.pas_id = IRIS_PAS_ID,
340	.inst_caps = &platform_inst_cap_sm8250,
341	.inst_fw_caps_dec = inst_fw_cap_sm8250_dec,
342	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
343	.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
344	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
345	.tz_cp_config_data = &tz_cp_config_sm8250,
346	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
347	.num_vpp_pipe = 4,
348	.max_session_count = 16,
349	.max_core_mbpf = NUM_MBS_8K,
350	.max_core_mbps = ((7680 * 4320) / 256) * 60,
351	.dec_input_config_params_default =
352		sm8250_vdec_input_config_param_default,
353	.dec_input_config_params_default_size =
354		ARRAY_SIZE(sm8250_vdec_input_config_param_default),
355	.enc_input_config_params = sm8250_venc_input_config_param,
356	.enc_input_config_params_size =
357		ARRAY_SIZE(sm8250_venc_input_config_param),
358
359	.dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl,
360	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl),
361	.dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
362	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
363
364	.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
365	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
366};
367
368const struct iris_platform_data sc7280_data = {
369	.get_instance = iris_hfi_gen1_get_instance,
370	.init_hfi_command_ops = &iris_hfi_gen1_command_ops_init,
371	.init_hfi_response_ops = iris_hfi_gen1_response_ops_init,
372	.get_vpu_buffer_size = iris_vpu_buf_size,
373	.vpu_ops = &iris_vpu2_ops,
374	.set_preset_registers = iris_set_sm8250_preset_registers,
375	.icc_tbl = sm8250_icc_table,
376	.icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
377	.bw_tbl_dec = sc7280_bw_table_dec,
378	.bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
379	.pmdomain_tbl = sm8250_pmdomain_table,
380	.pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
381	.opp_pd_tbl = sc7280_opp_pd_table,
382	.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
383	.clk_tbl = sc7280_clk_table,
384	.clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
385	/* Upper bound of DMA address range */
386	.dma_mask = 0xe0000000 - 1,
387	.fwname = "qcom/vpu/vpu20_p1.mbn",
388	.pas_id = IRIS_PAS_ID,
389	.inst_caps = &platform_inst_cap_sm8250,
390	.inst_fw_caps_dec = inst_fw_cap_sm8250_dec,
391	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
392	.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
393	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
394	.tz_cp_config_data = &tz_cp_config_sm8250,
395	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
396	.num_vpp_pipe = 1,
397	.no_aon = true,
398	.max_session_count = 16,
399	.max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
400	/* max spec for SC7280 is 4096x2176@60fps */
401	.max_core_mbps = 4096 * 2176 / 256 * 60,
402	.dec_input_config_params_default =
403		sm8250_vdec_input_config_param_default,
404	.dec_input_config_params_default_size =
405		ARRAY_SIZE(sm8250_vdec_input_config_param_default),
406	.enc_input_config_params = sm8250_venc_input_config_param,
407	.enc_input_config_params_size =
408		ARRAY_SIZE(sm8250_venc_input_config_param),
409
410	.dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl,
411	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl),
412	.dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
413	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
414
415	.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
416	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
417};