iris_hfi_queue.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#ifndef __IRIS_HFI_QUEUE_H__
  7#define __IRIS_HFI_QUEUE_H__
  8
  9struct iris_core;
 10
 11/*
 12 * Max 64 Buffers ( 32 input buffers and 32 output buffers)
 13 * can be queued by v4l2 framework at any given time.
 14 */
 15#define IFACEQ_MAX_BUF_COUNT		64
 16/*
 17 * Max session supported are 16.
 18 * this value is used to calcualte the size of
 19 * individual shared queue.
 20 */
 21#define IFACE_MAX_PARALLEL_SESSIONS	16
 22#define IFACEQ_DFLT_QHDR		0x0101
 23#define IFACEQ_MAX_PKT_SIZE		1024 /* Maximum size of a packet in the queue */
 24
 25/*
 26 * SFR: Subsystem Failure Reason
 27 * when hardware goes into bad state/failure, firmware fills this memory
 28 * and driver will get to know the actual failure reason from this SFR buffer.
 29 */
 30#define SFR_SIZE			SZ_4K /* Iris hardware requires 4K queue alignment */
 31
 32#define IFACEQ_QUEUE_SIZE		(IFACEQ_MAX_PKT_SIZE * \
 33					 IFACEQ_MAX_BUF_COUNT * IFACE_MAX_PARALLEL_SESSIONS)
 34
 35/*
 36 * Memory layout of the shared queues:
 37 *
 38 *   ||=================||  ^        ^         ^
 39 *   ||                 ||  |        |         |
 40 *   ||    Queue Table  || 288 Bytes |         |
 41 *   ||      Header     ||  |        |         |
 42 *   ||                 ||  |        |         |
 43 *   ||-----------------||  V        |         |
 44 *   ||-----------------||  ^        |         |
 45 *   ||                 ||  |        |         |
 46 *   ||  Command Queue  || 56 Bytes  |         |
 47 *   ||     Header      ||  |        |         |
 48 *   ||                 ||  |        |         |
 49 *   ||-----------------||  V       456 Bytes  |
 50 *   ||-----------------||  ^        |         |
 51 *   ||                 ||  |        |         |
 52 *   ||  Message Queue  || 56 Bytes  |         |
 53 *   ||     Header      ||  |        |         |
 54 *   ||                 ||  |        |         |
 55 *   ||-----------------||  V        |         Buffer size aligned to 4k
 56 *   ||-----------------||  ^        |         Overall Queue Size = 2,404 KB
 57 *   ||                 ||  |        |         |
 58 *   ||   Debug Queue   || 56 Bytes  |         |
 59 *   ||     Header      ||  |        |         |
 60 *   ||                 ||  |        |         |
 61 *   ||=================||  V        V         |
 62 *   ||=================||           ^         |
 63 *   ||                 ||           |         |
 64 *   ||     Command     ||         800 KB      |
 65 *   ||      Queue      ||           |         |
 66 *   ||                 ||           |         |
 67 *   ||=================||           V         |
 68 *   ||=================||           ^         |
 69 *   ||                 ||           |         |
 70 *   ||     Message     ||         800 KB      |
 71 *   ||      Queue      ||           |         |
 72 *   ||                 ||           |         |
 73 *   ||=================||           V         |
 74 *   ||=================||           ^         |
 75 *   ||                 ||           |         |
 76 *   ||      Debug      ||         800 KB      |
 77 *   ||      Queue      ||           |         |
 78 *   ||                 ||           |         |
 79 *   ||=================||           V         |
 80 *   ||                 ||                     |
 81 *   ||=================||                     V
 82 */
 83
 84/*
 85 * Shared queues are used for communication between driver and firmware.
 86 * There are 3 types of queues:
 87 * Command queue - driver to write any command to firmware.
 88 * Message queue - firmware to send any response to driver.
 89 * Debug queue - firmware to write debug message.
 90 */
 91
 92/* Host-firmware shared queue ids */
 93enum iris_iface_queue {
 94	IFACEQ_CMDQ_ID,
 95	IFACEQ_MSGQ_ID,
 96	IFACEQ_DBGQ_ID,
 97	IFACEQ_NUMQ, /* not an index */
 98};
 99
100/**
101 * struct iris_hfi_queue_header
102 *
103 * @status: Queue status, bits (7:0), 0x1 - active, 0x0 - inactive
104 * @start_addr: Queue start address in non cached memory
105 * @queue_type: Queue ID
106 * @header_type: Default queue header
107 * @q_size: Queue size
108 *		Number of queue packets if pkt_size is non-zero
109 *		Queue size in bytes if pkt_size is zero
110 * @pkt_size: Size of queue packet entries
111 *		0x0: variable queue packet size
112 *		non zero: size of queue packet entry, fixed
113 * @pkt_drop_cnt: Number of packets dropped by sender
114 * @rx_wm: Receiver watermark, applicable in event driven mode
115 * @tx_wm: Sender watermark, applicable in event driven mode
116 * @rx_req: Receiver sets this bit if queue is empty
117 * @tx_req: Sender sets this bit if queue is full
118 * @rx_irq_status: Receiver sets this bit and triggers an interrupt to
119 *		the sender after packets are dequeued. Sender clears this bit
120 * @tx_irq_status: Sender sets this bit and triggers an interrupt to
121 *		the receiver after packets are queued. Receiver clears this bit
122 * @read_idx: Index till where receiver has consumed the packets from the queue.
123 * @write_idx: Index till where sender has written the packets into the queue.
124 */
125struct iris_hfi_queue_header {
126	u32 status;
127	u32 start_addr;
128	u16 queue_type;
129	u16 header_type;
130	u32 q_size;
131	u32 pkt_size;
132	u32 pkt_drop_cnt;
133	u32 rx_wm;
134	u32 tx_wm;
135	u32 rx_req;
136	u32 tx_req;
137	u32 rx_irq_status;
138	u32 tx_irq_status;
139	u32 read_idx;
140	u32 write_idx;
141};
142
143/**
144 * struct iris_hfi_queue_table_header
145 *
146 * @version: Queue table version number
147 * @size: Queue table size from version to last parametr in qhdr entry
148 * @qhdr0_offset: Offset to the start of first qhdr
149 * @qhdr_size: Queue header size in bytes
150 * @num_q: Total number of queues in Queue table
151 * @num_active_q: Total number of active queues
152 * @device_addr: Device address of the queue
153 * @name: Queue name in characters
154 * @q_hdr: Array of queue headers
155 */
156struct iris_hfi_queue_table_header {
157	u32 version;
158	u32 size;
159	u32 qhdr0_offset;
160	u32 qhdr_size;
161	u32 num_q;
162	u32 num_active_q;
163	void *device_addr;
164	char name[256]; /* NUL-terminated array of characters */
165	struct iris_hfi_queue_header q_hdr[IFACEQ_NUMQ];
166};
167
168struct iris_iface_q_info {
169	struct iris_hfi_queue_header *qhdr;
170	dma_addr_t	device_addr;
171	void		*kernel_vaddr;
172};
173
174int iris_hfi_queues_init(struct iris_core *core);
175void iris_hfi_queues_deinit(struct iris_core *core);
176
177int iris_hfi_queue_cmd_write_locked(struct iris_core *core, void *pkt, u32 pkt_size);
178int iris_hfi_queue_cmd_write(struct iris_core *core, void *pkt, u32 pkt_size);
179int iris_hfi_queue_msg_read(struct iris_core *core, void *pkt);
180int iris_hfi_queue_dbg_read(struct iris_core *core, void *pkt);
181
182#endif