iris_core.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#ifndef __IRIS_CORE_H__
  7#define __IRIS_CORE_H__
  8
  9#include <linux/types.h>
 10#include <linux/pm_domain.h>
 11#include <media/v4l2-device.h>
 12
 13#include "iris_hfi_common.h"
 14#include "iris_hfi_queue.h"
 15#include "iris_platform_common.h"
 16#include "iris_resources.h"
 17#include "iris_state.h"
 18
 19struct icc_info {
 20	const char		*name;
 21	u32			bw_min_kbps;
 22	u32			bw_max_kbps;
 23};
 24
 25#define IRIS_FW_VERSION_LENGTH		128
 26#define IFACEQ_CORE_PKT_SIZE		(1024 * 4)
 27
 28enum domain_type {
 29	ENCODER	= BIT(0),
 30	DECODER	= BIT(1),
 31};
 32
 33/**
 34 * struct iris_core - holds core parameters valid for all instances
 35 *
 36 * @dev: reference to device structure
 37 * @reg_base: IO memory base address
 38 * @irq: iris irq
 39 * @v4l2_dev: a holder for v4l2 device structure
 40 * @vdev_dec: iris video device structure for decoder
 41 * @vdev_enc: iris video device structure for encoder
 42 * @iris_v4l2_file_ops: iris v4l2 file ops
 43 * @iris_v4l2_ioctl_ops_dec: iris v4l2 ioctl ops for decoder
 44 * @iris_v4l2_ioctl_ops_enc: iris v4l2 ioctl ops for encoder
 45 * @iris_vb2_ops: iris vb2 ops
 46 * @icc_tbl: table of iris interconnects
 47 * @icc_count: count of iris interconnects
 48 * @pmdomain_tbl: table of iris power domains
 49 * @opp_pmdomain_tbl: table of opp power domains
 50 * @clock_tbl: table of iris clocks
 51 * @clk_count: count of iris clocks
 52 * @resets: table of iris reset clocks
 53 * @controller_resets: table of controller reset clocks
 54 * @iris_platform_data: a structure for platform data
 55 * @state: current state of core
 56 * @iface_q_table_daddr: device address for interface queue table memory
 57 * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory
 58 * @iface_q_table_vaddr: virtual address for interface queue table memory
 59 * @sfr_vaddr: virtual address for SFR (Sub System Failure Reason) register memory
 60 * @command_queue: shared interface queue to send commands to firmware
 61 * @message_queue: shared interface queue to receive responses from firmware
 62 * @debug_queue: shared interface queue to receive debug info from firmware
 63 * @lock: a lock for this strucure
 64 * @response_packet: a pointer to response packet from fw to driver
 65 * @header_id: id of packet header
 66 * @packet_id: id of packet
 67 * @power: a structure for clock and bw information
 68 * @hfi_ops: iris hfi command ops
 69 * @hfi_response_ops: iris hfi response ops
 70 * @core_init_done: structure of signal completion for system response
 71 * @intr_status: interrupt status
 72 * @sys_error_handler: a delayed work for handling system fatal error
 73 * @instances: a list_head of all instances
 74 * @inst_fw_caps_dec: an array of supported instance capabilities by decoder
 75 * @inst_fw_caps_enc: an array of supported instance capabilities by encoder
 76 */
 77
 78struct iris_core {
 79	struct device				*dev;
 80	void __iomem				*reg_base;
 81	int					irq;
 82	struct v4l2_device			v4l2_dev;
 83	struct video_device			*vdev_dec;
 84	struct video_device			*vdev_enc;
 85	const struct v4l2_file_operations	*iris_v4l2_file_ops;
 86	const struct v4l2_ioctl_ops		*iris_v4l2_ioctl_ops_dec;
 87	const struct v4l2_ioctl_ops		*iris_v4l2_ioctl_ops_enc;
 88	const struct vb2_ops			*iris_vb2_ops;
 89	struct icc_bulk_data			*icc_tbl;
 90	u32					icc_count;
 91	struct dev_pm_domain_list		*pmdomain_tbl;
 92	struct dev_pm_domain_list		*opp_pmdomain_tbl;
 93	struct clk_bulk_data			*clock_tbl;
 94	u32					clk_count;
 95	struct reset_control_bulk_data		*resets;
 96	struct reset_control_bulk_data		*controller_resets;
 97	const struct iris_platform_data		*iris_platform_data;
 98	enum iris_core_state			state;
 99	dma_addr_t				iface_q_table_daddr;
100	dma_addr_t				sfr_daddr;
101	void					*iface_q_table_vaddr;
102	void					*sfr_vaddr;
103	struct iris_iface_q_info		command_queue;
104	struct iris_iface_q_info		message_queue;
105	struct iris_iface_q_info		debug_queue;
106	struct mutex				lock; /* lock for core related operations */
107	u8					*response_packet;
108	u32					header_id;
109	u32					packet_id;
110	struct iris_core_power			power;
111	const struct iris_hfi_command_ops	*hfi_ops;
112	const struct iris_hfi_response_ops	*hfi_response_ops;
113	struct completion			core_init_done;
114	u32					intr_status;
115	struct delayed_work			sys_error_handler;
116	struct list_head			instances;
117	/* encoder and decoder have overlapping caps, so two different arrays are required */
118	struct platform_inst_fw_cap		inst_fw_caps_dec[INST_FW_CAP_MAX];
119	struct platform_inst_fw_cap		inst_fw_caps_enc[INST_FW_CAP_MAX];
120};
121
122int iris_core_init(struct iris_core *core);
123void iris_core_deinit(struct iris_core *core);
124
125#endif