camss.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * camss.c
   4 *
   5 * Qualcomm MSM Camera Subsystem - Core
   6 *
   7 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   8 * Copyright (C) 2015-2018 Linaro Ltd.
   9 */
  10#include <linux/clk.h>
  11#include <linux/interconnect.h>
  12#include <linux/media-bus-format.h>
  13#include <linux/media.h>
  14#include <linux/module.h>
  15#include <linux/platform_device.h>
  16#include <linux/of.h>
  17#include <linux/of_device.h>
  18#include <linux/of_graph.h>
  19#include <linux/pm_runtime.h>
  20#include <linux/pm_domain.h>
  21#include <linux/slab.h>
  22#include <linux/videodev2.h>
  23
  24#include <media/media-device.h>
  25#include <media/v4l2-async.h>
  26#include <media/v4l2-device.h>
  27#include <media/v4l2-mc.h>
  28#include <media/v4l2-fwnode.h>
  29
  30#include "camss.h"
  31
  32#define CAMSS_CLOCK_MARGIN_NUMERATOR 105
  33#define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
  34
  35static const struct parent_dev_ops vfe_parent_dev_ops;
  36
  37static const struct camss_subdev_resources csiphy_res_8x16[] = {
  38	/* CSIPHY0 */
  39	{
  40		.regulators = {},
  41		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
  42		.clock_rate = { { 0 },
  43				{ 0 },
  44				{ 0 },
  45				{ 100000000, 200000000 } },
  46		.reg = { "csiphy0", "csiphy0_clk_mux" },
  47		.interrupt = { "csiphy0" },
  48		.csiphy = {
  49			.id = 0,
  50			.hw_ops = &csiphy_ops_2ph_1_0,
  51			.formats = &csiphy_formats_8x16
  52		}
  53	},
  54
  55	/* CSIPHY1 */
  56	{
  57		.regulators = {},
  58		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
  59		.clock_rate = { { 0 },
  60				{ 0 },
  61				{ 0 },
  62				{ 100000000, 200000000 } },
  63		.reg = { "csiphy1", "csiphy1_clk_mux" },
  64		.interrupt = { "csiphy1" },
  65		.csiphy = {
  66			.id = 1,
  67			.hw_ops = &csiphy_ops_2ph_1_0,
  68			.formats = &csiphy_formats_8x16
  69		}
  70	}
  71};
  72
  73static const struct camss_subdev_resources csid_res_8x16[] = {
  74	/* CSID0 */
  75	{
  76		.regulators = { "vdda" },
  77		.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
  78			   "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
  79		.clock_rate = { { 0 },
  80				{ 0 },
  81				{ 0 },
  82				{ 0 },
  83				{ 100000000, 200000000 },
  84				{ 0 },
  85				{ 0 },
  86				{ 0 } },
  87		.reg = { "csid0" },
  88		.interrupt = { "csid0" },
  89		.csid = {
  90			.hw_ops = &csid_ops_4_1,
  91			.parent_dev_ops = &vfe_parent_dev_ops,
  92			.formats = &csid_formats_4_1
  93		}
  94	},
  95
  96	/* CSID1 */
  97	{
  98		.regulators = { "vdda" },
  99		.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
 100			   "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
 101		.clock_rate = { { 0 },
 102				{ 0 },
 103				{ 0 },
 104				{ 0 },
 105				{ 100000000, 200000000 },
 106				{ 0 },
 107				{ 0 },
 108				{ 0 } },
 109		.reg = { "csid1" },
 110		.interrupt = { "csid1" },
 111		.csid = {
 112			.hw_ops = &csid_ops_4_1,
 113			.parent_dev_ops = &vfe_parent_dev_ops,
 114			.formats = &csid_formats_4_1
 115		}
 116	},
 117};
 118
 119static const struct camss_subdev_resources ispif_res_8x16 = {
 120	/* ISPIF */
 121	.clock = { "top_ahb", "ahb", "ispif_ahb",
 122		   "csi0", "csi0_pix", "csi0_rdi",
 123		   "csi1", "csi1_pix", "csi1_rdi" },
 124	.clock_for_reset = { "vfe0", "csi_vfe0" },
 125	.reg = { "ispif", "csi_clk_mux" },
 126	.interrupt = { "ispif" },
 127};
 128
 129static const struct camss_subdev_resources vfe_res_8x16[] = {
 130	/* VFE0 */
 131	{
 132		.regulators = {},
 133		.clock = { "top_ahb", "vfe0", "csi_vfe0",
 134			   "vfe_ahb", "vfe_axi", "ahb" },
 135		.clock_rate = { { 0 },
 136				{ 50000000, 80000000, 100000000, 160000000,
 137				  177780000, 200000000, 266670000, 320000000,
 138				  400000000, 465000000 },
 139				{ 0 },
 140				{ 0 },
 141				{ 0 },
 142				{ 0 },
 143				{ 0 },
 144				{ 0 },
 145				{ 0 } },
 146		.reg = { "vfe0" },
 147		.interrupt = { "vfe0" },
 148		.vfe = {
 149			.line_num = 3,
 150			.hw_ops = &vfe_ops_4_1,
 151			.formats_rdi = &vfe_formats_rdi_8x16,
 152			.formats_pix = &vfe_formats_pix_8x16
 153		}
 154	}
 155};
 156
 157static const struct camss_subdev_resources csiphy_res_8x39[] = {
 158	/* CSIPHY0 */
 159	{
 160		.regulators = { "vdda" },
 161		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
 162		.clock_rate = { { 0 },
 163				{ 40000000, 80000000 },
 164				{ 0 },
 165				{ 100000000, 200000000 } },
 166		.reg = { "csiphy0", "csiphy0_clk_mux" },
 167		.interrupt = { "csiphy0" },
 168		.csiphy = {
 169			.id = 0,
 170			.hw_ops = &csiphy_ops_2ph_1_0,
 171			.formats = &csiphy_formats_8x16
 172		}
 173	},
 174
 175	/* CSIPHY1 */
 176	{
 177		.regulators = { "vdda" },
 178		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
 179		.clock_rate = { { 0 },
 180				{ 40000000, 80000000 },
 181				{ 0 },
 182				{ 100000000, 200000000 } },
 183		.reg = { "csiphy1", "csiphy1_clk_mux" },
 184		.interrupt = { "csiphy1" },
 185		.csiphy = {
 186			.id = 1,
 187			.hw_ops = &csiphy_ops_2ph_1_0,
 188			.formats = &csiphy_formats_8x16
 189		}
 190	}
 191};
 192
 193static const struct camss_subdev_resources csid_res_8x39[] = {
 194	/* CSID0 */
 195	{
 196		.regulators = {},
 197		.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
 198			   "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
 199		.clock_rate = { { 0 },
 200				{ 40000000, 80000000 },
 201				{ 0 },
 202				{ 0 },
 203				{ 100000000, 200000000 },
 204				{ 0 },
 205				{ 0 },
 206				{ 0 } },
 207		.reg = { "csid0" },
 208		.interrupt = { "csid0" },
 209		.csid = {
 210			.hw_ops = &csid_ops_4_1,
 211			.parent_dev_ops = &vfe_parent_dev_ops,
 212			.formats = &csid_formats_4_1
 213		}
 214	},
 215
 216	/* CSID1 */
 217	{
 218		.regulators = {},
 219		.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
 220			   "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
 221		.clock_rate = { { 0 },
 222				{ 40000000, 80000000 },
 223				{ 0 },
 224				{ 0 },
 225				{ 100000000, 200000000 },
 226				{ 0 },
 227				{ 0 },
 228				{ 0 } },
 229		.reg = { "csid1" },
 230		.interrupt = { "csid1" },
 231		.csid = {
 232			.hw_ops = &csid_ops_4_1,
 233			.parent_dev_ops = &vfe_parent_dev_ops,
 234			.formats = &csid_formats_4_1
 235		}
 236	},
 237
 238	/* CSID2 */
 239	{
 240		.regulators = {},
 241		.clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
 242			   "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
 243		.clock_rate = { { 0 },
 244				{ 40000000, 80000000 },
 245				{ 0 },
 246				{ 0 },
 247				{ 100000000, 200000000 },
 248				{ 0 },
 249				{ 0 },
 250				{ 0 } },
 251		.reg = { "csid2" },
 252		.interrupt = { "csid2" },
 253		.csid = {
 254			.hw_ops = &csid_ops_4_1,
 255			.parent_dev_ops = &vfe_parent_dev_ops,
 256			.formats = &csid_formats_4_1
 257		}
 258	},
 259};
 260
 261static const struct camss_subdev_resources ispif_res_8x39 = {
 262	/* ISPIF */
 263	.clock = { "top_ahb", "ispif_ahb", "ahb",
 264		   "csi0", "csi0_pix", "csi0_rdi",
 265		   "csi1", "csi1_pix", "csi1_rdi",
 266		   "csi2", "csi2_pix", "csi2_rdi" },
 267	.clock_for_reset = { "vfe0", "csi_vfe0" },
 268	.reg = { "ispif", "csi_clk_mux" },
 269	.interrupt = { "ispif" },
 270};
 271
 272static const struct camss_subdev_resources vfe_res_8x39[] = {
 273	/* VFE0 */
 274	{
 275		.regulators = {},
 276		.clock = { "top_ahb", "ispif_ahb", "vfe0", "csi_vfe0",
 277			   "vfe_ahb", "vfe_axi", "ahb" },
 278		.clock_rate = { { 0 },
 279				{ 40000000, 80000000 },
 280				{ 50000000, 80000000, 100000000, 160000000,
 281				  177780000, 200000000, 266670000, 320000000,
 282				  400000000, 465000000, 480000000, 600000000 },
 283				{ 0 },
 284				{ 0 },
 285				{ 0 },
 286				{ 0 } },
 287		.reg = { "vfe0" },
 288		.interrupt = { "vfe0" },
 289		.vfe = {
 290			.line_num = 3,
 291			.has_vbif = true,
 292			.vbif_name = "vfe0_vbif",
 293			.hw_ops = &vfe_ops_4_1,
 294			.formats_rdi = &vfe_formats_rdi_8x16,
 295			.formats_pix = &vfe_formats_pix_8x16
 296		}
 297	}
 298};
 299
 300static const struct camss_subdev_resources csid_res_8x53[] = {
 301	/* CSID0 */
 302	{
 303		.regulators = { "vdda" },
 304		.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
 305			   "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
 306		.clock_rate = { { 0 },
 307				{ 0 },
 308				{ 0 },
 309				{ 0 },
 310				{ 100000000, 200000000, 310000000,
 311				  400000000, 465000000 },
 312				{ 0 },
 313				{ 0 },
 314				{ 0 } },
 315		.reg = { "csid0" },
 316		.interrupt = { "csid0" },
 317		.csid = {
 318			.hw_ops = &csid_ops_4_7,
 319			.parent_dev_ops = &vfe_parent_dev_ops,
 320			.formats = &csid_formats_4_7
 321		}
 322	},
 323
 324	/* CSID1 */
 325	{
 326		.regulators = { "vdda" },
 327		.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
 328			   "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
 329		.clock_rate = { { 0 },
 330				{ 0 },
 331				{ 0 },
 332				{ 0 },
 333				{ 100000000, 200000000, 310000000,
 334				  400000000, 465000000 },
 335				{ 0 },
 336				{ 0 },
 337				{ 0 } },
 338		.reg = { "csid1" },
 339		.interrupt = { "csid1" },
 340		.csid = {
 341			.hw_ops = &csid_ops_4_7,
 342			.parent_dev_ops = &vfe_parent_dev_ops,
 343			.formats = &csid_formats_4_7
 344		}
 345	},
 346
 347	/* CSID2 */
 348	{
 349		.regulators = { "vdda" },
 350		.clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
 351			   "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
 352		.clock_rate = { { 0 },
 353				{ 0 },
 354				{ 0 },
 355				{ 0 },
 356				{ 100000000, 200000000, 310000000,
 357				  400000000, 465000000 },
 358				{ 0 },
 359				{ 0 },
 360				{ 0 } },
 361		.reg = { "csid2" },
 362		.interrupt = { "csid2" },
 363		.csid = {
 364			.hw_ops = &csid_ops_4_7,
 365			.parent_dev_ops = &vfe_parent_dev_ops,
 366			.formats = &csid_formats_4_7
 367		}
 368	},
 369};
 370
 371static const struct camss_subdev_resources ispif_res_8x53 = {
 372	/* ISPIF */
 373	.clock = { "top_ahb", "ahb", "ispif_ahb",
 374		   "csi0", "csi0_pix", "csi0_rdi",
 375		   "csi1", "csi1_pix", "csi1_rdi",
 376		   "csi2", "csi2_pix", "csi2_rdi" },
 377	.clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
 378	.reg = { "ispif", "csi_clk_mux" },
 379	.interrupt = { "ispif" },
 380};
 381
 382static const struct camss_subdev_resources vfe_res_8x53[] = {
 383	/* VFE0 */
 384	{
 385		.regulators = {},
 386		.clock = { "top_ahb", "ahb", "ispif_ahb",
 387			   "vfe0", "csi_vfe0", "vfe0_ahb", "vfe0_axi" },
 388		.clock_rate = { { 0 },
 389				{ 0 },
 390				{ 0 },
 391				{ 50000000, 100000000, 133330000,
 392				  160000000, 200000000, 266670000,
 393				  310000000, 400000000, 465000000 },
 394				{ 0 },
 395				{ 0 },
 396				{ 0 } },
 397		.reg = { "vfe0" },
 398		.interrupt = { "vfe0" },
 399		.vfe = {
 400			.line_num = 3,
 401			.has_pd = true,
 402			.pd_name = "vfe0",
 403			.hw_ops = &vfe_ops_4_1,
 404			.formats_rdi = &vfe_formats_rdi_8x16,
 405			.formats_pix = &vfe_formats_pix_8x16
 406		}
 407	},
 408
 409	/* VFE1 */
 410	{
 411		.regulators = {},
 412		.clock = { "top_ahb", "ahb", "ispif_ahb",
 413			   "vfe1", "csi_vfe1", "vfe1_ahb", "vfe1_axi" },
 414		.clock_rate = { { 0 },
 415				{ 0 },
 416				{ 0 },
 417				{ 50000000, 100000000, 133330000,
 418				  160000000, 200000000, 266670000,
 419				  310000000, 400000000, 465000000 },
 420				{ 0 },
 421				{ 0 },
 422				{ 0 } },
 423		.reg = { "vfe1" },
 424		.interrupt = { "vfe1" },
 425		.vfe = {
 426			.line_num = 3,
 427			.has_pd = true,
 428			.pd_name = "vfe1",
 429			.hw_ops = &vfe_ops_4_1,
 430			.formats_rdi = &vfe_formats_rdi_8x16,
 431			.formats_pix = &vfe_formats_pix_8x16
 432		}
 433	}
 434};
 435
 436static const struct resources_icc icc_res_8x53[] = {
 437	{
 438		.name = "cam_ahb",
 439		.icc_bw_tbl.avg = 38400,
 440		.icc_bw_tbl.peak = 76800,
 441	},
 442	{
 443		.name = "cam_vfe0_mem",
 444		.icc_bw_tbl.avg = 939524,
 445		.icc_bw_tbl.peak = 1342177,
 446	},
 447	{
 448		.name = "cam_vfe1_mem",
 449		.icc_bw_tbl.avg = 939524,
 450		.icc_bw_tbl.peak = 1342177,
 451	},
 452};
 453
 454static const struct camss_subdev_resources csiphy_res_8x96[] = {
 455	/* CSIPHY0 */
 456	{
 457		.regulators = {},
 458		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
 459		.clock_rate = { { 0 },
 460				{ 0 },
 461				{ 0 },
 462				{ 100000000, 200000000, 266666667 } },
 463		.reg = { "csiphy0", "csiphy0_clk_mux" },
 464		.interrupt = { "csiphy0" },
 465		.csiphy = {
 466			.id = 0,
 467			.hw_ops = &csiphy_ops_3ph_1_0,
 468			.formats = &csiphy_formats_8x96
 469		}
 470	},
 471
 472	/* CSIPHY1 */
 473	{
 474		.regulators = {},
 475		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
 476		.clock_rate = { { 0 },
 477				{ 0 },
 478				{ 0 },
 479				{ 100000000, 200000000, 266666667 } },
 480		.reg = { "csiphy1", "csiphy1_clk_mux" },
 481		.interrupt = { "csiphy1" },
 482		.csiphy = {
 483			.id = 1,
 484			.hw_ops = &csiphy_ops_3ph_1_0,
 485			.formats = &csiphy_formats_8x96
 486		}
 487	},
 488
 489	/* CSIPHY2 */
 490	{
 491		.regulators = {},
 492		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
 493		.clock_rate = { { 0 },
 494				{ 0 },
 495				{ 0 },
 496				{ 100000000, 200000000, 266666667 } },
 497		.reg = { "csiphy2", "csiphy2_clk_mux" },
 498		.interrupt = { "csiphy2" },
 499		.csiphy = {
 500			.id = 2,
 501			.hw_ops = &csiphy_ops_3ph_1_0,
 502			.formats = &csiphy_formats_8x96
 503		}
 504	}
 505};
 506
 507static const struct camss_subdev_resources csid_res_8x96[] = {
 508	/* CSID0 */
 509	{
 510		.regulators = { "vdda" },
 511		.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
 512			   "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
 513		.clock_rate = { { 0 },
 514				{ 0 },
 515				{ 0 },
 516				{ 0 },
 517				{ 100000000, 200000000, 266666667 },
 518				{ 0 },
 519				{ 0 },
 520				{ 0 } },
 521		.reg = { "csid0" },
 522		.interrupt = { "csid0" },
 523		.csid = {
 524			.hw_ops = &csid_ops_4_7,
 525			.parent_dev_ops = &vfe_parent_dev_ops,
 526			.formats = &csid_formats_4_7
 527		}
 528	},
 529
 530	/* CSID1 */
 531	{
 532		.regulators = { "vdda" },
 533		.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
 534			   "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
 535		.clock_rate = { { 0 },
 536				{ 0 },
 537				{ 0 },
 538				{ 0 },
 539				{ 100000000, 200000000, 266666667 },
 540				{ 0 },
 541				{ 0 },
 542				{ 0 } },
 543		.reg = { "csid1" },
 544		.interrupt = { "csid1" },
 545		.csid = {
 546			.hw_ops = &csid_ops_4_7,
 547			.parent_dev_ops = &vfe_parent_dev_ops,
 548			.formats = &csid_formats_4_7
 549		}
 550	},
 551
 552	/* CSID2 */
 553	{
 554		.regulators = { "vdda" },
 555		.clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
 556			   "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
 557		.clock_rate = { { 0 },
 558				{ 0 },
 559				{ 0 },
 560				{ 0 },
 561				{ 100000000, 200000000, 266666667 },
 562				{ 0 },
 563				{ 0 },
 564				{ 0 } },
 565		.reg = { "csid2" },
 566		.interrupt = { "csid2" },
 567		.csid = {
 568			.hw_ops = &csid_ops_4_7,
 569			.parent_dev_ops = &vfe_parent_dev_ops,
 570			.formats = &csid_formats_4_7
 571		}
 572	},
 573
 574	/* CSID3 */
 575	{
 576		.regulators = { "vdda" },
 577		.clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
 578			   "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" },
 579		.clock_rate = { { 0 },
 580				{ 0 },
 581				{ 0 },
 582				{ 0 },
 583				{ 100000000, 200000000, 266666667 },
 584				{ 0 },
 585				{ 0 },
 586				{ 0 } },
 587		.reg = { "csid3" },
 588		.interrupt = { "csid3" },
 589		.csid = {
 590			.hw_ops = &csid_ops_4_7,
 591			.parent_dev_ops = &vfe_parent_dev_ops,
 592			.formats = &csid_formats_4_7
 593		}
 594	}
 595};
 596
 597static const struct camss_subdev_resources ispif_res_8x96 = {
 598	/* ISPIF */
 599	.clock = { "top_ahb", "ahb", "ispif_ahb",
 600		   "csi0", "csi0_pix", "csi0_rdi",
 601		   "csi1", "csi1_pix", "csi1_rdi",
 602		   "csi2", "csi2_pix", "csi2_rdi",
 603		   "csi3", "csi3_pix", "csi3_rdi" },
 604	.clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
 605	.reg = { "ispif", "csi_clk_mux" },
 606	.interrupt = { "ispif" },
 607};
 608
 609static const struct camss_subdev_resources vfe_res_8x96[] = {
 610	/* VFE0 */
 611	{
 612		.regulators = {},
 613		.clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb",
 614			   "vfe0_ahb", "vfe_axi", "vfe0_stream"},
 615		.clock_rate = { { 0 },
 616				{ 0 },
 617				{ 75000000, 100000000, 300000000,
 618				  320000000, 480000000, 600000000 },
 619				{ 0 },
 620				{ 0 },
 621				{ 0 },
 622				{ 0 },
 623				{ 0 } },
 624		.reg = { "vfe0" },
 625		.interrupt = { "vfe0" },
 626		.vfe = {
 627			.line_num = 3,
 628			.has_pd = true,
 629			.hw_ops = &vfe_ops_4_7,
 630			.formats_rdi = &vfe_formats_rdi_8x96,
 631			.formats_pix = &vfe_formats_pix_8x96
 632		}
 633	},
 634
 635	/* VFE1 */
 636	{
 637		.regulators = {},
 638		.clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb",
 639			   "vfe1_ahb", "vfe_axi", "vfe1_stream"},
 640		.clock_rate = { { 0 },
 641				{ 0 },
 642				{ 75000000, 100000000, 300000000,
 643				  320000000, 480000000, 600000000 },
 644				{ 0 },
 645				{ 0 },
 646				{ 0 },
 647				{ 0 },
 648				{ 0 } },
 649		.reg = { "vfe1" },
 650		.interrupt = { "vfe1" },
 651		.vfe = {
 652			.line_num = 3,
 653			.has_pd = true,
 654			.hw_ops = &vfe_ops_4_7,
 655			.formats_rdi = &vfe_formats_rdi_8x96,
 656			.formats_pix = &vfe_formats_pix_8x96
 657		}
 658	}
 659};
 660
 661static const struct camss_subdev_resources csiphy_res_2290[] = {
 662	/* CSIPHY0 */
 663	{
 664		.regulators = { "vdd-csiphy-1p2", "vdd-csiphy-1p8" },
 665		.clock = { "top_ahb", "ahb", "csiphy0", "csiphy0_timer" },
 666		.clock_rate = { { 0 },
 667				{ 0 },
 668				{ 240000000, 341330000, 384000000 },
 669				{ 100000000, 200000000, 268800000 }  },
 670		.reg = { "csiphy0" },
 671		.interrupt = { "csiphy0" },
 672		.csiphy = {
 673			.id = 0,
 674			.hw_ops = &csiphy_ops_3ph_1_0,
 675			.formats = &csiphy_formats_sdm845
 676		}
 677	},
 678
 679	/* CSIPHY1 */
 680	{
 681		.regulators = { "vdd-csiphy-1p2", "vdd-csiphy-1p8" },
 682		.clock = { "top_ahb", "ahb", "csiphy1", "csiphy1_timer" },
 683		.clock_rate = { { 0 },
 684				{ 0 },
 685				{ 240000000, 341330000, 384000000 },
 686				{ 100000000, 200000000, 268800000 }  },
 687		.reg = { "csiphy1" },
 688		.interrupt = { "csiphy1" },
 689		.csiphy = {
 690			.id = 1,
 691			.hw_ops = &csiphy_ops_3ph_1_0,
 692			.formats = &csiphy_formats_sdm845
 693		}
 694	}
 695};
 696
 697static const struct camss_subdev_resources csid_res_2290[] = {
 698	/* CSID0 */
 699	{
 700		.regulators = {},
 701		.clock = { "top_ahb", "ahb", "csi0", "vfe0_cphy_rx", "vfe0" },
 702		.clock_rate = { { 0 },
 703				{ 0 },
 704				{ 192000000, 240000000, 384000000, 426400000 },
 705				{ 0 },
 706				{ 0 } },
 707		.reg = { "csid0" },
 708		.interrupt = { "csid0" },
 709		.csid = {
 710			.hw_ops = &csid_ops_340,
 711			.parent_dev_ops = &vfe_parent_dev_ops,
 712			.formats = &csid_formats_gen2
 713		}
 714	},
 715
 716	/* CSID1 */
 717	{
 718		.regulators = {},
 719		.clock = { "top_ahb", "ahb", "csi1", "vfe1_cphy_rx", "vfe1" },
 720		.clock_rate = { { 0 },
 721				{ 0 },
 722				{ 192000000, 240000000, 384000000, 426400000 },
 723				{ 0 },
 724				{ 0 } },
 725		.reg = { "csid1" },
 726		.interrupt = { "csid1" },
 727		.csid = {
 728			.hw_ops = &csid_ops_340,
 729			.parent_dev_ops = &vfe_parent_dev_ops,
 730			.formats = &csid_formats_gen2
 731		}
 732	}
 733};
 734
 735static const struct camss_subdev_resources vfe_res_2290[] = {
 736	/* VFE0 */
 737	{
 738		.regulators = {},
 739		.clock = { "top_ahb", "ahb", "axi", "vfe0", "camnoc_rt_axi", "camnoc_nrt_axi" },
 740		.clock_rate = { { 0 },
 741				{ 0 },
 742				{ 0 },
 743				{ 19200000, 153600000, 192000000, 256000000, 384000000, 460800000 },
 744				{ 0 },
 745				{ 0 }, },
 746		.reg = { "vfe0" },
 747		.interrupt = { "vfe0" },
 748		.vfe = {
 749			.line_num = 4,
 750			.hw_ops = &vfe_ops_340,
 751			.formats_rdi = &vfe_formats_rdi_845,
 752			.formats_pix = &vfe_formats_pix_845
 753		}
 754	},
 755
 756	/* VFE1 */
 757	{
 758		.regulators = {},
 759		.clock = { "top_ahb", "ahb", "axi", "vfe1", "camnoc_rt_axi", "camnoc_nrt_axi" },
 760		.clock_rate = { { 0 },
 761				{ 0 },
 762				{ 0 },
 763				{ 19200000, 153600000, 192000000, 256000000, 384000000, 460800000 },
 764				{ 0 },
 765				{ 0 }, },
 766		.reg = { "vfe1" },
 767		.interrupt = { "vfe1" },
 768		.vfe = {
 769			.line_num = 4,
 770			.hw_ops = &vfe_ops_340,
 771			.formats_rdi = &vfe_formats_rdi_845,
 772			.formats_pix = &vfe_formats_pix_845
 773		}
 774	},
 775};
 776
 777static const struct resources_icc icc_res_2290[] = {
 778	{
 779		.name = "ahb",
 780		.icc_bw_tbl.avg = 150000,
 781		.icc_bw_tbl.peak = 300000,
 782	},
 783	{
 784		.name = "hf_mnoc",
 785		.icc_bw_tbl.avg = 2097152,
 786		.icc_bw_tbl.peak = 3000000,
 787	},
 788	{
 789		.name = "sf_mnoc",
 790		.icc_bw_tbl.avg = 2097152,
 791		.icc_bw_tbl.peak = 3000000,
 792	},
 793};
 794
 795static const struct camss_subdev_resources csiphy_res_660[] = {
 796	/* CSIPHY0 */
 797	{
 798		.regulators = {},
 799		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer",
 800			   "csi0_phy", "csiphy_ahb2crif" },
 801		.clock_rate = { { 0 },
 802				{ 0 },
 803				{ 0 },
 804				{ 100000000, 200000000, 269333333 },
 805				{ 0 } },
 806		.reg = { "csiphy0", "csiphy0_clk_mux" },
 807		.interrupt = { "csiphy0" },
 808		.csiphy = {
 809			.id = 0,
 810			.hw_ops = &csiphy_ops_3ph_1_0,
 811			.formats = &csiphy_formats_8x96
 812		}
 813	},
 814
 815	/* CSIPHY1 */
 816	{
 817		.regulators = {},
 818		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer",
 819			   "csi1_phy", "csiphy_ahb2crif" },
 820		.clock_rate = { { 0 },
 821				{ 0 },
 822				{ 0 },
 823				{ 100000000, 200000000, 269333333 },
 824				{ 0 } },
 825		.reg = { "csiphy1", "csiphy1_clk_mux" },
 826		.interrupt = { "csiphy1" },
 827		.csiphy = {
 828			.id = 1,
 829			.hw_ops = &csiphy_ops_3ph_1_0,
 830			.formats = &csiphy_formats_8x96
 831		}
 832	},
 833
 834	/* CSIPHY2 */
 835	{
 836		.regulators = {},
 837		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer",
 838			   "csi2_phy", "csiphy_ahb2crif" },
 839		.clock_rate = { { 0 },
 840				{ 0 },
 841				{ 0 },
 842				{ 100000000, 200000000, 269333333 },
 843				{ 0 } },
 844		.reg = { "csiphy2", "csiphy2_clk_mux" },
 845		.interrupt = { "csiphy2" },
 846		.csiphy = {
 847			.id = 2,
 848			.hw_ops = &csiphy_ops_3ph_1_0,
 849			.formats = &csiphy_formats_8x96
 850		}
 851	}
 852};
 853
 854static const struct camss_subdev_resources csid_res_660[] = {
 855	/* CSID0 */
 856	{
 857		.regulators = { "vdda", "vdd_sec" },
 858		.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
 859			   "csi0", "csi0_phy", "csi0_pix", "csi0_rdi",
 860			   "cphy_csid0" },
 861		.clock_rate = { { 0 },
 862				{ 0 },
 863				{ 0 },
 864				{ 0 },
 865				{ 100000000, 200000000, 310000000,
 866				  404000000, 465000000 },
 867				{ 0 },
 868				{ 0 },
 869				{ 0 },
 870				{ 0 } },
 871		.reg = { "csid0" },
 872		.interrupt = { "csid0" },
 873		.csid = {
 874			.hw_ops = &csid_ops_4_7,
 875			.parent_dev_ops = &vfe_parent_dev_ops,
 876			.formats = &csid_formats_4_7
 877		}
 878	},
 879
 880	/* CSID1 */
 881	{
 882		.regulators = { "vdda", "vdd_sec" },
 883		.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
 884			   "csi1", "csi1_phy", "csi1_pix", "csi1_rdi",
 885			   "cphy_csid1" },
 886		.clock_rate = { { 0 },
 887				{ 0 },
 888				{ 0 },
 889				{ 0 },
 890				{ 100000000, 200000000, 310000000,
 891				  404000000, 465000000 },
 892				{ 0 },
 893				{ 0 },
 894				{ 0 },
 895				{ 0 } },
 896		.reg = { "csid1" },
 897		.interrupt = { "csid1" },
 898		.csid = {
 899			.hw_ops = &csid_ops_4_7,
 900			.parent_dev_ops = &vfe_parent_dev_ops,
 901			.formats = &csid_formats_4_7
 902		}
 903	},
 904
 905	/* CSID2 */
 906	{
 907		.regulators = { "vdda", "vdd_sec" },
 908		.clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
 909			   "csi2", "csi2_phy", "csi2_pix", "csi2_rdi",
 910			   "cphy_csid2" },
 911		.clock_rate = { { 0 },
 912				{ 0 },
 913				{ 0 },
 914				{ 0 },
 915				{ 100000000, 200000000, 310000000,
 916				  404000000, 465000000 },
 917				{ 0 },
 918				{ 0 },
 919				{ 0 },
 920				{ 0 } },
 921		.reg = { "csid2" },
 922		.interrupt = { "csid2" },
 923		.csid = {
 924			.hw_ops = &csid_ops_4_7,
 925			.parent_dev_ops = &vfe_parent_dev_ops,
 926			.formats = &csid_formats_4_7
 927		}
 928	},
 929
 930	/* CSID3 */
 931	{
 932		.regulators = { "vdda", "vdd_sec" },
 933		.clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
 934			   "csi3", "csi3_phy", "csi3_pix", "csi3_rdi",
 935			   "cphy_csid3" },
 936		.clock_rate = { { 0 },
 937				{ 0 },
 938				{ 0 },
 939				{ 0 },
 940				{ 100000000, 200000000, 310000000,
 941				  404000000, 465000000 },
 942				{ 0 },
 943				{ 0 },
 944				{ 0 },
 945				{ 0 } },
 946		.reg = { "csid3" },
 947		.interrupt = { "csid3" },
 948		.csid = {
 949			.hw_ops = &csid_ops_4_7,
 950			.parent_dev_ops = &vfe_parent_dev_ops,
 951			.formats = &csid_formats_4_7
 952		}
 953	}
 954};
 955
 956static const struct camss_subdev_resources ispif_res_660 = {
 957	/* ISPIF */
 958	.clock = { "top_ahb", "ahb", "ispif_ahb",
 959		   "csi0", "csi0_pix", "csi0_rdi",
 960		   "csi1", "csi1_pix", "csi1_rdi",
 961		   "csi2", "csi2_pix", "csi2_rdi",
 962		   "csi3", "csi3_pix", "csi3_rdi" },
 963	.clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
 964	.reg = { "ispif", "csi_clk_mux" },
 965	.interrupt = { "ispif" },
 966};
 967
 968static const struct camss_subdev_resources vfe_res_660[] = {
 969	/* VFE0 */
 970	{
 971		.regulators = {},
 972		.clock = { "throttle_axi", "top_ahb", "ahb", "vfe0",
 973			   "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi",
 974			   "vfe0_stream"},
 975		.clock_rate = { { 0 },
 976				{ 0 },
 977				{ 0 },
 978				{ 120000000, 200000000, 256000000,
 979				  300000000, 404000000, 480000000,
 980				  540000000, 576000000 },
 981				{ 0 },
 982				{ 0 },
 983				{ 0 },
 984				{ 0 },
 985				{ 0 } },
 986		.reg = { "vfe0" },
 987		.interrupt = { "vfe0" },
 988		.vfe = {
 989			.line_num = 3,
 990			.has_pd = true,
 991			.hw_ops = &vfe_ops_4_8,
 992			.formats_rdi = &vfe_formats_rdi_8x96,
 993			.formats_pix = &vfe_formats_pix_8x96
 994		}
 995	},
 996
 997	/* VFE1 */
 998	{
 999		.regulators = {},
1000		.clock = { "throttle_axi", "top_ahb", "ahb", "vfe1",
1001			   "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi",
1002			   "vfe1_stream"},
1003		.clock_rate = { { 0 },
1004				{ 0 },
1005				{ 0 },
1006				{ 120000000, 200000000, 256000000,
1007				  300000000, 404000000, 480000000,
1008				  540000000, 576000000 },
1009				{ 0 },
1010				{ 0 },
1011				{ 0 },
1012				{ 0 },
1013				{ 0 } },
1014		.reg = { "vfe1" },
1015		.interrupt = { "vfe1" },
1016		.vfe = {
1017			.line_num = 3,
1018			.has_pd = true,
1019			.hw_ops = &vfe_ops_4_8,
1020			.formats_rdi = &vfe_formats_rdi_8x96,
1021			.formats_pix = &vfe_formats_pix_8x96
1022		}
1023	}
1024};
1025
1026static const struct camss_subdev_resources csiphy_res_670[] = {
1027	/* CSIPHY0 */
1028	{
1029		.regulators = { "vdda-phy", "vdda-pll" },
1030		.clock = { "soc_ahb", "cpas_ahb",
1031			   "csiphy0", "csiphy0_timer" },
1032		.clock_rate = { { 0 },
1033				{ 0 },
1034				{ 0 },
1035				{ 19200000, 240000000, 269333333 } },
1036		.reg = { "csiphy0" },
1037		.interrupt = { "csiphy0" },
1038		.csiphy = {
1039			.id = 0,
1040			.hw_ops = &csiphy_ops_3ph_1_0,
1041			.formats = &csiphy_formats_sdm845
1042		}
1043	},
1044
1045	/* CSIPHY1 */
1046	{
1047		.regulators = { "vdda-phy", "vdda-pll" },
1048		.clock = { "soc_ahb", "cpas_ahb",
1049			   "csiphy1", "csiphy1_timer" },
1050		.clock_rate = { { 0 },
1051				{ 0 },
1052				{ 0 },
1053				{ 19200000, 240000000, 269333333 } },
1054		.reg = { "csiphy1" },
1055		.interrupt = { "csiphy1" },
1056		.csiphy = {
1057			.id = 1,
1058			.hw_ops = &csiphy_ops_3ph_1_0,
1059			.formats = &csiphy_formats_sdm845
1060		}
1061	},
1062
1063	/* CSIPHY2 */
1064	{
1065		.regulators = { "vdda-phy", "vdda-pll" },
1066		.clock = { "soc_ahb", "cpas_ahb",
1067			   "csiphy2", "csiphy2_timer" },
1068		.clock_rate = { { 0 },
1069				{ 0 },
1070				{ 0 },
1071				{ 19200000, 240000000, 269333333 } },
1072		.reg = { "csiphy2" },
1073		.interrupt = { "csiphy2" },
1074		.csiphy = {
1075			.id = 2,
1076			.hw_ops = &csiphy_ops_3ph_1_0,
1077			.formats = &csiphy_formats_sdm845
1078		}
1079	}
1080};
1081
1082static const struct camss_subdev_resources csid_res_670[] = {
1083	/* CSID0 */
1084	{
1085		.regulators = {},
1086		.clock = { "cpas_ahb", "soc_ahb", "vfe0",
1087			   "vfe0_cphy_rx", "csi0" },
1088		.clock_rate = { { 0 },
1089				{ 0 },
1090				{ 100000000, 320000000, 404000000, 480000000, 600000000 },
1091				{ 384000000 },
1092				{ 19200000, 75000000, 384000000, 538666667 } },
1093		.reg = { "csid0" },
1094		.interrupt = { "csid0" },
1095		.csid = {
1096			.hw_ops = &csid_ops_gen2,
1097			.parent_dev_ops = &vfe_parent_dev_ops,
1098			.formats = &csid_formats_gen2
1099		}
1100	},
1101
1102	/* CSID1 */
1103	{
1104		.regulators = {},
1105		.clock = { "cpas_ahb", "soc_ahb", "vfe1",
1106			   "vfe1_cphy_rx", "csi1" },
1107		.clock_rate = { { 0 },
1108				{ 0 },
1109				{ 100000000, 320000000, 404000000, 480000000, 600000000 },
1110				{ 384000000 },
1111				{ 19200000, 75000000, 384000000, 538666667 } },
1112		.reg = { "csid1" },
1113		.interrupt = { "csid1" },
1114		.csid = {
1115			.hw_ops = &csid_ops_gen2,
1116			.parent_dev_ops = &vfe_parent_dev_ops,
1117			.formats = &csid_formats_gen2
1118		}
1119	},
1120
1121	/* CSID2 */
1122	{
1123		.regulators = {},
1124		.clock = { "cpas_ahb", "soc_ahb", "vfe_lite",
1125			   "vfe_lite_cphy_rx", "csi2" },
1126		.clock_rate = { { 0 },
1127				{ 0 },
1128				{ 100000000, 320000000, 404000000, 480000000, 600000000 },
1129				{ 384000000 },
1130				{ 19200000, 75000000, 384000000, 538666667 } },
1131		.reg = { "csid2" },
1132		.interrupt = { "csid2" },
1133		.csid = {
1134			.is_lite = true,
1135			.hw_ops = &csid_ops_gen2,
1136			.parent_dev_ops = &vfe_parent_dev_ops,
1137			.formats = &csid_formats_gen2
1138		}
1139	}
1140};
1141
1142static const struct camss_subdev_resources vfe_res_670[] = {
1143	/* VFE0 */
1144	{
1145		.regulators = {},
1146		.clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
1147			   "vfe0", "vfe0_axi" },
1148		.clock_rate = { { 0 },
1149				{ 0 },
1150				{ 0 },
1151				{ 100000000, 320000000, 404000000, 480000000, 600000000 },
1152				{ 0 } },
1153		.reg = { "vfe0" },
1154		.interrupt = { "vfe0" },
1155		.vfe = {
1156			.line_num = 4,
1157			.has_pd = true,
1158			.pd_name = "ife0",
1159			.hw_ops = &vfe_ops_170,
1160			.formats_rdi = &vfe_formats_rdi_845,
1161			.formats_pix = &vfe_formats_pix_845
1162		}
1163	},
1164
1165	/* VFE1 */
1166	{
1167		.regulators = {},
1168		.clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
1169			   "vfe1", "vfe1_axi" },
1170		.clock_rate = { { 0 },
1171				{ 0 },
1172				{ 0 },
1173				{ 100000000, 320000000, 404000000, 480000000, 600000000 },
1174				{ 0 } },
1175		.reg = { "vfe1" },
1176		.interrupt = { "vfe1" },
1177		.vfe = {
1178			.line_num = 4,
1179			.has_pd = true,
1180			.pd_name = "ife1",
1181			.hw_ops = &vfe_ops_170,
1182			.formats_rdi = &vfe_formats_rdi_845,
1183			.formats_pix = &vfe_formats_pix_845
1184		}
1185	},
1186
1187	/* VFE-lite */
1188	{
1189		.regulators = {},
1190		.clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
1191			   "vfe_lite" },
1192		.clock_rate = { { 0 },
1193				{ 0 },
1194				{ 0 },
1195				{ 100000000, 320000000, 404000000, 480000000, 600000000 } },
1196		.reg = { "vfe_lite" },
1197		.interrupt = { "vfe_lite" },
1198		.vfe = {
1199			.is_lite = true,
1200			.line_num = 4,
1201			.hw_ops = &vfe_ops_170,
1202			.formats_rdi = &vfe_formats_rdi_845,
1203			.formats_pix = &vfe_formats_pix_845
1204		}
1205	}
1206};
1207
1208static const struct camss_subdev_resources csiphy_res_845[] = {
1209	/* CSIPHY0 */
1210	{
1211		.regulators = {},
1212		.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
1213				"cpas_ahb", "cphy_rx_src", "csiphy0",
1214				"csiphy0_timer_src", "csiphy0_timer" },
1215		.clock_rate = { { 0 },
1216				{ 0 },
1217				{ 0 },
1218				{ 0 },
1219				{ 0 },
1220				{ 0 },
1221				{ 0 },
1222				{ 19200000, 240000000, 269333333 } },
1223		.reg = { "csiphy0" },
1224		.interrupt = { "csiphy0" },
1225		.csiphy = {
1226			.id = 0,
1227			.hw_ops = &csiphy_ops_3ph_1_0,
1228			.formats = &csiphy_formats_sdm845
1229		}
1230	},
1231
1232	/* CSIPHY1 */
1233	{
1234		.regulators = {},
1235		.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
1236				"cpas_ahb", "cphy_rx_src", "csiphy1",
1237				"csiphy1_timer_src", "csiphy1_timer" },
1238		.clock_rate = { { 0 },
1239				{ 0 },
1240				{ 0 },
1241				{ 0 },
1242				{ 0 },
1243				{ 0 },
1244				{ 0 },
1245				{ 19200000, 240000000, 269333333 } },
1246		.reg = { "csiphy1" },
1247		.interrupt = { "csiphy1" },
1248		.csiphy = {
1249			.id = 1,
1250			.hw_ops = &csiphy_ops_3ph_1_0,
1251			.formats = &csiphy_formats_sdm845
1252		}
1253	},
1254
1255	/* CSIPHY2 */
1256	{
1257		.regulators = {},
1258		.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
1259				"cpas_ahb", "cphy_rx_src", "csiphy2",
1260				"csiphy2_timer_src", "csiphy2_timer" },
1261		.clock_rate = { { 0 },
1262				{ 0 },
1263				{ 0 },
1264				{ 0 },
1265				{ 0 },
1266				{ 0 },
1267				{ 0 },
1268				{ 19200000, 240000000, 269333333 } },
1269		.reg = { "csiphy2" },
1270		.interrupt = { "csiphy2" },
1271		.csiphy = {
1272			.id = 2,
1273			.hw_ops = &csiphy_ops_3ph_1_0,
1274			.formats = &csiphy_formats_sdm845
1275		}
1276	},
1277
1278	/* CSIPHY3 */
1279	{
1280		.regulators = {},
1281		.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
1282				"cpas_ahb", "cphy_rx_src", "csiphy3",
1283				"csiphy3_timer_src", "csiphy3_timer" },
1284		.clock_rate = { { 0 },
1285				{ 0 },
1286				{ 0 },
1287				{ 0 },
1288				{ 0 },
1289				{ 0 },
1290				{ 0 },
1291				{ 19200000, 240000000, 269333333 } },
1292		.reg = { "csiphy3" },
1293		.interrupt = { "csiphy3" },
1294		.csiphy = {
1295			.id = 3,
1296			.hw_ops = &csiphy_ops_3ph_1_0,
1297			.formats = &csiphy_formats_sdm845
1298		}
1299	}
1300};
1301
1302static const struct camss_subdev_resources csid_res_845[] = {
1303	/* CSID0 */
1304	{
1305		.regulators = { "vdda-phy", "vdda-pll" },
1306		.clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
1307				"soc_ahb", "vfe0", "vfe0_src",
1308				"vfe0_cphy_rx", "csi0",
1309				"csi0_src" },
1310		.clock_rate = { { 0 },
1311				{ 384000000 },
1312				{ 80000000 },
1313				{ 0 },
1314				{ 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
1315				{ 320000000 },
1316				{ 0 },
1317				{ 19200000, 75000000, 384000000, 538666667 },
1318				{ 384000000 } },
1319		.reg = { "csid0" },
1320		.interrupt = { "csid0" },
1321		.csid = {
1322			.hw_ops = &csid_ops_gen2,
1323			.parent_dev_ops = &vfe_parent_dev_ops,
1324			.formats = &csid_formats_gen2
1325		}
1326	},
1327
1328	/* CSID1 */
1329	{
1330		.regulators = { "vdda-phy", "vdda-pll" },
1331		.clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
1332				"soc_ahb", "vfe1", "vfe1_src",
1333				"vfe1_cphy_rx", "csi1",
1334				"csi1_src" },
1335		.clock_rate = { { 0 },
1336				{ 384000000 },
1337				{ 80000000 },
1338				{ 0 },
1339				{ 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
1340				{ 320000000 },
1341				{ 0 },
1342				{ 19200000, 75000000, 384000000, 538666667 },
1343				{ 384000000 } },
1344		.reg = { "csid1" },
1345		.interrupt = { "csid1" },
1346		.csid = {
1347			.hw_ops = &csid_ops_gen2,
1348			.parent_dev_ops = &vfe_parent_dev_ops,
1349			.formats = &csid_formats_gen2
1350		}
1351	},
1352
1353	/* CSID2 */
1354	{
1355		.regulators = { "vdda-phy", "vdda-pll" },
1356		.clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
1357				"soc_ahb", "vfe_lite", "vfe_lite_src",
1358				"vfe_lite_cphy_rx", "csi2",
1359				"csi2_src" },
1360		.clock_rate = { { 0 },
1361				{ 384000000 },
1362				{ 80000000 },
1363				{ 0 },
1364				{ 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
1365				{ 320000000 },
1366				{ 0 },
1367				{ 19200000, 75000000, 384000000, 538666667 },
1368				{ 384000000 } },
1369		.reg = { "csid2" },
1370		.interrupt = { "csid2" },
1371		.csid = {
1372			.is_lite = true,
1373			.hw_ops = &csid_ops_gen2,
1374			.parent_dev_ops = &vfe_parent_dev_ops,
1375			.formats = &csid_formats_gen2
1376		}
1377	}
1378};
1379
1380static const struct camss_subdev_resources vfe_res_845[] = {
1381	/* VFE0 */
1382	{
1383		.regulators = {},
1384		.clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
1385				"soc_ahb", "vfe0", "vfe0_axi",
1386				"vfe0_src", "csi0",
1387				"csi0_src"},
1388		.clock_rate = { { 0 },
1389				{ 0 },
1390				{ 80000000 },
1391				{ 0 },
1392				{ 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
1393				{ 0 },
1394				{ 320000000 },
1395				{ 19200000, 75000000, 384000000, 538666667 },
1396				{ 384000000 } },
1397		.reg = { "vfe0" },
1398		.interrupt = { "vfe0" },
1399		.vfe = {
1400			.line_num = 4,
1401			.pd_name = "ife0",
1402			.has_pd = true,
1403			.hw_ops = &vfe_ops_170,
1404			.formats_rdi = &vfe_formats_rdi_845,
1405			.formats_pix = &vfe_formats_pix_845
1406		}
1407	},
1408
1409	/* VFE1 */
1410	{
1411		.regulators = {},
1412		.clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
1413				"soc_ahb", "vfe1", "vfe1_axi",
1414				"vfe1_src", "csi1",
1415				"csi1_src"},
1416		.clock_rate = { { 0 },
1417				{ 0 },
1418				{ 80000000 },
1419				{ 0 },
1420				{ 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
1421				{ 0 },
1422				{ 320000000 },
1423				{ 19200000, 75000000, 384000000, 538666667 },
1424				{ 384000000 } },
1425		.reg = { "vfe1" },
1426		.interrupt = { "vfe1" },
1427		.vfe = {
1428			.line_num = 4,
1429			.pd_name = "ife1",
1430			.has_pd = true,
1431			.hw_ops = &vfe_ops_170,
1432			.formats_rdi = &vfe_formats_rdi_845,
1433			.formats_pix = &vfe_formats_pix_845
1434		}
1435	},
1436
1437	/* VFE-lite */
1438	{
1439		.regulators = {},
1440		.clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
1441				"soc_ahb", "vfe_lite",
1442				"vfe_lite_src", "csi2",
1443				"csi2_src"},
1444		.clock_rate = { { 0 },
1445				{ 0 },
1446				{ 80000000 },
1447				{ 0 },
1448				{ 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
1449				{ 320000000 },
1450				{ 19200000, 75000000, 384000000, 538666667 },
1451				{ 384000000 } },
1452		.reg = { "vfe_lite" },
1453		.interrupt = { "vfe_lite" },
1454		.vfe = {
1455			.is_lite = true,
1456			.line_num = 4,
1457			.hw_ops = &vfe_ops_170,
1458			.formats_rdi = &vfe_formats_rdi_845,
1459			.formats_pix = &vfe_formats_pix_845
1460		}
1461	}
1462};
1463
1464static const struct camss_subdev_resources csiphy_res_8250[] = {
1465	/* CSIPHY0 */
1466	{
1467		.regulators = { "vdda-phy", "vdda-pll" },
1468		.clock = { "csiphy0", "csiphy0_timer" },
1469		.clock_rate = { { 400000000 },
1470				{ 300000000 } },
1471		.reg = { "csiphy0" },
1472		.interrupt = { "csiphy0" },
1473		.csiphy = {
1474			.id = 0,
1475			.hw_ops = &csiphy_ops_3ph_1_0,
1476			.formats = &csiphy_formats_sdm845
1477		}
1478	},
1479	/* CSIPHY1 */
1480	{
1481		.regulators = { "vdda-phy", "vdda-pll" },
1482		.clock = { "csiphy1", "csiphy1_timer" },
1483		.clock_rate = { { 400000000 },
1484				{ 300000000 } },
1485		.reg = { "csiphy1" },
1486		.interrupt = { "csiphy1" },
1487		.csiphy = {
1488			.id = 1,
1489			.hw_ops = &csiphy_ops_3ph_1_0,
1490			.formats = &csiphy_formats_sdm845
1491		}
1492	},
1493	/* CSIPHY2 */
1494	{
1495		.regulators = { "vdda-phy", "vdda-pll" },
1496		.clock = { "csiphy2", "csiphy2_timer" },
1497		.clock_rate = { { 400000000 },
1498				{ 300000000 } },
1499		.reg = { "csiphy2" },
1500		.interrupt = { "csiphy2" },
1501		.csiphy = {
1502			.id = 2,
1503			.hw_ops = &csiphy_ops_3ph_1_0,
1504			.formats = &csiphy_formats_sdm845
1505		}
1506	},
1507	/* CSIPHY3 */
1508	{
1509		.regulators = { "vdda-phy", "vdda-pll" },
1510		.clock = { "csiphy3", "csiphy3_timer" },
1511		.clock_rate = { { 400000000 },
1512				{ 300000000 } },
1513		.reg = { "csiphy3" },
1514		.interrupt = { "csiphy3" },
1515		.csiphy = {
1516			.id = 3,
1517			.hw_ops = &csiphy_ops_3ph_1_0,
1518			.formats = &csiphy_formats_sdm845
1519		}
1520	},
1521	/* CSIPHY4 */
1522	{
1523		.regulators = { "vdda-phy", "vdda-pll" },
1524		.clock = { "csiphy4", "csiphy4_timer" },
1525		.clock_rate = { { 400000000 },
1526				{ 300000000 } },
1527		.reg = { "csiphy4" },
1528		.interrupt = { "csiphy4" },
1529		.csiphy = {
1530			.id = 4,
1531			.hw_ops = &csiphy_ops_3ph_1_0,
1532			.formats = &csiphy_formats_sdm845
1533		}
1534	},
1535	/* CSIPHY5 */
1536	{
1537		.regulators = { "vdda-phy", "vdda-pll" },
1538		.clock = { "csiphy5", "csiphy5_timer" },
1539		.clock_rate = { { 400000000 },
1540				{ 300000000 } },
1541		.reg = { "csiphy5" },
1542		.interrupt = { "csiphy5" },
1543		.csiphy = {
1544			.id = 5,
1545			.hw_ops = &csiphy_ops_3ph_1_0,
1546			.formats = &csiphy_formats_sdm845
1547		}
1548	}
1549};
1550
1551static const struct camss_subdev_resources csid_res_8250[] = {
1552	/* CSID0 */
1553	{
1554		.regulators = {},
1555		.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" },
1556		.clock_rate = { { 400000000 },
1557				{ 400000000 },
1558				{ 350000000, 475000000, 576000000, 720000000 },
1559				{ 100000000, 200000000, 300000000, 400000000 },
1560				{ 0 } },
1561		.reg = { "csid0" },
1562		.interrupt = { "csid0" },
1563		.csid = {
1564			.hw_ops = &csid_ops_gen2,
1565			.parent_dev_ops = &vfe_parent_dev_ops,
1566			.formats = &csid_formats_gen2
1567		}
1568	},
1569	/* CSID1 */
1570	{
1571		.regulators = {},
1572		.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" },
1573		.clock_rate = { { 400000000 },
1574				{ 400000000 },
1575				{ 350000000, 475000000, 576000000, 720000000 },
1576				{ 100000000, 200000000, 300000000, 400000000 },
1577				{ 0 } },
1578		.reg = { "csid1" },
1579		.interrupt = { "csid1" },
1580		.csid = {
1581			.hw_ops = &csid_ops_gen2,
1582			.parent_dev_ops = &vfe_parent_dev_ops,
1583			.formats = &csid_formats_gen2
1584		}
1585	},
1586	/* CSID2 */
1587	{
1588		.regulators = {},
1589		.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",  "vfe_lite_ahb" },
1590		.clock_rate = { { 400000000 },
1591				{ 400000000 },
1592				{ 400000000, 480000000 },
1593				{ 0 } },
1594		.reg = { "csid2" },
1595		.interrupt = { "csid2" },
1596		.csid = {
1597			.is_lite = true,
1598			.hw_ops = &csid_ops_gen2,
1599			.parent_dev_ops = &vfe_parent_dev_ops,
1600			.formats = &csid_formats_gen2
1601		}
1602	},
1603	/* CSID3 */
1604	{
1605		.regulators = {},
1606		.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",  "vfe_lite_ahb" },
1607		.clock_rate = { { 400000000 },
1608				{ 400000000 },
1609				{ 400000000, 480000000 },
1610				{ 0 } },
1611		.reg = { "csid3" },
1612		.interrupt = { "csid3" },
1613		.csid = {
1614			.is_lite = true,
1615			.hw_ops = &csid_ops_gen2,
1616			.parent_dev_ops = &vfe_parent_dev_ops,
1617			.formats = &csid_formats_gen2
1618		}
1619	}
1620};
1621
1622static const struct camss_subdev_resources vfe_res_8250[] = {
1623	/* VFE0 */
1624	{
1625		.regulators = {},
1626		.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
1627			   "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0",
1628			   "vfe0_axi", "cam_hf_axi" },
1629		.clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
1630				{ 19200000, 80000000 },
1631				{ 19200000 },
1632				{ 0 },
1633				{ 0 },
1634				{ 100000000, 200000000, 300000000, 400000000 },
1635				{ 350000000, 475000000, 576000000, 720000000 },
1636				{ 0 },
1637				{ 0 } },
1638		.reg = { "vfe0" },
1639		.interrupt = { "vfe0" },
1640		.vfe = {
1641			.line_num = 3,
1642			.has_pd = true,
1643			.pd_name = "ife0",
1644			.hw_ops = &vfe_ops_480,
1645			.formats_rdi = &vfe_formats_rdi_845,
1646			.formats_pix = &vfe_formats_pix_845
1647		}
1648	},
1649	/* VFE1 */
1650	{
1651		.regulators = {},
1652		.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
1653			   "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1",
1654			   "vfe1_axi", "cam_hf_axi" },
1655		.clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
1656				{ 19200000, 80000000 },
1657				{ 19200000 },
1658				{ 0 },
1659				{ 0 },
1660				{ 100000000, 200000000, 300000000, 400000000 },
1661				{ 350000000, 475000000, 576000000, 720000000 },
1662				{ 0 },
1663				{ 0 } },
1664		.reg = { "vfe1" },
1665		.interrupt = { "vfe1" },
1666		.vfe = {
1667			.line_num = 3,
1668			.has_pd = true,
1669			.pd_name = "ife1",
1670			.hw_ops = &vfe_ops_480,
1671			.formats_rdi = &vfe_formats_rdi_845,
1672			.formats_pix = &vfe_formats_pix_845
1673		}
1674	},
1675	/* VFE2 (lite) */
1676	{
1677		.regulators = {},
1678		.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
1679			   "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
1680			   "vfe_lite", "cam_hf_axi" },
1681		.clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
1682				{ 19200000, 80000000 },
1683				{ 19200000 },
1684				{ 0 },
1685				{ 0 },
1686				{ 0 },
1687				{ 400000000, 480000000 },
1688				{ 0 } },
1689		.reg = { "vfe_lite0" },
1690		.interrupt = { "vfe_lite0" },
1691		.vfe = {
1692			.is_lite = true,
1693			.line_num = 4,
1694			.hw_ops = &vfe_ops_480,
1695			.formats_rdi = &vfe_formats_rdi_845,
1696			.formats_pix = &vfe_formats_pix_845
1697		}
1698	},
1699	/* VFE3 (lite) */
1700	{
1701		.regulators = {},
1702		.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
1703			   "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
1704			   "vfe_lite", "cam_hf_axi" },
1705		.clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
1706				{ 19200000, 80000000 },
1707				{ 19200000 },
1708				{ 0 },
1709				{ 0 },
1710				{ 0 },
1711				{ 400000000, 480000000 },
1712				{ 0 } },
1713		.reg = { "vfe_lite1" },
1714		.interrupt = { "vfe_lite1" },
1715		.vfe = {
1716			.is_lite = true,
1717			.line_num = 4,
1718			.hw_ops = &vfe_ops_480,
1719			.formats_rdi = &vfe_formats_rdi_845,
1720			.formats_pix = &vfe_formats_pix_845
1721		}
1722	},
1723};
1724
1725static const struct resources_icc icc_res_sm8250[] = {
1726	{
1727		.name = "cam_ahb",
1728		.icc_bw_tbl.avg = 38400,
1729		.icc_bw_tbl.peak = 76800,
1730	},
1731	{
1732		.name = "cam_hf_0_mnoc",
1733		.icc_bw_tbl.avg = 2097152,
1734		.icc_bw_tbl.peak = 2097152,
1735	},
1736	{
1737		.name = "cam_sf_0_mnoc",
1738		.icc_bw_tbl.avg = 0,
1739		.icc_bw_tbl.peak = 2097152,
1740	},
1741	{
1742		.name = "cam_sf_icp_mnoc",
1743		.icc_bw_tbl.avg = 2097152,
1744		.icc_bw_tbl.peak = 2097152,
1745	},
1746};
1747
1748static const struct camss_subdev_resources csiphy_res_7280[] = {
1749	/* CSIPHY0 */
1750	{
1751		.regulators = { "vdda-phy", "vdda-pll" },
1752
1753		.clock = { "csiphy0", "csiphy0_timer" },
1754		.clock_rate = { { 300000000, 400000000 },
1755				{ 300000000 } },
1756		.reg = { "csiphy0" },
1757		.interrupt = { "csiphy0" },
1758		.csiphy = {
1759			.id = 0,
1760			.hw_ops = &csiphy_ops_3ph_1_0,
1761			.formats = &csiphy_formats_sdm845,
1762		}
1763	},
1764	/* CSIPHY1 */
1765	{
1766		.regulators = { "vdda-phy", "vdda-pll" },
1767
1768		.clock = { "csiphy1", "csiphy1_timer" },
1769		.clock_rate = { { 300000000, 400000000 },
1770				{ 300000000 } },
1771		.reg = { "csiphy1" },
1772		.interrupt = { "csiphy1" },
1773		.csiphy = {
1774			.id = 1,
1775			.hw_ops = &csiphy_ops_3ph_1_0,
1776			.formats = &csiphy_formats_sdm845,
1777		}
1778	},
1779	/* CSIPHY2 */
1780	{
1781		.regulators = { "vdda-phy", "vdda-pll" },
1782
1783		.clock = { "csiphy2", "csiphy2_timer" },
1784		.clock_rate = { { 300000000, 400000000 },
1785				{ 300000000 } },
1786		.reg = { "csiphy2" },
1787		.interrupt = { "csiphy2" },
1788		.csiphy = {
1789			.id = 2,
1790			.hw_ops = &csiphy_ops_3ph_1_0,
1791			.formats = &csiphy_formats_sdm845,
1792		}
1793	},
1794	/* CSIPHY3 */
1795	{
1796		.regulators = { "vdda-phy", "vdda-pll" },
1797
1798		.clock = { "csiphy3", "csiphy3_timer" },
1799		.clock_rate = { { 300000000, 400000000 },
1800				{ 300000000 } },
1801		.reg = { "csiphy3" },
1802		.interrupt = { "csiphy3" },
1803		.csiphy = {
1804			.id = 3,
1805			.hw_ops = &csiphy_ops_3ph_1_0,
1806			.formats = &csiphy_formats_sdm845,
1807		}
1808	},
1809	/* CSIPHY4 */
1810	{
1811		.regulators = { "vdda-phy", "vdda-pll" },
1812
1813		.clock = { "csiphy4", "csiphy4_timer" },
1814		.clock_rate = { { 300000000, 400000000 },
1815				{ 300000000 } },
1816		.reg = { "csiphy4" },
1817		.interrupt = { "csiphy4" },
1818		.csiphy = {
1819			.id = 4,
1820			.hw_ops = &csiphy_ops_3ph_1_0,
1821			.formats = &csiphy_formats_sdm845,
1822		}
1823	},
1824};
1825
1826static const struct camss_subdev_resources csid_res_7280[] = {
1827	/* CSID0 */
1828	{
1829		.regulators = {},
1830
1831		.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" },
1832		.clock_rate = { { 300000000, 400000000 },
1833				{ 0 },
1834				{ 380000000, 510000000, 637000000, 760000000 }
1835		},
1836
1837		.reg = { "csid0" },
1838		.interrupt = { "csid0" },
1839		.csid = {
1840			.is_lite = false,
1841			.hw_ops = &csid_ops_gen2,
1842			.parent_dev_ops = &vfe_parent_dev_ops,
1843			.formats = &csid_formats_gen2
1844		}
1845	},
1846	/* CSID1 */
1847	{
1848		.regulators = {},
1849
1850		.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" },
1851		.clock_rate = { { 300000000, 400000000 },
1852				{ 0 },
1853				{ 380000000, 510000000, 637000000, 760000000 }
1854		},
1855
1856		.reg = { "csid1" },
1857		.interrupt = { "csid1" },
1858		.csid = {
1859			.is_lite = false,
1860			.hw_ops = &csid_ops_gen2,
1861			.parent_dev_ops = &vfe_parent_dev_ops,
1862			.formats = &csid_formats_gen2
1863		}
1864	},
1865	/* CSID2 */
1866	{
1867		.regulators = {},
1868
1869		.clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" },
1870		.clock_rate = { { 300000000, 400000000 },
1871				{ 0 },
1872				{ 380000000, 510000000, 637000000, 760000000 }
1873		},
1874
1875		.reg = { "csid2" },
1876		.interrupt = { "csid2" },
1877		.csid = {
1878			.is_lite = false,
1879			.hw_ops = &csid_ops_gen2,
1880			.parent_dev_ops = &vfe_parent_dev_ops,
1881			.formats = &csid_formats_gen2
1882		}
1883	},
1884	/* CSID3 */
1885	{
1886		.regulators = {},
1887
1888		.clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
1889		.clock_rate = { { 300000000, 400000000 },
1890				{ 0 },
1891				{ 320000000, 400000000, 480000000, 600000000 }
1892		},
1893
1894		.reg = { "csid_lite0" },
1895		.interrupt = { "csid_lite0" },
1896		.csid = {
1897			.is_lite = true,
1898			.hw_ops = &csid_ops_gen2,
1899			.parent_dev_ops = &vfe_parent_dev_ops,
1900			.formats = &csid_formats_gen2
1901		}
1902	},
1903	/* CSID4 */
1904	{
1905		.regulators = {},
1906
1907		.clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
1908		.clock_rate = { { 300000000, 400000000 },
1909				{ 0 },
1910				{ 320000000, 400000000, 480000000, 600000000 }
1911		},
1912
1913		.reg = { "csid_lite1" },
1914		.interrupt = { "csid_lite1" },
1915		.csid = {
1916			.is_lite = true,
1917			.hw_ops = &csid_ops_gen2,
1918			.parent_dev_ops = &vfe_parent_dev_ops,
1919			.formats = &csid_formats_gen2
1920		}
1921	},
1922};
1923
1924static const struct camss_subdev_resources vfe_res_7280[] = {
1925	/* VFE0 */
1926	{
1927		.regulators = {},
1928
1929		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0",
1930			   "vfe0_axi", "gcc_axi_hf", "gcc_axi_sf" },
1931		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
1932				{ 80000000 },
1933				{ 0 },
1934				{ 380000000, 510000000, 637000000, 760000000 },
1935				{ 0 },
1936				{ 0 },
1937				{ 0 } },
1938
1939		.reg = { "vfe0" },
1940		.interrupt = { "vfe0" },
1941		.vfe = {
1942			.line_num = 3,
1943			.is_lite = false,
1944			.has_pd = true,
1945			.pd_name = "ife0",
1946			.hw_ops = &vfe_ops_170,
1947			.formats_rdi = &vfe_formats_rdi_845,
1948			.formats_pix = &vfe_formats_pix_845
1949		}
1950	},
1951	/* VFE1 */
1952	{
1953		.regulators = {},
1954
1955		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1",
1956			   "vfe1_axi", "gcc_axi_hf", "gcc_axi_sf" },
1957		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
1958				{ 80000000 },
1959				{ 0 },
1960				{ 380000000, 510000000, 637000000, 760000000 },
1961				{ 0 },
1962				{ 0 },
1963				{ 0 } },
1964
1965		.reg = { "vfe1" },
1966		.interrupt = { "vfe1" },
1967		.vfe = {
1968			.line_num = 3,
1969			.is_lite = false,
1970			.has_pd = true,
1971			.pd_name = "ife1",
1972			.hw_ops = &vfe_ops_170,
1973			.formats_rdi = &vfe_formats_rdi_845,
1974			.formats_pix = &vfe_formats_pix_845
1975		}
1976	},
1977	/* VFE2 */
1978	{
1979		.regulators = {},
1980
1981		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2",
1982			   "vfe2_axi", "gcc_axi_hf", "gcc_axi_sf" },
1983		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
1984				{ 80000000 },
1985				{ 0 },
1986				{ 380000000, 510000000, 637000000, 760000000 },
1987				{ 0 },
1988				{ 0 },
1989				{ 0 } },
1990
1991		.reg = { "vfe2" },
1992		.interrupt = { "vfe2" },
1993		.vfe = {
1994			.line_num = 3,
1995			.is_lite = false,
1996			.hw_ops = &vfe_ops_170,
1997			.has_pd = true,
1998			.pd_name = "ife2",
1999			.formats_rdi = &vfe_formats_rdi_845,
2000			.formats_pix = &vfe_formats_pix_845
2001		}
2002	},
2003	/* VFE3 (lite) */
2004	{
2005		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
2006			   "vfe_lite0", "gcc_axi_hf", "gcc_axi_sf" },
2007		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
2008				{ 80000000 },
2009				{ 0 },
2010				{ 320000000, 400000000, 480000000, 600000000 },
2011				{ 0 },
2012				{ 0 } },
2013
2014		.regulators = {},
2015		.reg = { "vfe_lite0" },
2016		.interrupt = { "vfe_lite0" },
2017		.vfe = {
2018			.line_num = 4,
2019			.is_lite = true,
2020			.hw_ops = &vfe_ops_170,
2021			.formats_rdi = &vfe_formats_rdi_845,
2022			.formats_pix = &vfe_formats_pix_845
2023		}
2024	},
2025	/* VFE4 (lite) */
2026	{
2027		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
2028			   "vfe_lite1", "gcc_axi_hf", "gcc_axi_sf" },
2029		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
2030				{ 80000000 },
2031				{ 0 },
2032				{ 320000000, 400000000, 480000000, 600000000 },
2033				{ 0 },
2034				{ 0 } },
2035
2036		.regulators = {},
2037		.reg = { "vfe_lite1" },
2038		.interrupt = { "vfe_lite1" },
2039		.vfe = {
2040			.line_num = 4,
2041			.is_lite = true,
2042			.hw_ops = &vfe_ops_170,
2043			.formats_rdi = &vfe_formats_rdi_845,
2044			.formats_pix = &vfe_formats_pix_845
2045		}
2046	},
2047};
2048
2049static const struct resources_icc icc_res_sc7280[] = {
2050	{
2051		.name = "ahb",
2052		.icc_bw_tbl.avg = 38400,
2053		.icc_bw_tbl.peak = 76800,
2054	},
2055	{
2056		.name = "hf_0",
2057		.icc_bw_tbl.avg = 2097152,
2058		.icc_bw_tbl.peak = 2097152,
2059	},
2060};
2061
2062static const struct camss_subdev_resources csiphy_res_sc8280xp[] = {
2063	/* CSIPHY0 */
2064	{
2065		.regulators = {},
2066		.clock = { "csiphy0", "csiphy0_timer" },
2067		.clock_rate = { { 400000000 },
2068				{ 300000000 } },
2069		.reg = { "csiphy0" },
2070		.interrupt = { "csiphy0" },
2071		.csiphy = {
2072			.id = 0,
2073			.hw_ops = &csiphy_ops_3ph_1_0,
2074			.formats = &csiphy_formats_sdm845
2075		}
2076	},
2077	/* CSIPHY1 */
2078	{
2079		.regulators = {},
2080		.clock = { "csiphy1", "csiphy1_timer" },
2081		.clock_rate = { { 400000000 },
2082				{ 300000000 } },
2083		.reg = { "csiphy1" },
2084		.interrupt = { "csiphy1" },
2085		.csiphy = {
2086			.id = 1,
2087			.hw_ops = &csiphy_ops_3ph_1_0,
2088			.formats = &csiphy_formats_sdm845
2089		}
2090	},
2091	/* CSIPHY2 */
2092	{
2093		.regulators = {},
2094		.clock = { "csiphy2", "csiphy2_timer" },
2095		.clock_rate = { { 400000000 },
2096				{ 300000000 } },
2097		.reg = { "csiphy2" },
2098		.interrupt = { "csiphy2" },
2099		.csiphy = {
2100			.id = 2,
2101			.hw_ops = &csiphy_ops_3ph_1_0,
2102			.formats = &csiphy_formats_sdm845
2103		}
2104	},
2105	/* CSIPHY3 */
2106	{
2107		.regulators = {},
2108		.clock = { "csiphy3", "csiphy3_timer" },
2109		.clock_rate = { { 400000000 },
2110				{ 300000000 } },
2111		.reg = { "csiphy3" },
2112		.interrupt = { "csiphy3" },
2113		.csiphy = {
2114			.id = 3,
2115			.hw_ops = &csiphy_ops_3ph_1_0,
2116			.formats = &csiphy_formats_sdm845
2117		}
2118	},
2119};
2120
2121static const struct camss_subdev_resources csid_res_sc8280xp[] = {
2122	/* CSID0 */
2123	{
2124		.regulators = { "vdda-phy", "vdda-pll" },
2125		.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" },
2126		.clock_rate = { { 400000000, 480000000, 600000000 },
2127				{ 0 },
2128				{ 0 },
2129				{ 0 } },
2130		.reg = { "csid0" },
2131		.interrupt = { "csid0" },
2132		.csid = {
2133			.hw_ops = &csid_ops_gen2,
2134			.parent_dev_ops = &vfe_parent_dev_ops,
2135			.formats = &csid_formats_gen2
2136		}
2137	},
2138	/* CSID1 */
2139	{
2140		.regulators = { "vdda-phy", "vdda-pll" },
2141		.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" },
2142		.clock_rate = { { 400000000, 480000000, 600000000 },
2143				{ 0 },
2144				{ 0 },
2145				{ 0 } },
2146		.reg = { "csid1" },
2147		.interrupt = { "csid1" },
2148		.csid = {
2149			.hw_ops = &csid_ops_gen2,
2150			.parent_dev_ops = &vfe_parent_dev_ops,
2151			.formats = &csid_formats_gen2
2152		}
2153	},
2154	/* CSID2 */
2155	{
2156		.regulators = { "vdda-phy", "vdda-pll" },
2157		.clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2", "vfe2_axi" },
2158		.clock_rate = { { 400000000, 480000000, 600000000 },
2159				{ 0 },
2160				{ 0 },
2161				{ 0 } },
2162		.reg = { "csid2" },
2163		.interrupt = { "csid2" },
2164		.csid = {
2165			.hw_ops = &csid_ops_gen2,
2166			.parent_dev_ops = &vfe_parent_dev_ops,
2167			.formats = &csid_formats_gen2
2168		}
2169	},
2170	/* CSID3 */
2171	{
2172		.regulators = { "vdda-phy", "vdda-pll" },
2173		.clock = { "vfe3_csid", "vfe3_cphy_rx", "vfe3", "vfe3_axi" },
2174		.clock_rate = { { 400000000, 480000000, 600000000 },
2175				{ 0 },
2176				{ 0 },
2177				{ 0 } },
2178		.reg = { "csid3" },
2179		.interrupt = { "csid3" },
2180		.csid = {
2181			.hw_ops = &csid_ops_gen2,
2182			.parent_dev_ops = &vfe_parent_dev_ops,
2183			.formats = &csid_formats_gen2
2184		}
2185	},
2186	/* CSID_LITE0 */
2187	{
2188		.regulators = { "vdda-phy", "vdda-pll" },
2189		.clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
2190		.clock_rate = { { 400000000, 480000000, 600000000 },
2191				{ 0 },
2192				{ 0 }, },
2193		.reg = { "csid0_lite" },
2194		.interrupt = { "csid0_lite" },
2195		.csid = {
2196			.is_lite = true,
2197			.hw_ops = &csid_ops_gen2,
2198			.parent_dev_ops = &vfe_parent_dev_ops,
2199			.formats = &csid_formats_gen2
2200		}
2201	},
2202	/* CSID_LITE1 */
2203	{
2204		.regulators = { "vdda-phy", "vdda-pll" },
2205		.clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
2206		.clock_rate = { { 400000000, 480000000, 600000000 },
2207				{ 0 },
2208				{ 0 }, },
2209		.reg = { "csid1_lite" },
2210		.interrupt = { "csid1_lite" },
2211		.csid = {
2212			.is_lite = true,
2213			.hw_ops = &csid_ops_gen2,
2214			.parent_dev_ops = &vfe_parent_dev_ops,
2215			.formats = &csid_formats_gen2
2216		}
2217	},
2218	/* CSID_LITE2 */
2219	{
2220		.regulators = { "vdda-phy", "vdda-pll" },
2221		.clock = { "vfe_lite2_csid", "vfe_lite2_cphy_rx", "vfe_lite2" },
2222		.clock_rate = { { 400000000, 480000000, 600000000 },
2223				{ 0 },
2224				{ 0 }, },
2225		.reg = { "csid2_lite" },
2226		.interrupt = { "csid2_lite" },
2227		.csid = {
2228			.is_lite = true,
2229			.hw_ops = &csid_ops_gen2,
2230			.parent_dev_ops = &vfe_parent_dev_ops,
2231			.formats = &csid_formats_gen2
2232		}
2233	},
2234	/* CSID_LITE3 */
2235	{
2236		.regulators = { "vdda-phy", "vdda-pll" },
2237		.clock = { "vfe_lite3_csid", "vfe_lite3_cphy_rx", "vfe_lite3" },
2238		.clock_rate = { { 400000000, 480000000, 600000000 },
2239				{ 0 },
2240				{ 0 }, },
2241		.reg = { "csid3_lite" },
2242		.interrupt = { "csid3_lite" },
2243		.csid = {
2244			.is_lite = true,
2245			.hw_ops = &csid_ops_gen2,
2246			.parent_dev_ops = &vfe_parent_dev_ops,
2247			.formats = &csid_formats_gen2
2248		}
2249	}
2250};
2251
2252static const struct camss_subdev_resources vfe_res_sc8280xp[] = {
2253	/* VFE0 */
2254	{
2255		.regulators = {},
2256		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe0", "vfe0_axi" },
2257		.clock_rate = { { 0 },
2258				{ 0 },
2259				{ 19200000, 80000000},
2260				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2261				{ 400000000, 558000000, 637000000, 760000000 },
2262				{ 0 }, },
2263		.reg = { "vfe0" },
2264		.interrupt = { "vfe0" },
2265		.vfe = {
2266			.line_num = 4,
2267			.pd_name = "ife0",
2268			.hw_ops = &vfe_ops_170,
2269			.formats_rdi = &vfe_formats_rdi_845,
2270			.formats_pix = &vfe_formats_pix_845
2271		}
2272	},
2273	/* VFE1 */
2274	{
2275		.regulators = {},
2276		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe1", "vfe1_axi" },
2277		.clock_rate = { { 0 },
2278				{ 0 },
2279				{ 19200000, 80000000},
2280				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2281				{ 400000000, 558000000, 637000000, 760000000 },
2282				{ 0 }, },
2283		.reg = { "vfe1" },
2284		.interrupt = { "vfe1" },
2285		.vfe = {
2286			.line_num = 4,
2287			.pd_name = "ife1",
2288			.hw_ops = &vfe_ops_170,
2289			.formats_rdi = &vfe_formats_rdi_845,
2290			.formats_pix = &vfe_formats_pix_845
2291		}
2292	},
2293	/* VFE2 */
2294	{
2295		.regulators = {},
2296		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe2", "vfe2_axi" },
2297		.clock_rate = { { 0 },
2298				{ 0 },
2299				{ 19200000, 80000000},
2300				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2301				{ 400000000, 558000000, 637000000, 760000000 },
2302				{ 0 }, },
2303		.reg = { "vfe2" },
2304		.interrupt = { "vfe2" },
2305		.vfe = {
2306			.line_num = 4,
2307			.pd_name = "ife2",
2308			.hw_ops = &vfe_ops_170,
2309			.formats_rdi = &vfe_formats_rdi_845,
2310			.formats_pix = &vfe_formats_pix_845
2311		}
2312	},
2313	/* VFE3 */
2314	{
2315		.regulators = {},
2316		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe3", "vfe3_axi" },
2317		.clock_rate = { { 0 },
2318				{ 0 },
2319				{ 19200000, 80000000},
2320				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2321				{ 400000000, 558000000, 637000000, 760000000 },
2322				{ 0 }, },
2323		.reg = { "vfe3" },
2324		.interrupt = { "vfe3" },
2325		.vfe = {
2326			.line_num = 4,
2327			.pd_name = "ife3",
2328			.hw_ops = &vfe_ops_170,
2329			.formats_rdi = &vfe_formats_rdi_845,
2330			.formats_pix = &vfe_formats_pix_845
2331		}
2332	},
2333	/* VFE_LITE_0 */
2334	{
2335		.regulators = {},
2336		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite0" },
2337		.clock_rate = { { 0 },
2338				{ 0 },
2339				{ 19200000, 80000000},
2340				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2341				{ 320000000, 400000000, 480000000, 600000000 }, },
2342		.reg = { "vfe_lite0" },
2343		.interrupt = { "vfe_lite0" },
2344		.vfe = {
2345			.is_lite = true,
2346			.line_num = 4,
2347			.hw_ops = &vfe_ops_170,
2348			.formats_rdi = &vfe_formats_rdi_845,
2349			.formats_pix = &vfe_formats_pix_845
2350		}
2351	},
2352	/* VFE_LITE_1 */
2353	{
2354		.regulators = {},
2355		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite1" },
2356		.clock_rate = { { 0 },
2357				{ 0 },
2358				{ 19200000, 80000000},
2359				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2360				{ 320000000, 400000000, 480000000, 600000000 }, },
2361		.reg = { "vfe_lite1" },
2362		.interrupt = { "vfe_lite1" },
2363		.vfe = {
2364			.is_lite = true,
2365			.line_num = 4,
2366			.hw_ops = &vfe_ops_170,
2367			.formats_rdi = &vfe_formats_rdi_845,
2368			.formats_pix = &vfe_formats_pix_845
2369		}
2370	},
2371	/* VFE_LITE_2 */
2372	{
2373		.regulators = {},
2374		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite2" },
2375		.clock_rate = { { 0 },
2376				{ 0 },
2377				{ 19200000, 80000000},
2378				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2379				{ 320000000, 400000000, 480000000, 600000000, }, },
2380		.reg = { "vfe_lite2" },
2381		.interrupt = { "vfe_lite2" },
2382		.vfe = {
2383			.is_lite = true,
2384			.line_num = 4,
2385			.hw_ops = &vfe_ops_170,
2386			.formats_rdi = &vfe_formats_rdi_845,
2387			.formats_pix = &vfe_formats_pix_845
2388		}
2389	},
2390	/* VFE_LITE_3 */
2391	{
2392		.regulators = {},
2393		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite3" },
2394		.clock_rate = { { 0 },
2395				{ 0 },
2396				{ 19200000, 80000000},
2397				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
2398				{ 320000000, 400000000, 480000000, 600000000 }, },
2399		.reg = { "vfe_lite3" },
2400		.interrupt = { "vfe_lite3" },
2401		.vfe = {
2402			.is_lite = true,
2403			.line_num = 4,
2404			.hw_ops = &vfe_ops_170,
2405			.formats_rdi = &vfe_formats_rdi_845,
2406			.formats_pix = &vfe_formats_pix_845
2407		}
2408	},
2409};
2410
2411static const struct resources_icc icc_res_sc8280xp[] = {
2412	{
2413		.name = "cam_ahb",
2414		.icc_bw_tbl.avg = 150000,
2415		.icc_bw_tbl.peak = 300000,
2416	},
2417	{
2418		.name = "cam_hf_mnoc",
2419		.icc_bw_tbl.avg = 2097152,
2420		.icc_bw_tbl.peak = 2097152,
2421	},
2422	{
2423		.name = "cam_sf_mnoc",
2424		.icc_bw_tbl.avg = 2097152,
2425		.icc_bw_tbl.peak = 2097152,
2426	},
2427	{
2428		.name = "cam_sf_icp_mnoc",
2429		.icc_bw_tbl.avg = 2097152,
2430		.icc_bw_tbl.peak = 2097152,
2431	},
2432};
2433
2434static const struct camss_subdev_resources csiphy_res_8550[] = {
2435	/* CSIPHY0 */
2436	{
2437		.regulators = { "vdda-phy", "vdda-pll" },
2438		.clock = { "csiphy0", "csiphy0_timer" },
2439		.clock_rate = { { 400000000, 480000000 },
2440				{ 400000000 } },
2441		.reg = { "csiphy0" },
2442		.interrupt = { "csiphy0" },
2443		.csiphy = {
2444			.id = 0,
2445			.hw_ops = &csiphy_ops_3ph_1_0,
2446			.formats = &csiphy_formats_sdm845
2447		}
2448	},
2449	/* CSIPHY1 */
2450	{
2451		.regulators = { "vdda-phy", "vdda-pll" },
2452		.clock = { "csiphy1", "csiphy1_timer" },
2453		.clock_rate = { { 400000000, 480000000 },
2454				{ 400000000 } },
2455		.reg = { "csiphy1" },
2456		.interrupt = { "csiphy1" },
2457		.csiphy = {
2458			.id = 1,
2459			.hw_ops = &csiphy_ops_3ph_1_0,
2460			.formats = &csiphy_formats_sdm845
2461		}
2462	},
2463	/* CSIPHY2 */
2464	{
2465		.regulators = { "vdda-phy", "vdda-pll" },
2466		.clock = { "csiphy2", "csiphy2_timer" },
2467		.clock_rate = { { 400000000, 480000000 },
2468				{ 400000000 } },
2469		.reg = { "csiphy2" },
2470		.interrupt = { "csiphy2" },
2471		.csiphy = {
2472			.id = 2,
2473			.hw_ops = &csiphy_ops_3ph_1_0,
2474			.formats = &csiphy_formats_sdm845
2475		}
2476	},
2477	/* CSIPHY3 */
2478	{
2479		.regulators = { "vdda-phy", "vdda-pll" },
2480		.clock = { "csiphy3", "csiphy3_timer" },
2481		.clock_rate = { { 400000000, 480000000 },
2482				{ 400000000 } },
2483		.reg = { "csiphy3" },
2484		.interrupt = { "csiphy3" },
2485		.csiphy = {
2486			.id = 3,
2487			.hw_ops = &csiphy_ops_3ph_1_0,
2488			.formats = &csiphy_formats_sdm845
2489		}
2490	},
2491	/* CSIPHY4 */
2492	{
2493		.regulators = { "vdda-phy", "vdda-pll" },
2494		.clock = { "csiphy4", "csiphy4_timer" },
2495		.clock_rate = { { 400000000, 480000000 },
2496				{ 400000000 } },
2497		.reg = { "csiphy4" },
2498		.interrupt = { "csiphy4" },
2499		.csiphy = {
2500			.id = 4,
2501			.hw_ops = &csiphy_ops_3ph_1_0,
2502			.formats = &csiphy_formats_sdm845
2503		}
2504	},
2505	/* CSIPHY5 */
2506	{
2507		.regulators = { "vdda-phy", "vdda-pll" },
2508		.clock = { "csiphy5", "csiphy5_timer" },
2509		.clock_rate = { { 400000000, 480000000 },
2510				{ 400000000 } },
2511		.reg = { "csiphy5" },
2512		.interrupt = { "csiphy5" },
2513		.csiphy = {
2514			.id = 5,
2515			.hw_ops = &csiphy_ops_3ph_1_0,
2516			.formats = &csiphy_formats_sdm845
2517		}
2518	},
2519	/* CSIPHY6 */
2520	{
2521		.regulators = { "vdda-phy", "vdda-pll" },
2522		.clock = { "csiphy6", "csiphy6_timer" },
2523		.clock_rate = { { 400000000, 480000000 },
2524				{ 400000000 } },
2525		.reg = { "csiphy6" },
2526		.interrupt = { "csiphy6" },
2527		.csiphy = {
2528			.id = 6,
2529			.hw_ops = &csiphy_ops_3ph_1_0,
2530			.formats = &csiphy_formats_sdm845
2531		}
2532	},
2533	/* CSIPHY7 */
2534	{
2535		.regulators = { "vdda-phy", "vdda-pll" },
2536		.clock = { "csiphy7", "csiphy7_timer" },
2537		.clock_rate = { { 400000000, 480000000 },
2538				{ 400000000 } },
2539		.reg = { "csiphy7" },
2540		.interrupt = { "csiphy7" },
2541		.csiphy = {
2542			.id = 7,
2543			.hw_ops = &csiphy_ops_3ph_1_0,
2544			.formats = &csiphy_formats_sdm845
2545		}
2546	}
2547};
2548
2549static const struct resources_wrapper csid_wrapper_res_sm8550 = {
2550	.reg = "csid_wrapper",
2551};
2552
2553static const struct camss_subdev_resources csid_res_8550[] = {
2554	/* CSID0 */
2555	{
2556		.regulators = {},
2557		.clock = { "csid", "csiphy_rx" },
2558		.clock_rate = { { 400000000, 480000000 },
2559				{ 400000000, 480000000 } },
2560		.reg = { "csid0" },
2561		.interrupt = { "csid0" },
2562		.csid = {
2563			.is_lite = false,
2564			.parent_dev_ops = &vfe_parent_dev_ops,
2565			.hw_ops = &csid_ops_gen3,
2566			.formats = &csid_formats_gen2
2567		}
2568	},
2569	/* CSID1 */
2570	{
2571		.regulators = {},
2572		.clock = { "csid", "csiphy_rx" },
2573		.clock_rate = { { 400000000, 480000000 },
2574				{ 400000000, 480000000 } },
2575		.reg = { "csid1" },
2576		.interrupt = { "csid1" },
2577		.csid = {
2578			.is_lite = false,
2579			.parent_dev_ops = &vfe_parent_dev_ops,
2580			.hw_ops = &csid_ops_gen3,
2581			.formats = &csid_formats_gen2
2582		}
2583	},
2584	/* CSID2 */
2585	{
2586		.regulators = {},
2587		.clock = { "csid", "csiphy_rx" },
2588		.clock_rate = { { 400000000, 480000000 },
2589				{ 400000000, 480000000 } },
2590		.reg = { "csid2" },
2591		.interrupt = { "csid2" },
2592		.csid = {
2593			.is_lite = false,
2594			.parent_dev_ops = &vfe_parent_dev_ops,
2595			.hw_ops = &csid_ops_gen3,
2596			.formats = &csid_formats_gen2
2597		}
2598	},
2599	/* CSID3 */
2600	{
2601		.regulators = {},
2602		.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
2603		.clock_rate = { { 400000000, 480000000 },
2604				{ 400000000, 480000000 } },
2605		.reg = { "csid_lite0" },
2606		.interrupt = { "csid_lite0" },
2607		.csid = {
2608			.is_lite = true,
2609			.parent_dev_ops = &vfe_parent_dev_ops,
2610			.hw_ops = &csid_ops_gen3,
2611			.formats = &csid_formats_gen2
2612		}
2613	},
2614	/* CSID4 */
2615	{
2616		.regulators = {},
2617		.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
2618		.clock_rate = { { 400000000, 480000000 },
2619				{ 400000000, 480000000 } },
2620		.reg = { "csid_lite1" },
2621		.interrupt = { "csid_lite1" },
2622		.csid = {
2623			.is_lite = true,
2624			.parent_dev_ops = &vfe_parent_dev_ops,
2625			.hw_ops = &csid_ops_gen3,
2626			.formats = &csid_formats_gen2
2627		}
2628	}
2629};
2630
2631static const struct camss_subdev_resources vfe_res_8550[] = {
2632	/* VFE0 */
2633	{
2634		.regulators = {},
2635		.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe0_fast_ahb",
2636			   "vfe0", "cpas_vfe0", "camnoc_axi" },
2637		.clock_rate = { { 0 },
2638				{ 80000000 },
2639				{ 300000000, 400000000 },
2640				{ 300000000, 400000000 },
2641				{ 466000000, 594000000, 675000000, 785000000 },
2642				{ 300000000, 400000000 },
2643				{ 300000000, 400000000 } },
2644		.reg = { "vfe0" },
2645		.interrupt = { "vfe0" },
2646		.vfe = {
2647			.line_num = 3,
2648			.is_lite = false,
2649			.has_pd = true,
2650			.pd_name = "ife0",
2651			.hw_ops = &vfe_ops_gen3,
2652			.formats_rdi = &vfe_formats_rdi_845,
2653			.formats_pix = &vfe_formats_pix_845
2654		}
2655	},
2656	/* VFE1 */
2657	{
2658		.regulators = {},
2659		.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe1_fast_ahb",
2660			   "vfe1", "cpas_vfe1", "camnoc_axi" },
2661		.clock_rate = {	{ 0 },
2662				{ 80000000 },
2663				{ 300000000, 400000000 },
2664				{ 300000000, 400000000 },
2665				{ 466000000, 594000000, 675000000, 785000000 },
2666				{ 300000000, 400000000 },
2667				{ 300000000, 400000000 } },
2668		.reg = { "vfe1" },
2669		.interrupt = { "vfe1" },
2670		.vfe = {
2671			.line_num = 3,
2672			.is_lite = false,
2673			.has_pd = true,
2674			.pd_name = "ife1",
2675			.hw_ops = &vfe_ops_gen3,
2676			.formats_rdi = &vfe_formats_rdi_845,
2677			.formats_pix = &vfe_formats_pix_845
2678		}
2679	},
2680	/* VFE2 */
2681	{
2682		.regulators = {},
2683		.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe2_fast_ahb",
2684			   "vfe2", "cpas_vfe2", "camnoc_axi" },
2685		.clock_rate = {	{ 0 },
2686				{ 80000000 },
2687				{ 300000000, 400000000 },
2688				{ 300000000, 400000000 },
2689				{ 466000000, 594000000, 675000000, 785000000 },
2690				{ 300000000, 400000000 },
2691				{ 300000000, 400000000 } },
2692		.reg = { "vfe2" },
2693		.interrupt = { "vfe2" },
2694		.vfe = {
2695			.line_num = 3,
2696			.is_lite = false,
2697			.has_pd = true,
2698			.pd_name = "ife2",
2699			.hw_ops = &vfe_ops_gen3,
2700			.formats_rdi = &vfe_formats_rdi_845,
2701			.formats_pix = &vfe_formats_pix_845
2702		}
2703	},
2704	/* VFE3 lite */
2705	{
2706		.regulators = {},
2707		.clock = { "gcc_axi_hf", "cpas_ahb", "vfe_lite_ahb",
2708			   "vfe_lite", "cpas_ife_lite", "camnoc_axi" },
2709		.clock_rate = {	{ 0 },
2710				{ 80000000 },
2711				{ 300000000, 400000000 },
2712				{ 400000000, 480000000 },
2713				{ 300000000, 400000000 },
2714				{ 300000000, 400000000 } },
2715		.reg = { "vfe_lite0" },
2716		.interrupt = { "vfe_lite0" },
2717		.vfe = {
2718			.line_num = 4,
2719			.is_lite = true,
2720			.hw_ops = &vfe_ops_gen3,
2721			.formats_rdi = &vfe_formats_rdi_845,
2722			.formats_pix = &vfe_formats_pix_845
2723		}
2724	},
2725	/* VFE4 lite */
2726	{
2727		.regulators = {},
2728		.clock = { "gcc_axi_hf", "cpas_ahb", "vfe_lite_ahb",
2729			   "vfe_lite", "cpas_ife_lite", "camnoc_axi" },
2730		.clock_rate = {	{ 0 },
2731				{ 80000000 },
2732				{ 300000000, 400000000 },
2733				{ 400000000, 480000000 },
2734				{ 300000000, 400000000 },
2735				{ 300000000, 400000000 } },
2736		.reg = { "vfe_lite1" },
2737		.interrupt = { "vfe_lite1" },
2738		.vfe = {
2739			.line_num = 4,
2740			.is_lite = true,
2741			.hw_ops = &vfe_ops_gen3,
2742			.formats_rdi = &vfe_formats_rdi_845,
2743			.formats_pix = &vfe_formats_pix_845
2744		}
2745	},
2746};
2747
2748static const struct resources_icc icc_res_sm8550[] = {
2749	{
2750		.name = "ahb",
2751		.icc_bw_tbl.avg = 2097152,
2752		.icc_bw_tbl.peak = 2097152,
2753	},
2754	{
2755		.name = "hf_0_mnoc",
2756		.icc_bw_tbl.avg = 2097152,
2757		.icc_bw_tbl.peak = 2097152,
2758	},
2759};
2760
2761static const struct camss_subdev_resources csiphy_res_sm8650[] = {
2762	/* CSIPHY0 */
2763	{
2764		.regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
2765		.clock = { "csiphy0", "csiphy0_timer" },
2766		.clock_rate = {	{ 400000000 },
2767				{ 400000000 } },
2768		.reg = { "csiphy0" },
2769		.interrupt = { "csiphy0" },
2770		.csiphy = {
2771			.id = 0,
2772			.hw_ops = &csiphy_ops_3ph_1_0,
2773			.formats = &csiphy_formats_sdm845,
2774		},
2775	},
2776	/* CSIPHY1 */
2777	{
2778		.regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
2779		.clock = { "csiphy1", "csiphy1_timer" },
2780		.clock_rate = { { 400000000 },
2781				{ 400000000 } },
2782		.reg = { "csiphy1" },
2783		.interrupt = { "csiphy1" },
2784		.csiphy = {
2785			.id = 1,
2786			.hw_ops = &csiphy_ops_3ph_1_0,
2787			.formats = &csiphy_formats_sdm845,
2788		},
2789	},
2790	/* CSIPHY2 */
2791	{
2792		.regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
2793		.clock = { "csiphy2", "csiphy2_timer" },
2794		.clock_rate = { { 400000000 },
2795				{ 400000000 } },
2796		.reg = { "csiphy2" },
2797		.interrupt = { "csiphy2" },
2798		.csiphy = {
2799			.id = 2,
2800			.hw_ops = &csiphy_ops_3ph_1_0,
2801			.formats = &csiphy_formats_sdm845,
2802		},
2803	},
2804	/* CSIPHY3 */
2805	{
2806		.regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
2807		.clock = { "csiphy3", "csiphy3_timer" },
2808		.clock_rate = { { 400000000 },
2809				{ 400000000 } },
2810		.reg = { "csiphy3" },
2811		.interrupt = { "csiphy3" },
2812		.csiphy = {
2813			.id = 3,
2814			.hw_ops = &csiphy_ops_3ph_1_0,
2815			.formats = &csiphy_formats_sdm845,
2816		},
2817	},
2818	/* CSIPHY4 */
2819	{
2820		.regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
2821		.clock = { "csiphy4", "csiphy4_timer" },
2822		.clock_rate = { { 400000000 },
2823				{ 400000000 } },
2824		.reg = { "csiphy4" },
2825		.interrupt = { "csiphy4" },
2826		.csiphy = {
2827			.id = 4,
2828			.hw_ops = &csiphy_ops_3ph_1_0,
2829			.formats = &csiphy_formats_sdm845,
2830		},
2831	},
2832	/* CSIPHY5 */
2833	{
2834		.regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
2835		.clock = { "csiphy5", "csiphy5_timer" },
2836		.clock_rate = { { 400000000 },
2837				{ 400000000 } },
2838		.reg = { "csiphy5" },
2839		.interrupt = { "csiphy5" },
2840		.csiphy = {
2841			.id = 5,
2842			.hw_ops = &csiphy_ops_3ph_1_0,
2843			.formats = &csiphy_formats_sdm845,
2844		},
2845	},
2846};
2847
2848static const struct camss_subdev_resources csid_res_sm8650[] = {
2849	/* CSID0 */
2850	{
2851		.regulators = { },
2852		.clock = { "csid", "csiphy_rx" },
2853		.clock_rate = { { 400000000 },
2854				{ 400000000, 480000000 } },
2855		.reg = { "csid0" },
2856		.interrupt = { "csid0" },
2857		.csid = {
2858			.parent_dev_ops = &vfe_parent_dev_ops,
2859			.hw_ops = &csid_ops_gen3,
2860			.formats = &csid_formats_gen2,
2861		},
2862	},
2863	/* CSID1 */
2864	{
2865		.regulators = { },
2866		.clock = { "csid", "csiphy_rx" },
2867		.clock_rate = { { 400000000 },
2868				{ 400000000, 480000000 } },
2869		.reg = { "csid1" },
2870		.interrupt = { "csid1" },
2871		.csid = {
2872			.parent_dev_ops = &vfe_parent_dev_ops,
2873			.hw_ops = &csid_ops_gen3,
2874			.formats = &csid_formats_gen2,
2875		},
2876	},
2877	/* CSID2 */
2878	{
2879		.regulators = { },
2880		.clock = { "csid", "csiphy_rx" },
2881		.clock_rate = { { 400000000 },
2882				{ 400000000, 480000000 } },
2883		.reg = { "csid2" },
2884		.interrupt = { "csid2" },
2885		.csid = {
2886			.parent_dev_ops = &vfe_parent_dev_ops,
2887			.hw_ops = &csid_ops_gen3,
2888			.formats = &csid_formats_gen2,
2889		},
2890	},
2891	/* CSID3 lite */
2892	{
2893		.regulators = { },
2894		.clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
2895		.clock_rate = { { 0 },
2896				{ 400000000, 480000000 },
2897				{ 0 } },
2898		.reg = { "csid_lite0" },
2899		.interrupt = { "csid_lite0" },
2900		.csid = {
2901			.is_lite = true,
2902			.parent_dev_ops = &vfe_parent_dev_ops,
2903			.hw_ops = &csid_ops_gen3,
2904			.formats = &csid_formats_gen2,
2905		},
2906	},
2907	/* CSID4 lite */
2908	{
2909		.regulators = { },
2910		.clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
2911		.clock_rate = { { 0 },
2912				{ 400000000, 480000000 },
2913				{ 0 } },
2914		.reg = { "csid_lite1" },
2915		.interrupt = { "csid_lite1" },
2916		.csid = {
2917			.is_lite = true,
2918			.parent_dev_ops = &vfe_parent_dev_ops,
2919			.hw_ops = &csid_ops_gen3,
2920			.formats = &csid_formats_gen2,
2921		},
2922	},
2923};
2924
2925static const struct camss_subdev_resources vfe_res_sm8650[] = {
2926	/* VFE0 */
2927	{
2928		.regulators = { },
2929		.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
2930			   "camnoc_axi", "vfe0_fast_ahb", "vfe0", "cpas_vfe0",
2931			   "qdss_debug_xo",
2932		},
2933		.clock_rate = {	{ 0 },
2934				{ 80000000 },
2935				{ 300000000, 400000000 },
2936				{ 300000000, 400000000 },
2937				{ 0 },
2938				{ 466000000, 594000000, 675000000, 785000000 },
2939				{ 0 },
2940				{ 0 },
2941		},
2942		.reg = { "vfe0" },
2943		.interrupt = { "vfe0" },
2944		.vfe = {
2945			.line_num = 3,
2946			.has_pd = true,
2947			.pd_name = "ife0",
2948			.hw_ops = &vfe_ops_gen3,
2949			.formats_rdi = &vfe_formats_rdi_845,
2950			.formats_pix = &vfe_formats_pix_845
2951		},
2952	},
2953	/* VFE1 */
2954	{
2955		.regulators = { },
2956		.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
2957			   "camnoc_axi", "vfe1_fast_ahb", "vfe1", "cpas_vfe1",
2958			   "qdss_debug_xo",
2959		},
2960		.clock_rate = {	{ 0 },
2961				{ 80000000 },
2962				{ 300000000, 400000000 },
2963				{ 300000000, 400000000 },
2964				{ 0 },
2965				{ 466000000, 594000000, 675000000, 785000000 },
2966				{ 0 },
2967				{ 0 },
2968		},
2969		.reg = { "vfe1" },
2970		.interrupt = { "vfe1" },
2971		.vfe = {
2972			.line_num = 3,
2973			.has_pd = true,
2974			.pd_name = "ife1",
2975			.hw_ops = &vfe_ops_gen3,
2976			.formats_rdi = &vfe_formats_rdi_845,
2977			.formats_pix = &vfe_formats_pix_845
2978		},
2979	},
2980	/* VFE2 */
2981	{
2982		.regulators = { },
2983		.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
2984			   "camnoc_axi", "vfe2_fast_ahb", "vfe2", "cpas_vfe2",
2985			   "qdss_debug_xo",
2986		},
2987		.clock_rate = { { 0 },
2988				{ 80000000 },
2989				{ 300000000, 400000000 },
2990				{ 300000000, 400000000 },
2991				{ 0 },
2992				{ 466000000, 594000000, 675000000, 785000000 },
2993				{ 0 },
2994				{ 0 },
2995		},
2996		.reg = { "vfe2" },
2997		.interrupt = { "vfe2" },
2998		.vfe = {
2999			.line_num = 3,
3000			.has_pd = true,
3001			.pd_name = "ife2",
3002			.hw_ops = &vfe_ops_gen3,
3003			.formats_rdi = &vfe_formats_rdi_845,
3004			.formats_pix = &vfe_formats_pix_845
3005		},
3006	},
3007	/* VFE3 lite */
3008	{
3009		.regulators = { },
3010		.clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
3011			   "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
3012			   "qdss_debug_xo",
3013		},
3014		.clock_rate = { { 0 },
3015				{ 80000000 },
3016				{ 300000000, 400000000 },
3017				{ 0 },
3018				{ 400000000, 480000000 },
3019				{ 0 },
3020				{ 0 },
3021		},
3022		.reg = { "vfe_lite0" },
3023		.interrupt = { "vfe_lite0" },
3024		.vfe = {
3025			.line_num = 4,
3026			.is_lite = true,
3027			.hw_ops = &vfe_ops_gen3,
3028			.formats_rdi = &vfe_formats_rdi_845,
3029			.formats_pix = &vfe_formats_pix_845
3030		},
3031	},
3032	/* VFE4 lite */
3033	{
3034		.regulators = { },
3035		.clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
3036			   "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
3037			   "qdss_debug_xo",
3038		},
3039		.clock_rate = {	{ 0 },
3040				{ 80000000 },
3041				{ 300000000, 400000000 },
3042				{ 0 },
3043				{ 400000000, 480000000 },
3044				{ 0 },
3045				{ 0 },
3046		},
3047		.reg = { "vfe_lite1" },
3048		.interrupt = { "vfe_lite1" },
3049		.vfe = {
3050			.line_num = 4,
3051			.is_lite = true,
3052			.hw_ops = &vfe_ops_gen3,
3053			.formats_rdi = &vfe_formats_rdi_845,
3054			.formats_pix = &vfe_formats_pix_845
3055		},
3056	},
3057};
3058
3059static const struct resources_icc icc_res_sm8650[] = {
3060	{
3061		.name = "ahb",
3062		.icc_bw_tbl.avg = 38400,
3063		.icc_bw_tbl.peak = 76800,
3064	},
3065	{
3066		.name = "hf_mnoc",
3067		.icc_bw_tbl.avg = 2097152,
3068		.icc_bw_tbl.peak = 2097152,
3069	},
3070};
3071
3072static const struct camss_subdev_resources csiphy_res_8300[] = {
3073	/* CSIPHY0 */
3074	{
3075		.regulators = { "vdda-phy", "vdda-pll" },
3076
3077		.clock = { "csiphy_rx", "csiphy0", "csiphy0_timer" },
3078		.clock_rate = {
3079			{ 400000000 },
3080			{ 0 },
3081			{ 400000000 },
3082		},
3083		.reg = { "csiphy0" },
3084		.interrupt = { "csiphy0" },
3085		.csiphy = {
3086			.id = 0,
3087			.hw_ops = &csiphy_ops_3ph_1_0,
3088			.formats = &csiphy_formats_sdm845,
3089		}
3090	},
3091	/* CSIPHY1 */
3092	{
3093		.regulators = { "vdda-phy", "vdda-pll" },
3094
3095		.clock = { "csiphy_rx", "csiphy1", "csiphy1_timer" },
3096		.clock_rate = {
3097			{ 400000000 },
3098			{ 0 },
3099			{ 400000000 },
3100		},
3101		.reg = { "csiphy1" },
3102		.interrupt = { "csiphy1" },
3103		.csiphy = {
3104			.id = 1,
3105			.hw_ops = &csiphy_ops_3ph_1_0,
3106			.formats = &csiphy_formats_sdm845,
3107		}
3108	},
3109	/* CSIPHY2 */
3110	{
3111		.regulators = { "vdda-phy", "vdda-pll" },
3112
3113		.clock = { "csiphy_rx", "csiphy2", "csiphy2_timer" },
3114		.clock_rate = {
3115			{ 400000000 },
3116			{ 0 },
3117			{ 400000000 },
3118		},
3119		.reg = { "csiphy2" },
3120		.interrupt = { "csiphy2" },
3121		.csiphy = {
3122			.id = 2,
3123			.hw_ops = &csiphy_ops_3ph_1_0,
3124			.formats = &csiphy_formats_sdm845,
3125		}
3126	},
3127};
3128
3129static const struct camss_subdev_resources csiphy_res_8775p[] = {
3130	/* CSIPHY0 */
3131	{
3132		.regulators = { "vdda-phy", "vdda-pll" },
3133		.clock = { "csiphy_rx", "csiphy0", "csiphy0_timer"},
3134		.clock_rate = {
3135			{ 400000000 },
3136			{ 0 },
3137			{ 400000000 },
3138		},
3139		.reg = { "csiphy0" },
3140		.interrupt = { "csiphy0" },
3141		.csiphy = {
3142			.id = 0,
3143			.hw_ops = &csiphy_ops_3ph_1_0,
3144			.formats = &csiphy_formats_sdm845
3145		}
3146	},
3147	/* CSIPHY1 */
3148	{
3149		.regulators = { "vdda-phy", "vdda-pll" },
3150		.clock = { "csiphy_rx", "csiphy1", "csiphy1_timer"},
3151		.clock_rate = {
3152			{ 400000000 },
3153			{ 0 },
3154			{ 400000000 },
3155		},
3156		.reg = { "csiphy1" },
3157		.interrupt = { "csiphy1" },
3158		.csiphy = {
3159			.id = 1,
3160			.hw_ops = &csiphy_ops_3ph_1_0,
3161			.formats = &csiphy_formats_sdm845
3162		}
3163	},
3164	/* CSIPHY2 */
3165	{
3166		.regulators = { "vdda-phy", "vdda-pll" },
3167		.clock = { "csiphy_rx", "csiphy2", "csiphy2_timer"},
3168		.clock_rate = {
3169			{ 400000000 },
3170			{ 0 },
3171			{ 400000000 },
3172		},
3173		.reg = { "csiphy2" },
3174		.interrupt = { "csiphy2" },
3175		.csiphy = {
3176			.id = 2,
3177			.hw_ops = &csiphy_ops_3ph_1_0,
3178			.formats = &csiphy_formats_sdm845
3179		}
3180	},
3181	/* CSIPHY3 */
3182	{
3183		.regulators = { "vdda-phy", "vdda-pll" },
3184		.clock = { "csiphy_rx", "csiphy3", "csiphy3_timer"},
3185		.clock_rate = {
3186			{ 400000000 },
3187			{ 0 },
3188			{ 400000000 },
3189		},
3190		.reg = { "csiphy3" },
3191		.interrupt = { "csiphy3" },
3192		.csiphy = {
3193			.id = 3,
3194			.hw_ops = &csiphy_ops_3ph_1_0,
3195			.formats = &csiphy_formats_sdm845
3196		}
3197	},
3198};
3199
3200static const struct camss_subdev_resources csid_res_8775p[] = {
3201	/* CSID0 */
3202	{
3203		.regulators = {},
3204		.clock = { "csid", "csiphy_rx"},
3205		.clock_rate = {
3206			{ 400000000, 400000000},
3207			{ 400000000, 400000000}
3208		},
3209		.reg = { "csid0" },
3210		.interrupt = { "csid0" },
3211		.csid = {
3212			.is_lite = false,
3213			.hw_ops = &csid_ops_gen3,
3214			.parent_dev_ops = &vfe_parent_dev_ops,
3215			.formats = &csid_formats_gen2
3216		}
3217	},
3218	/* CSID1 */
3219	{
3220		.regulators = {},
3221		.clock = { "csid", "csiphy_rx"},
3222		.clock_rate = {
3223			{ 400000000, 400000000},
3224			{ 400000000, 400000000}
3225		},
3226		.reg = { "csid1" },
3227		.interrupt = { "csid1" },
3228		.csid = {
3229			.is_lite = false,
3230			.hw_ops = &csid_ops_gen3,
3231			.parent_dev_ops = &vfe_parent_dev_ops,
3232			.formats = &csid_formats_gen2
3233		}
3234	},
3235
3236	/* CSID2 (lite) */
3237	{
3238		.regulators = {},
3239		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3240			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3241			   "vfe_lite"},
3242		.clock_rate = {
3243			{ 0, 0, 400000000, 400000000, 0},
3244			{ 0, 0, 400000000, 480000000, 0}
3245		},
3246		.reg = { "csid_lite0" },
3247		.interrupt = { "csid_lite0" },
3248		.csid = {
3249			.is_lite = true,
3250			.hw_ops = &csid_ops_gen3,
3251			.parent_dev_ops = &vfe_parent_dev_ops,
3252			.formats = &csid_formats_gen2
3253		}
3254	},
3255	/* CSID3 (lite) */
3256	{
3257		.regulators = {},
3258		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3259			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3260			   "vfe_lite"},
3261		.clock_rate = {
3262			{ 0, 0, 400000000, 400000000, 0},
3263			{ 0, 0, 400000000, 480000000, 0}
3264		},
3265		.reg = { "csid_lite1" },
3266		.interrupt = { "csid_lite1" },
3267		.csid = {
3268			.is_lite = true,
3269			.hw_ops = &csid_ops_gen3,
3270			.parent_dev_ops = &vfe_parent_dev_ops,
3271			.formats = &csid_formats_gen2
3272		}
3273	},
3274	/* CSID4 (lite) */
3275	{
3276		.regulators = {},
3277		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3278			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3279			   "vfe_lite"},
3280		.clock_rate = {
3281			{ 0, 0, 400000000, 400000000, 0},
3282			{ 0, 0, 400000000, 480000000, 0}
3283		},
3284		.reg = { "csid_lite2" },
3285		.interrupt = { "csid_lite2" },
3286		.csid = {
3287			.is_lite = true,
3288			.hw_ops = &csid_ops_gen3,
3289			.parent_dev_ops = &vfe_parent_dev_ops,
3290			.formats = &csid_formats_gen2
3291		}
3292	},
3293	/* CSID5 (lite) */
3294	{
3295		.regulators = {},
3296		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3297			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3298			   "vfe_lite"},
3299		.clock_rate = {
3300			{ 0, 0, 400000000, 400000000, 0},
3301			{ 0, 0, 400000000, 480000000, 0}
3302		},
3303		.reg = { "csid_lite3" },
3304		.interrupt = { "csid_lite3" },
3305		.csid = {
3306			.is_lite = true,
3307			.hw_ops = &csid_ops_gen3,
3308			.parent_dev_ops = &vfe_parent_dev_ops,
3309			.formats = &csid_formats_gen2
3310		}
3311	},
3312	/* CSID6 (lite) */
3313	{
3314		.regulators = {},
3315		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3316			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3317			   "vfe_lite"},
3318		.clock_rate = {
3319			{ 0, 0, 400000000, 400000000, 0},
3320			{ 0, 0, 400000000, 480000000, 0}
3321		},
3322		.reg = { "csid_lite4" },
3323		.interrupt = { "csid_lite4" },
3324		.csid = {
3325			.is_lite = true,
3326			.hw_ops = &csid_ops_gen3,
3327			.parent_dev_ops = &vfe_parent_dev_ops,
3328			.formats = &csid_formats_gen2
3329		}
3330	},
3331};
3332
3333static const struct camss_subdev_resources vfe_res_8775p[] = {
3334	/* VFE0 */
3335	{
3336		.regulators = {},
3337		.clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb",
3338			   "cpas_ahb", "gcc_axi_hf",
3339			   "cpas_fast_ahb_clk",
3340			   "camnoc_axi"},
3341		.clock_rate = {
3342			{ 0 },
3343			{ 480000000 },
3344			{ 300000000, 400000000 },
3345			{ 300000000, 400000000 },
3346			{ 0 },
3347			{ 300000000, 400000000 },
3348			{ 400000000 },
3349		},
3350		.reg = { "vfe0" },
3351		.interrupt = { "vfe0" },
3352		.vfe = {
3353			.line_num = 3,
3354			.is_lite = false,
3355			.has_pd = false,
3356			.pd_name = NULL,
3357			.hw_ops = &vfe_ops_gen3,
3358			.formats_rdi = &vfe_formats_rdi_845,
3359			.formats_pix = &vfe_formats_pix_845
3360		}
3361	},
3362	/* VFE1 */
3363	{
3364		.regulators = {},
3365		.clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb",
3366			   "cpas_ahb", "gcc_axi_hf",
3367			   "cpas_fast_ahb_clk",
3368			   "camnoc_axi"},
3369		.clock_rate = {
3370			{ 0 },
3371			{ 480000000 },
3372			{ 300000000, 400000000 },
3373			{ 300000000, 400000000 },
3374			{ 0 },
3375			{ 300000000, 400000000 },
3376			{ 400000000 },
3377		},
3378		.reg = { "vfe1" },
3379		.interrupt = { "vfe1" },
3380		.vfe = {
3381			.line_num = 3,
3382			.is_lite = false,
3383			.has_pd = false,
3384			.pd_name = NULL,
3385			.hw_ops = &vfe_ops_gen3,
3386			.formats_rdi = &vfe_formats_rdi_845,
3387			.formats_pix = &vfe_formats_pix_845
3388		}
3389	},
3390	/* VFE2 (lite) */
3391	{
3392		.regulators = {},
3393		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3394			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3395			   "vfe_lite"},
3396		.clock_rate = {
3397			{ 0, 0, 0, 0  },
3398			{ 300000000, 400000000, 400000000, 400000000 },
3399			{ 400000000, 400000000, 400000000, 400000000 },
3400			{ 400000000, 400000000, 400000000, 400000000 },
3401			{ 480000000, 600000000, 600000000, 600000000 },
3402		},
3403		.reg = { "vfe_lite0" },
3404		.interrupt = { "vfe_lite0" },
3405		.vfe = {
3406			.line_num = 4,
3407			.is_lite = true,
3408			.hw_ops = &vfe_ops_gen3,
3409			.formats_rdi = &vfe_formats_rdi_845,
3410			.formats_pix = &vfe_formats_pix_845
3411		}
3412	},
3413	/* VFE3 (lite) */
3414	{
3415		.regulators = {},
3416		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3417			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3418			   "vfe_lite"},
3419		.clock_rate = {
3420			{ 0, 0, 0, 0  },
3421			{ 300000000, 400000000, 400000000, 400000000 },
3422			{ 400000000, 400000000, 400000000, 400000000 },
3423			{ 400000000, 400000000, 400000000, 400000000 },
3424			{ 480000000, 600000000, 600000000, 600000000 },
3425		},
3426		.reg = { "vfe_lite1" },
3427		.interrupt = { "vfe_lite1" },
3428		.vfe = {
3429			.line_num = 4,
3430			.is_lite = true,
3431			.hw_ops = &vfe_ops_gen3,
3432			.formats_rdi = &vfe_formats_rdi_845,
3433			.formats_pix = &vfe_formats_pix_845
3434		}
3435	},
3436	/* VFE4 (lite) */
3437	{
3438		.regulators = {},
3439		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3440			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3441			   "vfe_lite"},
3442		.clock_rate = {
3443			{ 0, 0, 0, 0  },
3444			{ 300000000, 400000000, 400000000, 400000000 },
3445			{ 400000000, 400000000, 400000000, 400000000 },
3446			{ 400000000, 400000000, 400000000, 400000000 },
3447			{ 480000000, 600000000, 600000000, 600000000 },
3448		},
3449		.reg = { "vfe_lite2" },
3450		.interrupt = { "vfe_lite2" },
3451		.vfe = {
3452			.line_num = 4,
3453			.is_lite = true,
3454			.hw_ops = &vfe_ops_gen3,
3455			.formats_rdi = &vfe_formats_rdi_845,
3456			.formats_pix = &vfe_formats_pix_845
3457		}
3458	},
3459	/* VFE5 (lite) */
3460	{
3461		.regulators = {},
3462		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3463			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3464			   "vfe_lite"},
3465		.clock_rate = {
3466			{ 0, 0, 0, 0  },
3467			{ 300000000, 400000000, 400000000, 400000000 },
3468			{ 400000000, 400000000, 400000000, 400000000 },
3469			{ 400000000, 400000000, 400000000, 400000000 },
3470			{ 480000000, 600000000, 600000000, 600000000 },
3471		},
3472		.reg = { "vfe_lite3" },
3473		.interrupt = { "vfe_lite3" },
3474		.vfe = {
3475			.line_num = 4,
3476			.is_lite = true,
3477			.hw_ops = &vfe_ops_gen3,
3478			.formats_rdi = &vfe_formats_rdi_845,
3479			.formats_pix = &vfe_formats_pix_845
3480		}
3481	},
3482	/* VFE6 (lite) */
3483	{
3484		.regulators = {},
3485		.clock = { "cpas_vfe_lite", "vfe_lite_ahb",
3486			   "vfe_lite_csid", "vfe_lite_cphy_rx",
3487			   "vfe_lite"},
3488		.clock_rate = {
3489			{ 0, 0, 0, 0  },
3490			{ 300000000, 400000000, 400000000, 400000000 },
3491			{ 400000000, 400000000, 400000000, 400000000 },
3492			{ 400000000, 400000000, 400000000, 400000000 },
3493			{ 480000000, 600000000, 600000000, 600000000 },
3494		},
3495		.reg = { "vfe_lite4" },
3496		.interrupt = { "vfe_lite4" },
3497		.vfe = {
3498			.line_num = 4,
3499			.is_lite = true,
3500			.hw_ops = &vfe_ops_gen3,
3501			.formats_rdi = &vfe_formats_rdi_845,
3502			.formats_pix = &vfe_formats_pix_845
3503		}
3504	},
3505};
3506
3507static const struct resources_icc icc_res_qcs8300[] = {
3508	{
3509		.name = "ahb",
3510		.icc_bw_tbl.avg = 38400,
3511		.icc_bw_tbl.peak = 76800,
3512	},
3513	{
3514		.name = "hf_0",
3515		.icc_bw_tbl.avg = 2097152,
3516		.icc_bw_tbl.peak = 2097152,
3517	},
3518};
3519
3520static const struct resources_icc icc_res_sa8775p[] = {
3521	{
3522		.name = "ahb",
3523		.icc_bw_tbl.avg = 38400,
3524		.icc_bw_tbl.peak = 76800,
3525	},
3526	{
3527		.name = "hf_0",
3528		.icc_bw_tbl.avg = 2097152,
3529		.icc_bw_tbl.peak = 2097152,
3530	},
3531};
3532
3533static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
3534	/* CSIPHY0 */
3535	{
3536		.regulators = { "vdd-csiphy-0p8",
3537				"vdd-csiphy-1p2" },
3538		.clock = { "csiphy0", "csiphy0_timer" },
3539		.clock_rate = { { 300000000, 400000000, 480000000 },
3540				{ 266666667, 400000000 } },
3541		.reg = { "csiphy0" },
3542		.interrupt = { "csiphy0" },
3543		.csiphy = {
3544			.id = 0,
3545			.hw_ops = &csiphy_ops_3ph_1_0,
3546			.formats = &csiphy_formats_sdm845
3547		},
3548	},
3549	/* CSIPHY1 */
3550	{
3551		.regulators = { "vdd-csiphy-0p8",
3552				"vdd-csiphy-1p2" },
3553		.clock = { "csiphy1", "csiphy1_timer" },
3554		.clock_rate = { { 300000000, 400000000, 480000000 },
3555				{ 266666667, 400000000 } },
3556		.reg = { "csiphy1" },
3557		.interrupt = { "csiphy1" },
3558		.csiphy = {
3559			.id = 1,
3560			.hw_ops = &csiphy_ops_3ph_1_0,
3561			.formats = &csiphy_formats_sdm845
3562		},
3563	},
3564	/* CSIPHY2 */
3565	{
3566		.regulators = { "vdd-csiphy-0p8",
3567				"vdd-csiphy-1p2" },
3568		.clock = { "csiphy2", "csiphy2_timer" },
3569		.clock_rate = { { 300000000, 400000000, 480000000 },
3570				{ 266666667, 400000000 } },
3571		.reg = { "csiphy2" },
3572		.interrupt = { "csiphy2" },
3573		.csiphy = {
3574			.id = 2,
3575			.hw_ops = &csiphy_ops_3ph_1_0,
3576			.formats = &csiphy_formats_sdm845
3577		},
3578	},
3579	/* CSIPHY4 */
3580	{
3581		.regulators = { "vdd-csiphy-0p8",
3582				"vdd-csiphy-1p2" },
3583		.clock = { "csiphy4", "csiphy4_timer" },
3584		.clock_rate = { { 300000000, 400000000, 480000000 },
3585				{ 266666667, 400000000 } },
3586		.reg = { "csiphy4" },
3587		.interrupt = { "csiphy4" },
3588		.csiphy = {
3589			.id = 4,
3590			.hw_ops = &csiphy_ops_3ph_1_0,
3591			.formats = &csiphy_formats_sdm845
3592		},
3593	},
3594};
3595
3596static const struct camss_subdev_resources csid_res_x1e80100[] = {
3597	/* CSID0 */
3598	{
3599		.regulators = {},
3600		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
3601			   "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
3602		.clock_rate = { { 0 },
3603				{ 0 },
3604				{ 64000000, 80000000 },
3605				{ 80000000,  100000000, 200000000,
3606				  300000000, 400000000 },
3607				{ 300000000, 400000000, 480000000 },
3608				{ 300000000, 400000000, 480000000 }, },
3609		.reg = { "csid0" },
3610		.interrupt = { "csid0" },
3611		.csid = {
3612			.hw_ops = &csid_ops_680,
3613			.parent_dev_ops = &vfe_parent_dev_ops,
3614			.formats = &csid_formats_gen2
3615		},
3616	},
3617	/* CSID1 */
3618	{
3619		.regulators = {},
3620		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
3621			   "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
3622		.clock_rate = { { 0 },
3623				{ 0 },
3624				{ 64000000, 80000000 },
3625				{ 80000000,  100000000, 200000000,
3626				  300000000, 400000000 },
3627				{ 300000000, 400000000, 480000000 },
3628				{ 300000000, 400000000, 480000000 }, },
3629		.reg = { "csid1" },
3630		.interrupt = { "csid1" },
3631		.csid = {
3632			.hw_ops = &csid_ops_680,
3633			.parent_dev_ops = &vfe_parent_dev_ops,
3634			.formats = &csid_formats_gen2
3635		},
3636	},
3637	/* CSID2 */
3638	{
3639		.regulators = {},
3640		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
3641			   "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
3642		.clock_rate = { { 0 },
3643				{ 0 },
3644				{ 64000000, 80000000 },
3645				{ 80000000,  100000000, 200000000,
3646				  300000000, 400000000 },
3647				{ 300000000, 400000000, 480000000 },
3648				{ 300000000, 400000000, 480000000 }, },
3649		.reg = { "csid2" },
3650		.interrupt = { "csid2" },
3651		.csid = {
3652			.hw_ops = &csid_ops_680,
3653			.parent_dev_ops = &vfe_parent_dev_ops,
3654			.formats = &csid_formats_gen2
3655		},
3656	},
3657	/* CSID_LITE0 */
3658	{
3659		.regulators = {},
3660		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
3661			   "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
3662		.clock_rate = { { 0 },
3663				{ 0 },
3664				{ 64000000, 80000000 },
3665				{ 80000000,  100000000, 200000000,
3666				  300000000, 400000000 },
3667				{ 300000000, 400000000, 480000000 },
3668				{ 300000000, 400000000, 480000000 }, },
3669		.reg = { "csid_lite0" },
3670		.interrupt = { "csid_lite0" },
3671		.csid = {
3672			.is_lite = true,
3673			.hw_ops = &csid_ops_680,
3674			.parent_dev_ops = &vfe_parent_dev_ops,
3675			.formats = &csid_formats_gen2
3676		}
3677	},
3678	/* CSID_LITE1 */
3679	{
3680		.regulators = {},
3681		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
3682			   "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
3683		.clock_rate = { { 0 },
3684				{ 0 },
3685				{ 64000000, 80000000 },
3686				{ 80000000,  100000000, 200000000,
3687				  300000000, 400000000 },
3688				{ 300000000, 400000000, 480000000 },
3689				{ 300000000, 400000000, 480000000 }, },
3690
3691		.reg = { "csid_lite1" },
3692		.interrupt = { "csid_lite1" },
3693		.csid = {
3694			.is_lite = true,
3695			.hw_ops = &csid_ops_680,
3696			.parent_dev_ops = &vfe_parent_dev_ops,
3697			.formats = &csid_formats_gen2
3698		}
3699	},
3700};
3701
3702static const struct camss_subdev_resources vfe_res_x1e80100[] = {
3703	/* IFE0 */
3704	{
3705		.regulators = {},
3706		.clock = {"camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
3707			  "cpas_fast_ahb", "cpas_vfe0", "vfe0_fast_ahb",
3708			  "vfe0" },
3709		.clock_rate = { { 0 },
3710				{ 0 },
3711				{ 0 },
3712				{ 0 },
3713				{ 0 },
3714				{ 0 },
3715				{ 345600000, 432000000, 594000000, 675000000,
3716				  727000000 }, },
3717		.reg = { "vfe0" },
3718		.interrupt = { "vfe0" },
3719		.vfe = {
3720			.line_num = 4,
3721			.pd_name = "ife0",
3722			.hw_ops = &vfe_ops_680,
3723			.formats_rdi = &vfe_formats_rdi_845,
3724			.formats_pix = &vfe_formats_pix_845
3725		},
3726	},
3727	/* IFE1 */
3728	{
3729		.regulators = {},
3730		.clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
3731			   "cpas_fast_ahb", "cpas_vfe1", "vfe1_fast_ahb",
3732			   "vfe1"  },
3733		.clock_rate = { { 0 },
3734				{ 0 },
3735				{ 0 },
3736				{ 0 },
3737				{ 0 },
3738				{ 0 },
3739				{ 345600000, 432000000, 594000000, 675000000,
3740				  727000000 }, },
3741		.reg = { "vfe1" },
3742		.interrupt = { "vfe1" },
3743		.vfe = {
3744			.line_num = 4,
3745			.pd_name = "ife1",
3746			.hw_ops = &vfe_ops_680,
3747			.formats_rdi = &vfe_formats_rdi_845,
3748			.formats_pix = &vfe_formats_pix_845
3749		},
3750	},
3751	/* IFE_LITE_0 */
3752	{
3753		.regulators = {},
3754		.clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
3755			   "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite",
3756			   "vfe_lite_csid" },
3757		.clock_rate = { { 0 },
3758				{ 0 },
3759				{ 0 },
3760				{ 0 },
3761				{ 0 },
3762				{ 266666667, 400000000, 480000000 },
3763				{ 266666667, 400000000, 480000000 }, },
3764		.reg = { "vfe_lite0" },
3765		.interrupt = { "vfe_lite0" },
3766		.vfe = {
3767			.is_lite = true,
3768			.line_num = 4,
3769			.hw_ops = &vfe_ops_680,
3770			.formats_rdi = &vfe_formats_rdi_845,
3771			.formats_pix = &vfe_formats_pix_845
3772		},
3773	},
3774	/* IFE_LITE_1 */
3775	{
3776		.regulators = {},
3777		.clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
3778			   "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite",
3779			   "vfe_lite_csid" },
3780		.clock_rate = { { 0 },
3781				{ 0 },
3782				{ 0 },
3783				{ 0 },
3784				{ 0 },
3785				{ 266666667, 400000000, 480000000 },
3786				{ 266666667, 400000000, 480000000 }, },
3787		.reg = { "vfe_lite1" },
3788		.interrupt = { "vfe_lite1" },
3789		.vfe = {
3790			.is_lite = true,
3791			.line_num = 4,
3792			.hw_ops = &vfe_ops_680,
3793			.formats_rdi = &vfe_formats_rdi_845,
3794			.formats_pix = &vfe_formats_pix_845
3795		},
3796	},
3797};
3798
3799static const struct resources_icc icc_res_x1e80100[] = {
3800	{
3801		.name = "ahb",
3802		.icc_bw_tbl.avg = 150000,
3803		.icc_bw_tbl.peak = 300000,
3804	},
3805	{
3806		.name = "hf_mnoc",
3807		.icc_bw_tbl.avg = 2097152,
3808		.icc_bw_tbl.peak = 2097152,
3809	},
3810	{
3811		.name = "sf_mnoc",
3812		.icc_bw_tbl.avg = 2097152,
3813		.icc_bw_tbl.peak = 2097152,
3814	},
3815	{
3816		.name = "sf_icp_mnoc",
3817		.icc_bw_tbl.avg = 2097152,
3818		.icc_bw_tbl.peak = 2097152,
3819	},
3820};
3821
3822static const struct resources_wrapper csid_wrapper_res_x1e80100 = {
3823	.reg = "csid_wrapper",
3824};
3825
3826/*
3827 * camss_add_clock_margin - Add margin to clock frequency rate
3828 * @rate: Clock frequency rate
3829 *
3830 * When making calculations with physical clock frequency values
3831 * some safety margin must be added. Add it.
3832 */
3833inline void camss_add_clock_margin(u64 *rate)
3834{
3835	*rate *= CAMSS_CLOCK_MARGIN_NUMERATOR;
3836	*rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR);
3837}
3838
3839/*
3840 * camss_enable_clocks - Enable multiple clocks
3841 * @nclocks: Number of clocks in clock array
3842 * @clock: Clock array
3843 * @dev: Device
3844 *
3845 * Return 0 on success or a negative error code otherwise
3846 */
3847int camss_enable_clocks(int nclocks, struct camss_clock *clock,
3848			struct device *dev)
3849{
3850	int ret;
3851	int i;
3852
3853	for (i = 0; i < nclocks; i++) {
3854		ret = clk_prepare_enable(clock[i].clk);
3855		if (ret) {
3856			dev_err(dev, "clock enable failed: %d\n", ret);
3857			goto error;
3858		}
3859	}
3860
3861	return 0;
3862
3863error:
3864	for (i--; i >= 0; i--)
3865		clk_disable_unprepare(clock[i].clk);
3866
3867	return ret;
3868}
3869
3870/*
3871 * camss_disable_clocks - Disable multiple clocks
3872 * @nclocks: Number of clocks in clock array
3873 * @clock: Clock array
3874 */
3875void camss_disable_clocks(int nclocks, struct camss_clock *clock)
3876{
3877	int i;
3878
3879	for (i = nclocks - 1; i >= 0; i--)
3880		clk_disable_unprepare(clock[i].clk);
3881}
3882
3883/*
3884 * camss_find_sensor_pad - Find the media pad via which the sensor is linked
3885 * @entity: Media entity to start searching from
3886 *
3887 * Return a pointer to sensor media pad or NULL if not found
3888 */
3889struct media_pad *camss_find_sensor_pad(struct media_entity *entity)
3890{
3891	struct media_pad *pad;
3892
3893	while (1) {
3894		pad = &entity->pads[0];
3895		if (!(pad->flags & MEDIA_PAD_FL_SINK))
3896			return NULL;
3897
3898		pad = media_pad_remote_pad_first(pad);
3899		if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
3900			return NULL;
3901
3902		entity = pad->entity;
3903
3904		if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
3905			return pad;
3906	}
3907}
3908
3909/**
3910 * camss_get_link_freq - Get link frequency from sensor
3911 * @entity: Media entity in the current pipeline
3912 * @bpp: Number of bits per pixel for the current format
3913 * @lanes: Number of lanes in the link to the sensor
3914 *
3915 * Return link frequency on success or a negative error code otherwise
3916 */
3917s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
3918			unsigned int lanes)
3919{
3920	struct media_pad *sensor_pad;
3921
3922	sensor_pad = camss_find_sensor_pad(entity);
3923	if (!sensor_pad)
3924		return -ENODEV;
3925
3926	return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes);
3927}
3928
3929/*
3930 * camss_get_pixel_clock - Get pixel clock rate from sensor
3931 * @entity: Media entity in the current pipeline
3932 * @pixel_clock: Received pixel clock value
3933 *
3934 * Return 0 on success or a negative error code otherwise
3935 */
3936int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock)
3937{
3938	struct media_pad *sensor_pad;
3939	struct v4l2_subdev *subdev;
3940	struct v4l2_ctrl *ctrl;
3941
3942	sensor_pad = camss_find_sensor_pad(entity);
3943	if (!sensor_pad)
3944		return -ENODEV;
3945
3946	subdev = media_entity_to_v4l2_subdev(sensor_pad->entity);
3947
3948	ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
3949
3950	if (!ctrl)
3951		return -EINVAL;
3952
3953	*pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
3954
3955	return 0;
3956}
3957
3958int camss_pm_domain_on(struct camss *camss, int id)
3959{
3960	int ret = 0;
3961
3962	if (id < camss->res->vfe_num) {
3963		struct vfe_device *vfe = &camss->vfe[id];
3964
3965		ret = vfe->res->hw_ops->pm_domain_on(vfe);
3966	}
3967
3968	return ret;
3969}
3970
3971void camss_pm_domain_off(struct camss *camss, int id)
3972{
3973	if (id < camss->res->vfe_num) {
3974		struct vfe_device *vfe = &camss->vfe[id];
3975
3976		vfe->res->hw_ops->pm_domain_off(vfe);
3977	}
3978}
3979
3980static int vfe_parent_dev_ops_get(struct camss *camss, int id)
3981{
3982	int ret = -EINVAL;
3983
3984	if (id < camss->res->vfe_num) {
3985		struct vfe_device *vfe = &camss->vfe[id];
3986
3987		ret = vfe_get(vfe);
3988	}
3989
3990	return ret;
3991}
3992
3993static int vfe_parent_dev_ops_put(struct camss *camss, int id)
3994{
3995	if (id < camss->res->vfe_num) {
3996		struct vfe_device *vfe = &camss->vfe[id];
3997
3998		vfe_put(vfe);
3999	}
4000
4001	return 0;
4002}
4003
4004static void __iomem
4005*vfe_parent_dev_ops_get_base_address(struct camss *camss, int id)
4006{
4007	if (id < camss->res->vfe_num) {
4008		struct vfe_device *vfe = &camss->vfe[id];
4009
4010		return vfe->base;
4011	}
4012
4013	return NULL;
4014}
4015
4016static const struct parent_dev_ops vfe_parent_dev_ops = {
4017	.get = vfe_parent_dev_ops_get,
4018	.put = vfe_parent_dev_ops_put,
4019	.get_base_address = vfe_parent_dev_ops_get_base_address
4020};
4021
4022/*
4023 * camss_of_parse_endpoint_node - Parse port endpoint node
4024 * @dev: Device
4025 * @node: Device node to be parsed
4026 * @csd: Parsed data from port endpoint node
4027 *
4028 * Return 0 on success or a negative error code on failure
4029 */
4030static int camss_of_parse_endpoint_node(struct device *dev,
4031					struct device_node *node,
4032					struct camss_async_subdev *csd)
4033{
4034	struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg;
4035	struct v4l2_mbus_config_mipi_csi2 *mipi_csi2;
4036	struct v4l2_fwnode_endpoint vep = { { 0 } };
4037	unsigned int i;
4038	int ret;
4039
4040	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep);
4041	if (ret)
4042		return ret;
4043
4044	/*
4045	 * Most SoCs support both D-PHY and C-PHY standards, but currently only
4046	 * D-PHY is supported in the driver.
4047	 */
4048	if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
4049		dev_err(dev, "Unsupported bus type %d\n", vep.bus_type);
4050		return -EINVAL;
4051	}
4052
4053	csd->interface.csiphy_id = vep.base.port;
4054
4055	mipi_csi2 = &vep.bus.mipi_csi2;
4056	lncfg->clk.pos = mipi_csi2->clock_lane;
4057	lncfg->clk.pol = mipi_csi2->lane_polarities[0];
4058	lncfg->num_data = mipi_csi2->num_data_lanes;
4059
4060	lncfg->data = devm_kcalloc(dev,
4061				   lncfg->num_data, sizeof(*lncfg->data),
4062				   GFP_KERNEL);
4063	if (!lncfg->data)
4064		return -ENOMEM;
4065
4066	for (i = 0; i < lncfg->num_data; i++) {
4067		lncfg->data[i].pos = mipi_csi2->data_lanes[i];
4068		lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1];
4069	}
4070
4071	return 0;
4072}
4073
4074/*
4075 * camss_of_parse_ports - Parse ports node
4076 * @dev: Device
4077 * @notifier: v4l2_device notifier data
4078 *
4079 * Return number of "port" nodes found in "ports" node
4080 */
4081static int camss_of_parse_ports(struct camss *camss)
4082{
4083	struct device *dev = camss->dev;
4084	struct device_node *node = NULL;
4085	struct device_node *remote = NULL;
4086	int ret, num_subdevs = 0;
4087
4088	for_each_endpoint_of_node(dev->of_node, node) {
4089		struct camss_async_subdev *csd;
4090
4091		remote = of_graph_get_remote_port_parent(node);
4092		if (!remote) {
4093			dev_err(dev, "Cannot get remote parent\n");
4094			ret = -EINVAL;
4095			goto err_cleanup;
4096		}
4097
4098		csd = v4l2_async_nf_add_fwnode(&camss->notifier,
4099					       of_fwnode_handle(remote),
4100					       struct camss_async_subdev);
4101		of_node_put(remote);
4102		if (IS_ERR(csd)) {
4103			ret = PTR_ERR(csd);
4104			goto err_cleanup;
4105		}
4106
4107		ret = camss_of_parse_endpoint_node(dev, node, csd);
4108		if (ret < 0)
4109			goto err_cleanup;
4110
4111		num_subdevs++;
4112	}
4113
4114	return num_subdevs;
4115
4116err_cleanup:
4117	of_node_put(node);
4118	return ret;
4119}
4120
4121/*
4122 * camss_init_subdevices - Initialize subdev structures and resources
4123 * @camss: CAMSS device
4124 *
4125 * Return 0 on success or a negative error code on failure
4126 */
4127static int camss_init_subdevices(struct camss *camss)
4128{
4129	struct platform_device *pdev = to_platform_device(camss->dev);
4130	const struct camss_resources *res = camss->res;
4131	unsigned int i;
4132	int ret;
4133
4134	for (i = 0; i < camss->res->csiphy_num; i++) {
4135		ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i],
4136					     &res->csiphy_res[i],
4137					     res->csiphy_res[i].csiphy.id);
4138		if (ret < 0) {
4139			dev_err(camss->dev,
4140				"Failed to init csiphy%d sub-device: %d\n",
4141				i, ret);
4142			return ret;
4143		}
4144	}
4145
4146	/* note: SM8250 requires VFE to be initialized before CSID */
4147	for (i = 0; i < camss->res->vfe_num; i++) {
4148		ret = msm_vfe_subdev_init(camss, &camss->vfe[i],
4149					  &res->vfe_res[i], i);
4150		if (ret < 0) {
4151			dev_err(camss->dev,
4152				"Fail to init vfe%d sub-device: %d\n", i, ret);
4153			return ret;
4154		}
4155	}
4156
4157	/* Get optional CSID wrapper regs shared between CSID devices */
4158	if (res->csid_wrapper_res) {
4159		char *reg = res->csid_wrapper_res->reg;
4160		void __iomem *base;
4161
4162		base = devm_platform_ioremap_resource_byname(pdev, reg);
4163		if (IS_ERR(base))
4164			return PTR_ERR(base);
4165		camss->csid_wrapper_base = base;
4166	}
4167
4168	for (i = 0; i < camss->res->csid_num; i++) {
4169		ret = msm_csid_subdev_init(camss, &camss->csid[i],
4170					   &res->csid_res[i], i);
4171		if (ret < 0) {
4172			dev_err(camss->dev,
4173				"Failed to init csid%d sub-device: %d\n",
4174				i, ret);
4175			return ret;
4176		}
4177	}
4178
4179	ret = msm_ispif_subdev_init(camss, res->ispif_res);
4180	if (ret < 0) {
4181		dev_err(camss->dev, "Failed to init ispif sub-device: %d\n",
4182		ret);
4183		return ret;
4184	}
4185
4186	return 0;
4187}
4188
4189/*
4190 * camss_link_err - print error in case link creation fails
4191 * @src_name: name for source of the link
4192 * @sink_name: name for sink of the link
4193 */
4194inline void camss_link_err(struct camss *camss,
4195			   const char *src_name,
4196			   const char *sink_name,
4197			   int ret)
4198{
4199	dev_err(camss->dev,
4200		"Failed to link %s->%s entities: %d\n",
4201		src_name,
4202		sink_name,
4203		ret);
4204}
4205
4206/*
4207 * camss_link_entities - Register subdev nodes and create links
4208 * @camss: CAMSS device
4209 *
4210 * Return 0 on success or a negative error code on failure
4211 */
4212static int camss_link_entities(struct camss *camss)
4213{
4214	int i, j, k;
4215	int ret;
4216
4217	for (i = 0; i < camss->res->csiphy_num; i++) {
4218		for (j = 0; j < camss->res->csid_num; j++) {
4219			ret = media_create_pad_link(&camss->csiphy[i].subdev.entity,
4220						    MSM_CSIPHY_PAD_SRC,
4221						    &camss->csid[j].subdev.entity,
4222						    MSM_CSID_PAD_SINK,
4223						    0);
4224			if (ret < 0) {
4225				camss_link_err(camss,
4226					       camss->csiphy[i].subdev.entity.name,
4227					       camss->csid[j].subdev.entity.name,
4228					       ret);
4229				return ret;
4230			}
4231		}
4232	}
4233
4234	if (camss->ispif) {
4235		for (i = 0; i < camss->res->csid_num; i++) {
4236			for (j = 0; j < camss->ispif->line_num; j++) {
4237				ret = media_create_pad_link(&camss->csid[i].subdev.entity,
4238							    MSM_CSID_PAD_SRC,
4239							    &camss->ispif->line[j].subdev.entity,
4240							    MSM_ISPIF_PAD_SINK,
4241							    0);
4242				if (ret < 0) {
4243					camss_link_err(camss,
4244						       camss->csid[i].subdev.entity.name,
4245						       camss->ispif->line[j].subdev.entity.name,
4246						       ret);
4247					return ret;
4248				}
4249			}
4250		}
4251
4252		for (i = 0; i < camss->ispif->line_num; i++)
4253			for (k = 0; k < camss->res->vfe_num; k++)
4254				for (j = 0; j < camss->vfe[k].res->line_num; j++) {
4255					struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev;
4256					struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
4257
4258					ret = media_create_pad_link(&ispif->entity,
4259								    MSM_ISPIF_PAD_SRC,
4260								    &vfe->entity,
4261								    MSM_VFE_PAD_SINK,
4262								    0);
4263					if (ret < 0) {
4264						camss_link_err(camss, ispif->entity.name,
4265							       vfe->entity.name,
4266							       ret);
4267						return ret;
4268					}
4269				}
4270	} else {
4271		for (i = 0; i < camss->res->csid_num; i++)
4272			for (k = 0; k < camss->res->vfe_num; k++)
4273				for (j = 0; j < camss->vfe[k].res->line_num; j++) {
4274					struct v4l2_subdev *csid = &camss->csid[i].subdev;
4275					struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
4276
4277					ret = media_create_pad_link(&csid->entity,
4278								    MSM_CSID_PAD_FIRST_SRC + j,
4279								    &vfe->entity,
4280								    MSM_VFE_PAD_SINK,
4281								    0);
4282					if (ret < 0) {
4283						camss_link_err(camss, csid->entity.name,
4284							       vfe->entity.name,
4285							       ret);
4286						return ret;
4287					}
4288				}
4289	}
4290
4291	return 0;
4292}
4293
4294void camss_reg_update(struct camss *camss, int hw_id, int port_id, bool is_clear)
4295{
4296	struct csid_device *csid;
4297
4298	if (hw_id < camss->res->csid_num) {
4299		csid = &camss->csid[hw_id];
4300
4301		csid->res->hw_ops->reg_update(csid, port_id, is_clear);
4302	}
4303}
4304
4305void camss_buf_done(struct camss *camss, int hw_id, int port_id)
4306{
4307	struct vfe_device *vfe;
4308
4309	if (hw_id < camss->res->vfe_num) {
4310		vfe = &camss->vfe[hw_id];
4311
4312		vfe->res->hw_ops->vfe_buf_done(vfe, port_id);
4313	}
4314}
4315
4316/*
4317 * camss_register_entities - Register subdev nodes and create links
4318 * @camss: CAMSS device
4319 *
4320 * Return 0 on success or a negative error code on failure
4321 */
4322static int camss_register_entities(struct camss *camss)
4323{
4324	int i;
4325	int ret;
4326
4327	for (i = 0; i < camss->res->csiphy_num; i++) {
4328		ret = msm_csiphy_register_entity(&camss->csiphy[i],
4329						 &camss->v4l2_dev);
4330		if (ret < 0) {
4331			dev_err(camss->dev,
4332				"Failed to register csiphy%d entity: %d\n",
4333				i, ret);
4334			goto err_reg_csiphy;
4335		}
4336	}
4337
4338	for (i = 0; i < camss->res->csid_num; i++) {
4339		ret = msm_csid_register_entity(&camss->csid[i],
4340					       &camss->v4l2_dev);
4341		if (ret < 0) {
4342			dev_err(camss->dev,
4343				"Failed to register csid%d entity: %d\n",
4344				i, ret);
4345			goto err_reg_csid;
4346		}
4347	}
4348
4349	ret = msm_ispif_register_entities(camss->ispif,
4350					  &camss->v4l2_dev);
4351	if (ret < 0) {
4352		dev_err(camss->dev, "Failed to register ispif entities: %d\n", ret);
4353		goto err_reg_ispif;
4354	}
4355
4356	for (i = 0; i < camss->res->vfe_num; i++) {
4357		ret = msm_vfe_register_entities(&camss->vfe[i],
4358						&camss->v4l2_dev);
4359		if (ret < 0) {
4360			dev_err(camss->dev,
4361				"Failed to register vfe%d entities: %d\n",
4362				i, ret);
4363			goto err_reg_vfe;
4364		}
4365	}
4366
4367	return 0;
4368
4369err_reg_vfe:
4370	for (i--; i >= 0; i--)
4371		msm_vfe_unregister_entities(&camss->vfe[i]);
4372
4373err_reg_ispif:
4374	msm_ispif_unregister_entities(camss->ispif);
4375
4376	i = camss->res->csid_num;
4377err_reg_csid:
4378	for (i--; i >= 0; i--)
4379		msm_csid_unregister_entity(&camss->csid[i]);
4380
4381	i = camss->res->csiphy_num;
4382err_reg_csiphy:
4383	for (i--; i >= 0; i--)
4384		msm_csiphy_unregister_entity(&camss->csiphy[i]);
4385
4386	return ret;
4387}
4388
4389/*
4390 * camss_unregister_entities - Unregister subdev nodes
4391 * @camss: CAMSS device
4392 *
4393 * Return 0 on success or a negative error code on failure
4394 */
4395static void camss_unregister_entities(struct camss *camss)
4396{
4397	unsigned int i;
4398
4399	for (i = 0; i < camss->res->csiphy_num; i++)
4400		msm_csiphy_unregister_entity(&camss->csiphy[i]);
4401
4402	for (i = 0; i < camss->res->csid_num; i++)
4403		msm_csid_unregister_entity(&camss->csid[i]);
4404
4405	msm_ispif_unregister_entities(camss->ispif);
4406
4407	for (i = 0; i < camss->res->vfe_num; i++)
4408		msm_vfe_unregister_entities(&camss->vfe[i]);
4409}
4410
4411static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async,
4412				       struct v4l2_subdev *subdev,
4413				       struct v4l2_async_connection *asd)
4414{
4415	struct camss *camss = container_of(async, struct camss, notifier);
4416	struct camss_async_subdev *csd =
4417		container_of(asd, struct camss_async_subdev, asd);
4418	u8 id = csd->interface.csiphy_id;
4419	struct csiphy_device *csiphy = &camss->csiphy[id];
4420
4421	csiphy->cfg.csi2 = &csd->interface.csi2;
4422	subdev->host_priv = csiphy;
4423
4424	return 0;
4425}
4426
4427static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async)
4428{
4429	struct camss *camss = container_of(async, struct camss, notifier);
4430	struct v4l2_device *v4l2_dev = &camss->v4l2_dev;
4431	struct v4l2_subdev *sd;
4432
4433	list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
4434		struct csiphy_device *csiphy = sd->host_priv;
4435		struct media_entity *input, *sensor;
4436		unsigned int i;
4437		int ret;
4438
4439		if (!csiphy)
4440			continue;
4441
4442		input = &csiphy->subdev.entity;
4443		sensor = &sd->entity;
4444
4445		for (i = 0; i < sensor->num_pads; i++) {
4446			if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE)
4447				break;
4448		}
4449		if (i == sensor->num_pads) {
4450			dev_err(camss->dev,
4451				"No source pad in external entity\n");
4452			return -EINVAL;
4453		}
4454
4455		ret = media_create_pad_link(sensor, i, input,
4456					    MSM_CSIPHY_PAD_SINK,
4457					    MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
4458		if (ret < 0) {
4459			camss_link_err(camss, sensor->name, input->name, ret);
4460			return ret;
4461		}
4462	}
4463
4464	return v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
4465}
4466
4467static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = {
4468	.bound = camss_subdev_notifier_bound,
4469	.complete = camss_subdev_notifier_complete,
4470};
4471
4472static const struct media_device_ops camss_media_ops = {
4473	.link_notify = v4l2_pipeline_link_notify,
4474};
4475
4476static int camss_configure_pd(struct camss *camss)
4477{
4478	const struct camss_resources *res = camss->res;
4479	struct device *dev = camss->dev;
4480	int vfepd_num;
4481	int i;
4482	int ret;
4483
4484	camss->genpd_num = of_count_phandle_with_args(dev->of_node,
4485						      "power-domains",
4486						      "#power-domain-cells");
4487	if (camss->genpd_num < 0) {
4488		dev_err(dev, "Power domains are not defined for camss\n");
4489		return camss->genpd_num;
4490	}
4491
4492	/*
4493	 * If a platform device has just one power domain, then it is attached
4494	 * at platform_probe() level, thus there shall be no need and even no
4495	 * option to attach it again, this is the case for CAMSS on MSM8916.
4496	 */
4497	if (camss->genpd_num == 1)
4498		return 0;
4499
4500	/* count the # of VFEs which have flagged power-domain */
4501	for (vfepd_num = i = 0; i < camss->res->vfe_num; i++) {
4502		if (res->vfe_res[i].vfe.has_pd)
4503			vfepd_num++;
4504	}
4505
4506	/*
4507	 * If the number of power-domains is greater than the number of VFEs
4508	 * then the additional power-domain is for the entire CAMSS block.
4509	 */
4510	if (!(camss->genpd_num > vfepd_num))
4511		return 0;
4512
4513	/*
4514	 * If a power-domain name is defined try to use it.
4515	 * It is possible we are running a new kernel with an old dtb so
4516	 * fallback to indexes even if a pd_name is defined but not found.
4517	 */
4518	if (camss->res->pd_name) {
4519		camss->genpd = dev_pm_domain_attach_by_name(camss->dev,
4520							    camss->res->pd_name);
4521		if (IS_ERR(camss->genpd))
4522			return PTR_ERR(camss->genpd);
4523	}
4524
4525	if (!camss->genpd) {
4526		/*
4527		 * Legacy magic index. TITAN_TOP GDSC must be the last
4528		 * item in the power-domain list.
4529		 */
4530		camss->genpd = dev_pm_domain_attach_by_id(camss->dev,
4531							  camss->genpd_num - 1);
4532		if (IS_ERR(camss->genpd))
4533			return PTR_ERR(camss->genpd);
4534	}
4535
4536	if (!camss->genpd)
4537		return -ENODEV;
4538
4539	camss->genpd_link = device_link_add(camss->dev, camss->genpd,
4540					    DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
4541					    DL_FLAG_RPM_ACTIVE);
4542	if (!camss->genpd_link) {
4543		ret = -EINVAL;
4544		goto fail_pm;
4545	}
4546
4547	return 0;
4548
4549fail_pm:
4550	dev_pm_domain_detach(camss->genpd, true);
4551
4552	return ret;
4553}
4554
4555static int camss_icc_get(struct camss *camss)
4556{
4557	const struct resources_icc *icc_res;
4558	int i;
4559
4560	icc_res = camss->res->icc_res;
4561
4562	for (i = 0; i < camss->res->icc_path_num; i++) {
4563		camss->icc_path[i] = devm_of_icc_get(camss->dev,
4564						     icc_res[i].name);
4565		if (IS_ERR(camss->icc_path[i]))
4566			return PTR_ERR(camss->icc_path[i]);
4567	}
4568
4569	return 0;
4570}
4571
4572static void camss_genpd_subdevice_cleanup(struct camss *camss)
4573{
4574	int i;
4575
4576	for (i = 0; i < camss->res->vfe_num; i++)
4577		msm_vfe_genpd_cleanup(&camss->vfe[i]);
4578}
4579
4580static void camss_genpd_cleanup(struct camss *camss)
4581{
4582	if (camss->genpd_num == 1)
4583		return;
4584
4585	camss_genpd_subdevice_cleanup(camss);
4586
4587	if (camss->genpd_link)
4588		device_link_del(camss->genpd_link);
4589
4590	dev_pm_domain_detach(camss->genpd, true);
4591}
4592
4593/*
4594 * camss_probe - Probe CAMSS platform device
4595 * @pdev: Pointer to CAMSS platform device
4596 *
4597 * Return 0 on success or a negative error code on failure
4598 */
4599static int camss_probe(struct platform_device *pdev)
4600{
4601	struct device *dev = &pdev->dev;
4602	struct camss *camss;
4603	int ret;
4604
4605	camss = devm_kzalloc(dev, sizeof(*camss), GFP_KERNEL);
4606	if (!camss)
4607		return -ENOMEM;
4608
4609	camss->res = of_device_get_match_data(dev);
4610
4611	atomic_set(&camss->ref_count, 0);
4612	camss->dev = dev;
4613	platform_set_drvdata(pdev, camss);
4614
4615	camss->csiphy = devm_kcalloc(dev, camss->res->csiphy_num,
4616				     sizeof(*camss->csiphy), GFP_KERNEL);
4617	if (!camss->csiphy)
4618		return -ENOMEM;
4619
4620	camss->csid = devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->csid),
4621				   GFP_KERNEL);
4622	if (!camss->csid)
4623		return -ENOMEM;
4624
4625	if (camss->res->version == CAMSS_8x16 ||
4626	    camss->res->version == CAMSS_8x39 ||
4627	    camss->res->version == CAMSS_8x53 ||
4628	    camss->res->version == CAMSS_8x96) {
4629		camss->ispif = devm_kcalloc(dev, 1, sizeof(*camss->ispif), GFP_KERNEL);
4630		if (!camss->ispif)
4631			return -ENOMEM;
4632	}
4633
4634	camss->vfe = devm_kcalloc(dev, camss->res->vfe_num,
4635				  sizeof(*camss->vfe), GFP_KERNEL);
4636	if (!camss->vfe)
4637		return -ENOMEM;
4638
4639	ret = camss_icc_get(camss);
4640	if (ret < 0)
4641		return ret;
4642
4643	ret = camss_configure_pd(camss);
4644	if (ret < 0) {
4645		dev_err(dev, "Failed to configure power domains: %d\n", ret);
4646		return ret;
4647	}
4648
4649	ret = camss_init_subdevices(camss);
4650	if (ret < 0)
4651		goto err_genpd_cleanup;
4652
4653	ret = dma_set_mask_and_coherent(dev, 0xffffffff);
4654	if (ret)
4655		goto err_genpd_cleanup;
4656
4657	camss->media_dev.dev = camss->dev;
4658	strscpy(camss->media_dev.model, "Qualcomm Camera Subsystem",
4659		sizeof(camss->media_dev.model));
4660	camss->media_dev.ops = &camss_media_ops;
4661	media_device_init(&camss->media_dev);
4662
4663	camss->v4l2_dev.mdev = &camss->media_dev;
4664	ret = v4l2_device_register(camss->dev, &camss->v4l2_dev);
4665	if (ret < 0) {
4666		dev_err(dev, "Failed to register V4L2 device: %d\n", ret);
4667		goto err_media_device_cleanup;
4668	}
4669
4670	v4l2_async_nf_init(&camss->notifier, &camss->v4l2_dev);
4671
4672	pm_runtime_enable(dev);
4673
4674	ret = camss_of_parse_ports(camss);
4675	if (ret < 0)
4676		goto err_v4l2_device_unregister;
4677
4678	ret = camss_register_entities(camss);
4679	if (ret < 0)
4680		goto err_v4l2_device_unregister;
4681
4682	ret = camss_link_entities(camss);
4683	if (ret < 0)
4684		goto err_register_subdevs;
4685
4686	ret = media_device_register(&camss->media_dev);
4687	if (ret < 0) {
4688		dev_err(dev, "Failed to register media device: %d\n", ret);
4689		goto err_register_subdevs;
4690	}
4691
4692	camss->notifier.ops = &camss_subdev_notifier_ops;
4693	ret = v4l2_async_nf_register(&camss->notifier);
4694	if (ret) {
4695		dev_err(dev,
4696			"Failed to register async subdev nodes: %d\n", ret);
4697		goto err_media_device_unregister;
4698	}
4699
4700	return 0;
4701
4702err_media_device_unregister:
4703	media_device_unregister(&camss->media_dev);
4704err_register_subdevs:
4705	camss_unregister_entities(camss);
4706err_v4l2_device_unregister:
4707	v4l2_device_unregister(&camss->v4l2_dev);
4708	v4l2_async_nf_cleanup(&camss->notifier);
4709	pm_runtime_disable(dev);
4710err_media_device_cleanup:
4711	media_device_cleanup(&camss->media_dev);
4712err_genpd_cleanup:
4713	camss_genpd_cleanup(camss);
4714
4715	return ret;
4716}
4717
4718void camss_delete(struct camss *camss)
4719{
4720	v4l2_device_unregister(&camss->v4l2_dev);
4721	media_device_unregister(&camss->media_dev);
4722	media_device_cleanup(&camss->media_dev);
4723
4724	pm_runtime_disable(camss->dev);
4725}
4726
4727/*
4728 * camss_remove - Remove CAMSS platform device
4729 * @pdev: Pointer to CAMSS platform device
4730 *
4731 * Always returns 0.
4732 */
4733static void camss_remove(struct platform_device *pdev)
4734{
4735	struct camss *camss = platform_get_drvdata(pdev);
4736
4737	v4l2_async_nf_unregister(&camss->notifier);
4738	v4l2_async_nf_cleanup(&camss->notifier);
4739	camss_unregister_entities(camss);
4740
4741	if (atomic_read(&camss->ref_count) == 0)
4742		camss_delete(camss);
4743
4744	camss_genpd_cleanup(camss);
4745}
4746
4747static const struct camss_resources msm8916_resources = {
4748	.version = CAMSS_8x16,
4749	.csiphy_res = csiphy_res_8x16,
4750	.csid_res = csid_res_8x16,
4751	.ispif_res = &ispif_res_8x16,
4752	.vfe_res = vfe_res_8x16,
4753	.csiphy_num = ARRAY_SIZE(csiphy_res_8x16),
4754	.csid_num = ARRAY_SIZE(csid_res_8x16),
4755	.vfe_num = ARRAY_SIZE(vfe_res_8x16),
4756};
4757
4758static const struct camss_resources msm8939_resources = {
4759	.version = CAMSS_8x39,
4760	.csiphy_res = csiphy_res_8x39,
4761	.csid_res = csid_res_8x39,
4762	.ispif_res = &ispif_res_8x39,
4763	.vfe_res = vfe_res_8x39,
4764	.csiphy_num = ARRAY_SIZE(csiphy_res_8x39),
4765	.csid_num = ARRAY_SIZE(csid_res_8x39),
4766	.vfe_num = ARRAY_SIZE(vfe_res_8x39),
4767};
4768
4769static const struct camss_resources msm8953_resources = {
4770	.version = CAMSS_8x53,
4771	.icc_res = icc_res_8x53,
4772	.icc_path_num = ARRAY_SIZE(icc_res_8x53),
4773	.csiphy_res = csiphy_res_8x96,
4774	.csid_res = csid_res_8x53,
4775	.ispif_res = &ispif_res_8x53,
4776	.vfe_res = vfe_res_8x53,
4777	.csiphy_num = ARRAY_SIZE(csiphy_res_8x96),
4778	.csid_num = ARRAY_SIZE(csid_res_8x53),
4779	.vfe_num = ARRAY_SIZE(vfe_res_8x53),
4780};
4781
4782static const struct camss_resources msm8996_resources = {
4783	.version = CAMSS_8x96,
4784	.csiphy_res = csiphy_res_8x96,
4785	.csid_res = csid_res_8x96,
4786	.ispif_res = &ispif_res_8x96,
4787	.vfe_res = vfe_res_8x96,
4788	.csiphy_num = ARRAY_SIZE(csiphy_res_8x96),
4789	.csid_num = ARRAY_SIZE(csid_res_8x96),
4790	.vfe_num = ARRAY_SIZE(vfe_res_8x96),
4791};
4792
4793static const struct camss_resources qcm2290_resources = {
4794	.version = CAMSS_2290,
4795	.csiphy_res = csiphy_res_2290,
4796	.csid_res = csid_res_2290,
4797	.vfe_res = vfe_res_2290,
4798	.icc_res = icc_res_2290,
4799	.icc_path_num = ARRAY_SIZE(icc_res_2290),
4800	.csiphy_num = ARRAY_SIZE(csiphy_res_2290),
4801	.csid_num = ARRAY_SIZE(csid_res_2290),
4802	.vfe_num = ARRAY_SIZE(vfe_res_2290),
4803};
4804
4805static const struct camss_resources qcs8300_resources = {
4806	.version = CAMSS_8300,
4807	.pd_name = "top",
4808	.csiphy_res = csiphy_res_8300,
4809	.csid_res = csid_res_8775p,
4810	.csid_wrapper_res = &csid_wrapper_res_sm8550,
4811	.vfe_res = vfe_res_8775p,
4812	.icc_res = icc_res_qcs8300,
4813	.csiphy_num = ARRAY_SIZE(csiphy_res_8300),
4814	.csid_num = ARRAY_SIZE(csid_res_8775p),
4815	.vfe_num = ARRAY_SIZE(vfe_res_8775p),
4816	.icc_path_num = ARRAY_SIZE(icc_res_qcs8300),
4817};
4818
4819static const struct camss_resources sa8775p_resources = {
4820	.version = CAMSS_8775P,
4821	.pd_name = "top",
4822	.csiphy_res = csiphy_res_8775p,
4823	.csid_res = csid_res_8775p,
4824	.csid_wrapper_res = &csid_wrapper_res_sm8550,
4825	.vfe_res = vfe_res_8775p,
4826	.icc_res = icc_res_sa8775p,
4827	.csiphy_num = ARRAY_SIZE(csiphy_res_8775p),
4828	.csid_num = ARRAY_SIZE(csid_res_8775p),
4829	.vfe_num = ARRAY_SIZE(vfe_res_8775p),
4830	.icc_path_num = ARRAY_SIZE(icc_res_sa8775p),
4831};
4832
4833static const struct camss_resources sdm660_resources = {
4834	.version = CAMSS_660,
4835	.csiphy_res = csiphy_res_660,
4836	.csid_res = csid_res_660,
4837	.ispif_res = &ispif_res_660,
4838	.vfe_res = vfe_res_660,
4839	.csiphy_num = ARRAY_SIZE(csiphy_res_660),
4840	.csid_num = ARRAY_SIZE(csid_res_660),
4841	.vfe_num = ARRAY_SIZE(vfe_res_660),
4842};
4843
4844static const struct camss_resources sdm670_resources = {
4845	.version = CAMSS_845,
4846	.csiphy_res = csiphy_res_670,
4847	.csid_res = csid_res_670,
4848	.vfe_res = vfe_res_670,
4849	.csiphy_num = ARRAY_SIZE(csiphy_res_670),
4850	.csid_num = ARRAY_SIZE(csid_res_670),
4851	.vfe_num = ARRAY_SIZE(vfe_res_670),
4852};
4853
4854static const struct camss_resources sdm845_resources = {
4855	.version = CAMSS_845,
4856	.pd_name = "top",
4857	.csiphy_res = csiphy_res_845,
4858	.csid_res = csid_res_845,
4859	.vfe_res = vfe_res_845,
4860	.csiphy_num = ARRAY_SIZE(csiphy_res_845),
4861	.csid_num = ARRAY_SIZE(csid_res_845),
4862	.vfe_num = ARRAY_SIZE(vfe_res_845),
4863};
4864
4865static const struct camss_resources sm8250_resources = {
4866	.version = CAMSS_8250,
4867	.pd_name = "top",
4868	.csiphy_res = csiphy_res_8250,
4869	.csid_res = csid_res_8250,
4870	.vfe_res = vfe_res_8250,
4871	.icc_res = icc_res_sm8250,
4872	.icc_path_num = ARRAY_SIZE(icc_res_sm8250),
4873	.csiphy_num = ARRAY_SIZE(csiphy_res_8250),
4874	.csid_num = ARRAY_SIZE(csid_res_8250),
4875	.vfe_num = ARRAY_SIZE(vfe_res_8250),
4876};
4877
4878static const struct camss_resources sc8280xp_resources = {
4879	.version = CAMSS_8280XP,
4880	.pd_name = "top",
4881	.csiphy_res = csiphy_res_sc8280xp,
4882	.csid_res = csid_res_sc8280xp,
4883	.ispif_res = NULL,
4884	.vfe_res = vfe_res_sc8280xp,
4885	.icc_res = icc_res_sc8280xp,
4886	.icc_path_num = ARRAY_SIZE(icc_res_sc8280xp),
4887	.csiphy_num = ARRAY_SIZE(csiphy_res_sc8280xp),
4888	.csid_num = ARRAY_SIZE(csid_res_sc8280xp),
4889	.vfe_num = ARRAY_SIZE(vfe_res_sc8280xp),
4890};
4891
4892static const struct camss_resources sc7280_resources = {
4893	.version = CAMSS_7280,
4894	.pd_name = "top",
4895	.csiphy_res = csiphy_res_7280,
4896	.csid_res = csid_res_7280,
4897	.vfe_res = vfe_res_7280,
4898	.icc_res = icc_res_sc7280,
4899	.icc_path_num = ARRAY_SIZE(icc_res_sc7280),
4900	.csiphy_num = ARRAY_SIZE(csiphy_res_7280),
4901	.csid_num = ARRAY_SIZE(csid_res_7280),
4902	.vfe_num = ARRAY_SIZE(vfe_res_7280),
4903};
4904
4905static const struct camss_resources sm8550_resources = {
4906	.version = CAMSS_8550,
4907	.pd_name = "top",
4908	.csiphy_res = csiphy_res_8550,
4909	.csid_res = csid_res_8550,
4910	.vfe_res = vfe_res_8550,
4911	.csid_wrapper_res = &csid_wrapper_res_sm8550,
4912	.icc_res = icc_res_sm8550,
4913	.icc_path_num = ARRAY_SIZE(icc_res_sm8550),
4914	.csiphy_num = ARRAY_SIZE(csiphy_res_8550),
4915	.csid_num = ARRAY_SIZE(csid_res_8550),
4916	.vfe_num = ARRAY_SIZE(vfe_res_8550),
4917};
4918
4919static const struct camss_resources sm8650_resources = {
4920	.version = CAMSS_8650,
4921	.pd_name = "top",
4922	.csiphy_res = csiphy_res_sm8650,
4923	.csid_res = csid_res_sm8650,
4924	.csid_wrapper_res = &csid_wrapper_res_sm8550,
4925	.vfe_res = vfe_res_sm8650,
4926	.icc_res = icc_res_sm8650,
4927	.icc_path_num = ARRAY_SIZE(icc_res_sm8650),
4928	.csiphy_num = ARRAY_SIZE(csiphy_res_sm8650),
4929	.csid_num = ARRAY_SIZE(csid_res_sm8650),
4930	.vfe_num = ARRAY_SIZE(vfe_res_sm8650),
4931};
4932
4933static const struct camss_resources x1e80100_resources = {
4934	.version = CAMSS_X1E80100,
4935	.pd_name = "top",
4936	.csiphy_res = csiphy_res_x1e80100,
4937	.csid_res = csid_res_x1e80100,
4938	.vfe_res = vfe_res_x1e80100,
4939	.csid_wrapper_res = &csid_wrapper_res_x1e80100,
4940	.icc_res = icc_res_x1e80100,
4941	.icc_path_num = ARRAY_SIZE(icc_res_x1e80100),
4942	.csiphy_num = ARRAY_SIZE(csiphy_res_x1e80100),
4943	.csid_num = ARRAY_SIZE(csid_res_x1e80100),
4944	.vfe_num = ARRAY_SIZE(vfe_res_x1e80100),
4945};
4946
4947static const struct of_device_id camss_dt_match[] = {
4948	{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
4949	{ .compatible = "qcom,msm8939-camss", .data = &msm8939_resources },
4950	{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
4951	{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
4952	{ .compatible = "qcom,qcm2290-camss", .data = &qcm2290_resources },
4953	{ .compatible = "qcom,qcs8300-camss", .data = &qcs8300_resources },
4954	{ .compatible = "qcom,sa8775p-camss", .data = &sa8775p_resources },
4955	{ .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
4956	{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
4957	{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
4958	{ .compatible = "qcom,sdm670-camss", .data = &sdm670_resources },
4959	{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
4960	{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
4961	{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
4962	{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
4963	{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
4964	{ }
4965};
4966
4967MODULE_DEVICE_TABLE(of, camss_dt_match);
4968
4969static int __maybe_unused camss_runtime_suspend(struct device *dev)
4970{
4971	struct camss *camss = dev_get_drvdata(dev);
4972	int i;
4973	int ret;
4974
4975	for (i = 0; i < camss->res->icc_path_num; i++) {
4976		ret = icc_set_bw(camss->icc_path[i], 0, 0);
4977		if (ret)
4978			return ret;
4979	}
4980
4981	return 0;
4982}
4983
4984static int __maybe_unused camss_runtime_resume(struct device *dev)
4985{
4986	struct camss *camss = dev_get_drvdata(dev);
4987	const struct resources_icc *icc_res = camss->res->icc_res;
4988	int i;
4989	int ret;
4990
4991	for (i = 0; i < camss->res->icc_path_num; i++) {
4992		ret = icc_set_bw(camss->icc_path[i],
4993				 icc_res[i].icc_bw_tbl.avg,
4994				 icc_res[i].icc_bw_tbl.peak);
4995		if (ret)
4996			return ret;
4997	}
4998
4999	return 0;
5000}
5001
5002static const struct dev_pm_ops camss_pm_ops = {
5003	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5004				pm_runtime_force_resume)
5005	SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL)
5006};
5007
5008static struct platform_driver qcom_camss_driver = {
5009	.probe = camss_probe,
5010	.remove = camss_remove,
5011	.driver = {
5012		.name = "qcom-camss",
5013		.of_match_table = camss_dt_match,
5014		.pm = &camss_pm_ops,
5015	},
5016};
5017
5018module_platform_driver(qcom_camss_driver);
5019
5020MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver");
5021MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
5022MODULE_LICENSE("GPL v2");