camss-vfe-gen3.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen3
  4 *
  5 * Copyright (c) 2024 Qualcomm Technologies, Inc.
  6 */
  7
  8#include <linux/interrupt.h>
  9#include <linux/io.h>
 10#include <linux/iopoll.h>
 11
 12#include "camss.h"
 13#include "camss-vfe.h"
 14
 15#define IS_VFE_690(vfe) \
 16	    ((vfe->camss->res->version == CAMSS_8775P) \
 17	    || (vfe->camss->res->version == CAMSS_8300))
 18
 19#define BUS_REG_BASE_690 \
 20	    (vfe_is_lite(vfe) ? 0x480 : 0x400)
 21#define BUS_REG_BASE_780 \
 22	    (vfe_is_lite(vfe) ? 0x200 : 0xC00)
 23#define BUS_REG_BASE \
 24	    (IS_VFE_690(vfe) ? BUS_REG_BASE_690 : BUS_REG_BASE_780)
 25
 26#define VFE_TOP_CORE_CFG (0x24)
 27#define VFE_DISABLE_DSCALING_DS4  BIT(21)
 28#define VFE_DISABLE_DSCALING_DS16 BIT(22)
 29
 30#define VFE_BUS_WM_TEST_BUS_CTRL_690 (BUS_REG_BASE + 0xFC)
 31#define VFE_BUS_WM_TEST_BUS_CTRL_780 (BUS_REG_BASE + 0xDC)
 32#define VFE_BUS_WM_TEST_BUS_CTRL \
 33	    (IS_VFE_690(vfe) ? VFE_BUS_WM_TEST_BUS_CTRL_690 \
 34	     : VFE_BUS_WM_TEST_BUS_CTRL_780)
 35/*
 36 * Bus client mapping:
 37 *
 38 * Full VFE:
 39 * VFE_690: 16 = RDI0, 17 = RDI1, 18 = RDI2
 40 * VFE_780: 23 = RDI0, 24 = RDI1, 25 = RDI2
 41 *
 42 * VFE LITE:
 43 * VFE_690 : 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5
 44 * VFE_780 : 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4
 45 */
 46#define RDI_WM_690(n)	((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n))
 47#define RDI_WM_780(n)	((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
 48#define RDI_WM(n)	(IS_VFE_690(vfe) ? RDI_WM_690(n) : RDI_WM_780(n))
 49
 50#define VFE_BUS_WM_CGC_OVERRIDE		(BUS_REG_BASE + 0x08)
 51#define		WM_CGC_OVERRIDE_ALL		(0x7FFFFFF)
 52
 53#define VFE_BUS_WM_CFG(n)		(BUS_REG_BASE + 0x200 + (n) * 0x100)
 54#define		WM_CFG_EN			BIT(0)
 55#define		WM_VIR_FRM_EN			BIT(1)
 56#define		WM_CFG_MODE			BIT(16)
 57#define VFE_BUS_WM_IMAGE_ADDR(n)	(BUS_REG_BASE + 0x204 + (n) * 0x100)
 58#define VFE_BUS_WM_FRAME_INCR(n)	(BUS_REG_BASE + 0x208 + (n) * 0x100)
 59#define VFE_BUS_WM_IMAGE_CFG_0(n)	(BUS_REG_BASE + 0x20c + (n) * 0x100)
 60#define		WM_IMAGE_CFG_0_DEFAULT_WIDTH	(0xFFFF)
 61#define VFE_BUS_WM_IMAGE_CFG_2(n)	(BUS_REG_BASE + 0x214 + (n) * 0x100)
 62#define		WM_IMAGE_CFG_2_DEFAULT_STRIDE	(0xFFFF)
 63#define VFE_BUS_WM_PACKER_CFG(n)	(BUS_REG_BASE + 0x218 + (n) * 0x100)
 64
 65#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n)	(BUS_REG_BASE + 0x230 + (n) * 0x100)
 66#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n)	(BUS_REG_BASE + 0x234 + (n) * 0x100)
 67#define VFE_BUS_WM_FRAMEDROP_PERIOD(n)		(BUS_REG_BASE + 0x238 + (n) * 0x100)
 68#define VFE_BUS_WM_FRAMEDROP_PATTERN(n)		(BUS_REG_BASE + 0x23c + (n) * 0x100)
 69
 70#define VFE_BUS_WM_MMU_PREFETCH_CFG(n)		(BUS_REG_BASE + 0x260 + (n) * 0x100)
 71#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n)	(BUS_REG_BASE + 0x264 + (n) * 0x100)
 72
 73static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
 74{
 75	struct v4l2_pix_format_mplane *pix =
 76		&line->video_out.active_fmt.fmt.pix_mp;
 77
 78	wm = RDI_WM(wm);
 79
 80	/* no clock gating at bus input */
 81	writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
 82
 83	writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
 84
 85	if (IS_VFE_690(vfe))
 86		writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height,
 87		       vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
 88	else
 89		writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
 90		       vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
 91
 92	writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
 93	       vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
 94	writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
 95	       vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
 96	writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
 97
 98	/* TOP CORE CFG */
 99	if (IS_VFE_690(vfe))
100		writel(VFE_DISABLE_DSCALING_DS4 | VFE_DISABLE_DSCALING_DS16,
101			vfe->base + VFE_TOP_CORE_CFG);
102
103	/* no dropped frames, one irq per frame */
104	writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
105	writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
106	writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
107	writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
108
109	writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
110	writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
111
112	writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
113}
114
115static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
116{
117	wm = RDI_WM(wm);
118	writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
119}
120
121static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
122			  struct vfe_line *line)
123{
124	wm = RDI_WM(wm);
125
126	if (IS_VFE_690(vfe))
127		writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
128	else
129		writel((addr >> 8), vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
130
131	dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n",
132		wm, addr);
133}
134
135static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
136{
137	int port_id = line_id;
138
139	camss_reg_update(vfe->camss, vfe->id, port_id, false);
140}
141
142static inline void vfe_reg_update_clear(struct vfe_device *vfe,
143					enum vfe_line_id line_id)
144{
145	int port_id = line_id;
146
147	camss_reg_update(vfe->camss, vfe->id, port_id, true);
148}
149
150static const struct camss_video_ops vfe_video_ops_gen3 = {
151	.queue_buffer = vfe_queue_buffer_v2,
152	.flush_buffers = vfe_flush_buffers,
153};
154
155static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
156{
157	vfe->video_ops = vfe_video_ops_gen3;
158}
159
160static void vfe_global_reset(struct vfe_device *vfe)
161{
162	vfe_isr_reset_ack(vfe);
163}
164
165static irqreturn_t vfe_isr(int irq, void *dev)
166{
167	/* nop */
168	return IRQ_HANDLED;
169}
170
171static int vfe_halt(struct vfe_device *vfe)
172{
173	/* rely on vfe_disable_output() to stop the VFE */
174	return 0;
175}
176
177const struct vfe_hw_ops vfe_ops_gen3 = {
178	.global_reset = vfe_global_reset,
179	.hw_version = vfe_hw_version,
180	.isr = vfe_isr,
181	.pm_domain_off = vfe_pm_domain_off,
182	.pm_domain_on = vfe_pm_domain_on,
183	.reg_update = vfe_reg_update,
184	.reg_update_clear = vfe_reg_update_clear,
185	.subdev_init = vfe_subdev_init,
186	.vfe_disable = vfe_disable,
187	.vfe_enable = vfe_enable_v2,
188	.vfe_halt = vfe_halt,
189	.vfe_wm_start = vfe_wm_start,
190	.vfe_wm_stop = vfe_wm_stop,
191	.vfe_buf_done = vfe_buf_done,
192	.vfe_wm_update = vfe_wm_update,
193};