camss-vfe-340.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module 340 (TFE)
  4 *
  5 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
  6 */
  7
  8#include <linux/delay.h>
  9#include <linux/bitfield.h>
 10#include <linux/interrupt.h>
 11#include <linux/io.h>
 12#include <linux/iopoll.h>
 13
 14#include "camss.h"
 15#include "camss-vfe.h"
 16
 17#define TFE_GLOBAL_RESET_CMD				(0x014)
 18#define		TFE_GLOBAL_RESET_CMD_CORE	BIT(0)
 19
 20#define TFE_REG_UPDATE_CMD				(0x02c)
 21
 22#define TFE_IRQ_CMD					(0x030)
 23#define		TFE_IRQ_CMD_CLEAR		BIT(0)
 24#define TFE_IRQ_MASK_0					(0x034)
 25#define		TFE_IRQ_MASK_0_RST_DONE		BIT(0)
 26#define		TFE_IRQ_MASK_0_BUS_WR		BIT(1)
 27#define TFE_IRQ_MASK_1					(0x038)
 28#define TFE_IRQ_MASK_2					(0x03c)
 29#define TFE_IRQ_CLEAR_0					(0x040)
 30
 31#define TFE_IRQ_STATUS_0				(0x04c)
 32
 33#define BUS_REG(a)					(0xa00 + (a))
 34
 35#define TFE_BUS_IRQ_MASK_0				BUS_REG(0x18)
 36#define		TFE_BUS_IRQ_MASK_RUP_DONE_MASK	GENMASK(3, 0)
 37#define		TFE_BUS_IRQ_MASK_RUP_DONE(sc)	FIELD_PREP(TFE_BUS_IRQ_MASK_RUP_DONE_MASK, BIT(sc))
 38#define		TFE_BUS_IRQ_MASK_BUF_DONE_MASK	GENMASK(15, 8)
 39#define		TFE_BUS_IRQ_MASK_BUF_DONE(sg)	FIELD_PREP(TFE_BUS_IRQ_MASK_BUF_DONE_MASK, BIT(sg))
 40#define		TFE_BUS_IRQ_MASK_0_CONS_VIOL	BIT(28)
 41#define		TFE_BUS_IRQ_MASK_0_VIOL		BIT(30)
 42#define		TFE_BUS_IRQ_MASK_0_IMG_VIOL	BIT(31)
 43
 44#define TFE_BUS_IRQ_MASK_1				BUS_REG(0x1c)
 45#define TFE_BUS_IRQ_CLEAR_0				BUS_REG(0x20)
 46#define TFE_BUS_IRQ_STATUS_0				BUS_REG(0x28)
 47#define TFE_BUS_IRQ_CMD					BUS_REG(0x30)
 48#define		TFE_BUS_IRQ_CMD_CLEAR		BIT(0)
 49
 50#define TFE_BUS_STATUS_CLEAR				BUS_REG(0x60)
 51#define TFE_BUS_VIOLATION_STATUS			BUS_REG(0x64)
 52#define TFE_BUS_OVERFLOW_STATUS				BUS_REG(0x68)
 53#define TFE_BUS_IMAGE_SZ_VIOLATION_STATUS		BUS_REG(0x70)
 54
 55#define TFE_BUS_CLIENT_CFG(c)				BUS_REG(0x200 + (c) * 0x100)
 56#define		TFE_BUS_CLIENT_CFG_EN		BIT(0)
 57#define		TFE_BUS_CLIENT_CFG_MODE_FRAME	BIT(16)
 58#define TFE_BUS_IMAGE_ADDR(c)				BUS_REG(0x204 + (c) * 0x100)
 59#define TFE_BUS_FRAME_INCR(c)				BUS_REG(0x208 + (c) * 0x100)
 60#define TFE_BUS_IMAGE_CFG_0(c)				BUS_REG(0x20c + (c) * 0x100)
 61#define		TFE_BUS_IMAGE_CFG_0_DEFAULT	0xffff
 62#define TFE_BUS_IMAGE_CFG_1(c)				BUS_REG(0x210 + (c) * 0x100)
 63#define TFE_BUS_IMAGE_CFG_2(c)				BUS_REG(0x214 + (c) * 0x100)
 64#define		TFE_BUS_IMAGE_CFG_2_DEFAULT	0xffff
 65#define TFE_BUS_PACKER_CFG(c)				BUS_REG(0x218 + (c) * 0x100)
 66#define		TFE_BUS_PACKER_CFG_FMT_PLAIN64	0xa
 67#define TFE_BUS_IRQ_SUBSAMPLE_CFG_0(c)			BUS_REG(0x230 + (c) * 0x100)
 68#define TFE_BUS_IRQ_SUBSAMPLE_CFG_1(c)			BUS_REG(0x234 + (c) * 0x100)
 69#define TFE_BUS_FRAMEDROP_CFG_0(c)			BUS_REG(0x238 + (c) * 0x100)
 70#define TFE_BUS_FRAMEDROP_CFG_1(c)			BUS_REG(0x23c + (c) * 0x100)
 71
 72/*
 73 * TODO: differentiate the port id based on requested type of RDI, BHIST etc
 74 *
 75 * TFE write master IDs (clients)
 76 *
 77 * BAYER		0
 78 * IDEAL_RAW		1
 79 * STATS_TINTLESS_BG	2
 80 * STATS_BHIST		3
 81 * STATS_AWB_BG		4
 82 * STATS_AEC_BG		5
 83 * STATS_BAF		6
 84 * RDI0			7
 85 * RDI1			8
 86 * RDI2			9
 87 */
 88#define RDI_WM(n)		(7 + (n))
 89#define TFE_WM_NUM		10
 90
 91enum tfe_iface {
 92	TFE_IFACE_PIX,
 93	TFE_IFACE_RDI0,
 94	TFE_IFACE_RDI1,
 95	TFE_IFACE_RDI2,
 96	TFE_IFACE_NUM
 97};
 98
 99enum tfe_subgroups {
100	TFE_SUBGROUP_BAYER,
101	TFE_SUBGROUP_IDEAL_RAW,
102	TFE_SUBGROUP_HDR,
103	TFE_SUBGROUP_BG,
104	TFE_SUBGROUP_BAF,
105	TFE_SUBGROUP_RDI0,
106	TFE_SUBGROUP_RDI1,
107	TFE_SUBGROUP_RDI2,
108	TFE_SUBGROUP_NUM
109};
110
111static enum tfe_iface tfe_line_iface_map[VFE_LINE_NUM_MAX] = {
112	[VFE_LINE_RDI0] = TFE_IFACE_RDI0,
113	[VFE_LINE_RDI1] = TFE_IFACE_RDI1,
114	[VFE_LINE_RDI2] = TFE_IFACE_RDI2,
115	[VFE_LINE_PIX] = TFE_IFACE_PIX,
116};
117
118static enum vfe_line_id tfe_subgroup_line_map[TFE_SUBGROUP_NUM] = {
119	[TFE_SUBGROUP_BAYER] = VFE_LINE_PIX,
120	[TFE_SUBGROUP_IDEAL_RAW] = VFE_LINE_PIX,
121	[TFE_SUBGROUP_HDR] = VFE_LINE_PIX,
122	[TFE_SUBGROUP_BG] = VFE_LINE_PIX,
123	[TFE_SUBGROUP_BAF] = VFE_LINE_PIX,
124	[TFE_SUBGROUP_RDI0] = VFE_LINE_RDI0,
125	[TFE_SUBGROUP_RDI1] = VFE_LINE_RDI1,
126	[TFE_SUBGROUP_RDI2] = VFE_LINE_RDI2,
127};
128
129static inline enum tfe_iface  __line_to_iface(enum vfe_line_id line_id)
130{
131	if (line_id <= VFE_LINE_NONE || line_id >= VFE_LINE_NUM_MAX) {
132		pr_warn("VFE: Invalid line %d\n", line_id);
133		return TFE_IFACE_RDI0;
134	}
135
136	return tfe_line_iface_map[line_id];
137}
138
139static inline enum vfe_line_id __iface_to_line(unsigned int iface)
140{
141	int i;
142
143	for (i = 0; i < VFE_LINE_NUM_MAX; i++) {
144		if (tfe_line_iface_map[i] == iface)
145			return i;
146	}
147
148	return VFE_LINE_NONE;
149}
150
151static inline enum vfe_line_id __subgroup_to_line(enum tfe_subgroups sg)
152{
153	if (sg >= TFE_SUBGROUP_NUM)
154		return VFE_LINE_NONE;
155
156	return tfe_subgroup_line_map[sg];
157}
158
159static void vfe_global_reset(struct vfe_device *vfe)
160{
161	writel(TFE_IRQ_MASK_0_RST_DONE, vfe->base + TFE_IRQ_MASK_0);
162	writel(TFE_GLOBAL_RESET_CMD_CORE, vfe->base + TFE_GLOBAL_RESET_CMD);
163}
164
165static irqreturn_t vfe_isr(int irq, void *dev)
166{
167	struct vfe_device *vfe = dev;
168	u32 status;
169	int i;
170
171	status = readl_relaxed(vfe->base + TFE_IRQ_STATUS_0);
172	writel_relaxed(status, vfe->base + TFE_IRQ_CLEAR_0);
173	writel_relaxed(TFE_IRQ_CMD_CLEAR, vfe->base + TFE_IRQ_CMD);
174
175	if (status & TFE_IRQ_MASK_0_RST_DONE) {
176		dev_dbg(vfe->camss->dev, "VFE%u: Reset done!", vfe->id);
177		vfe_isr_reset_ack(vfe);
178	}
179
180	if (status & TFE_IRQ_MASK_0_BUS_WR) {
181		u32 bus_status = readl_relaxed(vfe->base + TFE_BUS_IRQ_STATUS_0);
182
183		writel_relaxed(bus_status, vfe->base + TFE_BUS_IRQ_CLEAR_0);
184		writel_relaxed(TFE_BUS_IRQ_CMD_CLEAR, vfe->base + TFE_BUS_IRQ_CMD);
185
186		for (i = 0; i < TFE_IFACE_NUM; i++) {
187			if (bus_status & TFE_BUS_IRQ_MASK_RUP_DONE(i))
188				vfe->res->hw_ops->reg_update_clear(vfe, __iface_to_line(i));
189		}
190
191		for (i = 0; i < TFE_SUBGROUP_NUM; i++) {
192			if (bus_status & TFE_BUS_IRQ_MASK_BUF_DONE(i))
193				vfe_buf_done(vfe, __subgroup_to_line(i));
194		}
195
196		if (bus_status & TFE_BUS_IRQ_MASK_0_CONS_VIOL)
197			dev_err_ratelimited(vfe->camss->dev, "VFE%u: Bad config violation",
198					    vfe->id);
199
200		if (bus_status & TFE_BUS_IRQ_MASK_0_VIOL)
201			dev_err_ratelimited(vfe->camss->dev, "VFE%u: Input data violation",
202					    vfe->id);
203
204		if (bus_status & TFE_BUS_IRQ_MASK_0_IMG_VIOL)
205			dev_err_ratelimited(vfe->camss->dev, "VFE%u: Image size violation",
206					    vfe->id);
207	}
208
209	status = readl_relaxed(vfe->base + TFE_BUS_OVERFLOW_STATUS);
210	if (status) {
211		writel_relaxed(status, vfe->base + TFE_BUS_STATUS_CLEAR);
212		for (i = 0; i < TFE_WM_NUM; i++) {
213			if (status & BIT(i))
214				dev_err_ratelimited(vfe->camss->dev,
215						    "VFE%u: bus overflow for wm %u\n",
216						    vfe->id, i);
217		}
218	}
219
220	return IRQ_HANDLED;
221}
222
223static int vfe_halt(struct vfe_device *vfe)
224{
225	/* rely on vfe_disable_output() to stop the VFE */
226	return 0;
227}
228
229static void vfe_enable_irq(struct vfe_device *vfe)
230{
231	writel(TFE_IRQ_MASK_0_RST_DONE | TFE_IRQ_MASK_0_BUS_WR,
232	       vfe->base + TFE_IRQ_MASK_0);
233	writel(TFE_BUS_IRQ_MASK_RUP_DONE_MASK | TFE_BUS_IRQ_MASK_BUF_DONE_MASK |
234	       TFE_BUS_IRQ_MASK_0_CONS_VIOL | TFE_BUS_IRQ_MASK_0_VIOL |
235	       TFE_BUS_IRQ_MASK_0_IMG_VIOL, vfe->base + TFE_BUS_IRQ_MASK_0);
236}
237
238static void vfe_wm_update(struct vfe_device *vfe, u8 rdi, u32 addr,
239			  struct vfe_line *line)
240{
241	u8 wm = RDI_WM(rdi);
242
243	writel_relaxed(addr, vfe->base + TFE_BUS_IMAGE_ADDR(wm));
244}
245
246static void vfe_wm_start(struct vfe_device *vfe, u8 rdi, struct vfe_line *line)
247{
248	struct v4l2_pix_format_mplane *pix = &line->video_out.active_fmt.fmt.pix_mp;
249	u32 stride = pix->plane_fmt[0].bytesperline;
250	u8 wm = RDI_WM(rdi);
251
252	/* Configuration for plain RDI frames */
253	writel_relaxed(TFE_BUS_IMAGE_CFG_0_DEFAULT, vfe->base + TFE_BUS_IMAGE_CFG_0(wm));
254	writel_relaxed(0u, vfe->base + TFE_BUS_IMAGE_CFG_1(wm));
255	writel_relaxed(TFE_BUS_IMAGE_CFG_2_DEFAULT, vfe->base + TFE_BUS_IMAGE_CFG_2(wm));
256	writel_relaxed(stride * pix->height, vfe->base + TFE_BUS_FRAME_INCR(wm));
257	writel_relaxed(TFE_BUS_PACKER_CFG_FMT_PLAIN64, vfe->base + TFE_BUS_PACKER_CFG(wm));
258
259	/* No dropped frames, one irq per frame */
260	writel_relaxed(0, vfe->base + TFE_BUS_FRAMEDROP_CFG_0(wm));
261	writel_relaxed(1, vfe->base + TFE_BUS_FRAMEDROP_CFG_1(wm));
262	writel_relaxed(0, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_0(wm));
263	writel_relaxed(1, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_1(wm));
264
265	vfe_enable_irq(vfe);
266
267	writel(TFE_BUS_CLIENT_CFG_EN | TFE_BUS_CLIENT_CFG_MODE_FRAME,
268	       vfe->base + TFE_BUS_CLIENT_CFG(wm));
269
270	dev_dbg(vfe->camss->dev, "VFE%u: Started RDI%u width %u height %u stride %u\n",
271		vfe->id, rdi, pix->width, pix->height, stride);
272}
273
274static void vfe_wm_stop(struct vfe_device *vfe, u8 rdi)
275{
276	u8 wm = RDI_WM(rdi);
277
278	writel(0, vfe->base + TFE_BUS_CLIENT_CFG(wm));
279
280	dev_dbg(vfe->camss->dev, "VFE%u: Stopped RDI%u\n", vfe->id, rdi);
281}
282
283static const struct camss_video_ops vfe_video_ops_520 = {
284	.queue_buffer = vfe_queue_buffer_v2,
285	.flush_buffers = vfe_flush_buffers,
286};
287
288static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
289{
290	vfe->video_ops = vfe_video_ops_520;
291}
292
293static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
294{
295	vfe->reg_update |= BIT(__line_to_iface(line_id));
296	writel_relaxed(vfe->reg_update, vfe->base + TFE_REG_UPDATE_CMD);
297}
298
299static void vfe_reg_update_clear(struct vfe_device *vfe, enum vfe_line_id line_id)
300{
301	vfe->reg_update &= ~BIT(__line_to_iface(line_id));
302}
303
304const struct vfe_hw_ops vfe_ops_340 = {
305	.global_reset = vfe_global_reset,
306	.hw_version = vfe_hw_version,
307	.isr = vfe_isr,
308	.pm_domain_off = vfe_pm_domain_off,
309	.pm_domain_on = vfe_pm_domain_on,
310	.subdev_init = vfe_subdev_init,
311	.vfe_disable = vfe_disable,
312	.vfe_enable = vfe_enable_v2,
313	.vfe_halt = vfe_halt,
314	.vfe_wm_start = vfe_wm_start,
315	.vfe_wm_stop = vfe_wm_stop,
316	.vfe_buf_done = vfe_buf_done,
317	.vfe_wm_update = vfe_wm_update,
318	.reg_update = vfe_reg_update,
319	.reg_update_clear = vfe_reg_update_clear,
320};